RENESAS R5F21322ANFP

REJ09B0458-0010
R8C/32A Group
16
Hardware Manual
RENESAS MCU
M16C FAMILY / R8C/Tiny SERIES
Preliminary
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.0.10
Revision Date: Apr 01, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1.
Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/32A Group. Make sure to refer to the latest versions of these documents.
The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type
Datasheet
Description
Document Title
Document No.
REJ03B0229
Hardware overview and electrical characteristics R8C/32A Group
Datasheet
R8C/32A Group
This hardware
Hardware manual Hardware specifications (pin assignments,
Hardware Manual manual
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set
R8C/Tiny Series
REJ09B0001
Software Manual
Available from Renesas
Application note Information on using peripheral functions and
Technology Web site.
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”
“bit,” or “pin” to distinguish the three categories.
Examples
the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing is
appended to numeric values given in decimal format.
Examples
Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3.
Register Notation
The symbols and terms used in register diagrams are described below.
x.x.x
XXX Register (Symbol)
Address XXXXh
Bit
b7
Symbol XXX7
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
XXX6
0
Symbol
XXX0 XXX bit
XXX1
—
—
XXX4
XXX5
XXX6
XXX7
b5
XXX5
0
b4
XXX4
0
b3
—
0
Bit Name
b2
—
0
b1
XXX1
0
b0
XXX0
0
Function
b1 b0
0 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
Reserved bit
Set to 0.
XXX bit
Function varies according to the operating mode.
XXX bit
0: XXX
1: XXX
*2
*1
R/W
R/W
R/W
—
R/W
R/W
W
R/W
R
*3
*1
R/W: Read and write.
R: Read only.
W: Write only.
−: Nothing is assigned.
*2
• Reserved bit
Reserved bit. Set to specified value.
*3
• Nothing is assigned.
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value.
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Full Form
Asynchronous Communication Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment Bus
Input/Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connection
Phase Locked Loop
Pulse Width Modulation
Special Function Register
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1.
Overview ......................................................................................................................................... 1
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
2.
Features .....................................................................................................................................................
Applications ..........................................................................................................................................
Specifications ........................................................................................................................................
Product List ...............................................................................................................................................
Block Diagram .........................................................................................................................................
Pin Assignment ..........................................................................................................................................
Pin Functions .............................................................................................................................................
1
1
2
4
5
6
8
Central Processing Unit (CPU) ..................................................................................................... 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.10
3.
Data Registers (R0, R1, R2, and R3) ......................................................................................................
Address Registers (A0 and A1) ...............................................................................................................
Frame Base Register (FB) .......................................................................................................................
Interrupt Table Register (INTB) ..............................................................................................................
Program Counter (PC) .............................................................................................................................
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..................................................................
Static Base Register (SB) ........................................................................................................................
Flag Register (FLG) ................................................................................................................................
Carry Flag (C) .....................................................................................................................................
Debug Flag (D) ...................................................................................................................................
Zero Flag (Z) .......................................................................................................................................
Sign Flag (S) .......................................................................................................................................
Register Bank Select Flag (B) ............................................................................................................
Overflow Flag (O) ..............................................................................................................................
Interrupt Enable Flag (I) .....................................................................................................................
Stack Pointer Select Flag (U) ..............................................................................................................
Processor Interrupt Priority Level (IPL) .............................................................................................
Reserved Bit ........................................................................................................................................
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
Memory ......................................................................................................................................... 13
3.1
R8C/32A Group ...................................................................................................................................... 13
4.
Special Function Registers (SFRs) ............................................................................................... 14
5.
Resets ........................................................................................................................................... 26
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
5.2.1
5.2.2
5.3
5.4
5.5
5.6
Registers ..................................................................................................................................................
Processor Mode Register 0 (PM0) ......................................................................................................
Reset Source Determination Register (RSTFR) .................................................................................
Option Function Select Register (OFS) ..............................................................................................
Option Function Select Register 2 (OFS2) .........................................................................................
Hardware Reset .......................................................................................................................................
When Power Supply is Stable .............................................................................................................
Power On ............................................................................................................................................
Power-On Reset Function .......................................................................................................................
Voltage Monitor 0 Reset .........................................................................................................................
Watchdog Timer Reset ............................................................................................................................
Software Reset .........................................................................................................................................
A-1
28
28
28
29
30
31
31
31
33
34
35
35
5.7
5.8
6.
Cold Start-Up/Warm Start-Up Determination Function ......................................................................... 36
Reset Source Determination Function ..................................................................................................... 36
Voltage Detection Circuit .............................................................................................................. 37
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.3
6.3.1
6.3.2
6.3.3
6.4
6.5
6.6
7.
Overview .................................................................................................................................................
Registers ..................................................................................................................................................
Voltage Monitor Circuit/Comparator A Control Register (CMPA) ...................................................
Voltage Monitor Circuit Edge Select Register (VCAC) ....................................................................
Voltage Detect Register (VCA1) ........................................................................................................
Voltage Detect Register 2 (VCA2) .....................................................................................................
Voltage Detection 1 Level Select Register (VD1LS) .........................................................................
Voltage Monitor 0 Circuit Control Register (VW0C) ........................................................................
Voltage Monitor 1 Circuit Control Register (VW1C) ........................................................................
Voltage Monitor 2 Circuit Control Register (VW2C) ........................................................................
Option Function Select Register (OFS) ..............................................................................................
VCC Input Voltage ..................................................................................................................................
Monitoring Vdet0 ...............................................................................................................................
Monitoring Vdet1 ...............................................................................................................................
Monitoring Vdet2 ...............................................................................................................................
Voltage Monitor 0 Reset .........................................................................................................................
Voltage Monitor 1 Interrupt ....................................................................................................................
Voltage Monitor 2 Interrupt ....................................................................................................................
37
41
41
42
42
43
44
45
46
47
48
49
49
49
49
50
51
53
I/O Ports ........................................................................................................................................ 55
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.5
7.6
Functions of I/O Ports .............................................................................................................................
Effect on Peripheral Functions ................................................................................................................
Pins Other than I/O Ports .........................................................................................................................
Registers ..................................................................................................................................................
Port Pi Direction Register (PDi) (i = 1, 3, 4) ......................................................................................
Port Pi Register (Pi) (i = 1, 3, 4) .........................................................................................................
Timer RA Pin Select Register (TRASR) ............................................................................................
Timer RC Pin Select Register (TRBRCSR) .......................................................................................
Timer RC Pin Select Register 0 (TRCPSR0) .....................................................................................
Timer RC Pin Select Register 1 (TRCPSR1) .....................................................................................
UART0 Pin Select Register (U0SR) ...................................................................................................
UART2 Pin Select Register 0 (U2SR0) ..............................................................................................
UART2 Pin Select Register 1 (U2SR1) ..............................................................................................
SSU/IIC Pin Select Register (SSUIICSR) ..........................................................................................
INT Interrupt Input Pin Select Register (INTSR) ...............................................................................
Pull-Up Control Register 0 (PUR0) ....................................................................................................
Pull-Up Control Register 1 (PUR1) ....................................................................................................
Port P1 Drive Capacity Control Register (P1DRR) ............................................................................
Drive Capacity Control Register 0 (DRR0) ........................................................................................
Drive Capacity Control Register 1 (DRR1) ........................................................................................
Input Threshold Control Register 0 (VLT0) .......................................................................................
Input Threshold Control Register 1 (VLT1) .......................................................................................
Port Settings ............................................................................................................................................
Unassigned Pin Handling ........................................................................................................................
A-2
55
56
56
65
65
66
67
67
68
68
69
70
70
71
71
72
72
73
74
75
76
76
77
86
8.
Bus ................................................................................................................................................ 87
9.
Clock Generation Circuit ............................................................................................................... 89
9.1
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
9.2.12
9.2.13
9.2.14
9.3
9.4
9.4.1
9.4.2
9.5
9.6
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
9.6.6
9.6.7
9.6.8
9.6.9
9.6.10
9.7
9.7.1
9.7.2
9.7.3
9.8
9.8.1
9.9
9.9.1
9.9.2
9.9.3
9.9.4
10.
10.1
Overview ................................................................................................................................................. 89
Registers .................................................................................................................................................. 92
System Clock Control Register 0 (CM0) ............................................................................................ 92
System Clock Control Register 1 (CM1) ............................................................................................ 93
System Clock Control Register 3 (CM3) ............................................................................................ 94
Oscillation Stop Detection Register (OCD) ........................................................................................ 95
High-Speed On-Chip Oscillator Control Register 7 (FRA7) .............................................................. 95
High-Speed On-Chip Oscillator Control Register 0 (FRA0) .............................................................. 96
High-Speed On-Chip Oscillator Control Register 1 (FRA1) .............................................................. 96
High-Speed On-Chip Oscillator Control Register 2 (FRA2) .............................................................. 97
Clock Prescaler Reset Flag (CPSRF) .................................................................................................. 97
High-Speed On-Chip Oscillator Control Register 4 (FRA4) .............................................................. 98
High-Speed On-Chip Oscillator Control Register 5 (FRA5) .............................................................. 98
High-Speed On-Chip Oscillator Control Register 6 (FRA6) .............................................................. 98
High-Speed On-Chip Oscillator Control Register 3 (FRA3) .............................................................. 98
Voltage Detect Register 2 (VCA2) ..................................................................................................... 99
XIN Clock ............................................................................................................................................. 101
On-Chip Oscillator Clock ...................................................................................................................... 102
Low-Speed On-Chip Oscillator Clock .............................................................................................. 102
High-Speed On-Chip Oscillator Clock ............................................................................................. 102
XCIN Clock ........................................................................................................................................... 103
CPU Clock and Peripheral Function Clock ........................................................................................... 104
System Clock .................................................................................................................................... 104
CPU Clock ........................................................................................................................................ 104
Peripheral Function Clock (f1, f2, f4, f8, and f32) ........................................................................... 104
fOCO ................................................................................................................................................. 104
fOCO40M ......................................................................................................................................... 104
fOCO-F ............................................................................................................................................. 104
fOCO-S ............................................................................................................................................. 105
fOCO128 ........................................................................................................................................... 105
fC, fC2, fC4, and fC32 ...................................................................................................................... 105
fOCO-WDT ...................................................................................................................................... 105
Power Control ........................................................................................................................................ 106
Standard Operating Mode ................................................................................................................. 106
Wait Mode ........................................................................................................................................ 108
Stop Mode ......................................................................................................................................... 112
Oscillation Stop Detection Function ..................................................................................................... 115
How to Use Oscillation Stop Detection Function ............................................................................. 116
Notes on Clock Generation Circuit ....................................................................................................... 119
Stop Mode ......................................................................................................................................... 119
Wait Mode ........................................................................................................................................ 119
Oscillation Stop Detection Function ................................................................................................. 119
Oscillation Circuit Constants ............................................................................................................ 119
Protection .................................................................................................................................... 120
Register .................................................................................................................................................. 120
A-3
10.1.1
11.
Protect Register (PRCR) ................................................................................................................... 120
Interrupts ..................................................................................................................................... 121
11.1
Overview ............................................................................................................................................... 121
11.1.1 Types of Interrupts ............................................................................................................................ 121
11.1.2 Software Interrupts ........................................................................................................................... 122
11.1.3 Special Interrupts .............................................................................................................................. 123
11.1.4 Peripheral Function Interrupts .......................................................................................................... 123
11.1.5 Interrupts and Interrupt Vectors ........................................................................................................ 124
11.2
Registers ................................................................................................................................................ 126
11.2.1 Interrupt Control Register
(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC, U2BCNIC, VCMP1IC,
VCMP2IC) ........................................................................................................................................ 126
11.2.2 Interrupt Control Register (FMRDYIC TRCIC, SSUIC/IICIC) ...................................................... 127
11.2.3 INTi Interrupt Control Register (INTiIC) (i = 0, 1, 3) ...................................................................... 128
11.3
Interrupt Control .................................................................................................................................... 129
11.3.1 I Flag ................................................................................................................................................. 129
11.3.2 IR Bit ................................................................................................................................................. 129
11.3.3 Bits ILVL2 to ILVL0, IPL ................................................................................................................ 129
11.3.4 Interrupt Sequence ............................................................................................................................ 130
11.3.5 Interrupt Response Time ................................................................................................................... 131
11.3.6 IPL Change when Interrupt Request is Acknowledged .................................................................... 131
11.3.7 Saving Registers ............................................................................................................................... 132
11.3.8 Returning from Interrupt Routine ..................................................................................................... 134
11.3.9 Interrupt Priority ............................................................................................................................... 134
11.3.10 Interrupt Priority Level Selection Circuit ......................................................................................... 135
11.4
INT Interrupt ......................................................................................................................................... 136
11.4.1 INTi Interrupt (i = 0, 1, 3) ................................................................................................................. 136
11.4.2 INT Interrupt Input Pin Select Register (INTSR) ............................................................................. 136
11.4.3 External Input Enable Register 0 (INTEN) ...................................................................................... 137
11.4.4 INT Input Filter Select Register 0 (INTF) ........................................................................................ 137
11.4.5 INTi Input Filter (i = 0, 1, 3) ............................................................................................................. 138
11.5
Key Input Interrupt ................................................................................................................................ 139
11.5.1 Key Input Enable Register 0 (KIEN) ................................................................................................ 140
11.6
Address Match Interrupt ........................................................................................................................ 141
11.6.1 Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1) ...................................................... 142
11.6.2 Address Match Interrupt Register i (RMADi) (i = 0 or 1) ................................................................ 142
11.7
Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and
Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources) .................................... 143
11.8
Notes on Interrupts ................................................................................................................................ 145
11.8.1 Reading Address 00000h .................................................................................................................. 145
11.8.2 SP Setting .......................................................................................................................................... 145
11.8.3 External Interrupt and Key Input Interrupt ....................................................................................... 145
11.8.4 Changing Interrupt Sources .............................................................................................................. 146
11.8.5 Rewriting Interrupt Control Register ................................................................................................ 147
12.
12.1
12.2
ID Code Areas ............................................................................................................................ 148
Overview ............................................................................................................................................... 148
Functions ............................................................................................................................................... 149
A-4
12.3
Forced Erase Function ...........................................................................................................................
12.4
Standard Serial II/O Mode Disabled Function ......................................................................................
12.5
Notes on ID Code Areas ........................................................................................................................
12.5.1 Setting Example of ID Code Areas ...................................................................................................
13.
150
150
151
151
Option Function Select Area ....................................................................................................... 152
13.1
Overview ............................................................................................................................................... 152
13.2
Registers ................................................................................................................................................ 153
13.2.1 Option Function Select Register (OFS) ............................................................................................ 153
13.2.2 Option Function Select Register 2 (OFS2) ....................................................................................... 154
13.3
Notes on Option Function Select Area .................................................................................................. 155
13.3.1 Setting Example of Option Function Select Area ............................................................................. 155
14.
Watchdog Timer .......................................................................................................................... 156
14.1
Overview ............................................................................................................................................... 156
14.2
Registers ................................................................................................................................................ 158
14.2.1 Processor Mode Register 1 (PM1) .................................................................................................... 158
14.2.2 Watchdog Timer Reset Register (WDTR) ........................................................................................ 158
14.2.3 Watchdog Timer Start Register (WDTS) ......................................................................................... 158
14.2.4 Watchdog Timer Control Register (WDTC) .................................................................................... 159
14.2.5 Count Source Protection Mode Register (CSPR) ............................................................................. 159
14.2.6 Option Function Select Register (OFS) ............................................................................................ 160
14.2.7 Option Function Select Register 2 (OFS2) ....................................................................................... 161
14.3
Functional Description ......................................................................................................................... 162
14.3.1 Common Items for Multiple Modes ................................................................................................. 162
14.3.2 Count Source Protection Mode Disabled .......................................................................................... 163
14.3.3 Count Source Protection Mode Enabled ........................................................................................... 164
15.
DTC ............................................................................................................................................ 165
15.1
Overview ............................................................................................................................................... 165
15.2
Registers ................................................................................................................................................ 166
15.2.1 DTC Control Register (DTCCR) ...................................................................................................... 167
15.2.2 DTC Block Size Register (DTBLS) ................................................................................................. 167
15.2.3 DTC Transfer Count Register (DTCCT) .......................................................................................... 168
15.2.4 DTC Transfer Count Reload Register (DTRLD) ............................................................................. 168
15.2.5 DTC Source Address Register (DTSAR) ......................................................................................... 168
15.2.6 DTC Destination Register (DTDAR) ............................................................................................... 168
15.2.7 DTC Activation Enable Registers (DTCENi) (i = 0 to 3, 5, 6) ........................................................ 169
15.2.8 DTC Activation Control Register (DTCTL) .................................................................................... 170
15.3
Function Description ............................................................................................................................. 171
15.3.1 Overview ........................................................................................................................................... 171
15.3.2 Activation Sources ............................................................................................................................ 171
15.3.3 Control Data Allocation and DTC Vector Table .............................................................................. 173
15.3.4 Normal Mode .................................................................................................................................... 176
15.3.5 Repeat Mode ..................................................................................................................................... 177
15.3.6 Chain Transfers ................................................................................................................................. 178
15.3.7 Interrupt Sources ............................................................................................................................... 178
15.3.8 Operation Timings ............................................................................................................................ 179
15.3.9 Number of DTC Execution Cycles ................................................................................................... 180
A-5
15.4
Notes on DTC ........................................................................................................................................
15.4.1 DTC activation source ......................................................................................................................
15.4.2 DTCENi Registers (i = 0 to 3, 5, 6) ..................................................................................................
15.4.3 Peripheral Modules ...........................................................................................................................
181
181
181
181
16.
General Overview of Timers ....................................................................................................... 182
17.
Timer RA ..................................................................................................................................... 184
17.1
17.2
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.3
17.3.1
17.3.2
17.4
17.4.1
17.5
17.5.1
17.6
17.6.1
17.6.2
17.7
17.7.1
17.7.2
17.8
18.
Overview ...............................................................................................................................................
Registers ................................................................................................................................................
Timer RA Control Register (TRACR) ..............................................................................................
Timer RA I/O Control Register (TRAIOC) ......................................................................................
Timer RA Mode Register (TRAMR) ................................................................................................
Timer RA Prescaler Register (TRAPRE) .........................................................................................
Timer RA Register (TRA) ................................................................................................................
Timer RA Pin Select Register (TRASR) ..........................................................................................
Timer Mode ...........................................................................................................................................
Timer RA I/O Control Register (TRAIOC) in Timer Mode ............................................................
Timer Write Control during Count Operation ..................................................................................
Pulse Output Mode ................................................................................................................................
Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode .................................................
Event Counter Mode .............................................................................................................................
Timer RA I/O Control Register (TRAIOC) in Event Counter Mode ...............................................
Pulse Width Measurement Mode ..........................................................................................................
Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode ............................
Operating Example ...........................................................................................................................
Pulse Period Measurement Mode ..........................................................................................................
Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode ...........................
Operating Example ...........................................................................................................................
Notes on Timer RA ...............................................................................................................................
184
185
185
185
186
186
187
187
188
188
189
190
191
192
193
194
195
196
197
198
199
200
Timer RB ..................................................................................................................................... 201
18.1
18.2
18.2.1
18.2.2
18.2.3
18.2.4
18.2.5
18.2.6
18.2.7
18.3
18.3.1
18.3.2
18.4
18.4.1
18.4.2
18.5
18.5.1
Overview ...............................................................................................................................................
Registers ................................................................................................................................................
Timer RB Control Register (TRBCR) ..............................................................................................
Timer RB One-Shot Control Register (TRBOCR) ...........................................................................
Timer RB I/O Control Register (TRBIOC) ......................................................................................
Timer RB Mode Register (TRBMR) ................................................................................................
Timer RB Prescaler Register (TRBPRE) ..........................................................................................
Timer RB Secondary Register (TRBSC) ..........................................................................................
Timer RB Primary Register (TRBPR) ..............................................................................................
Timer Mode ...........................................................................................................................................
Timer RB I/O Control Register (TRBIOC) in Timer Mode .............................................................
Timer Write Control during Count Operation ..................................................................................
Programmable Waveform Generation Mode ........................................................................................
Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode ..........
Operating Example ...........................................................................................................................
Programmable One-shot Generation Mode ...........................................................................................
Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode ............
A-6
201
202
202
202
203
203
204
204
205
206
206
207
209
210
211
212
213
18.5.2 Operating Example ...........................................................................................................................
18.5.3 One-Shot Trigger Selection ..............................................................................................................
18.6
Programmable Wait One-Shot Generation Mode .................................................................................
18.6.1 Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode ...
18.6.2 Operating Example ...........................................................................................................................
18.7
Notes on Timer RB ................................................................................................................................
18.7.1 Timer Mode ......................................................................................................................................
18.7.2 Programmable Waveform Generation Mode ....................................................................................
18.7.3 Programmable One-shot Generation Mode ......................................................................................
18.7.4 Programmable Wait One-shot Generation Mode .............................................................................
19.
214
215
216
217
218
219
219
219
220
220
Timer RC ..................................................................................................................................... 221
19.1
Overview ...............................................................................................................................................
19.2
Registers ................................................................................................................................................
19.2.1 Module Standby Control Register (MSTCR) ...................................................................................
19.2.2 Timer RC Mode Register (TRCMR) ................................................................................................
19.2.3 Timer RC Control Register 1 (TRCCR1) .........................................................................................
19.2.4 Timer RC Interrupt Enable Register (TRCIER) ...............................................................................
19.2.5 Timer RC Status Register (TRCSR) .................................................................................................
19.2.6 Timer RC I/O Control Register 0 (TRCIOR0) .................................................................................
19.2.7 Timer RC I/O Control Register 1 (TRCIOR1) .................................................................................
19.2.8 Timer RC Counter (TRC) .................................................................................................................
19.2.9 Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD) ..........
19.2.10 Timer RC Control Register 2 (TRCCR2) .........................................................................................
19.2.11 Timer RC Digital Filter Function Select Register (TRCDF) ............................................................
19.2.12 Timer RC Output Master Enable Register (TRCOER) ....................................................................
19.2.13 Timer RC Trigger Control Register (TRCADCR) ...........................................................................
19.2.14 Timer RC Pin Select Register (TRBRCSR) .....................................................................................
19.2.15 Timer RC Pin Select Register 0 (TRCPSR0) ...................................................................................
19.2.16 Timer RC Pin Select Register 1 (TRCPSR1) ...................................................................................
19.3
Common Items for Multiple Modes ......................................................................................................
19.3.1 Count Source .....................................................................................................................................
19.3.2 Buffer Operation ...............................................................................................................................
19.3.3 Digital Filter ......................................................................................................................................
19.3.4 Forced Cutoff of Pulse Output ..........................................................................................................
19.4
Timer Mode (Input Capture Function) ..................................................................................................
19.4.1 Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function .....................................
19.4.2 Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function .....................................
19.4.3 Operating Example ...........................................................................................................................
19.5
Timer Mode (Output Compare Function) .............................................................................................
19.5.1 Timer RC Control Register 1 (TRCCR1) for Output Compare Function ........................................
19.5.2 Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function ................................
19.5.3 Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function ................................
19.5.4 Operating Example ...........................................................................................................................
19.5.5 Changing Output Pins in Registers TRCGRC and TRCGRD ..........................................................
19.6
PWM Mode ...........................................................................................................................................
19.6.1 Timer RC Control Register 1 (TRCCR1) in PWM Mode ................................................................
19.6.2 Timer RC Control Register 2 (TRCCR2) .........................................................................................
19.6.3 Operating Example ...........................................................................................................................
A-7
221
223
224
224
225
225
226
227
227
228
228
229
229
230
230
231
232
232
233
233
234
236
237
239
241
242
243
244
246
247
248
249
250
252
254
254
256
19.7
PWM2 Mode ......................................................................................................................................... 258
19.7.1 Timer RC Control Register 1 (TRCCR1) in PWM2 Mode .............................................................. 260
19.7.2 Timer RC Control Register 2 (TRCCR2) in PWM2 Mode .............................................................. 261
19.7.3 Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode ................................. 261
19.7.4 Operating Example ........................................................................................................................... 263
19.8
Timer RC Interrupt ................................................................................................................................ 266
19.9
Notes on Timer RC ................................................................................................................................ 267
19.9.1 TRC Register .................................................................................................................................... 267
19.9.2
TRCSR Register .............................................................................................................................. 267
19.9.3 TRCCR1 Register ............................................................................................................................. 267
19.9.4 Count Source Switching ................................................................................................................... 267
19.9.5 Input Capture Function ..................................................................................................................... 268
19.9.6 TRCMR Register in PWM2 Mode ................................................................................................... 268
19.9.7 Count Source fOCO40M .................................................................................................................. 268
20.
Timer RE ..................................................................................................................................... 269
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.2.6
20.2.7
20.2.8
20.3
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.4
20.4.1
20.4.2
20.4.3
21.
Overview ...............................................................................................................................................
Real-Time Clock Mode .........................................................................................................................
Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode .........................................
Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode .........................................
Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode ...............................................
Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode ................................
Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode ..............................................
Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode ..............................................
Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode .............................
Operating Example ...........................................................................................................................
Output Compare Mode ..........................................................................................................................
Timer RE Counter Data Register (TRESEC) in Output Compare Mode .........................................
Timer RE Compare Data Register (TREMIN) in Output Compare Mode .......................................
Timer RE Control Register 1 (TRECR1) in Output Compare Mode ...............................................
Timer RE Control Register 2 (TRECR2) in Output Compare Mode ...............................................
Timer RE Count Source Select Register (TRECSR) in Output Compare Mode ..............................
Operating Example ...........................................................................................................................
Notes on Timer RE ................................................................................................................................
Starting and Stopping Count .............................................................................................................
Register Setting .................................................................................................................................
Time Reading Procedure of Real-Time Clock Mode .......................................................................
269
270
272
272
273
273
274
275
276
277
278
280
280
281
281
282
283
284
284
284
286
Serial Interface (UART0) ............................................................................................................ 287
21.1
Overview ............................................................................................................................................... 287
21.2
Registers ................................................................................................................................................ 289
21.2.1 UART0 Transmit/Receive Mode Register (U0MR) ......................................................................... 289
21.2.2 UART0 Bit Rate Register (U0BRG) ................................................................................................ 289
21.2.3 UART0 Transmit Buffer Register (U0TB) ....................................................................................... 290
21.2.4 UART0 Transmit/Receive Control Register 0 (U0C0) .................................................................... 291
21.2.5 UART0 Transmit/Receive Control Register 1 (U0C1) .................................................................... 291
21.2.6 UART0 Receive Buffer Register (U0RB) ........................................................................................ 292
21.2.7 UART0 Pin Select Register (U0SR) ................................................................................................. 293
21.3
Clock Synchronous Serial I/O Mode ..................................................................................................... 294
A-8
21.3.1 Polarity Select Function ....................................................................................................................
21.3.2 LSB First/MSB First Select Function ...............................................................................................
21.3.3 Continuous Receive Mode ................................................................................................................
21.4
Clock Asynchronous Serial I/O (UART) Mode ....................................................................................
21.4.1 Bit Rate .............................................................................................................................................
21.5
Notes on Serial Interface (UART0) .......................................................................................................
22.
298
298
299
300
305
306
Serial Interface (UART2) ............................................................................................................ 307
22.1
Overview ...............................................................................................................................................
22.2
Registers ................................................................................................................................................
22.2.1 UART2 Transmit/Receive Mode Register (U2MR) .........................................................................
22.2.2 UART2 Bit Rate Register (U2BRG) ................................................................................................
22.2.3 UART2 Transmit Buffer Register (U2TB) .......................................................................................
22.2.4 UART2 Transmit/Receive Control Register 0 (U2C0) ....................................................................
22.2.5 UART2 Transmit/Receive Control Register 1 (U2C1) ....................................................................
22.2.6 UART2 Receive Buffer Register (U2RB) ........................................................................................
22.2.7 UART2 Digital Filter Function Select Register (URXDF) ..............................................................
22.2.8 UART2 Special Mode Register 5 (U2SMR5) ..................................................................................
22.2.9 UART2 Special Mode Register 4 (U2SMR4) ..................................................................................
22.2.10 UART2 Special Mode Register 3 (U2SMR3) ..................................................................................
22.2.11 UART2 Special Mode Register 2 (U2SMR2) ..................................................................................
22.2.12 UART2 Special Mode Register (U2SMR) .......................................................................................
22.2.13 UART2 Pin Select Register 0 (U2SR0) ............................................................................................
22.2.14 UART2 Pin Select Register 1 (U2SR1) ............................................................................................
22.3
Clock Synchronous Serial I/O Mode .....................................................................................................
22.3.1 Measure for Dealing with Communication Errors ...........................................................................
22.3.2 CLK Polarity Select Function ...........................................................................................................
22.3.3 LSB First/MSB First Select Function ...............................................................................................
22.3.4 Continuous Receive Mode ................................................................................................................
22.3.5 Serial Data Logic Switching Function ..............................................................................................
22.3.6 CTS/RTS Function ............................................................................................................................
22.4
Clock Asynchronous Serial I/O (UART) Mode ....................................................................................
22.4.1 Bit Rate .............................................................................................................................................
22.4.2 Measure for Dealing with Communication Errors ...........................................................................
22.4.3 LSB First/MSB First Select Function ...............................................................................................
22.4.4 Serial Data Logic Switching Function ..............................................................................................
22.4.5 TXD and RXD I/O Polarity Inverse Function ..................................................................................
22.4.6 CTS/RTS Function ............................................................................................................................
22.4.7 RXD2 Digital Filter Select Function ................................................................................................
22.5
Special Mode 1 (I2C Mode) ..................................................................................................................
22.5.1 Detection of Start and Stop Conditions ............................................................................................
22.5.2 Output of Start and Stop Conditions .................................................................................................
22.5.3 Arbitration .........................................................................................................................................
22.5.4 Transfer Clock ..................................................................................................................................
22.5.5 SDA Output ......................................................................................................................................
22.5.6 SDA Input .........................................................................................................................................
22.5.7 ACK and NACK ...............................................................................................................................
22.5.8 Initialization of Transmission/Reception ..........................................................................................
22.6
Multiprocessor Communication Function .............................................................................................
A-9
307
309
309
309
310
311
312
313
314
314
315
315
316
316
317
317
318
322
322
323
323
324
324
325
329
330
330
331
331
332
332
333
339
340
341
341
341
342
342
342
343
22.6.1 Multiprocessor Transmission ............................................................................................................
22.6.2 Multiprocessor Reception .................................................................................................................
22.6.3 RXD2 Digital Filter Select Function ................................................................................................
22.7
Notes on Serial Interface (UART2) .......................................................................................................
22.7.1 Clock Synchronous Serial I/O Mode ................................................................................................
22.7.2 Clock Asynchronous Serial I/O (UART) Mode ...............................................................................
22.7.3 Special Mode 1 (I2C Mode) ..............................................................................................................
23.
23.1
24.
Clock Synchronous Serial Interface ............................................................................................ 352
Mode Selection ...................................................................................................................................... 352
Synchronous Serial Communication Unit (SSU) ........................................................................ 353
24.1
Overview ...............................................................................................................................................
24.2
Registers ................................................................................................................................................
24.2.1 Module Standby Control Register (MSTCR) ...................................................................................
24.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................
24.2.3 SS Bit Counter Register (SSBR) ......................................................................................................
24.2.4 SS Transmit Data Register (SSTDR) ................................................................................................
24.2.5 SS Receive Data Register (SSRDR) .................................................................................................
24.2.6 SS Control Register H (SSCRH) ......................................................................................................
24.2.7 SS Control Register L (SSCRL) .......................................................................................................
24.2.8 SS Mode Register (SSMR) ...............................................................................................................
24.2.9 SS Enable Register (SSER) ..............................................................................................................
24.2.10 SS Status Register (SSSR) ................................................................................................................
24.2.11 SS Mode Register 2 (SSMR2) ..........................................................................................................
24.3
Common Items for Multiple Modes ......................................................................................................
24.3.1 Transfer Clock ..................................................................................................................................
24.3.2 SS Shift Register (SSTRSR) .............................................................................................................
24.3.3 Interrupt Requests .............................................................................................................................
24.3.4 Communication Modes and Pin Functions .......................................................................................
24.4
Clock Synchronous Communication Mode ..........................................................................................
24.4.1 Initialization in Clock Synchronous Communication Mode ............................................................
24.4.2 Data Transmission ............................................................................................................................
24.4.3 Data Reception ..................................................................................................................................
24.5
Operation in 4-Wire Bus Communication Mode ..................................................................................
24.5.1 Initialization in 4-Wire Bus Communication Mode .........................................................................
24.5.2 Data Transmission ............................................................................................................................
24.5.3 Data Reception ..................................................................................................................................
24.5.4 SCS Pin Control and Arbitration ......................................................................................................
24.6
Notes on Synchronous Serial Communication Unit ..............................................................................
25.
346
347
349
350
350
351
351
353
355
355
355
356
356
357
357
358
359
360
361
362
363
363
365
366
367
368
368
369
371
375
376
377
379
381
382
I2C bus Interface ......................................................................................................................... 383
25.1
Overview ............................................................................................................................................... 383
25.2
Registers ................................................................................................................................................ 386
25.2.1 Module Standby Control Register (MSTCR) ................................................................................... 386
25.2.2 SSU/IIC Pin Select Register (SSUIICSR) ........................................................................................ 386
25.2.3 IIC bus Transmit Data Register (ICDRT) ......................................................................................... 387
25.2.4 IIC bus Receive Data Register (ICDRR) .......................................................................................... 387
25.2.5 IIC bus Control Register 1 (ICCR1) ................................................................................................. 388
A - 10
25.2.6 IIC bus Control Register 2 (ICCR2) .................................................................................................
25.2.7 IIC bus Mode Register (ICMR) ........................................................................................................
25.2.8 IIC bus Interrupt Enable Register (ICIER) .......................................................................................
25.2.9 IIC bus Status Register (ICSR) .........................................................................................................
25.2.10 Slave Address Register (SAR) ..........................................................................................................
25.2.11 IIC bus Shift Register (ICDRS) ........................................................................................................
25.3
Common Items for Multiple Modes ......................................................................................................
25.3.1 Transfer Clock ..................................................................................................................................
25.3.2 Interrupt Requests .............................................................................................................................
25.4
I2C bus Interface Mode .........................................................................................................................
25.4.1 I2C bus Format .................................................................................................................................
25.4.2 Master Transmit Operation ...............................................................................................................
25.4.3 Master Receive Operation ................................................................................................................
25.4.4 Slave Transmit Operation .................................................................................................................
25.4.5 Slave Receive Operation ...................................................................................................................
25.5
Clock Synchronous Serial Mode ...........................................................................................................
25.5.1 Clock Synchronous Serial Format ....................................................................................................
25.5.2 Transmit Operation ...........................................................................................................................
25.5.3 Receive Operation .............................................................................................................................
25.6
Examples of Register Setting ................................................................................................................
25.7
Noise Canceller .....................................................................................................................................
25.8
Bit Synchronization Circuit ...................................................................................................................
25.9
Notes on I2C bus Interface ....................................................................................................................
26.
Hardware LIN .............................................................................................................................. 417
26.1
26.2
26.3
26.3.1
26.3.2
26.3.3
26.4
26.4.1
26.4.2
26.4.3
26.4.4
26.5
26.6
27.
389
390
391
392
393
393
394
394
395
396
396
397
399
402
405
407
407
408
409
410
414
415
416
Overview ...............................................................................................................................................
Input/Output Pins ..................................................................................................................................
Registers ................................................................................................................................................
LIN Control Register 2 (LINCR2) ....................................................................................................
LIN Control Register (LINCR) .........................................................................................................
LIN Status Register (LINST) ............................................................................................................
Function Description .............................................................................................................................
Master Mode .....................................................................................................................................
Slave Mode .......................................................................................................................................
Bus Collision Detection Function .....................................................................................................
Hardware LIN End Processing .........................................................................................................
Interrupt Requests ..................................................................................................................................
Notes on Hardware LIN ........................................................................................................................
417
418
419
419
420
420
421
421
424
428
429
430
431
A/D Converter ............................................................................................................................. 432
27.1
Overview ............................................................................................................................................... 432
27.2
Registers ................................................................................................................................................ 434
27.2.1 On-Chip Reference Voltage Control Register (OCVREFCR) ......................................................... 434
27.2.2 A/D Register i (ADi) (i = 0 to 7) ...................................................................................................... 435
27.2.3 A/D Mode Register (ADMOD) ........................................................................................................ 436
27.2.4 A/D Input Select Register (ADINSEL) ............................................................................................ 437
27.2.5 A/D Control Register 0 (ADCON0) ................................................................................................. 438
27.2.6 A/D Control Register 1 (ADCON1) ................................................................................................. 439
27.3
Common Items for Multiple Modes ...................................................................................................... 440
A - 11
27.3.1
27.3.2
27.3.3
27.3.4
27.3.5
27.3.6
27.3.7
27.4
27.5
27.6
27.7
27.8
27.9
27.10
27.11
28.
30.1
30.2
30.3
Overview ...............................................................................................................................................
Registers ................................................................................................................................................
Voltage Monitor Circuit/Comparator A Control Register (CMPA) .................................................
Voltage Monitor Circuit Edge Select Register (VCAC) ..................................................................
Voltage Detect Register (VCA1) ......................................................................................................
Voltage Detect Register 2 (VCA2) ...................................................................................................
Voltage Monitor 1 Circuit Control Register (VW1C) ......................................................................
Voltage Monitor 2 Circuit Control Register (VW2C) ......................................................................
Monitoring Comparison Results ...........................................................................................................
Monitoring Comparator A1 ..............................................................................................................
Monitoring Comparator A2 ..............................................................................................................
Functional Description ..........................................................................................................................
Comparator A1 .................................................................................................................................
Comparator A2 .................................................................................................................................
Comparator A1 and Comparator A2 Interrupts .....................................................................................
Non-Maskable Interrupts ..................................................................................................................
Maskable Interrupts ..........................................................................................................................
456
458
458
458
459
460
461
462
463
463
463
464
464
467
470
470
470
Comparator B ............................................................................................................................. 471
29.1
29.2
29.2.1
29.2.2
29.2.3
29.3
29.3.1
29.4
30.
440
440
442
443
443
443
443
445
446
447
449
451
453
454
455
Comparator A ............................................................................................................................. 456
28.1
28.2
28.2.1
28.2.2
28.2.3
28.2.4
28.2.5
28.2.6
28.3
28.3.1
28.3.2
28.4
28.4.1
28.4.2
28.5
28.5.1
28.5.2
29.
Input/Output Pins ..............................................................................................................................
A/D Conversion Cycles ....................................................................................................................
A/D Conversion Start Condition .......................................................................................................
A/D Conversion Result .....................................................................................................................
Low Current Consumption Function ................................................................................................
Extended Analog Input Pins .............................................................................................................
A/D Open-Circuit Detection Assist Function ...................................................................................
One-Shot Mode .....................................................................................................................................
Repeat Mode 0 .......................................................................................................................................
Repeat Mode 1 .......................................................................................................................................
Single Sweep Mode ...............................................................................................................................
Repeat Sweep Mode ..............................................................................................................................
Internal Equivalent Circuit of Analog Input ..........................................................................................
Output Impedance of Sensor under A/D Conversion ............................................................................
Notes on A/D Converter ........................................................................................................................
Overview ...............................................................................................................................................
Registers ................................................................................................................................................
Comparator B Control Register (INTCMP) .....................................................................................
External Input Enable Register 0 (INTEN) ......................................................................................
INT Input Filter Select Register 0 (INTF) ........................................................................................
Functional Description ..........................................................................................................................
Comparator Bi Digital Filter (i = 1 or 3) ..........................................................................................
Comparator B1 and Comparator B3 Interrupts .....................................................................................
471
473
473
473
474
475
476
477
Flash Memory ............................................................................................................................. 478
Overview ............................................................................................................................................... 478
Memory Map ......................................................................................................................................... 479
Functions to Prevent Flash Memory from being Rewritten .................................................................. 480
A - 12
30.3.1 ID Code Check Function ..................................................................................................................
30.3.2 ROM Code Protect Function ............................................................................................................
30.3.3 Option Function Select Register (OFS) ............................................................................................
30.4
CPU Rewrite Mode ...............................................................................................................................
30.4.1 Flash Memory Status Register (FST) ...............................................................................................
30.4.2 Flash Memory Control Register 0 (FMR0) ......................................................................................
30.4.3 Flash Memory Control Register 1 (FMR1) ......................................................................................
30.4.4 Flash Memory Control Register 2 (FMR2) ......................................................................................
30.4.5 EW0 Mode ........................................................................................................................................
30.4.6 EW1 Mode ........................................................................................................................................
30.4.7 Suspend Operation ............................................................................................................................
30.4.8 How to Set and Exit Each Mode .......................................................................................................
30.4.9 BGO (BackGround Operation) Function ..........................................................................................
30.4.10 Data Protect Function .......................................................................................................................
30.4.11 Software Commands .........................................................................................................................
30.4.12 Status Register ..................................................................................................................................
30.4.13 Sequence Status ................................................................................................................................
30.4.14 Erase Status .......................................................................................................................................
30.4.15 Program Status ..................................................................................................................................
30.4.16 Suspend Status ..................................................................................................................................
30.4.17 Full Status Check ..............................................................................................................................
30.5
Standard Serial I/O Mode ......................................................................................................................
30.5.1 ID Code Check Function ..................................................................................................................
30.6
Parallel I/O Mode ..................................................................................................................................
30.6.1 ROM Code Protect Function ............................................................................................................
30.7
Notes on Flash Memory ........................................................................................................................
30.7.1 CPU Rewrite Mode ...........................................................................................................................
31.
480
481
481
482
483
485
487
489
490
490
490
491
492
493
494
504
504
504
504
504
505
507
507
510
510
511
511
Reducing Power Consumption ................................................................................................... 514
31.1
Overview ...............................................................................................................................................
31.2
Key Points and Processing Methods for Reducing Power Consumption .............................................
31.2.1 Voltage Detection Circuit .................................................................................................................
31.2.2 Ports ..................................................................................................................................................
31.2.3 Clocks ...............................................................................................................................................
31.2.4 Wait Mode, Stop Mode .....................................................................................................................
31.2.5 Stopping Peripheral Function Clocks ...............................................................................................
31.2.6 Timers ...............................................................................................................................................
31.2.7 A/D Converter ...................................................................................................................................
31.2.8 Clock Synchronous Serial Interface .................................................................................................
31.2.9 Reducing Internal Power Consumption ............................................................................................
31.2.10 Stopping Flash Memory ....................................................................................................................
31.2.11 Low-Current-Consumption Read Mode ...........................................................................................
31.2.12 Others ................................................................................................................................................
514
514
514
514
514
514
514
514
514
514
515
516
517
517
32.
Electrical Characteristics ............................................................................................................ 518
33.
Usage Notes ............................................................................................................................... 545
33.1
Notes on Clock Generation Circuit ....................................................................................................... 545
33.1.1 Stop Mode ......................................................................................................................................... 545
A - 13
33.1.2 Wait Mode ........................................................................................................................................ 545
33.1.3 Oscillation Stop Detection Function ................................................................................................. 545
33.1.4 Oscillation Circuit Constants ............................................................................................................ 545
33.2
Notes on Interrupts ................................................................................................................................ 546
33.2.1 Reading Address 00000h .................................................................................................................. 546
33.2.2 SP Setting .......................................................................................................................................... 546
33.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 546
33.2.4 Changing Interrupt Sources .............................................................................................................. 547
33.2.5 Rewriting Interrupt Control Register ................................................................................................ 548
33.3
Notes on ID Code Areas ........................................................................................................................ 549
33.3.1 Setting Example of ID Code Areas ................................................................................................... 549
33.4
Notes on Option Function Select Area .................................................................................................. 549
33.4.1 Setting Example of Option Function Select Area ............................................................................. 549
33.5
Notes on DTC ........................................................................................................................................ 550
33.5.1 DTC activation source ...................................................................................................................... 550
33.5.2 DTCENi Registers (i = 0 to 3, 5, 6) .................................................................................................. 550
33.5.3 Peripheral Modules ........................................................................................................................... 550
33.6
Notes on Timer RA ............................................................................................................................... 551
33.7
Notes on Timer RB ................................................................................................................................ 552
33.7.1 Timer Mode ...................................................................................................................................... 552
33.7.2 Programmable Waveform Generation Mode .................................................................................... 552
33.7.3 Programmable One-shot Generation Mode ...................................................................................... 552
33.7.4 Programmable Wait One-shot Generation Mode ............................................................................. 553
33.8
Notes on Timer RC ................................................................................................................................ 554
33.8.1 TRC Register .................................................................................................................................... 554
33.8.2
TRCSR Register .............................................................................................................................. 554
33.8.3 TRCCR1 Register ............................................................................................................................. 554
33.8.4 Count Source Switching ................................................................................................................... 554
33.8.5 Input Capture Function ..................................................................................................................... 555
33.8.6 TRCMR Register in PWM2 Mode ................................................................................................... 555
33.8.7 Count Source fOCO40M .................................................................................................................. 555
33.9
Notes on Timer RE ................................................................................................................................ 556
33.9.1 Starting and Stopping Count ............................................................................................................. 556
33.9.2 Register Setting ................................................................................................................................. 556
33.9.3 Time Reading Procedure of Real-Time Clock Mode ....................................................................... 558
33.10 Notes on Serial Interface (UART0) ....................................................................................................... 559
33.11 Notes on Serial Interface (UART2) ....................................................................................................... 560
33.11.1 Clock Synchronous Serial I/O Mode ................................................................................................ 560
33.11.2 Clock Asynchronous Serial I/O (UART) Mode ............................................................................... 561
33.11.3 Special Mode 1 (I2C Mode) .............................................................................................................. 561
33.12 Notes on Synchronous Serial Communication Unit .............................................................................. 562
33.13 Notes on I2C bus Interface .................................................................................................................... 562
33.14 Notes on Hardware LIN ........................................................................................................................ 562
33.15 Notes on A/D Converter ........................................................................................................................ 562
33.16 Notes on Flash Memory ........................................................................................................................ 563
33.16.1 CPU Rewrite Mode ........................................................................................................................... 563
33.17 Notes on Noise ...................................................................................................................................... 566
33.17.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 566
A - 14
33.17.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 566
34.
Notes on On-Chip Debugger ...................................................................................................... 567
Appendix 1. Package Dimensions ........................................................................................................ 568
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 569
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 570
Index ..................................................................................................................................................... 571
A - 15
SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
Register
Symbol
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
PM0
PM1
CM0
CM1
MSTCR
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
High-Speed On-Chip Oscillator Control Register 7 FRA7
Count Source Protection Mode Register
CSPR
Page
28
158
92
93
224, 355,
386
94
120
28
95
158
158
159
95
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
159
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
96
96
97
434
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
97
98
98
98
High-Speed On-Chip Oscillator Control Register 3 FRA3
Voltage Monitor Circuit/Comparator A Control
CMPA
Register
Voltage Monitor Circuit Edge Select Register
VCAC
Address
Register
0040h
0041h Flash Memory Ready Interrupt Control
Register
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register
0048h
0049h
004Ah Timer RE Interrupt Control Register
004Bh UART2 Transmit Interrupt Control Register
004Ch UART2 Receive Interrupt Control Register
004Dh Key Input Interrupt Control Register
004Eh A/D Conversion Interrupt Control Register
004Fh SSU Interrupt Control Register / IIC bus
Interrupt Control Register
0050h
0051h UART0 Transmit Interrupt Control Register
0052h UART0 Receive Interrupt Control Register
0053h
0054h
0055h
0056h Timer RA Interrupt Control Register
0057h
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
98
41, 458
42, 458
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
42, 459
43, 99,
460
Voltage Detection 1 Level Select Register
VD1LS
44
Voltage Monitor 0 Circuit Control Register
Voltage Monitor 1 Circuit Control Register
Voltage Monitor 2 Circuit Control Register
VW0C
VW1C
VW2C
45
46, 461
47, 462
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
003Fh
Note:
1.
The blank regions are reserved. Do not access locations in these
regions.
B-1
Symbol
Page
FMRDYIC
127
TRCIC
127
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC/IICIC
126
126
126
126
126
127
S0TIC
S0RIC
126
126
TRAIC
126
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
126
128
128
INT0 Interrupt Control Register
UART2 Bus Collision Detection Interrupt
Control Register
INT0IC
U2BCNIC
128
126
Voltage Monitor 1/Compare A1 Interrupt
Control Register
Voltage Monitor 2/Compare A2 Interrupt
Control Register
VCMP1IC
126
VCMP2IC
126
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Note:
1.
Register
DTC Start Control Register
Symbol
DTCTL
Page
170
DTC Start Enable Register 0
DTC Start Enable Register 1
DTC Start Enable Register 2
DTC Start Enable Register 3
DTCEN0
DTCEN1
DTCEN2
DTCEN3
169
169
169
169
DTC Start Enable Register 5
DTC Start Enable Register 6
DTCEN5
DTCEN6
169
169
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
289
289
290
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
291
291
292
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
309
309
310
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
311
312
313
UART2 Digital Filter Function Select Register
URXDF
314
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
314
315
315
316
316
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
The blank regions are reserved. Do not access locations in these
regions.
B-2
A/D Register 0
Register
Symbol
AD0
Page
435
A/D Register 1
AD1
435
A/D Register 2
AD2
435
A/D Register 3
AD3
435
A/D Register 4
AD4
435
A/D Register 5
AD5
435
A/D Register 6
AD6
435
A/D Register 7
AD7
435
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
ADMOD
ADINSEL
ADCON0
ADCON1
436
437
438
439
Port P1 Register
P1
66
Port P1 Direction Register
PD1
65
Port P3 Register
P3
66
Port P3 Direction Register
Port P4 Register
PD3
P4
65
66
Port P4 Direction Register
PD4
65
Address
Register
0100h Timer RA Control Register
0101h Timer RA I/O Control Register
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
TRBMR
TRBPRE
TRBSC
TRBPR
Page
185
185, 188, 191,
193, 195, 198
186
186
187
419
420
420
202
202
203, 206, 210,
213, 217
203
204
204
205
0118h
Timer RE Second Data Register / Counter
Data Register
Timer RE Minute Data Register / Compare
Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
272, 280
TREMIN
272, 280
TREHR
TREWK
TRECR1
TRECR2
TRECSR
273
273
274, 281
275, 281
276, 282
Timer RC Mode Register
Timer RC Control Register 1
TRCMR
TRCCR1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
224
225, 246, 254,
260
225
226
227, 241, 247
227, 242, 248
228
Timer RC General Register A
TRCGRA
228
Timer RC General Register B
TRCGRB
228
Timer RC General Register C
TRCGRC
228
Timer RC General Register D
TRCGRD
228
Timer RC Control Register 2
Timer RC Digital Filter Function Select
Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
229, 254, 261
229, 261
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
Symbol
TRACR
TRAIOC
TRCOER
TRCADCR
230
230
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
013Dh
013Eh
013Fh
Note:
1.
The blank regions are reserved. Do not access locations in these
regions.
B-3
Register
Symbol
Page
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
Note:
1.
Register
Timer RA Pin Select Register
Timer RC Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
Page
67, 187
67, 231
68, 232
68, 232
UART0 Pin Select Register
U0SR
69, 293
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
U2SR0
U2SR1
SSUIICSR
INT Interrupt Input Pin Select Register
INTSR
71, 136
SS Bit Counter Register
SS Transmit Data Register L / IIC bus Transmit
Data Register
SS Transmit Data Register H
SS Receive Data Register L / IIC bus Receive
Data Register
SS Receive Data Register H
SSBR
SSTDR /
ICDRT
SSTDRH
SSRDR /
ICDRR
SSRDRH
356
356, 387
SS Control Register H / IIC bus Control
SSCRH /
Register 1
ICCR1
SS Control Register L / IIC bus Control Register 2 SSCRL /
ICCR2
SS Mode Register / IIC bus Mode Register
SSMR /
ICMR
SS Enable Register / IIC bus Interrupt Enable SSER /
Register
ICIER
SS Status Register / IIC bus Status Register
SSSR / ICSR
SS Mode Register 2 / Slave Address Register SSMR2 /
SAR
70, 317
70, 317
71, 355, 386
357, 387
357, 388
358, 389
359, 390
360, 391
361, 392
362, 393
Flash Memory Status Register
FST
483
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
485
487
489
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
The blank regions are reserved. Do not access locations in these
regions.
B-4
Register
Address Match Interrupt Register 0
Symbol
RMAD0
Page
142
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
142
142
Address Match Interrupt Enable Register 1
AIER1
142
Pull-Up Control Register 0
Pull-Up Control Register 1
PUR0
PUR1
72
72
Port P1 Drive Capacity Control Register
P1DRR
73
Drive Capacity Control Register 0
Drive Capacity Control Register 1
DRR0
DRR1
74
75
Input Threshold Control Register 0
Input Threshold Control Register 1
VLT0
VLT1
76
76
Comparator B Control Register 0
INTCMP
473
External Input Enable Register 0
INTEN
137, 473
INT Input Filter Select Register 0
INTF
137, 474
Key Input Enable Register 0
KIEN
140
Address
2C00h
2C01h
2C02h
2C03h
2C04h
2C05h
2C06h
2C07h
2C08h
2C09h
2C0Ah
:
:
2C3Ah
2C3Bh
2C3Ch
2C3Dh
2C3Eh
2C3Fh
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
Register
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
DTC Transfer Vector Area
Symbol
Page
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
Address
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
2C6Fh
Note:
1.
The blank regions are reserved. Do not access locations in these
regions.
B-5
Register
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
Page
Address
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
Note:
1.
Register
Symbol
Page
DTCD14
DTCD15
DTCD16
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
2D01h
FFDBh
Register
Symbol
Page
DTCD22
DTCD23
Option Function Select Register 2
OFS2
30, 154, 161
Option Function Select Register
OFS
29, 48, 153,
160, 481
:
FFFFh
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
The blank regions are reserved. Do not access locations in these
regions.
B-6
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/32A Group
REJ09B0458-0010
Rev.0.10
Apr 01, 2008
RENESAS MCU
1.
Overview
1.1
Features
The R8C/32A Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated
instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions
at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/32A Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ09B0458-0010 Rev.0.10
Page 1 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/32A Group.
Table 1.1
Item
CPU
Specifications for R8C/32A Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RE
REJ09B0458-0010 Rev.0.10
Page 2 of 572
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
500 ns (f(XIN) = 2 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/32A Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 15, selectable pull-up resistor
• High current drive ports: 15
4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz)
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator,
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Number of interrupt vectors: 69
• External Interrupt: 7 (INT × 3, Key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 21
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications for R8C/32A Group (2)
Function
UART0
UART2
Specification
Clock synchronous serial I/O/UART
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),
multiprocessor communication function
1 (shared with I2C-bus)
Synchronous Serial
Communication Unit (SSU)
I2C bus
LIN Module
A/D Converter
Comparator A
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 4 channels, includes sample and hold function, with sweep
mode
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input available
2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
f(XIN) = 2 MHz (VCC = 1.8 to 5.5 V)
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 10 MHz)
TBD (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
TBD (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
20-pin LSSOP
Package code: PLSP0020JB-A (previous code: 20P2F-A)
Note:
1. Specify the D version if D version functions are to be used.
REJ09B0458-0010 Rev.0.10
Page 3 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/32A Group, and Figure 1.1 shows a Part Number, Memory Size, and Package
of R8C/32A Group.
Table 1.3
Product List for R8C/32A Group
Part No.
R5F21321ANSP (D)
R5F21322ANSP (D)
R5F21324ANSP (D)
R5F21321ADSP (D)
R5F21322ADSP (D)
R5F21324ADSP (D)
ROM Capacity
Program ROM
Data flash
4 Kbytes
1 Kbyte × 4
8 Kbytes
1 Kbyte × 4
16 Kbytes
1 Kbyte × 4
4 Kbytes
1 Kbyte × 4
8 Kbytes
1 Kbyte × 4
16 Kbytes
1 Kbyte × 4
Current of Apr. 2008
RAM
Capacity
512 bytes
1 Kbyte
1.5 Kbytes
512 bytes
1 Kbyte
1.5 Kbytes
Package Type
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Remarks
N version
D version
(D): Under development
Part No.
R 5 F 21 32 4 A N FP
Package type:
FP: PLSP0020JB-A (0.65 mm pin-pitch)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
1: 4 KB
2: 8 KB
4: 16 KB
R8C/32A Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/32A Group
REJ09B0458-0010 Rev.0.10
Page 4 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
8
4
Port P1
Port P3
3
1
Port P4
Peripheral functions
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
UART or
clock synchronous serial I/O
(8 bits × 2)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
Watchdog timer
(15 bits)
A/D converter
(10 bits × 4 channels)
System clock generation
circuit
LIN module
Low-speed on-chip oscillator
for watchdog timer
Comparator B
Voltage detection circuit
Comparator A
DTC
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ROM (1)
USP
ISP
INTB
A0
A1
FB
Memory
RAM (2)
PC
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
REJ09B0458-0010 Rev.0.10
Page 5 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1.4
1. Overview
Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
20
P1_0/AN8/LVCMP1/KI0(/TRCIOD)
2
19
P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
RESET
3
18
P1_2/AN10/LVREF/Kl2(/TRCIOB)
P4_7/XOUT(/XCOUT)
4
VSS/AVSS
5
P4_6/XIN(/XCIN)
6
VCC/AVCC
7
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
8
P3_5/SCL/SSCK(/CLK2/TRCIOD)
9
10
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
R8C/32A Group
1
MODE
PLSP0020JB-A
(20P2F-A)
(top view)
P4_2/VREF
17
P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)
16
P1_4(/TXD0/TRCCLK)
15
P1_5(/INT1/RXD0/TRAIO)
14
P1_6/LVCOUT2/IVREF1(/CLK0)
13
P1_7/IVCMP1/INT1(/TRAIO)
12
P4_5/ADTRG/INT0(/RXD2/SCL2)
11
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ09B0458-0010 Rev.0.10
Page 6 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 1.4
1. Overview
Pin Name Information by Pin Number
I/O Pin Functions for Peripheral Modules
Pin
Number
Control Pin
1
2
3
MODE
4
5
6
7
8
Port
Interrupt
Timer
Serial
Interface
SSU
I2C
bus
P4_2
RESET
XOUT(/XCOUT)
VSS/AVSS
XIN(/XCIN)
VCC/AVCC
P4_7
P4_6
P3_7
TRAO
9
10
P3_5
P3_4
(TRCIOD)
(TRCIOC)
11
P3_3
INT3
12
P4_5
INT0
13
P1_7
14
15
P1_6
P1_5
16
17
INT1
(RXD2/SCL2/ SSO
TXD2/SDA2)
(CLK2)
SSCK
(RXD2/SCL2/
SSI
TXD2/SDA2)
(TRCCLK) (CTS2/RTS2)
(RXD2/SCL2)
(TRAIO)
(INT1)
(TRAIO)
P1_4
P1_3
KI3
18
P1_2
KI2
(TRCCLK)
TRBO
(/TRCIOC)
(TRCIOB)
19
P1_1
KI1
20
P1_0
KI0
(CLK0)
(RXD0)
Apr 01, 2008
SCS
SDA
SCL
IVREF3
IVCMP3
ADTRG
IVCMP1
LVCOUT2/IVREF1
(TXD0)
(TRCIOA/
TRCTRG)
(TRCIOD)
Note:
1. Can be assigned to the pin in parentheses by a program.
REJ09B0458-0010 Rev.0.10
Page 7 of 572
A/D Converter,
Comparator A,
Comparator B,
Voltage Detection Circuit
VREF
AN11/LVCOUT1
AN10/LVREF
AN9/LVCMP2
AN8/LVCMP1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1.5
1. Overview
Pin Functions
Tables 1.5 and 1.6 list Pin Functions.
Table 1.5
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input
VCC, VSS
−
Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
I/O (2)
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins (1). To use an external clock, input it
to the XOUT pin and leave the XIN pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0, INT1, INT3
I
INT interrupt input pins.
INT0 is timer RB, and RC input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
Serial interface
I2C bus
SSU
I/O
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins (1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RA I/O pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
CLK0, CLK2
I/O
Transfer clock I/O pins
RXD0, RXD2
I
Serial data input pins
TXD0, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
I: Input
O: Output
I/O: Input and output
Notes:
1. Refer to the oscillator manufacturer for oscillation characteristics.
2. To use an externally generated clock, input it to XOUT.
REJ09B0458-0010 Rev.0.10
Page 8 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
1. Overview
Table 1.6
Pin Functions (2)
Item
Pin Name
I/O Type
Description
Reference voltage input
VREF
I
Reference voltage input pin to A/D converter
A/D converter
AN8 to AN11
I
Analog input pins to A/D converter
ADTRG
I
AD external trigger input pin
LVCMP1, LVCMP2
I
Comparator A analog voltage input pins
LVREF
I
Comparator A reference voltage input pin
Comparator A
LVCOUT1, LVCOUT2
O
Comparator A output pins
Comparator B
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
IVREF1, IVREF3
I
Comparator B reference voltage input pins
Voltage detection circuit
LVCMP2
I
Detection voltage input pin for voltage detection 2
I/O port
P1_0 to P1_7,
P3_3 to P3_5, P3_7,
P4_5 to P4_7
Input port
P4_2
I: Input
O: Output
REJ09B0458-0010 Rev.0.10
Page 9 of 572
I/O: Input and output
Apr 01, 2008
I/O
I
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for
input or output individually.
Any port set to input can be set to use a pull-up resistor
or not by a program.
All ports can be used as LED drive ports.
Input-only port
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ09B0458-0010 Rev.0.10
Page 10 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ09B0458-0010 Rev.0.10
Page 11 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ09B0458-0010 Rev.0.10
Page 12 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
3.
3. Memory
Memory
3.1
R8C/32A Group
Figure 3.1 is a Memory Map of R8C/32A Group. The R8C/32A Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1.5-Kbyte internal
RAM area is allocated addresses 00400h to 009FFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0FFD8h
0XXXXh
02C00h
02FFFh
03000h
Reserved area
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
R5F21321ANFP, R5F21321ADFP
R5F21322ANFP, R5F21322ADFP
R5F21324ANFP, R5F21324ADFP
Figure 3.1
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
4 Kbytes
8 Kbytes
0F000h
0E000h
−
−
512 bytes
1 Kbyte
005FFh
007FFh
16 Kbytes
0C000h
−
1.5 Kbytes
009FFh
Memory Map of R8C/32A Group
REJ09B0458-0010 Rev.0.10
Page 13 of 572
Internal RAM
Size
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXX00XXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
00h
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit / Comparator A Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Software reset, watchdog timer reset, or oscillation
stop detection reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ09B0458-0010 Rev.0.10
Page 14 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
Register
003Ah
Voltage Monitor 2 Circuit Control Register
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Flash Memory Ready Interrupt Control Register
0042h
0043h
0044h
0045h
0046h
0047h
Timer RC Interrupt Control Register
0048h
0049h
004Ah
Timer RE Interrupt Control Register
004Bh
UART2 Transmit Interrupt Control Register
004Ch
UART2 Receive Interrupt Control Register
004Dh
Key Input Interrupt Control Register
004Eh
A/D Conversion Interrupt Control Register
004Fh
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
0050h
0051h
UART0 Transmit Interrupt Control Register
0052h
UART0 Receive Interrupt Control Register
0053h
0054h
0055h
0056h
Timer RA Interrupt Control Register
0057h
0058h
Timer RB Interrupt Control Register
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
005Eh
UART2 Bus Collision Detection Interrupt Control Register
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
Voltage Monitor 1 / Compare A1 Interrupt Control Register
0073h
Voltage Monitor 2 / Compare A2 Interrupt Control Register
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ09B0458-0010 Rev.0.10
Page 15 of 572
Apr 01, 2008
VW2C
Symbol
After Reset
10000010b
FMRDYIC
XXXXX000b
TRCIC
XXXXX000b
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC / IICIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
S0TIC
S0RIC
XXXXX000b
XXXXX000b
TRAIC
XXXXX000b
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
DTC Activation Control Register
Register
Symbol
DTCTL
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTCEN0
DTCEN1
DTCEN2
DTCEN3
00h
00h
00h
00h
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN5
DTCEN6
00h
00h
UART0 Transmit / Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit / Receive Control Register 0
UART0 Transmit / Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit / Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit / Receive Control Register 0
UART2 Transmit / Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 16 of 572
Apr 01, 2008
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
Register
00C0h
A/D Register 0
00C1h
00C2h
A/D Register 1
00C3h
00C4h
A/D Register 2
00C5h
00C6h
A/D Register 3
00C7h
00C8h
A/D Register 4
00C9h
00CAh
A/D Register 5
00CBh
00CCh
A/D Register 6
00CDh
00CEh
A/D Register 7
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Mode Register
00D5h
A/D Input Select Register
00D6h
A/D Control Register 0
00D7h
A/D Control Register 1
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
Port P1 Register
00E2h
00E3h
Port P1 Direction Register
00E4h
00E5h
Port P3 Register
00E6h
00E7h
Port P3 Direction Register
00E8h
Port P4 Register
00E9h
00EAh
Port P4 Direction Register
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 17 of 572
Apr 01, 2008
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
After Reset
XXXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
P1
XXh
PD1
00h
P3
XXh
PD3
P4
00h
XXh
PD4
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 18 of 572
Apr 01, 2008
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
Register
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 19 of 572
Apr 01, 2008
Symbol
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
Register
0180h
Timer RA Pin Select Register
0181h
Timer RC Pin Select Register
0182h
Timer RC Pin Select Register 0
0183h
Timer RC Pin Select Register 1
0184h
0185h
0186h
0187h
0188h
UART0 Pin Select Register
0189h
018Ah
UART2 Pin Select Register 0
018Bh
UART2 Pin Select Register 1
018Ch
SSU / IIC Pin Select Register
018Dh
018Eh
INT Interrupt Input Pin Select Register
018Fh
0190h
0191h
0192h
0193h
SS Bit Counter Register
0194h
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
0195h
SS Transmit Data Register H
0196h
SS Receive Data Register L / IIC bus Receive Data Register (2)
0197h
SS Receive Data Register H (2)
0198h
SS Control Register H / IIC bus Control Register 1 (2)
0199h
SS Control Register L / IIC bus Control Register 2 (2)
019Ah
SS Mode Register / IIC bus Mode Register (2)
019Bh
SS Enable Register / IIC bus Interrupt Enable Register (2)
019Ch
SS Status Register / IIC bus Status Register (2)
019Dh
SS Mode Register 2 / Slave Address Register (2)
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Flash Memory Status Register
01B3h
01B4h
Flash Memory Control Register 0
01B5h
Flash Memory Control Register 1
01B6h
Flash Memory Control Register 2
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ09B0458-0010 Rev.0.10
Page 20 of 572
Apr 01, 2008
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
After Reset
U0SR
00h
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
INTSR
00h
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FST
10000X00b
FMR0
FMR1
FMR2
00h
00h
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
Register
01C0h
Address Match Interrupt Register 0
01C1h
01C2h
01C3h
Address Match Interrupt Enable Register 0
01C4h
Address Match Interrupt Register 1
01C5h
01C6h
01C7h
Address Match Interrupt Enable Register 1
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
Pull-Up Control Register 0
01E1h
Pull-Up Control Register 1
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
Port P1 Drive Capacity Control Register
01F1h
01F2h
Drive Capacity Control Register 0
01F3h
Drive Capacity Control Register 1
01F4h
01F5h
Input Threshold Control Register 0
01F6h
Input Threshold Control Register 1
01F7h
01F8h
Comparator B Control Register 0
01F9h
01FAh
External Input Enable Register 0
01FBh
01FCh
INT Input Filter Select Register 0
01FDh
01FEh
Key Input Enable Register 0
01FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 21 of 572
Apr 01, 2008
Symbol
RMAD0
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
PUR0
PUR1
00h
00h
P1DRR
00h
DRR0
DRR1
00h
00h
VLT0
VLT1
00h
00h
INTCMP
00h
INTEN
00h
INTF
00h
KIEN
00h
AIER0
RMAD1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
Register
2C00h
DTC Transfer Vector Area
2C01h
DTC Transfer Vector Area
2C02h
DTC Transfer Vector Area
2C03h
DTC Transfer Vector Area
2C04h
DTC Transfer Vector Area
2C05h
DTC Transfer Vector Area
2C06h
DTC Transfer Vector Area
2C07h
DTC Transfer Vector Area
2C08h
DTC Transfer Vector Area
2C09h
DTC Transfer Vector Area
2C0Ah
DTC Transfer Vector Area
:
DTC Transfer Vector Area
:
DTC Transfer Vector Area
2C3Ah
DTC Transfer Vector Area
2C3Bh
DTC Transfer Vector Area
2C3Ch
DTC Transfer Vector Area
2C3Dh
DTC Transfer Vector Area
2C3Eh
DTC Transfer Vector Area
2C3Fh
DTC Transfer Vector Area
2C40h
DTC Control Data 0
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
DTC Control Data 1
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
DTC Control Data 2
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
DTC Control Data 3
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
DTC Control Data 4
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
DTC Control Data 5
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 22 of 572
Apr 01, 2008
Symbol
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
Register
2C70h
DTC Control Data 6
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
DTC Control Data 7
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
DTC Control Data 8
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
DTC Control Data 9
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
DTC Control Data 10
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
DTC Control Data 11
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
DTC Control Data 12
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
DTC Control Data 13
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 23 of 572
Apr 01, 2008
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
Register
2CB0h
DTC Control Data 14
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
DTC Control Data 15
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
DTC Control Data 16
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
DTC Control Data 17
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
DTC Control Data 18
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
DTC Control Data 19
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
DTC Control Data 20
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
DTC Control Data 21
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ09B0458-0010 Rev.0.10
Page 24 of 572
Apr 01, 2008
Symbol
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 4.12
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
4. Special Function Registers (SFRs)
SFR Information (12) (1)
DTC Control Data 22
Register
Symbol
DTCD22
DTC Control Data 23
DTCD23
FFDBh
Option Function Select Register 2
:
FFFFh
Option Function Select Register
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. This register cannot be changed by a program. Use a flash programmer to write to it.
REJ09B0458-0010 Rev.0.10
Page 25 of 572
Apr 01, 2008
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
OFS2
(Note 2)
OFS
(Note 2)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.
5. Resets
Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, watchdog timer reset,
and software reset.
Table 5.1 lists the Reset Names and Sources and Figure 5.1 shows the Block Diagram of Reset Circuit.
Table 5.1
Reset Names and Sources
Reset Name
Source
Hardware reset
Power-on reset
Voltage monitor 0 reset
Watchdog timer reset
Software reset
Input voltage of RESET pin is held “L”
VCC rises
VCC falls (monitor voltage: Vdet0)
Underflow of watchdog timer
Write 1 to PM03 bit in PM0 register
Hardware reset
RESET
VCC
Power-on reset
circuit
Voltage
detection
circuit
Watchdog
timer
Power-on reset
Voltage monitor 0 reset
Watchdog timer
reset
Pin, CPU, and SFR
CPU
Software reset
Note:
1. The CWR bit in the RSTFR register is set to 0 (cold start-up) after power-on or
voltage monitor 0 reset. This bit remains unchanged at a software reset,
watchdog timer reset, or oscillation detection reset.
Figure 5.1
Block Diagram of Reset Circuit
REJ09B0458-0010 Rev.0.10
Page 26 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5. Resets
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence.
Table 5.2
Pin Functions while RESET Pin Level is “L”
Pin Name
P1, P3_3 to P3_5, P3_7
P4_2, P4_5 to P4_7
Pin Function
Input port
Input port
b15
b0
0000h
Data register (R0)
0000h
Data register (R1)
0000h
Data register (R2)
0000h
0000h
0000h
0000h
Data register (R3)
b19
Address register (A0)
Address register (A1)
Frame base register (FB)
b0
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
b0
User stack pointer (USP)
0000h
Interrupt stack pointer (ISP)
0000h
Static base register (SB)
b0
Flag register (FLG)
0000h
b8
IPL
Figure 5.2
Program counter (PC)
0000h
b15
b15
Interrupt table register (INTB)
b0
b7
U I O B S Z D C
CPU Register Status after Reset
fOCO-S
RESET pin
10 cycles or more are needed (1)
fOCO-S clock × 8 cycles (2)
Internal reset
signal
Start time of flash memory
(CPU clock × 178 cycles)
CPU clock × 28 cycles
CPU clock
0FFFCh
0FFFEh
Address
(internal address
signal)
0FFFDh
Content of reset vector
Notes:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 8 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same time.
Figure 5.3
Reset Sequence
REJ09B0458-0010 Rev.0.10
Page 27 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.1
5. Resets
Registers
5.1.1
Processor Mode Register 0 (PM0)
Address 0004h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b6
—
0
b5
—
0
b4
—
0
Symbol
Bit Name
—
Reserved bits
—
—
PM03 Software reset bit
b4
b5
b6
b7
—
—
—
—
b3
PM03
0
b2
—
0
b1
—
0
b0
—
0
Function
R/W
R/W
Set to 0.
The MCU is reset when this bit is set to 1. When
read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
—
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM0 register.
5.1.2
Reset Source Determination Register (RSTFR)
Address 000Bh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b6
—
X
b5
—
X
b4
—
X
Symbol
Bit Name
CWR Cold start-up/warm start-up
determine flag (2, 3)
HWR Hardware reset detect flag
b3
WDR
0
b2
SWR
0
b1
HWR
X
b0
CWR
X
(Note 1)
R/W
R/W
Reserved bits
Function
0: Cold start-up
1: Warm start-up
0: Not detected
1: Detected
0: Not detected
1: Detected
0: Not detected
1: Detected
When read, the content is undefined.
Reserved bit
Set to 0.
R/W
b2
SWR
Software reset detect flag
b3
WDR
Watchdog timer reset detect flag
b4
b5
b6
b7
—
—
—
—
R
R
R
R
Notes:
1. The CWR bit is set to 0 (cold start-up) after power-on or voltage monitor 0 reset. This bit remains unchanged at a
software reset, or watchdog timer reset.
2. If 1 is written to the CWR bit by a program, it is set to 1. (Writing 0 does not affect this bit.)
3. When the VW0C0 bit in the VW0C register is set to 0 (voltage monitor 0 reset disabled), the CWR bit value is
undefined.
REJ09B0458-0010 Rev.0.10
Page 28 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.1.3
5. Resets
Option Function Select Register (OFS)
Address 0FFFFh
Bit
b7
Symbol CSPROINI
When shipping
1
b6
LVDAS
1
b5
b4
b3
b2
VDSEL1 VDSEL0 ROMCP1 ROMCR
1
1
1
1
Bit
b0
Symbol
Bit Name
WDTON Watchdog timer start select bit
b1
b2
—
Reserved bit
ROMCR ROM code protect disable bit
b3
ROMCP1 ROM code protect bit
b4
b5
VDSEL0 Voltage detection 0 level select bit (2)
VDSEL1
b6
b7
LVDAS
Voltage detection 0 circuit start bit (3)
CSPROINI Count source protection mode
after reset select bit
b1
—
1
b0
WDTON
1
(Note 1)
Function
0: Watchdog timer automatically starts after reset.
1: Watchdog timer is stopped after reset.
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
R/W
R/W
b5 b4
R/W
R/W
0 0: 3.80 V selected (Vdet0_3)
0 1: 2.85 V selected (Vdet0_2)
1 0: 2.35 V selected (Vdet0_1)
1 1: 1.90 V selected (Vdet0_0)
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
R/W
R/W
R/W
R/W
R/W
Notes:
1. If the block including the OFS register is erased, the OFS register value is set to FFh.
2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of
voltage monitor 0 reset and power-on reset.
3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset).
The OFS register is allocated in the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
LVDAS Bit (Voltage Detection 0 Circuit Start Bit)
The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
REJ09B0458-0010 Rev.0.10
Page 29 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.1.4
5. Resets
Option Function Select Register 2 (OFS2)
Address 0FFDBh
Bit
b7
Symbol
—
When shipping
1
b6
—
1
b5
—
1
b4
—
1
b3
b2
b1
b0
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
1
1
1
1
(Note 1)
Bit
b0
b1
Symbol
Bit Name
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
b2
b3
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1 set bit
b4
b5
b6
b7
—
—
—
—
Reserved bits
Function
b1 b0
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
b3 b2
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
Set to 1.
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh.
The OFS2 register is located on the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 14.3.1.1 Refresh Acknowledgment Period.
REJ09B0458-0010 Rev.0.10
Page 30 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.2
5. Resets
Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock with no division is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.4 shows an Example of Hardware Reset Circuit and Operation and Figure 5.5 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.2.1
When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs.
(3) Apply “H” to the RESET pin.
5.2.2
Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 32. Electrical
Characteristics).
(4) Wait for 10 µs.
(5) Apply “H” to the RESET pin.
REJ09B0458-0010 Rev.0.10
Page 31 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5. Resets
VCC
1.8 V
VCC
0V
RESET
RESET
0.2 VCC or below
0V
td(P-R) + 10 µs or more
Note:
1. Refer to 32. Electrical Characteristics.
Figure 5.4
Example of Hardware Reset Circuit and Operation
Supply voltage
detection circuit
RESET
5V
VCC
1.8 V
VCC
0V
5V
RESET
0V
td(P-R) + 10 µs or more
Example when
VCC = 5 V
Note:
1. Refer to 32. Electrical Characteristics.
Figure 5.5
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
REJ09B0458-0010 Rev.0.10
Page 32 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.3
5. Resets
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 8, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
After power-on reset, voltage monitor 0 reset is enabled when the LVDAS bit in the OFS register is set to 0
(voltage monitor 0 reset enabled after reset).
Figure 5.6 shows an Example of Power-On Reset Circuit and Operation.
VCC
4.7 kΩ
(reference)
RESET
Vdet0
trth
trth
Vccmin
Vpor1
External
Power VCC
tw(por1)
Internal
reset signal
(“L” valid)
1
×8
fOCO-S
1
×8
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
2. Refer to 32. Electrical Characteristics.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.6
Example of Power-On Reset Circuit and Operation
REJ09B0458-0010 Rev.0.10
Page 33 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.4
5. Resets
Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0. The Vdet0 voltage detection level can be changed by the
settings of bits VDSEL0 to VDSEL1 in the OFS register.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 8, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock with no
division is automatically selected as the CPU clock after reset.
The LVDAS bit in the OFS register can be used to select whether voltage monitor 0 reset is enabled or disabled
after a reset. The setting of the LVDAS bit is enabled at all resets.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to
0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to
1.
Bits VDSEL0 to VDSEL1 and LVDAS cannot be changed by a program. To set these bits, write values to b4 to b6
of address 0FFFFh using a flash programmer.
Refer to 5.1.3 Option Function Select Register (OFS) for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
Figure 5.7 shows an Example of Voltage Monitor 0 Reset Circuit and Operation.
VCC
4.7 kΩ
(reference)
RESET
tw(Vdet0)
VCC
Vdet0
Vccmin
Vpor1
Sampling time (1, 2)
Internal reset signal
(“L” valid)
1
×8
fOCO-S
Notes:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (1.8 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 32. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.7
Example of Voltage Monitor 0 Reset Circuit and Operation
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.5
5. Resets
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock with no division is automatically
selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after watchdog timer reset.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.
The underflow period and refresh acknowledge period for the watchdog timer can be set by bits WDTUFS0 to
WDTUFS1 and bits WDTRCS0 to WDTRCS1 in the OFS2 register, respectively.
Refer to 14. Watchdog Timer for details of the watchdog timer.
5.6
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock with no division is automatically selected for the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after software reset.
The internal RAM is not reset.
REJ09B0458-0010 Rev.0.10
Page 35 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
5.7
5. Resets
Cold Start-Up/Warm Start-Up Determination Function
The cold start-up/warm start-up determination function uses the CWR bit in the RSTFR register to determine cold
start-up (reset process) at power-on and warm start-up (reset process) when a reset occurred during operation.
The CWR bit is set to 0 (cold start-up) at power-on and also set to 0 at a voltage monitor 0 reset. If 1 is written to
the CWR bit by a program, it is set to 1. This bit remains unchanged at a software reset, or watchdog timer reset.
The cold start-up/warm stat-up determination function uses voltage monitor 0 reset.
To set the bits associated with voltage monitor 0 reset, follow Table 6.3 Procedure for Setting Bits Associated
with Voltage Monitor 0 Reset.
Figure 5.8 shows an Operating Example of Cold Start-Up/Warm Start-Up Function
5V
VCC
Vdet0
0V
Set to 1 by
a program.
Set to 1 by
a program.
CWR bit in RSTFR register
Voltage monitor 0 reset
The above applies when the digital filter is not used.
Figure 5.8
5.8
Operating Example of Cold Start-Up/Warm Start-Up Function
Reset Source Determination Function
The RSTFR register can be used to detect whether a hardware reset, software reset, or watchdog timer reset has
occurred.
If a hardware reset occurs, the HWR bit is set to 1 (detected). If a software reset occurs, the SWR bit is set to 1
(detected). If a watchdog timer reset occurs, the WDR bit is set to 1 (detected).
REJ09B0458-0010 Rev.0.10
Page 36 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.
6. Voltage Detection Circuit
Voltage Detection Circuit
The voltage detection circuit monitors the voltage input to the VCC pin. This circuit can be used to monitor the VCC
input voltage by a program.
6.1
Overview
The detection voltage of voltage detection 0 can be selected among four levels using the OFS register.
The detection voltage of voltage detection 1 can be selected among 16 levels using the VD1LS register.
As a detection target, the voltage input to VCC and the LVCMP2 pin can be switched for voltage detection 2 only.
The voltage monitor 0 reset, and voltage monitor 1 interrupt and voltage monitor 2 interrupt can also be used.
Note that voltage monitor 1 and voltage monitor 2 share the voltage detection circuit with comparator A1 and
comparator A2. Either voltage monitor 1 and voltage monitor 2 or comparator A1 and comparator A2 can be
selected.
Table 6.1
VCC
monitor
Process at
voltage
detection
Voltage Detection Circuit Specifications
Item
Voltage to
monitor
Detection
target
Voltage Monitor 0
Vdet0
Voltage Monitor 1
Vdet1
Voltage Monitor 2
Vdet2
Whether passing through
Vdet0 by falling
Whether passing through
Vdet1 by rising or falling
Detection
voltage
Selectable among
4 levels using the OFS
register.
Selectable among
16 levels using the VD1LS
register.
Monitor
None
The VW1C3 bit in
the VW1C register
Whether VCC is higher or
lower than Vdet1
Reset
Voltage monitor 0 reset
Reset at Vdet0 > VCC;
CPU operation restarts
at VCC > Vdet0
None
None
Whether passing through
Vdet2 by rising or falling
The input voltage to VCC
and the LVCMP2 pin can be
switched by the VCA24 bit
in the VCA2 register.
The detection voltage level
varies depending on when
VCC is selected or when
LVCMP2 is selected.
Each value is set as the
fixed level.
The VCA13 bit in
the VCA1 register
Whether VCC or LVCMP2
input voltage is higher or
lower than Vdet2
None
Voltage monitor 1 interrupt
Non-maskable or maskable
selectable
Interrupt request at:
Vdet1 > VCC
and/or
VCC > Vdet1
Supported
Voltage monitor 2 interrupt
Non-maskable or maskable
selectable
Interrupt request at:
Vdet2 > VCC (LVCMP2)
and/or
VCC (LVCMP2) > Vdet2
Supported
Interrupts
Digital filter
Switching
Supported
enable/disable
Sampling
(fOCO-S divided by n) × 4 (fOCO-S divided by n) × 2
time
n: 1, 2, 4, and 8
n: 1, 2, 4, and 8
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
(fOCO-S divided by n) × 2
n: 1, 2, 4, and 8
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6. Voltage Detection Circuit
Shared with comparator A
VCA27
VCA24 = 1
LVCMP2
Voltage detection 2 signal
+
VCA24 = 0
VCC
-
≥ Vdet2
VCA1 register
b3
VCA13 bit
VCA26
Level
Selection
Circuit
(16 levels)
Voltage detection 1 signal
+
-
≥ Vdet1
VW1C register
VD1S3 to VD1S0
b3
VW1C3 bit
VCA25
Level
Selection
Circuit
(4 levels)
Voltage detection 0 signal
+
Internal
reference
voltage
-
≥ Vdet0
VDSEL1 to VDSEL0
Figure 6.1
Table 6.2
Pin Name
LVCMP2
VCA13: Bit in VCA1 register
VCA24, VCA25, VCA26, VCA27: Bits in VCA2 register
VW1C3: Bit in VW1C register
VD1S0 to VD1S3: Bits in VD1LS register
VDSEL0, VDSEL1: Bits in OFS register
Voltage Detection Circuit Block Diagram
Pin Configuration of Voltage Detection Circuit
I/O
Function
Input
Detection target voltage pin for voltage detection 2
REJ09B0458-0010 Rev.0.10
Page 38 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6. Voltage Detection Circuit
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
= 10b
Voltage detection 0 circuit
1/2
fOCO-S
1/2
1/2
= 11b
VCA25
VW0C1
Level selection
VCC
+
Digital filter
VDSEL1
to VDSEL0
Internal reference voltage
Voltage
detection 0
signal
When VCA25 bit is set to 0 (disabled),
voltage detection 0 signal is driven high.
Voltage monitor 0
reset signal
VW0C1
VW0C0
VW0C0, VW0C1, VW0F0, VW0F1: Bits in VW0C register
VCA25: Bit in VCA2 register
VDSEL0, VDSEL1: Bits in OFS register
Figure 6.2
Block Diagram of Voltage Monitor 0 Reset Generation Circuit
Voltage monitor 1 interrupt generation circuit
VW1F1 to VW1F0
= 00b
= 01b
= 10b
Voltage detection 1 circuit
fOCO-S
1/2
1/2
1/2
= 11b
VW1C2 bit is set to 0 (not detected) by writing 0 by a program.
When VCA26 bit is set to 0 (voltage detection 1 circuit disabled),
VW1C2 bit is set to 0.
VCA26
VW1C3
VCC
Level
selection
VCA22 = 0
+
VCA21 = 0
-
VD1S3
to VD1S0
Watchdog timer
interrupt signal
VW1C1 = 0
Digital filter
Voltage
detection 1
signal
Edge
selection
circuit
VW1C1 = 1
Internal reference voltage
VW1C2
Voltage monitor 1
interrupt signal
When VCA26 bit is set to 0 (disabled),
voltage detection 1 signal is driven high.
VCA1C
VW1C7
VW1C0
Non-maskable
interrupt signal
Comparator A1
interrupt signal
COMPSEL
IRQ1SEL
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA21, VCA22, VCA26: Bits in VCA2 register
VD1S0 to VD1S3: Bits in VD1LS register
COMPSEL, IRQ1SEL: Bits in CMPA register
VCA1C: Bit in VCAC register
Figure 6.3
Block Diagram of Voltage Monitor 1 Interrupt Generation Circuit
REJ09B0458-0010 Rev.0.10
Page 39 of 572
Apr 01, 2008
Maskable
interrupt signal
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6. Voltage Detection Circuit
Voltage monitor 2 interrupt generation circuit
VW2F1 to VW2F0
= 00b
= 01b
Voltage detection 2 circuit
= 10b
1/2
fOCO-S
1/2
1/2
= 11b
VW2C2 bit is set to 0 (not detected) by writing 0 by a program.
When VCA27 bit is set to 0 (voltage detection 2 circuit disabled),
VW2C2 bit is set to 0.
VCA27
VCA24 = 1
LVCMP2
VCA13
VCC
VCA24 = 0
VCA23 = 0
-
Watchdog timer
interrupt signal
VW2C1 = 0
+
Digital filter
Voltage
detection 2
signal
Edge
selection
circuit
VW2C1 = 1
VW2C2
Internal reference voltage
Voltage monitor 2
interrupt signal
When VCA27 bit is set to 0 (disabled),
voltage detection 2 signal is driven high.
VCAC2
VW2C6
VW2C0
Non-maskable
interrupt signal
Comparator A2
interrupt signal
Watchdog timer block
VW2C3
Watchdog timer underflow signal
VW2C3 bit is set to 0 (not detected)
by writing 0 by a program.
COMPSEL
IRQ2SEL
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C
VCA13: Bit in VCA1 register
VCA23, VCA24, VCA27: Bits in VCA2 register
COMPSEL, IRQ2SEL: Bits in CMPA register
VCAC2: Bit in VCAC register
Figure 6.4
Block Diagram of Voltage Monitor 2 Interrupt Generation Circuit
REJ09B0458-0010 Rev.0.10
Page 40 of 572
Apr 01, 2008
Maskable
interrupt signal
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2
6. Voltage Detection Circuit
Registers
6.2.1
Voltage Monitor Circuit/Comparator A Control Register (CMPA)
Address 0030h
Bit
b7
Symbol COMPSEL
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
CM1POR
b6
—
0
b5
IRQ2SEL
0
Bit Name
LVCOUT1 output polarity
select bit
b4
IRQ1SEL
0
b3
CM2OE
0
b2
CM1OE
0
b1
CM2POR
0
b0
CM1POR
0
Function
0: Non-inverted comparator A1 comparison result is
output to LVCOUT1.
1: Inverted comparator A1 comparison result is
output to LVCOUT1.
CM2POR LVCOUT2 output polarity
0: Non-inverted Comparator A2 comparison result is
select bit
output to LVCOUT2.
1: Inverted comparator A2 comparison result is
output to LVCOUT2.
CM1OE LVCOUT1 output enable bit
0: Output disabled
1: Output enabled
CM2OE LVCOUT2 output enable bit
0: Output disabled
1: Output enabled
IRQ1SEL Voltage monitor 1/comparator A1 0: Non-maskable interrupt
interrupt type select bit
1: Maskable interrupt
IRQ2SEL Voltage monitor 2/comparator A2 0: Non-maskable interrupt
interrupt type select bit
1: Maskable interrupt
—
Reserved bit
Set to 0.
COMPSEL Voltage monitor/comparator A
0: Bits IRQ1SEL and IRQ2SEL disabled
interrupt type selection enable bit 1: Bits IRQ1SEL and IRQ2SEL enabled
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.2
Voltage Monitor Circuit Edge Select Register (VCAC)
Address 0031h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
6. Voltage Detection Circuit
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
VCAC2
0
b1
VCAC1
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
VCAC1 Voltage monitor 1 circuit edge select bit (1) 0: One edge
1: Both edges
VCAC2 Voltage monitor 2 circuit edge select bit (2) 0: One edge
1: Both edges
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
—
R/W
—
R/W
R/W
—
Notes:
1. When the VCA1 bit is set tot 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit
after setting the VCAC1 bit to 0.
2. When the VCA2 bit is set tot 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit
after setting the VCAC2 bit to 0.
6.2.3
Voltage Detect Register (VCA1)
Address 0033h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
VCA13
1
b2
—
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Reserved bits
Set to 0.
—
—
VCA13 Voltage detection 2 signal monitor flag (1) 0: VCC < Vdet2
1: VCC ≥ Vdet2
or voltage detection 2 circuit disabled
—
Reserved bits
Set to 0.
—
—
—
R/W
R/W
R
R/W
Note:
1. When the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled), the VCA13 bit is
enabled.
When the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled), the VCA13 bit is set to
1 (VCC ≥ Vdet2).
REJ09B0458-0010 Rev.0.10
Page 42 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.4
6. Voltage Detection Circuit
Voltage Detect Register 2 (VCA2)
Address 0034h
Bit
b7
b6
b5
b4
b3
Symbol VCA27
VCA26
VCA25
VCA24
VCA23
After Reset The LVDAS bit in the OFS register is set to 1.
0
0
0
0
0
After Reset The LVDAS bit in the OFS register is set to 0.
0
0
1
0
0
Bit
b0
b5
Symbol
Bit Name
VCA20 Internal power low consumption
enable bit (1)
VCA21 Comparator A1 reference voltage
input select bit
VCA22 LVCMP1 comparison voltage
external input select bit
VCA23 Comparator A2 reference voltage
input select bit
VCA24 LVCMP2 comparison voltage
external input select bit
VCA25 Voltage detection 0 enable bit (3)
b6
VCA26
b7
VCA27
b1
b2
b3
b4
Voltage detection 1/comparator A1
enable bit (4)
Voltage detection 2/comparator A2
enable bit (5)
b2
VCA22
b1
VCA21
b0
VCA20
0
0
0
0
0
0
Function
0: Low consumption disabled
1: Low consumption enabled (2)
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
1: LVCMP1 pin input voltage
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
(Vdet2_0)
1: LVCMP2 pin input voltage (Vdet2_EXT)
0: Voltage detection 0 circuit disabled
1: Voltage detection 0 circuit enabled
0: Voltage detection 1/comparator A1 circuit disabled
1: Voltage detection 1/comparator A1 circuit enabled
0: Voltage detection 2/comparator A2 circuit disabled
1: Voltage detection 2/comparator A2 circuit enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in
Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit.
2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
3. To use voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation.
4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit
to 1.
After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit
starts operation.
5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27
bit to 1.
After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit
starts operation.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register.
REJ09B0458-0010 Rev.0.10
Page 43 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.5
6. Voltage Detection Circuit
Voltage Detection 1 Level Select Register (VD1LS)
Address 0036h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
VD1S3
0
Symbol
Bit Name
VD1S0 Voltage detection 1 level select bit
VD1S1 (Reference voltage when the voltage falls)
VD1S2
VD1S3
—
—
—
—
Reserved bits
b2
VD1S2
1
b1
VD1S1
1
b0
VD1S0
1
Function
b3 b2 b1 b0
0 0 0 0: 2.20 V
0 0 0 1: 2.35 V
0 0 1 0: 2.50 V
0 0 1 1: 2.65 V
0 1 0 0: 2.80 V
0 1 0 1: 2.95 V
0 1 1 0: 3.10 V
0 1 1 1: 3.25 V
1 0 0 0: 3.40 V
1 0 0 1: 3.55 V
1 0 1 0: 3.70 V
1 0 1 1: 3.85 V
1 1 0 0: 4.00 V
1 1 0 1: 4.15 V
1 1 1 0: 4.30 V
1 1 1 1: 4.45 V
Set to 0.
(Vdet1_0)
(Vdet1_1)
(Vdet1_2)
(Vdet1_3)
(Vdet1_4)
(Vdet1_5)
(Vdet1_6)
(Vdet1_7)
(Vdet1_8)
(Vdet1_9)
(Vdet1_A)
(Vdet1_B)
(Vdet1_C)
(Vdet1_D)
(Vdet1_E)
(Vdet1_F)
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VD1LS register.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.6
6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register (VW0C)
Address 0038h
Bit
b7
b6
b5
b4
Symbol
—
—
VW0F1 VW0F0
After Reset The LVDAS bit in the OFS register is set to 1.
1
1
0
0
After Reset The LVDAS bit in the OFS register is set to 0.
1
1
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b3
—
b2
—
b1
VW0C1
b0
VW0C0
X
0
1
0
X
0
1
1
Symbol
Bit Name
VW0C0 Voltage monitor 0 reset enable bit (1)
Function
0: Disabled
1: Enabled
VW0C1 Voltage monitor 0 digital filter disabled mode 0: Digital filter enabled mode
select bit
(digital filter circuit enabled)
1: Digital filter disabled mode
(digital filter circuit disabled)
—
Reserved bit
Set to 0.
—
Reserved bit
When read, the content is undefined.
b5 b4
VW0F0 Sampling clock select bit
0 0: fOCO-S divided by 1
VW0F1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
—
Reserved bits
Set to 1.
—
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Note:
1. The VW0C0 bit is enabled when the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disabled) when the VCA25 bit in the VCA2 register is set to 0 (voltage
detection 0 circuit disabled). To set the VW0C0 bit to 1 (enabled), follow the procedure in Table 6.3 Procedure
for Setting Bits Associated with Voltage Monitor 0 Reset.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW0C register.
REJ09B0458-0010 Rev.0.10
Page 45 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.7
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register (VW1C)
Address 0039h
Bit
b7
Symbol VW1C7
After Reset
1
b6
—
0
b5
VW1F1
0
b4
VW1F0
0
b3
VW1C3
1
b2
VW1C2
0
b1
VW1C1
1
b0
VW1C0
0
Bit
b0
Symbol
Bit Name
VW1C0 Voltage monitor 1 reset enable bit (1)
Function
0: Disabled
1: Enabled
Voltage monitor 0 digital filter
0: Digital filter enabled mode
(digital filter circuit enabled)
disable mode select bit (2)
1: Digital filter disable mode
(digital filter circuit disabled)
0: Not detected
Voltage change detection flag (3, 4)
1: Vdet1 passing detected
Voltage detection 1 signal monitor flag (3) 0: VCC < Vdet1
1: VCC ≥ Vdet1
or voltage detection 1 circuit disabled
b5 b4
Sampling clock select bit
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
Reserved bit
Set to 1.
Voltage monitor 1 reset
0: When VCC reaches Vdet1 or above.
1: When VCC reaches Vdet1 or below.
generation condition select bit (5)
R/W
R/W
b1
VW1C1
R/W
b2
VW1C2
b3
VW1C3
b4
b5
VW1F0
VW1F1
b6
b7
—
VW1C7
R/W
R
R/W
R/W
R/W
R/W
Notes:
1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
To set the VW0C0 bit to 1 (enabled), follow the procedure shown in Table 6.4 Procedure for Setting Bits
Associated with Voltage Monitor 1 Interrupt.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit.
3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1(voltage detection 1
circuit enabled).
4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged
even if 1 is written to it).
5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC1 bit to 0, set the VW1C7 bit.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before writing the VW1C register.
Rewriting the VW1C register may set the VW1C2 bit to 1. Set the VW1C2 bit to 0 after rewriting the VW1C
register.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.8
Voltage Monitor 2 Circuit Control Register (VW2C)
Address 003Ah
Bit
b7
Symbol VW2C7
After Reset
1
Bit
b0
b1
b2
b3
b4
b5
b6
b7
6. Voltage Detection Circuit
b6
—
0
b5
VW2F1
0
b4
VW2F0
0
b3
VW2C3
0
b2
VW2C2
0
b1
VW2C1
1
b0
VW2C0
0
Symbol
Bit Name
Function
VW2C0 Voltage monitor 2 interrupt enable bit (1) 0: Disabled
1: Enabled
VW2C1 Voltage monitor 2 digital filter
0: Digital filter enable mode
(digital filter circuit enabled)
disable mode select bit (2)
1: Digital filter disable mode
(digital filter circuit disabled)
VW2C2 Voltage change detection flag (3, 4)
0: Not detected
1: Vdet2 passing detected
VW2C3 WDT detection monitor flag (4)
0: Not detected
1: Detected
b5 b4
VW2F0 Sampling clock select bit
0 0: fOCO-S divided by 1
VW2F1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
—
Reserved bit
Set to 0.
VW2C7 Voltage monitor 2 interrupt
0: When VCC or LVCMP2 reaches Vdet2
or above.
generation condition select bit (5)
1: When VCC or LVCMP2 reaches Vdet2
or below.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
To set the VW2C0 bit to 1 (enabled), follow the procedure shown in Table 6.5 Procedure for Setting Bits
Associated with Voltage Monitor 2 Interrupt.
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit.
3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if
1 is written to it).
5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC2 bit to 0, set the VW2C7 bit.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register.
Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0.
REJ09B0458-0010 Rev.0.10
Page 47 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.2.9
6. Voltage Detection Circuit
Option Function Select Register (OFS)
Address 0FFFFh
Bit
b7
Symbol CSPROINI
When shipping
1
b6
LVDAS
1
b5
b4
b3
b2
VDSEL1 VDSEL0 ROMCP1 ROMCR
1
1
1
1
Bit
b0
Symbol
Bit Name
WDTON Watchdog timer start select bit
b1
b2
—
Reserved bit
ROMCR ROM code protect disable bit
b3
ROMCP1 ROM code protect bit
b4
b5
VDSEL0 Voltage detection 0 level select bit (2)
VDSEL1
b6
b7
LVDAS
Voltage detection 0 circuit start bit (3)
CSPROINI Count source protection mode
after reset select bit
b1
—
1
b0
WDTON
1
(Note 1)
Function
0: Watchdog timer automatically starts after reset.
1: Watchdog timer is stopped after reset.
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
R/W
R/W
b5 b4
R/W
R/W
0 0: 3.80 V selected (Vdet0_3)
0 1: 2.85 V selected (Vdet0_2)
1 0: 2.35 V selected (Vdet0_1)
1 1: 1.90 V selected (Vdet0_0)
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
R/W
R/W
R/W
R/W
R/W
Notes:
1. If the block including the OFS register is erased, the OFS register value is set to FFh.
2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of
voltage monitor 0 reset and power-on reset.
3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset).
The OFS register is allocated in the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
LVDAS Bit (Voltage Detection 0 Circuit Start Bit)
The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
REJ09B0458-0010 Rev.0.10
Page 48 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.3
6. Voltage Detection Circuit
VCC Input Voltage
6.3.1
Monitoring Vdet0
Vdet0 cannot be monitored.
6.3.2
Monitoring Vdet1
Once the following settings are made, the comparison result of voltage monitor 1 can be monitored by the
VW1C3 bit in the VW1C register after td(E-A) has elapsed (refer to 32. Electrical Characteristics).
(1) Set bits VD1S3 to VD1S0 in the VD1LS register (voltage detection 1 detection voltage).
(2) Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage).
(3) Set the VCA22 bit in the VCA2 register to 0 (VCC voltage).
(4) Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).
6.3.3
Monitoring Vdet2
Once the following settings are made, the comparison result of voltage monitor 2 can be monitored by the
VCA13 bit in the VCA1 register after td(E-A) has elapsed (refer to 32. Electrical Characteristics).
(1) Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage).
(2) Set the VCA24 bit in the VCA2 register to 0 (VCC voltage), or 1 (LVCMP2 pin input voltage).
(3) Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.4
6. Voltage Detection Circuit
Voltage Monitor 0 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 0 Reset and Figure 6.5 shows an
Operating Example of Voltage Monitor 0 Reset.
To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter
disabled).
Table 6.3
Step
1
2
Procedure for Setting Bits Associated with Voltage Monitor 0 Reset
When Using Digital Filter
When Using No Digital Filter
Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled).
Wait for td(E-A).
Select the sampling clock of the digital filter by Set the VW0C7 bit in the VW0C register to 1.
bits VW0F0 and VW0F1 in the VW0C register.
Set the VW0C1 bit in the VW0C register to 0
Set the VW0C1 bit in the VW0C register to 1
(digital filter enabled).
(digital filter disabled).
Set the VW0C2 bit in the VW0C register to 0.
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on).
Wait for 4 cycles of the sampling clock of
− (No wait time required)
the digital filter.
Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled).
3
4 (1)
5
6
7
8
Note:
1. When the VW0C0 bit is set to 0, steps 3 and 4 can be executed simultaneously (with one instruction).
VCC
Vdet0
Sampling clock of
digital filter × 4 cycles
VW0C1 bit is set to 0
(digital filter enabled)
1
× 32
fOCO-S
Internal reset signal
1
× 32
fOCO-S
VW0C1 bit is set to 1
(digital filter disabled)
Internal reset signal
VW0C1 and VW0C7: Bits in VW0C register
The above applies when:
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
When the internal reset signal is driven low, the pins, CPU, and SFRs are initialized.
When the internal reset signal level changes from low to high,
a program is executed beginning with the address indicated by the reset vector.
Refer to 4. Special Function Registers (SFRs) for the states of the SFRs after reset.
Figure 6.5
Operating Example of Voltage Monitor 0 Reset
REJ09B0458-0010 Rev.0.10
Page 50 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.5
6. Voltage Detection Circuit
Voltage Monitor 1 Interrupt
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt. Figure 6.6 shows an
Operating Example of Voltage Monitor 1 Interrupt.
To use the voltage monitor 1 interrupt to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter
disabled).
Table 6.4
Step
1
2
3 (1)
4 (1)
5
6
7 (2)
8
9 (3)
10
11
12
13
14
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt
When Using Digital Filter
When Using No Digital Filter
Select the voltage detection 1 detection voltage by bits VD1S3 to VD1S0 in the VD1LS register.
Set the VCA21 bit in the VCA2 register to 0 (internal reference voltage).
Set the VCA22 bit in the VCA2 register to 0 (VCC voltage).
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled).
Wait for td(E-A).
Set the COMPSEL bit in the CMPA register to 1.
Select the interrupt type by the IRQ1SEL in the CMPA register.
Select the sampling clock of the digital filter by Set the VW1C1 bit in the VW1C register to 1
bits VW1F0 and VW1F1 in the VW1C register. (digital filter disabled).
Set the VW1C1 bit in the VW1C register to 0 −
(digital filter enabled).
Select the interrupt request timing by the VCAC1 bit in the VCAC register and
the VW1C7 bit in the VW1C register.
Set the VW1C2 bit in the VW1C register to 0.
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on)
Wait for 2 cycles of the sampling clock of
− (No wait time required)
the digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt enabled)
Notes:
1. When the VW1C0 bit is set to 0, steps 2, 3 and 4 can be executed simultaneously (with one instruction).
2. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed simultaneously (with one instruction).
3. When the VW1C0 bit is set to 0, steps 8 and 9 can be executed simultaneously (with one instruction).
REJ09B0458-0010 Rev.0.10
Page 51 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6. Voltage Detection Circuit
VCC
Vdet1
1.8 V (1)
1
VW1C3 bit
0
Sampling clock of
digital filter × 2 cycles
Sampling clock of
digital filter × 2 cycles
1
VW1C2 bit
VW1C1 bit is set to 0
(digital filter enabled)
and
VCAC1 bit is set to 1
(both edges)
0
Set to 0 by a program.
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 1
interrupt request
VW1C1 bit is set to 0
(digital filter enabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 0
(when VCC reaches Vdet1
or above)
VW1C1 bit is set to 0
(digital filter enabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 1
(when VCC reaches Vdet1
or below)
Set to 0 by a program.
1
VW1C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 1
interrupt request
Set to 0 by a program.
1
VW1C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 1
interrupt request
Set to 0 by a program.
1
VW1C2 bit
VW1C1 bit is set to 1
(digital filter disabled)
and
VCAC1 bit is set to 1
(both edges)
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 1
interrupt request
Set to 0 by a program.
VW1C1 bit is set to 1
(digital filter disabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 0
(when VCC reaches Vdet1
or above)
VW1C1 bit is set to 1
(digital filter disabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 1
(when VCC reaches Vdet1
or below)
1
VW1C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 1
interrupt request
Set to 0 by a program.
1
VW1C2 bit
0
Voltage monitor 1
interrupt request
Set to 0 when an interrupt request
is acknowledged.
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
The above applies when:
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt enabled)
Note:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.
Figure 6.6
Operating Example of Voltage Monitor 1 Interrupt
REJ09B0458-0010 Rev.0.10
Page 52 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6.6
6. Voltage Detection Circuit
Voltage Monitor 2 Interrupt
Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt. Figure 6.7 shows an
Operating Example of Voltage Monitor 2 Interrupt.
To use the voltage monitor 2 interrupt to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter
disabled).
Table 6.5
Step
1
2 (1)
3 (1)
4
5
6 (2)
7
8 (3)
9
10
11
12
13
Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt
When Using Digital Filter
When Using No Digital Filter
Set the VCA23 bit in the VCA2 register to 0 (internal reference voltage).
Set the VCA24 bit in the VCA2 register to 0 (VCC voltage) or 1 (LCVCMP2 pin input voltage).
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled).
Wait for td(E-A).
Set the COMPSEL bit in the CMPA register to 1.
Select the interrupt type by the IRQ2SEL in the CMPA register.
Select the sampling clock of the digital filter by Set the VW2C1 bit in the VW2C register to 1
bits VW2F0 and VW2F1 in the VW2C register. (digital filter disabled).
Set the VW2C1 bit in the VW2C register to 0 −
(digital filter enabled).
Select the interrupt request timing by the VCAC2 bit in the VCAC register and
the VW2C7 bit in the VW2C register.
Set the VW2C2 bit in the VW2C register to 0.
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on).
Wait for 2 cycles of the sampling clock of
− (No wait time required)
the digital filter.
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt enabled).
Notes:
1. When the VW2C0 bit is set to 0, steps 1, 2 and 3 can be executed simultaneously (with one instruction).
2. When the VW2C0 bit is set to 0, steps 5 and 6 can be executed simultaneously (with one instruction).
3. When the VW2C0 bit is set to 0, steps 7 and 8 can be executed simultaneously (with one instruction).
REJ09B0458-0010 Rev.0.10
Page 53 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
6. Voltage Detection Circuit
VCC or LVCMP2
Vdet2
1.8 V (1)
1
VW1C3 bit
0
Sampling clock of
digital filter × 2 cycles
Sampling clock of
digital filter × 2 cycles
1
VW2C1 bit is set to 0
(digital filter enabled)
and
VCAC2 bit is set to 1
(both edges)
VW2C2 bit
0
Set to 0 by a program.
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 2
interrupt request
VW2C1 bit is set to 0
(digital filter enabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 0
(when VCC or LVCMP2
reaches Vdet2 or above)
VW2C1 bit is set to 0
(digital filter enabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 1
(when VCC or LVCMP2
reaches Vdet2 or below)
Set to 0 by a program.
1
VW2C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 2
interrupt request
Set to 0 by a program.
1
VW2C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 2
interrupt request
Set to 0 by a program.
1
VW2C1 bit is set to 1
(digital filter disabled)
and
VCAC2 bit is set to 1
(both edges)
VW2C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 2
interrupt request
Set to 0 by a program.
VW2C1 bit is set to 1
(digital filter disabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 0
(when VCC or LVCMP2
reaches Vdet2 or above)
VW2C1 bit is set to 1
(digital filter disabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 1
(when VCC or LVCMP2
reaches Vdet2 or below)
1
VW2C2 bit
0
Set to 0 when an interrupt request
is acknowledged.
Voltage monitor 2
interrupt request
Set to 0 by a program.
1
VW2C2 bit
0
Voltage monitor 2
interrupt request
Set to 0 when an interrupt request
is acknowledged.
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C3, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
The above applies when:
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt enabled)
Note:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 1.8 V.
Figure 6.7
Operating Example of Voltage Monitor 2 Interrupt
REJ09B0458-0010 Rev.0.10
Page 54 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.
7. I/O Ports
I/O Ports
There are 15 I/O ports P1, P3_3 to P3_5, P3_7, and P4_5 to P4_7 (P4_6 and P4_7 can be used as I/O ports if the XIN
clock oscillation circuit and the XCIN clock oscillation circuit are not used.).
If the A/D converter is not used, P4_2 can be used as an input-only port.
Table 7.1 lists an Overview of I/O Ports.
Table 7.1
Ports
Overview of I/O Ports
I/O Type of Output
I/O Setting
Internal Pull-Up
Resister
Drive Capacity
Switch
Input Level Switch
P1
I/O CMOS3 state
P3_3
I/O CMOS3 state
P3_4, P3_5,
P3_7
I/O CMOS3 state
Set in 1-bit units Set in 4-bit units (1) Set in 1-bit units (2) Set in 8-bit units (4)
Set in 1-bit units Set in 1-bit units (1) Set in 1-bit units (3) Set in 4-bit units (4)
Set in 1-bit units Set in 3-bit units (1) Set in 3-bit units (3)
P4_5, P4_6 (5),
P4_7 (5)
I/O CMOS3 state
Set in 1-bit units Set in 3-bit units (1) Set in 3-bit units (3) Set in 4-bit units (4)
P4_2 (6)
I
(No output
function)
None
None
None
Notes:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0 and
PUR1.
2. Whether the drive capacity of the output transistor is set to low or high can be selected using the P1DRR
register.
3. Whether the drive capacity of the output transistor is set to low or high can be selected using registers DRR0
and DRR1.
4. The input threshold value can be selected among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC)
using registers VLT0 and VLT1.
5. When the XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used, these ports can be
used as I/O ports.
6. When the A/D converter is not used, this port can be used as an input-only ports.
7.1
Functions of I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 1, 3, 4) register controls I/O of the ports P1, P3_3 to P3_5, P3_7, and P4_5
to P4_7. The Pi register consists of a port latch to hold output data and a circuit to read pin states.
Figures 7.1 to 7.7 show the Configurations of I/O Ports. Table 7.2 lists the Functions of I/O Ports.
Table 7.2
Functions of I/O Ports
Operation When
Value of PDi_j Bit in PDi Register (1)
Accessing
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Pi Register
Read
Read the pin input level.
Read the port latch.
Write to the port latch. The value written to
Write
Write to the port latch.
the port latch is output from the pin.
i = 1, 3, 4, j = 0 to 7
Note:
1. Nothing is assigned to bits PD4_0 to PD4_2.
Also, bits PD3_0 to PD3_2, PD3_6, PD4_3, and PD4_4 are reserved bits.
REJ09B0458-0010 Rev.0.10
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.2
7. I/O Ports
Effect on Peripheral Functions
I/O ports function as I/O ports for peripheral functions (Refer to Table 1.4 Pin Name Information by Pin
Number).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, j = 0 to
7).
Refer to the description of each function for information on how to set peripheral functions.
Table 7.3
Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions
(i = 1, 3, 4, j = 0 to 7)
I/O of Peripheral Function
PDi_j Bit Settings for Shared Pin Function
Input
Set this bit to 0 (input mode).
Output
This bit can be set to either 0 or 1 (output regardless of the port setting).
7.3
Pins Other than I/O Ports
Figure 7.8 shows the Configuration of I/O Pins.
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P1_0 to P1_2
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Port latch
Data bus
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Analog input of A/D converter
Analog input of comparator A
Drive capacity selection
P1_3
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Port latch
Data bus
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Analog input of A/D converter
Drive capacity selection
Note:
1.
Figure 7.1
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Ports (1)
REJ09B0458-0010 Rev.0.10
Page 57 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P1_4
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Drive capacity selection
P1_5
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual
peripheral function
Input to external interrupt
Digital
filter
Drive capacity selection
Note:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.2
Configuration of I/O Ports (2)
REJ09B0458-0010 Rev.0.10
Page 58 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P1_6
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Analog input of comparator B
Drive capacity selection
P1_7
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual
peripheral function
Analog input of
comparator B
Input to external interrupt
Note:
1.
Figure 7.3
Digital
filter
Drive capacity selection
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Ports (3)
REJ09B0458-0010 Rev.0.10
Page 59 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P3_3
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Port latch
Data bus
(Note 1)
Input level
switch function
Pin select register
Input to individual
peripheral function
Analog input of
comparator B
Input to external interrupt
Digital
filter
P3_4
Drive capacity selection
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Analog input of comparator B
Drive capacity selection
Note:
1.
Figure 7.4
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Ports (4)
REJ09B0458-0010 Rev.0.10
Page 60 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P3_5
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual peripheral function
Drive capacity selection
P3_7
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Data bus
Port latch
(Note 1)
Input level
switch function
Pin select register
Input to individual
peripheral function
Drive capacity selection
Note:
1.
Figure 7.5
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Ports (5)
REJ09B0458-0010 Rev.0.10
Page 61 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P4_2/VREF
(Note 1)
Input level
switch function
Data bus
(Note 1)
P4_5
Drive capacity selection
Pull-up selection
Direction
register
Pin select
register
1
(Note 1)
Output from individual
peripheral function
Port latch
Data bus
(Note 1)
Input level
switch function
Pin select register
Input to individual
peripheral function
Input to external interrupt
A/D trigger input
Digital
filter
Drive capacity selection
Note:
1.
Figure 7.6
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Ports (6)
REJ09B0458-0010 Rev.0.10
Page 62 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
P4_6/XIN/XCIN
Drive capacity selection
Pull-up selection
Direction
register
(Note 1)
Port latch
Data bus
(Note 1)
CM01
Input level
switch function
CM13
0
1
CM04, CM13
Drive capacity selection
CM11
XIN
oscillation
circuit
P4_7/XOUT/XCOUT
CM12
XCIN
oscillation
circuit
CM03
CM05
RfXIN
RfXCIN
Drive capacity selection
Pull-up selection
0
Direction
register
1
CM01
(Note 1)
Port latch
Data bus
(Note 1)
Input level
switch function
Drive capacity selection
Note:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
CM01, CM03, CM04, CM05: Bits in CM0 register
CM11, CM12, CM13: Bits in CM1 register
Figure 7.7
Configuration of I/O Ports (7)
REJ09B0458-0010 Rev.0.10
Page 63 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
MODE
MODE signal input
(Note 1)
RESET
(Note 1)
RESET signal input
(Note 1)
Note:
1.
Figure 7.8
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Configuration of I/O Pins
REJ09B0458-0010 Rev.0.10
Page 64 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4
7. I/O Ports
Registers
7.4.1
Port Pi Direction Register (PDi) (i = 1, 3, 4)
Address 00E3h (PD1), 00E7h (PD3 (1)), 00EAh (PD4 (2))
Bit
Symbol
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b7
PDi_7
0
Symbol
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
b6
PDi_6
0
b5
PDi_5
0
Bit Name
Port Pi_0 direction bit
Port Pi_1 direction bit
Port Pi_2 direction bit
Port Pi_3 direction bit
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit
Port Pi_7 direction bit
b4
PDi_4
0
b3
PDi_3
0
b2
PDi_2
0
b1
PDi_1
0
b0
PDi_0
0
Function
0: Input mode (functions as an input port)
1: Output mode (functions as an output port)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are reserved bits. If it is necessary to set bits PD3_0 to
PD3_2 and PD3_6, set to 0. When read, the content is 0.
2. Bits PD4_0 to PD4_2 in the PD4 register are unavailable on this MCU. If it is necessary to set bits PD4_0 to
PD4_2 set to 0. When read, the content is 0. Bits PD4_3, PD4_4 are reserved bits. If it is necessary to set bits
PD4_3 and PD4_4, set to 0. When read, the content is 0.
The PDi register selects whether I/O ports are used for input or output. Each bit in the PDi register corresponds
to one port.
REJ09B0458-0010 Rev.0.10
Page 65 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.2
7. I/O Ports
Port Pi Register (Pi) (i = 1, 3, 4)
Address 00E1h(P1), 00E5h(P3 (1)), 00E8h(P4 (2))
Bit
Symbol
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b7
Pi_7
X
Symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
b6
Pi_6
X
b5
Pi_5
X
b4
Pi_4
X
b3
Pi_3
X
b2
Pi_2
X
Bit Name
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit
Port Pi_7 bit
b1
Pi_1
X
Function
0: “L” level
1: “H” level
b0
Pi_0
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Bits P3_0 to P3_2 and P3_6 in the P3 register are reserved bits. If it is necessary to set bits P3_0 to P3_2 and
P3_6, set to 0. When read, the content is 0.
2. Bits P4_0 to P4_1 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 to P4_1 set to
0. When read, the content is 0. Bits P4_3, P4_4 are reserved bits. If it is necessary to set bits P4_3 and P4_4, set
to 0. When read, the content is 0.
Data input and output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to retain output data and a circuit to read the pin status. The value written
in the port latch is output from the pin. Each bit in the Pi register corresponds to one port.
Pi_j Bit (i = 1, 3, 4, j = 0 to 7) (Port Pi_j Bit)
The pin level of any I/O port which is set to input mode can be read by reading the corresponding bit in this
register. The pin level of any I/O port which is set to output mode can be controlled by writing to the
corresponding bit in this register.
REJ09B0458-0010 Rev.0.10
Page 66 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.3
7. I/O Ports
Timer RA Pin Select Register (TRASR)
Address 0180h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b6
—
0
b5
—
0
Symbol
Bit Name
TRAIOSEL0 TRAIO pin select bit
TRAIOSEL1
b2
b3
b4
b5
b6
b7
—
—
—
—
—
—
Reserved bits
b4
—
0
b3
—
0
b2
—
0
b1
b0
TRAIOSEL1 TRAIOSEL0
0
0
Function
R/W
R/W
R/W
b1 b0
0 0: TRAIO pin not used
0 1: P1_7 assigned
1 0: P1_5 assigned
1 1: Do not set.
Set to 0.
R/W
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this
register.
Set the TRASR register before setting the timer RA associated registers. Also, do not change the setting value
in this register during timer RA operation.
7.4.4
Timer RC Pin Select Register (TRBRCSR)
Address 0181h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
TRCCLKSEL1 TRCCLKSEL0
0
0
b3
—
0
b2
—
0
b1
—
0
Symbol
Bit Name
Function
—
Reserved bits
Set to 0.
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b5 b4
TRCCLKSEL0 TRCCLK pin select bit
0 0: TRCCLK pin not used
TRCCLKSEL1
0 1: P1_4 assigned
1 0: P3_3 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b0
—
0
R/W
R/W
—
R/W
R/W
R/W
—
The TRBRCSR register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set bits TRCCLKSEL0 and TRCCLKSEL1 before setting the timer RC associated registers. Also, do not
change the setting values of bits TRCCLKSEL0 and TRCCLKSEL1 during timer RC operation.
REJ09B0458-0010 Rev.0.10
Page 67 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.5
7. I/O Ports
Timer RC Pin Select Register 0 (TRCPSR0)
Address 0182h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
TRCIOBSEL0
0
b3
—
0
b2
—
0
b1
—
0
b0
TRCIOASEL0
0
Bit
b0
Symbol
Bit Name
TRCIOASEL0 TRCIOA/TRCTRG pin select bit
b1
b2
b3
b4
—
Reserved bits
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
TRCIOBSEL0 TRCIOB pin select bit
0: TRCIOB pin not used
1: P1_2 assigned
—
Reserved bits
Set to 0.
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5
b6
b7
Function
0: TRCIOA/TRCTRG pin not used
1: P1_1 assigned
Set to 0.
R/W
R/W
R/W
—
R/W
R/W
—
The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value
in this register during timer RC operation.
7.4.6
Timer RC Pin Select Register 1 (TRCPSR1)
Address 0183h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
TRCIODSEL1 TRCIODSEL0
0
0
Symbol
Bit Name
TRCIOCSEL0 TRCIOC pin select bit
TRCIOCSEL1
b3
b2
—
0
—
0
b1
b0
TRCIOCSEL1 TRCIOCSEL0
0
0
Function
b1 b0
0 0: TRCIOC pin not used
0 1: P1_3 assigned
1 0: P3_4 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5 b4
TRCIODSEL0 TRCIOD pin select bit
0 0: TRCIOD pin not used
TRCIODSEL1
0 1: P1_0 assigned
1 0: P3_5 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
—
The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value
in this register during timer RC operation.
REJ09B0458-0010 Rev.0.10
Page 68 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.7
UART0 Pin Select Register (U0SR)
Address 0188h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
7. I/O Ports
b6
—
0
b5
—
0
Symbol
Bit Name
TXD0SEL0 TXD0 pin select bit
b4
CLK0SEL0
0
b3
—
0
b2
RXD0SEL0
0
b1
—
0
b0
TXD0SEL0
0
Function
0: TXD0 pin not used
1: P1_4 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
RXD0SEL0 RXD0 pin select bit
0: RXD0 pin not used
1: P1_5 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
CLK0SEL0 CLK0 pin select bit
0: CLK0 pin not used
1: P1_6 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
R/W
R/W
—
R/W
—
R/W
—
The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this
register.
Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value in
this register during UART0 operation.
REJ09B0458-0010 Rev.0.10
Page 69 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.8
7. I/O Ports
UART2 Pin Select Register 0 (U2SR0)
Address 018Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b6
—
0
b5
b4
RXD2SEL1 RXD2SEL0
0
0
Symbol
Bit Name
TXD2SEL0 TXD2/SDA2 pin select bit
TXD2SEL1
b3
—
0
b2
—
0
b1
b0
TXD2SEL1 TXD2SEL0
0
0
Function
b1 b0
0 0: TXD2/SDA2 pin not used
0 1: P3_7 assigned
1 0: P3_4 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5 b4
RXD2SEL0 RXD2/SCL2 pin select bit
0 0: RXD2/SCL2 pin not used
RXD2SEL1
0 1: P3_4 assigned
1 0: P3_7 assigned
1 1: P4_5 assigned
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b2
b3
b4
b5
b6
b7
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
—
The U2SR0 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this
register.
Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in
this register during UART2 operation.
7.4.9
UART2 Pin Select Register 1 (U2SR1)
Address 018Bh
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
CTS2SEL0
0
b3
—
0
b2
—
0
b1
—
0
b0
CLK2SEL0
0
Bit
b0
Symbol
Bit Name
CLK2SEL0 CLK2 pin select bit
R/W
R/W
b1
b2
b3
b4
—
—
—
CTS2SEL0 CTS2/RTS2 pin select bit
R/W
—
b5
b6
b7
Function
0: CLK2 pin not used
1: P3_5 assigned
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
0: CTS2/RTS2 pin not used
1: P3_3 assigned
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
Set to 0.
R/W
R/W
—
R/W
The U2SR1 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this
register.
Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in
this register during UART2 operation.
REJ09B0458-0010 Rev.0.10
Page 70 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.10
7. I/O Ports
SSU/IIC Pin Select Register (SSUIICSR)
Address 018Ch
Bit
b7
Symbol
—
After Reset
0
Bit
b0
Symbol
IICSEL
b1
b2
b3
b4
b5
b6
b7
—
—
—
—
—
—
—
7.4.11
b2
b3
b4
b5
b6
b7
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
IICSEL
0
Bit Name
SSU/I2C bus switch bit
Function
0: SSU function selected
1: I2C bus function selected
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
Reserved bits
R/W
R/W
—
Set to 0.
INT Interrupt Input Pin Select Register (INTSR)
Address 018Eh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b6
—
0
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
INT1SEL0
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
INT1SEL0 INT1 pin select bit
0: P1_7 assigned
1: P1_5 assigned
—
Reserved bits
Set to 0.
—
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
Reserved bits
Set to 0.
—
b0
—
0
R/W
—
R/W
R/W
—
R/W
The INTSR register selects which pin is assigned to the INT1 input. To use INT1, set this register.
Set the INTSR register before setting the INT1 associated registers. Also, do not change the setting values in
this register during INT1 operation.
REJ09B0458-0010 Rev.0.10
Page 71 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.12
7. I/O Ports
Pull-Up Control Register 0 (PUR0)
Address 01E0h
Bit
b7
Symbol PU07
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
—
—
PU02
PU03
—
—
PU06
PU07
b6
PU06
0
b5
—
0
b4
—
0
Bit Name
Reserved bits
b3
PU03
0
b2
PU02
0
b1
—
0
b0
—
0
Function
R/W
R/W
Set to 0.
P1_0 to P1_3 pull-up
P1_4 to P1_7 pull-up
Reserved bits
0: Not pulled up
1: Pulled up (1)
Set to 0.
R/W
R/W
R/W
P3_3 pull-up
P3_4, P3_5, P3_7 pull-up
0: Not pulled up
1: Pulled up (1)
R/W
R/W
Note:
1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up.
For ports set to output as I/O pins for peripheral functions, the setting values in the PUR0 register are invalid
and no pull-up resistor is connected.
7.4.13
Pull-Up Control Register 1 (PUR1)
Address 01E1h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
Symbol
Bit Name
—
Reserved bit
PU11 P4_5 to P4_7 pull-up
—
—
—
—
—
—
Reserved bits
b4
—
0
b3
—
0
b2
—
0
b1
PU11
0
b0
—
0
Function
Set to 0.
0: Not pulled up
1: Pulled up (1)
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
R/W
R/W
R/W
R/W
—
Note:
1. When this bit is set to 1 (pulled up), the pin whose port direction bit is set to 0 (input mode) is pulled up.
For ports set to output as I/O pins for peripheral functions, the setting values in the PUR1 register are invalid
and no pull-up resistor is connected.
REJ09B0458-0010 Rev.0.10
Page 72 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.14
7. I/O Ports
Port P1 Drive Capacity Control Register (P1DRR)
Address 01F0h
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol P1DRR7 P1DRR6 P1DRR5 P1DRR4 P1DRR3 P1DRR2 P1DRR1 P1DRR0
After Reset
0
0
0
0
0
0
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
P1DRR0
P1DRR1
P1DRR2
P1DRR3
P1DRR4
P1DRR5
P1DRR6
P1DRR7
Bit Name
P1_0 drive capacity
P1_1 drive capacity
P1_2 drive capacity
P1_3 drive capacity
P1_4 drive capacity
P1_5 drive capacity
P1_6 drive capacity
P1_7 drive capacity
Function
0: Low
1: High (1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. Both “H” and “L” output are set to high drive capacity.
The P1DRR register selects whether the drive capacity of the P1 output transistor is set to low or high.
The P1DRRi bit (i = 0 to 7) is used to select whether the drive capacity of the output transistor is set to low or
high for each pin.
REJ09B0458-0010 Rev.0.10
Page 73 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.15
7. I/O Ports
Drive Capacity Control Register 0 (DRR0)
Address 01F2h
Bit
b7
Symbol DRR07
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
—
—
—
—
—
—
DRR06
DRR07
b6
DRR06
0
b5
—
0
b4
—
0
b3
—
0
Bit Name
Reserved bits
b2
—
0
b1
—
0
Function
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
P3_3 drive capacity
P3_4, P3_5, P3_7 drive capacity
0: Low
1: High (1)
b0
—
0
R/W
R/W
—
R/W
R/W
Note:
1. Both “H” and “L” output are set to high drive capacity.
DRR06 Bit (P3_3 drive capacity)
The DRR06 bit selects whether the drive capacity of the P3_3 output transistors is set to low or high. This bit is
used to select whether the drive capacity of the output transistors is set to low or high for this pin.
DRR07 Bit (P3_4, P3_5, P3_7 drive capacity)
The DRR07 bit selects whether the drive capacity of the P3_4, P3_5, P3_7 output transistors is set to low or
high. This bit is used to select whether the drive capacity of the output transistors is set to low or high for three
pins.
REJ09B0458-0010 Rev.0.10
Page 74 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.16
7. I/O Ports
Drive Capacity Control Register 1 (DRR1)
Address 01F3h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
DRR11
0
Symbol
Bit Name
—
Reserved bit
DRR11 P4_5 to P4_7 drive capacity
—
—
—
—
—
—
b0
—
0
Function
Set to 0.
0: Low
1: High (1)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bits
Set to 0.
R/W
R/W
R/W
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
R/W
Note:
1. Both “H” and “L” output are set to high drive capacity.
DRR11 Bit (P4_5 to P4_7 drive capacity)
The DRR11 bit selects whether the drive capacity of the P4_5 to P4_7 output transistors is set to low or high.
This bit is used to select whether the drive capacity of the output transistors is set to low or high for four pins.
REJ09B0458-0010 Rev.0.10
Page 75 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.4.17
7. I/O Ports
Input Threshold Control Register 0 (VLT0)
Address 01F5h
Bit
b7
Symbol VLT07
After Reset
0
b6
VLT06
0
b5
—
0
Bit
b0
b1
b2
b3
Symbol
Bit Name
—
Reserved bits
—
VLT02 P1 input level select bit
VLT03
b4
b5
b6
b7
—
—
VLT06
VLT07
b4
—
0
b3
VLT03
0
b2
VLT02
0
b1
—
0
b0
—
0
Function
R/W
R/W
Set to 0.
R/W
R/W
b3 b2
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
Set to 0.
Reserved bits
P3_3 to P3_5, P3_7 input level select
bit
R/W
R/W
R/W
b7 b6
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
The VLT0 register selects the voltage level of the input threshold values for ports P1, P3_3 to P3_5, and P3_7.
Bits VLT02 to VLT03 and bits VLT06 to VLT07 are used to select the input threshold values among three
voltage levels (0.35 VCC, 0.50 VCC, and 0.70 VCC).
7.4.18
Input Threshold Control Register 1 (VLT1)
Address 01F6h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
Symbol
Bit Name
VLT10 P4_2, P4_5 to P4_7 input level select
VLT11 bit
—
—
—
—
—
—
Reserved bits
b3
—
0
b2
—
0
b1
VLT11
0
Function
b1 b0
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b0
VLT10
0
R/W
R/W
R/W
R/W
—
The VLT1 register selects the voltage level of the input threshold values for ports P4_2 and P4_5 to P4_7. Bits
VLT10 to VLT15 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50
VCC, and 0.70 VCC).
REJ09B0458-0010 Rev.0.10
Page 76 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.5
7. I/O Ports
Port Settings
Tables 7.4 to 7.24 list the port settings.
Table 7.4
Port P1_0/KI0/AN8/TRCIOD/LVCMP1
Register
PD1
KIEN
Bit
PD1_0
KI0EN
0
X
X
X
X
X
X
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
0
0
0
0
0
1
0
X
X
X
X
X
X
0
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
Setting
Value
ADINSEL
CH
ADGSEL
2 1 0
1
0
TRCPSR1
TRCIODSEL
1
0
Other than
01b
Other than
01b
Other than
01b
Other than
01b
VCA2
Timer RC Setting
VCA22
—
X
X
Input port (1)
X
X
Output port (2)
X
X
KI0 input (1)
X
X
A/D converter input (AN8) (1)
1
X
Refer to Table 7.24
TRCIOD Pin Setting
TRCIOD input (1)
1
X
Refer to Table 7.24
TRCIOD Pin Setting
TRCIOD output (2)
1
X
Other than
01b
Function
Comparator A1 input
(LVCMP1)
X: 0 or 1
Notes:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR0 bit in the P1DRR register to 1.
Table 7.5
Port P1_1/KI1/AN9/TRCIOA/TRCTRG/LVCMP2
Register
PD1
KIEN
Bit
PD1_1
KI1EN
0
X
X
X
X
X
1
X
X
X
X
1
X
X
0
0
0
0
Setting
Value
ADINSEL
CH
ADGSEL
2 1 0
1
0
TRCPSR0
VCA2
Timer RC Setting
TRCIOASEL0
VCA24
—
X
0
X
X
Input port (1)
X
X
0
X
X
Output port (2)
X
X
X
0
X
X
KI1 input (1)
1
0
1
0
X
X
A/D converter input (AN9) (1)
0
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
0
0
X
X
X
X
X
0
1
Refer to Table 7.21
TRCIOA Pin Setting
Refer to Table 7.21
TRCIOA Pin Setting
X: 0 or 1
Notes:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR1 bit in the P1DRR register to 1.
REJ09B0458-0010 Rev.0.10
Page 77 of 572
Apr 01, 2008
X
Function
TRCIOA input (1)
TRCIOA output (2)
Comparator A2 input
(LVCMP2)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 7.6
Register
Bit
7. I/O Ports
Port P1_2/KI2/AN10/TRCIOB/LVREF
PD1
KIEN
PD1_2 KI2EN
Setting
Value
ADINSEL
CH
2 1 0
TRCPSR0
Timer RC
Setting
VCA2
ADGSEL
TRCIOBSEL0 VCA21 VCA23
1
0
Function
—
0
X
X
X
X
X
X
0
X
X
X
Input port (1)
1
X
X
X
X
X
X
0
X
X
X
Output port (2)
0
1
X
X
X
X
X
0
X
X
X
KI2 input (1)
0
0
0
1
0
0
1
0
X
X
X
A/D converter input (AN10) (1)
0
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
1
X
X
0
0
X
X
X
X
X
0
1
X
X
Comparator A1 reference
voltage input (LVREF)
0
0
X
X
X
X
X
0
X
1
X
Comparator A2 reference
voltage input (LVREF)
Refer to Table
7.22 TRCIOB
Pin Setting
Refer to Table
7.22 TRCIOB
Pin Setting
TRCIOB input (1)
TRCIOB output (2)
X: 0 or 1
Notes:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR2 bit in the P1DRR register to 1.
Table 7.7
Register
Bit
Setting
Value
Port P1_3/KI3/AN11/TRCIOC/LVCOUT1
PD1
KIEN
ADINSEL
TRCPSR1
ACMR Timer RB Setting Timer RC Setting
ADGSEL TRCIOCSEL
CH
Function
CM10E
—
—
PD1_3 KI3EN
2 1 0 1
0
1
0
Other than
Other than TRBO
0
X
X X X X
X
0
X
Input port (1)
01b
usage conditions
Other than TRBO
Other than
X
0
1
X
X X X X
X
Output port (2)
usage conditions
01b
Other than
Other than TRBO
0
1
X X X X
X
0
X
KI3 input (1)
01b
usage conditions
A/D converter
Other than TRBO
Other than
X
0
0
0
0 1 1 0
1
usage conditions
01b
input (AN11) (1)
Refer to Table
7.20 TRBO Pin
X
X
X X X X
X
X
X
0
X
TRBO output (2)
Setting
Refer to Table
Other than TRBO
7.22 TRCIOB
0
X
X X X X
X
0
1
0
TRCIOC input (1)
usage conditions
Pin Setting
Refer to Table
Other than TRBO
7.22 TRCIOB
X
X
X X X X
X
0
1
0
TRCIOC output (2)
usage conditions
Pin Setting
Comparator A1
X
X
X X X X
X
X
X
1
X
X
output
(LVCOUT1)
X: 0 or 1
Notes:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR3 bit in the P1DRR register to 1.
REJ09B0458-0010 Rev.0.10
Page 78 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
Table 7.8
Port P1_4/TXD0/TRCCLK
Register
PD1
U0SR
2
U1MR
SMD
1
Bit
PD1_4
TXD0SEL0
0
1
2
TRCCR1
TCK
1
0
0
0
X
X
X
X
X
X
X
X
Input port (1)
0
X
X
X
X
X
X
X
X
Output port (2)
X
X
X
X
X
TXD0 output (2, 3)
1
1
0
1
0
X
X
0
1
1
0
1
TRCCLK input (1)
0
Setting
Value
X
1
0
0
0
1
X
TRBRCSR
TRCCLKSEL
1
0
Function
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR4 bit in the P1DRR register to 1.
3. N-channel open-drain output by setting the NODC bit in the U0C0 register to 1.
Table 7.9
Port P1_5/RXD0/TRAIO/INT1
Register
PD1
U0SR
Bit
PD1_5
RXD0SEL0
Setting
Value
TRASR
TRAIOSEL
1
0
TRAIOC
TOPCR
TRAMR
TMOD
2
1
0
INTSR
INT1SEL
2
1
0
INTEN
INTCMP
Function
INT1EN INT1CP0
0
X
Other than 10b
X
X
X
X
X
X
X
X
X
Input port (1)
1
X
Other than 10b
X
X
X
X
X
X
X
X
X
Output port (2)
0
1
Other than 10b
X
X
X
X
X
X
X
X
X
RXD0 input (1)
0
X
0
Other than
000b, 001b
X
X
X
X
X
TRAIO input (1)
0
X
X
X
X
0
0
1
1
0
INT1 input (1)
0
0
1
1
0
TRAIO/INT1 input (1)
X
X
X
X
X
TRAIO pulse
output (2)
1
0
Other than 10b
X
0
X
1
0
0
Other than
000b, 001b
X
X
1
0
0
0
0
1
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR5 bit in the P1DRR register to 1.
Table 7.10
Port P1_6/CLK0/IVREF1/LVCOUT2
Register
PD1
U0SR
Bit
PD1_6
CLK0SEL0
0
0
X
X
X
X
1
0
X
X
X
X
0
1
X
X
X
1
X
1
0
0
1
0
0
0
X
X
X
X
X
X
X
X
Setting
Value
2
U0MR
SMD
CKDIR
1
0
INTCMP
ACMR
INT1CP0
CM10E
X
0
Input port (1)
X
0
Output port (2)
X
0
CLK0 (external clock) input (1)
X
0
X
1
0
CLK0 (internal clock) output (2)
Comparator B1 reference voltage input (IVREF1)
X
X
1
Comparator A2 output (2)
Function
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR6 bit in the P1DRR register to 1.
REJ09B0458-0010 Rev.0.10
Page 79 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
Table 7.11
Port P1_7/INT1/TRAIO/IVCMP1
Register
PD1
TRASR
TRAIOSEL
1
0
TRAIOC
Bit
PD1_7
0
Other than 01b
1
Other than 01b
0
Setting
Value
0
0
1
X
0
0
1
0
1
INTSR
INT1SEL
2
1
0
X
X
X
X
X
X
X
X
X
Input port (1)
X
X
X
X
X
X
X
X
X
Output port (2)
0
Other than
000b, 001b
X
X
X
X
X
TRAIO input (1)
X
X
X
0
0
0
1
0
INT1 input (1)
0
Other than
000b, 001b
0
0
0
1
0
TRAIO/INT1 input (1)
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
1
1
TRAIO pulse output (2)
Comparator B1 input (IVCMP1)
TOPCR
Other than 01b
0
TRAMR
TMOD
2
1
0
Other than 01b
X
INTEN
INTCMP
Function
INT1EN INT1CP0
X: 0 or 1
Notes:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P1DRR7 bit in the P1DRR register to 1.
Table 7.12
Register
Bit
Setting
Value
PD3
PD3_3
Port P3_3/INT3/TRCCLK/SCS/CTS2/RTS2/IVCMP3
SSMR2
CSS
1
0
0
0
0
1
0
0
INTEN
INT3EN
TRBRCSR
TRCCR1
TRCCLKSEL
TCK
U2SR1
1
0
2
1
0
X
X
X
X
X
X
0
X
X
X
X
X
0
0
1
X
X
X
0
0
0
X
1
0
X
0
1
X
X
1
0
1
1
X
0
0
0
X
0
0
0
X
CTS2SEL0
U2MR
U2CO
SMD
INTCMP
CRS CRD INT3CP0
Function
2
1
0
0
X
X
X
X
X
X
Input port (1)
X
0
X
X
X
X
X
X
Output port (2)
X
X
0
X
X
X
X
X
0
INT3 input (1)
1
0
1
0
X
X
X
X
X
X
TRCCLK input (1)
X
X
X
X
X
X
X
X
X
SCS input (1)
X
X
X
X
X
X
X
X
X
X
SCS output (2, 3)
X
X
X
X
X
X
1
Other than
000b
0
0
X
CTS2 input (1)
0
X
X
X
X
X
X
1
Other than
000b
1
0
X
RTS2 output (2)
0
1
X
X
X
0
X
X
1
Comparator B3 input
(IVCMP1)
Other than 10b
X
X
X
X: 0 or 1
Notes:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1.
3. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open-drain output).
REJ09B0458-0010 Rev.0.10
Page 80 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 7.13
7. I/O Ports
Port P3_4/TRCIOC/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3
Synchronous Serial
Communication Unit
(Refer to Table 24.4
Register PD3 SSUIICSR
TRCPSR1
U2SR0
Association between
Communication
Modes and I/O Pins.)
TRCIOC
RXD2
TXD2
SSI output SSI input
SEL
SEL
SEL
Bit
PD3_4 IICSEL
control
control
1
0
1
0
1
0
Other
Other
Other
0
X
0
0
than 10b than 01b than 10b
Other
Other
Other
1
X
0
0
than 10b than 01b than 10b
Setting
Value
U2MR
U2SMR INTCMP
Timer RC
Setting
Function
SMD
IICM
INT3
CP0
—
X
X
X
X
Input port (1)
X
X
X
X
X
Output port (2)
2
1
0
X
X
X
0
X
0
0
1
0
Other
Other
than 01b than 10b
X
X
X
X
X
X
X
0
0
1
0
Other
Other
than 01b than 10b
X
X
X
X
X
X
0
0
1
X
X
X
X
X
X
X
Refer to
Table 7.23
TRCIOC
Pin Setting
Refer to
Table 7.23
TRCIOC
Pin Setting
X
X
0
1
0
X
X
X
X
X
X
SSI output (2, 3)
0
X
0
0
X
X
X
X
X
X
RXD2 input (1)
0
X
0
0
0
1
0
1
X
X
SCL2 input/
output (2, 4)
X
X
X
TXD2
output (2, 4)
X
X
Other
than 10b
X
X
X
X
X
X
0
1
0
1
X
X
X
X
Other
than 10b
Other
than 10b
0
X
X
0
0
X
X
X
X
1
0
0
X
0
0
X
X
X
X
1
0
0
X
0
0
Other
Other
Other
than 10b than 01b than 10b
1
1
0
1
0
0
1
0
1
X
X
X
X
X
X
1
X
0
1
TRCIOC
input (1)
TRCIOC
output (2)
SSI input (1)
SDA2 input/
output (2, 4)
Comparator B3
reference
voltage input
(IVREF3)
X: 0 or 1
Notes:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit in the
SSMR2 register to 0 (standard mode).
4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
REJ09B0458-0010 Rev.0.10
Page 81 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 7.14
Register
Bit
PD3
PD3_5
Port P3_5/SCL/SSCK/TRCIOD/CLK2
Synchronous Serial
Communication Unit (Refer
SSUIICSR ICCR1 to Table 24.4 Association
between Communication
Modes and I/O Pins.)
TRCPSR1
SSCK input
control
TRCIODSEL
0
0
X
X
Other than
10b
0
Other than
10b
SSCK output
control
X X X
X
X
Input port (1)
0
X X X
X
X
Output port (2)
X
X
X X X
X
X
SCL input/output (2)
X
X
X
X X X
X
X
SSCK input (1)
X
X
X
X X X
X
X
SSCK output (2, 3)
1
0
0
X X X
X
Refer to Table
7.24 TRCIOD TRCIOD input (1)
Pin Setting
1
0
0
X X X
X
Refer to Table
7.24 TRCIOD TRCIOD output (2)
Pin Setting
X
X
1
X X X
1
X
CLK2 input (2)
X
X
1
0 0 1
0
X
CLK2 output (2, 4)
X
1
0
0
X
0
0
1
0
X
X
X
1
1
X
X
X
X
0
X
0
1
X
0
X
1
0
X
0
X
0
X
0
0
1
0
X
X
0
X
0
0
1
0
X
X
0
X
0
0
1
0
X
X
0
X
0
0
1
0
X
X
SMD
—
0
0
Timer RC
Setting
U2MR
CKDIR
ICE
1
U2SR1
Function
IICSEL
0
Setting
Value
7. I/O Ports
1
0
CLK2SEL0
2 1 0
X: 0 or 1
Notes:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
3. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 (N-channel open-drain output).
4. N-channel open-drain output by setting the NODC bit in the U2SMR3 register to 1.
Table 7.15
Register
Bit
PD3
Synchronous Serial
Communication Unit (Refer
SSUIICSR ICCR1 to Table 24.4 Association
between Communication
Modes and I/O Pins.)
U2SR0
U2MR
SSO output
control
SSO input
control
RXD2SEL TXD2SEL
1
0
X
X
0
X
0
0
1
0
X
X
0
X
0
0
X
1
1
X
X
X
X
X
X
0
X
0
1
X
X
X
0
X
1
0
X
X
1
0
X
X
0
X
0
0
1
0
1
0
X
X
0
X
0
0
1
0
1
0
X
X
1
0
0
IICSEL
X
0
X
1
X
0
0
1
0
X
X
0
X
0
0
1
0
X
X
0
X
0
0
0
SMD
IICM
TOENA
X
X
0
Input port (1)
X
X
X
0
Output port (2)
X
X
X
X
X
SDA input/output (2)
X
X
X
X
X
X
SSO input (1)
X
X
X
X
X
X
SSO output (2, 3)
Other than
01b
X
X
X
X
0
RXD2 input (1)
Other than
01b
0
1
0
1
X
SCL2 input/
output (2, 4)
0
0
X
X
TXD2
output (2, 4)
2
1
0
Other than Other than
10b
01b
X
X
Other than Other than
10b
01b
X
X
X
X
1
0
0
X
0
U2SMR TRAIOC
Function
ICE
PD3_7
0
Setting
Value
Port P3_7/SSO/TXD2/SDA2/RXD2/SCL2/TRAO/SDA
X
X
X
0
0
1
1
Other than Other than
01b
01b
1
1
1
1
0
0
1
0
1
X
SDA2 input/
output (2, 4)
X
X
X
X
1
TRAO output (2)
X: 0 or 1
Notes:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
3. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output).
4. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
REJ09B0458-0010 Rev.0.10
Page 82 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
Table 7.16
Port P4_2/VREF
Register
Bit
ADCON1
ADSTBY
0
1
Setting
Value
Table 7.17
Function
Input port
Input port/VREF input
Port P4_5/INT0/RXD2/SCL2/ADTRG
Register
PD4
INTEN
Bit
PD4_5
INT0EN
0
Setting
Value
U2SR0
RXD2SEL
1
0
2
U2MR
SMD
1
X
1
0
Other than 11b
X
X
X
X
X
X
Input port (1)
X
Other than 11b
X
X
X
X
X
X
Output port (2)
0
1
Other than 11b
X
X
X
X
X
X
INT0 input (1)
0
X
X
X
X
X
X
X
RXD2 input (1)
0
X
0
1
1
1
1
1
Other than 11b
U2SMR
IICM
ADMOD
ADCAP
1
0
Function
0
1
0
1
X
X
SCL2 input/output (2, 3)
X
X
X
X
1
1
ADTRG input (1)
X: 0 or 1
Notes:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.
3. N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
Table 7.18
Register
Bit
Port P4_6/XIN/XCIN
PD4
CM0
CM1
Circuit specifications
Oscillation Feedback
PD4_6 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13
buffer
resistor
Function
0
X
X
0
X
0
X
X
0
OFF
OFF
Input port (1)
1
X
X
0
X
0
X
X
0
OFF
OFF
ON
ON
ON
OFF
0
OFF
ON
1
OFF
OFF
ON
ON
ON
OFF
0
OFF
ON
1
OFF
OFF
Output port (2)
XIN-XOUT oscillation
(on-chip feedback resistor enabled)
XIN-XOUT oscillation
(on-chip feedback resistor disabled)
XIN-XOUT oscillation stop
(on-chip feedback resistor enabled)
XIN-XOUT oscillation stop
(on-chip feedback resistor disabled)
XCIN-XCOUT oscillation
(on-chip feedback resistor enabled)
XCIN-XCOUT oscillation
(on-chip feedback resistor disabled)
XCIN-XCOUT oscillation stop
(on-chip feedback resistor enabled)
XCIN-XCOUT oscillation stop
(on-chip feedback resistor disabled)
Oscillation stop (STOP mode)
0
0
1
0
X
X
0
X
1
1
Setting
Value
X
0
0
1
1
1
X
0
X
1
1
X
X
X
1
X
X
OFF
X: 0 or 1
Notes:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.
REJ09B0458-0010 Rev.0.10
Page 83 of 572
Apr 01, 2008
OFF
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 7.19
Register
Bit
7. I/O Ports
Port P4_7/XOUT/XCOUT
PD4
CM0
CM1
Circuit specifications
Oscillation Feedback
PD4_7 CM01 CM03 CM04 CM05 CM10 CM11 CM12 CM13
buffer
resistor
Function
0
X
X
0
X
0
X
X
0
OFF
OFF
Input port (1)
1
X
X
0
X
0
X
X
0
OFF
OFF
ON
ON
ON
OFF
0
OFF
ON
1
OFF
OFF
ON
ON
ON
OFF
0
OFF
ON
1
OFF
OFF
Output port (2)
XIN-XOUT oscillation
(on-chip feedback resistor enabled)
XIN-XOUT oscillation
(on-chip feedback resistor disabled)
XIN-XOUT oscillation stop
(on-chip feedback resistor enabled)
XIN-XOUT oscillation stop
(on-chip feedback resistor disabled)
XCIN-XCOUT oscillation
(on-chip feedback resistor enabled) (3)
XCIN-XCOUT oscillation
(on-chip feedback resistor disabled) (3)
XCIN-XCOUT oscillation stop
(on-chip feedback resistor enabled)
XCIN-XCOUT oscillation stop
(on-chip feedback resistor disabled)
Oscillation stop (STOP mode)
0
0
1
0
X
X
0
X
1
1
Setting
Value
X
0
0
1
1
1
X
0
X
1
1
X
X
X
1
X
X
OFF
OFF
X: 0 or 1
Note:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Output drive capacity high by setting the DRR11 bit in the DRR1 register to 1.
3. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as
the CMOS level signal directly.
REJ09B0458-0010 Rev.0.10
Page 84 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7. I/O Ports
Table 7.20
TRBO Pin Setting
Register
TRBIOC
Bit
TOCNT (1)
0
0
0
1
Setting
value
TRBMR
TMOD1
TMOD0
0
1
1
0
1
0
1
1
Function
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Programmable output port
Note:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
Table 7.21
Register
Bit
TRCIOA Pin Setting
TRCOER
EA
TRCMR
PWM2
IOA2
0
1
0
0
1
1
1
0
Setting
Value
TRCIOR0
IOA1
0
1
IOA0
1
X
1
X
X
X
TRCCR2
TCEG1
TCEG0
Function
X
X
Timer waveform output
(output compare function)
X
X
X
Timer mode (input capture function)
X
0
1
1
X
PWM2 mode TRCTRG input
X: 0 or 1
Table 7.22
Register
Bit
Setting
Value
TRCIOB Pin Setting
TRCOER
EB
0
0
TRCMR
PWM2
PWMB
0
X
1
1
IOB2
X
X
0
1
0
0
0
1
1
0
1
TRCIOR0
IOB1
X
X
0
1
IOB0
X
X
1
X
X
X
Function
PWM2 mode waveform output
PWM mode waveform output
Timer waveform output (output compare
function)
Timer mode (input capture function)
X: 0 or 1
Table 7.23
Register
Bit
Setting
Value
TRCIOC Pin Setting
TRCOER
EC
0
TRCMR
PWM2
PWMC
1
1
IOC2
X
0
1
0
0
0
1
1
0
1
TRCIOR1
IOC1
X
0
1
IOC0
X
1
X
X
X
TRCIOR1
IOD1
X
0
1
IOD0
X
1
X
X
X
Function
PWM mode waveform output
Timer waveform output (output compare
function)
Timer mode (input capture function)
X: 0 or 1
Table 7.24
Register
Bit
Setting
Value
TRCIOD Pin Setting
TRCOER
ED
0
TRCMR
PWM2
PWMD
1
1
IOD2
X
0
1
0
0
0
1
1
0
1
X: 0 or 1
REJ09B0458-0010 Rev.0.10
Page 85 of 572
Apr 01, 2008
Function
PWM mode waveform output
Timer waveform output (output compare
function)
Timer mode (input capture function)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
7.6
7. I/O Ports
Unassigned Pin Handling
Table 7.25 lists Unassigned Pin Handling. Figure 7.9 shows the Unassigned Pin Handling.
Table 7.25
Unassigned Pin Handling
Pin Name
Connection
Ports P1, P3_3 to P3_5, • After setting to input mode, connect each pin to VSS via a resistor (pull-down)
P3_7, P4_5
or connect each pin to VCC via a resistor (pull-up). (2)
• After setting to output mode, leave these pins open. (1, 2)
Ports P4_6, P4_7
Connect to VCC via a pull-up resistor (2)
Port P4_2/VREF
Connect to VCC
RESET (3)
Connect to VCC via a pull-up resistor (2)
Notes:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
MCU
Port P1,
P3_3 to P3_5,
P3_7, P4_5
(Input mode )
:
:
(Input mode)
(Output mode)
P4_6, P4_7
RESET (1)
Port P4_2/VREF
Note:
1. When the power-on reset function is in use.
Figure 7.9
Unassigned Pin Handling
REJ09B0458-0010 Rev.0.10
Page 86 of 572
Apr 01, 2008
:
:
Open
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
8.
8. Bus
Bus
The bus cycles differ when accessing ROM/RAM and when accessing SFR.
Table 8.1 lists Bus Cycles by Access Area of R8C/32A Group (with Data Flash).
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 8.2 shows Access Units and Bus Operations.
Table 8.1
Bus Cycles by Access Area of R8C/32A Group (with Data Flash)
Access Area
SFR/Data flash
Program ROM/RAM
Table 8.2
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Access Units and Bus Operations
SFR, Data flash
Area
Even address
Byte access
CPU clock
CPU clock
Address
Even
Data
Odd address
Byte access
Odd
Address
Data
CPU clock
Address
Data
Even + 1
Data
Data
REJ09B0458-0010 Rev.0.10
Page 87 of 572
Data
Odd
Data
Address
Data
Even
Data
Even + 1
Data
CPU clock
CPU clock
Address
Data
CPU clock
Even
Data
Data
Even
CPU clock
CPU clock
Data
Odd address
Word access
Address
Data
Address
Even address
Word access
ROM (program ROM), RAM
Odd
Data
Apr 01, 2008
Odd + 1
Data
Address
Data
Odd
Data
Odd + 1
Data
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
8. Bus
However, only the following SFRs are connected with the 16-bit bus:
Interrupts: Each interrupt control register
Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH
UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2,
and U2SMR
A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, ADMOD, ADINSEL, ADCON0,
and ADCON1
Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, Data flash, Even
address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time.
REJ09B0458-0010 Rev.0.10
Page 88 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.
9. Clock Generation Circuit
Clock Generation Circuit
The following five circuits are incorporated in the clock generation circuit:
• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
• Low-speed on-chip oscillator for watchdog timer
9.1
Overview
Table 9.1 lists the Specification Overview of Clock Generation Circuit. Figure 9.1 shows a Clock Generation
Circuit (With XIN and XCIN Pins Shared). Figure 9.2 shows a Peripheral Function Clock and Figure 9.3 shows a
Procedure for Reducing Internal Power Consumption Using VCA20 bit.
Table 9.1
Specification Overview of Clock Generation Circuit
Item
Applications
XIN Clock
XCIN Clock
Oscillation Circuit Oscillation Circuit
• CPU clock
source
• Peripheral
function clock
source
• CPU clock
source
• Peripheral
function clock
source
Clock frequency 0 to 20 MHz
32.768 kHz
Connectable
oscillator
• Ceramic
resonator
• Crystal
oscillator
• Crystal
oscillator
Oscillator
connect pins
Oscillation stop,
restart function
Oscillator status
after reset
Others
XIN, XOUT (1)
On-Chip Oscillator
High-Speed
Low-Speed
On-Chip Oscillator On-Chip Oscillator
• CPU clock
• CPU clock
source
source
• Peripheral
• Peripheral
function clock
function clock
source
source
• CPU and
• CPU and
peripheral
peripheral
function clock
function clock
source when XIN source when XIN
clock stops
clock stops
oscillating
oscillating
(3)
Approx. 125 kHz
Approx. 40 MHz
−
Low-Speed
On-Chip Oscillator
for Watchdog Timer
• Watchdog timer
clock source
Approx. 125 kHz
−
−
XCIN, XCOUT (1) − (1)
− (1)
−
Usable
Usable
Usable
Usable
Usable
Stop
Stop
Stop
Oscillate
Stop
Externally
generated clock
can be input (2)
• Externally
−
generated clock
can be input
• On-chip
feedback
resistor Rf
(connected/
not connected
selectable)
−
−
Notes:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit and the XCIN clock oscillation circuit are not used.
2. To input an external clock, set the CM05 bit in the CM0 register to 1 (XIN clock stops), the CM11 bit in the CM1
register to 1 (internal feedback resistor disabled), and the CM13 bit to 1 (XIN-XOUT pin).
3. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
REJ09B0458-0010 Rev.0.10
Page 89 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
CSPRO
Low-speed on-chip oscillator
for watchdog timer
fOCO-WDT
fC
fC2
fC4
fC
1/2
1/2
fC32
1/8
FRA1 register
Frequency adjustable
High-speed
on-chip oscillator
FRA00
fOCO40M
FRA2 register
Divider
fOCO-F
fOCO (On-chip oscillator clock)
FRA01 = 1
Peripheral
function
clock
fOCO
FRA01 = 0
FRA03 = 1
Divider
(1/128)
fOCO128
FRA03 = 0
Low-speed
on-chip oscillator
CM14
CM10 = 1 (stop mode)
Power-on reset circuit
fOCO-S
S Q
Voltage detection circuit
R
RESET
Power-on reset
Software reset
Interrupt request
fOCO-S
b
f1
c
f2
S Q
d
Oscillation stop detection
WAIT instruction
CM30
R
f4
e
XIN clock
OCD2 = 1
Stop signal
f32
CM07 = 0
a
CM07 = 1
XOUT/XCOUT
XIN/XCIN
f8
g
Divider
h
CPU clock
OCD2 = 0
CM01 = 0
CM13
CM05
System clock
CM02
CM04
CM01
CM03
1/2
a
1/2
g
e
d
c
b
XIN clock
1/2
1/2
XCIN clock
1/2
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to
CM16 = 10b
h
CM06 = 0
CM17 to CM16 = 01b
CM02, CM03, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
CM30: Bit in CM3 register
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01, FRA03: Bits in FRA0 register
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
Forcible discharge when OCD0 = 0
XIN clock
Pulse generation circuit
for clock edge detection
and charge/discharge
control
Charge/discharge
circuit
OCD1
Oscillation stop detection
Interrupt generation circuit
Watchdog timer interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
OCD2 bit switch signal
CM14 bit switch signal
Figure 9.1
Clock Generation Circuit (With XIN and XCIN Pins Shared)
REJ09B0458-0010 Rev.0.10
Page 90 of 572
Apr 01, 2008
Oscillation stop detection,
Watchdog timer,
Voltage monitor 1 interrupt,
Voltage monitor 2 interrupt
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
fC
fC4
fC32
fOCO40M
fOCO128
fOCO
fOCO-F
Watchdog
timer
fOCO-WDT
INT0
Timer RA
Timer RB
Timer RC
Timer RE
A/D converter
f1
f2
f4
f8
f32
CPU
CPU clock
Figure 9.2
Peripheral Function Clock
REJ09B0458-0010 Rev.0.10
Page 91 of 572
Apr 01, 2008
UART0 UART2
SSU /
I2C bus
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2
9. Clock Generation Circuit
Registers
9.2.1
System Clock Control Register 0 (CM0)
Address 0006h
Bit
b7
Symbol CM07
After Reset
0
Bit
b0
b1
b6
CM06
0
b5
CM05
1
b4
CM04
0
b3
CM03
1
b2
CM02
0
b1
CM01
0
b0
—
0
Symbol
Bit Name
—
Reserved bit
CM01 XIN-XCIN switch bit
b2
CM02
b3
CM03
b4
CM04
b5
CM05
b6
CM06
b7
CM07
Function
Set to 0.
0: P4_6 and P4_7 set as XIN-XOUT pin
1: P4_6 and P4_7 set as XCIN-XCOUT pin
Wait mode peripheral function clock 0: Peripheral function clock does not stop in wait mode
stop bit
1: Peripheral function clock stops in wait mode
XCIN clock stop bit
0: XCIN clock oscillates
1: XCIN clock stops
0: I/O ports P4_6 and P4_7
Port/XCIN-XCOUT switch bit (5)
1: XCIN-XCOUT pin (6)
XIN clock (XIN-XOUT) stop bit (1, 3) 0: XIN clock oscillates
1: XIN clock stops (2)
System clock division select bit 0 (4) 0: Bits CM16 and CM17 in CM1 register enabled
1: Divide-by-8 mode
0: XIN clock
XIN, XCIN clock select bit (7)
1: XCIN clock
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. The CM05 bit stops the XIN clock when the high-speed on-chip oscillator mode or low-speed on-chip oscillator
mode is selected. This bit cannot be used to detect whether the XIN clock has stopped. To stop the XIN clock,
set the bits in the following order:
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (on-chip oscillator clock selected).
2. During external clock input, only the clock oscillation buffer stops and clock input is acknowledged.
3. Only when the CM05 bit is set to 1 (XIN clock stops) and the CM13 bit in the CM1 register is set to 0 (P4_6 and
P4_7), P4_6 and P4_7 can be used as I/O ports.
4. When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
5. The CM04 bit can be set to 1 by a program but cannot be set to 0.
6. To use the XCIN clock, set the CM04 bit to 1.
7. Set the CM07 bit to 1 (XCIN clock) from 0 after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allowing XCIN
clock oscillation to stabilize.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM0 register.
REJ09B0458-0010 Rev.0.10
Page 92 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.2
9. Clock Generation Circuit
System Clock Control Register 1 (CM1)
Address 0007h
Bit
b7
Symbol CM17
After Reset
0
Bit
b0
b6
CM16
0
b5
—
1
b4
CM14
0
b3
CM13
0
b2
CM12
0
b1
CM11
0
b0
CM10
0
Symbol
Bit Name
CM10 All clock stop control bit (2)
b1
CM11
b2
CM12
b3
CM13
b4
CM14
b5
b6
b7
—
CM16
CM17
Function
0: Clock oscillates
1: All clocks stop (stop mode)
XIN-XOUT on-chip feedback resistor 0: On-chip feedback resistor enabled
select bit
1: On-chip feedback resistor disabled
XCIN-XCOUT on-chip feedback
0: On-chip feedback resistor enabled
resistor select bit
1: On-chip feedback resistor disabled
0: I/O ports P4_6 and P4_7
Port/XCIN-XCOUT switch bit (5)
1: XIN-XOUT pin
Low-speed on-chip oscillator stop bit 0: Low-speed on-chip oscillator on
(3, 4)
1: Low-speed on-chip oscillator off
Reserved bit
Set to 1.
System clock division select bit 1 (1) b7 b6
0 0: No division mode
0 1: Divide-by-2 mode
1 0: Divide-by-4 mode
1 1: Divide-by-16 mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. When the CM06 bit is set to 0 (bits CM16 and CM17 enabled), bits CM16 and CM17 are enabled.
2. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
3. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit can be set to 1 (low-speed on-chip oscillator
off). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip
oscillator on). It remains unchanged even if 1 is written to it.
4. To use the voltage monitor 1 interrupt or voltage monitor 2 interrupt (when the digital filter is used), set the CM14
bit to 0 (low-speed on-chip oscillator on).
5. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM1 register.
REJ09B0458-0010 Rev.0.10
Page 93 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.3
9. Clock Generation Circuit
System Clock Control Register 3 (CM3)
Address 0009h
Bit
b7
Symbol CM37
After Reset
0
Bit
b0
b6
CM36
0
b5
CM35
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
CM30
0
Symbol
Bit Name
CM30 Wait control bit (1)
b1
b2
b3
b4
b5
—
—
—
—
CM35
b6
b7
CM36
CM37
Function
0: Other than wait mode
1: MCU enters wait mode
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
CPU clock division when exiting
wait mode select bit (2)
0: Following settings are enabled:
CM06 bit in CM0 register
Bits CM16 and CM17 in CM1 register
1: No division
R/W
CPU clock when exiting wait mode
or stop mode select bit
b7 b6
R/W
R/W
0 0: MCU exits with the CPU clock immediately
before entering wait or stop mode.
0 1: Do not set.
1 0: High-speed on-chip oscillator clock selected (3)
1 1: XIN clock selected (4)
—
Notes:
1. When the MCU exits wait mode by a peripheral function interrupt, the CM30 bit is set to 0 (other than wait mode).
2. Set the CM35 bit to 0 in stop mode. When the MCU enters wait mode, if the CM35 bit is set to 1 (no division), the
CM06 bit in the CM0 register is set to 0 (bits CM16 and CM17 enabled) and bits CM17 and CM16 in the CM1
register is set to 00b (no division mode).
3. When bits CM37 and CM36 are set to 10b (high-speed on-chip oscillator clock selected), the following will be set
when the MCU exits wait mode or stop mode.
• OCD2 bit in OCD register = 1 (on-chip oscillator selected)
• FRA00 bit in FRA0 register = 1 (high-speed on-chip oscillator on)
• FRA01 bit in FRA0 register = 1 (high-speed on-chip oscillator selected)
4. When bits CM37 and CM36 are set to 11b (XIN clock selected), the following will be set when the MCU exits wait
mode or stop mode.
• OM05 bit in OM0 register = 1 (XIN clock oscillates)
• OM13 bit in OM1 register = 1 (XIN-XOUT pin)
• OCD2 bit in OCD register = 0 (XIN clock selected)
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the CM3 register.
CM30 bit (Wait Control Bit)
When the CM30 bit is set to 1 (MCU enters wait mode), the CPU clock stops (wait mode). Since the XIN clock,
XCIN clock, and the on-chip oscillator clock do not stop, the peripheral functions using these clocks continue
operating.
The MCU exits wait mode by a reset or peripheral function interrupt. If the MCU enters wait mode while the I
flag is set to 0 (maskable interrupt disabled), it resumes executing the instruction immediately after the
instruction to set the CM30 bit to 1 when exiting wait mode. If the MCU enters wait mode with the WAIT
instruction, interrupt handling is performed by the CPU when exiting wait mode.
REJ09B0458-0010 Rev.0.10
Page 94 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.4
Oscillation Stop Detection Register (OCD)
Address 000Ch
Bit
b7
Symbol
—
After Reset
0
Bit
b0
9. Clock Generation Circuit
b6
—
0
b5
—
0
b4
—
0
b3
OCD3
0
b2
OCD2
1
b1
OCD1
0
b0
OCD0
0
Symbol
Bit Name
Function
OCD0 Oscillation stop detection enable bit (6) 0: Oscillation stop detection function disabled (1)
1: Oscillation stop detection function enabled
OCD1 Oscillation stop detection interrupt
0: Disabled (1)
enable bit
1: Enabled
OCD2 System clock select bit (3)
0: XIN clock selected (6)
1: On-chip oscillator clock selected (2)
0: XIN clock oscillates
OCD3 Clock monitor bit (4, 5)
1: XIN clock stops
—
Reserved bits
Set to 0.
—
—
—
b1
b2
b3
b4
b5
b6
b7
R/W
R/W
R/W
R/W
R
R/W
Notes:
1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or lowspeed on-chip oscillator mode (XIN clock stops).
2. If the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator
on).
3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if XIN clock oscillation stop is detected
while bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains
unchanged even when set to 0 (XIN clock selected).
4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled).
5. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
6. Refer to Figure 9.10 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock for the switching procedure when the XIN clock re-oscillates after detecting oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.
9.2.5
High-Speed On-Chip Oscillator Control Register 7 (FRA7)
Address 0015h
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 32 MHz frequency correction data is stored.
The frequency can be adjusted by transferring this value to the FRA3 register and by
transferring the correction value in the FRA6 register to the FRA1 register.
REJ09B0458-0010 Rev.0.10
Page 95 of 572
Apr 01, 2008
R/W
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.6
9. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 0 (FRA0)
Address 0023h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
—
0
b3
FRA03
0
b2
—
0
b1
FRA01
0
b0
FRA00
0
Bit
b0
Symbol
Bit Name
FRA00 High-speed on-chip oscillator enable bit
Function
0: High-speed on-chip oscillator off
1: HIgh-speed on-chip oscillator on
High-speed on-chip oscillator select bit (1) 0: Low-speed on-chip oscillator selected (2)
1: High-speed on-chip oscillator selected
Reserved bits
Set to 0.
fOCO128 clock select bit
0: fOCO-S divided by 128 selected
1: fOCO-F divided by 128 selected
Reserved bits
Set to 0.
R/W
R/W
b1
FRA01
R/W
b2
b3
—
FRA03
b4
b5
b6
b7
—
—
—
—
R/W
R/W
R/W
Notes:
1. Change the FRA01 bit in the following conditions.
• FRA00 = 1 (high-speed on-chip oscillator on)
• The CM14 bit in the CM1 register = 0 (low-speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register:
All division mode can be set when VCC = 3.0 V to 5.5 V 000b to 111b
Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V
010b to 111b (divide-by-4 or more)
Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V
110b to 111b (divide-by-8 or more)
2. When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (highspeed on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA0 register.
9.2.7
High-Speed On-Chip Oscillator Control Register 1 (FRA1)
Address 0024h
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 The frequency of the high-speed on-chip oscillator can be adjusted by setting as follows:
40 MHz:
FRA3 = value after reset
36.864 MHz: Transfer the value in the FRA4 register to the FRA1 register and the value in
the FRA5 register to the FRA3 register.
32 MHz:
Transfer the value in the FRA6 register to the FRA1 register and the value in
the FRA7 register to the FRA3 register.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA1 register.
REJ09B0458-0010 Rev.0.10
Page 96 of 572
Apr 01, 2008
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.8
9. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 2 (FRA2)
Address 0025h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b6
—
0
b5
—
0
b4
—
0
b3
—
0
Symbol
Bit Name
FRA20 High-speed on-chip oscillator frequency
FRA21 switching bit
FRA22
b2
FRA22
0
b1
FRA21
0
b0
FRA20
0
Function
Division selection
These bits select the division ratio for the highspeed on-chip oscillator clock.
R/W
R/W
R/W
R/W
b2 b1 b0
b3
b4
b5
b6
b7
—
—
—
—
—
0 0 0: Divide-by-2 mode
0 0 1: Divide-by-3 mode
0 1 0: Divide-by-4 mode
0 1 1: Divide-by-5 mode
1 0 0: Divide-by-6 mode
1 0 1: Divide-by-7 mode
1 1 0: Divide-by-8 mode
1 1 1: Divide-by-9 mode
Set to 0.
Reserved bits
R/W
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA2 register.
9.2.9
Clock Prescaler Reset Flag (CPSRF)
Address 0028h
Bit
b7
Symbol CPSR
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
Symbol
Bit Name
—
Reserved bits
—
—
—
—
—
—
CPSR Clock prescaler reset flag
REJ09B0458-0010 Rev.0.10
Page 97 of 572
Apr 01, 2008
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
—
0
Function
Set to 0.
Setting this bit to 1 initializes the clock prescaler.
(When read, the content is 0)
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.10
9. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 4 (FRA4)
Address 0029h
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 36.864 MHz frequency correction data is stored.
The frequency can be adjusted by transferring this value to the FRA1 register and by
transferring the correction value in the FRA5 register to the FRA3 register.
9.2.11
High-Speed On-Chip Oscillator Control Register 5 (FRA5)
Address 002Ah
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 36.864 MHz frequency correction data is stored.
The frequency can be adjusted by transferring this value to the FRA3 register and by
transferring the correction value in the FRA4 register to the FRA1 register.
9.2.12
R/W
R
High-Speed On-Chip Oscillator Control Register 6 (FRA6)
Address 002Bh
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 32 MHz frequency correction data is stored.
The frequency can be adjusted by transferring this value to the FRA1 register and by
transferring the correction value in the FRA7 register to the FRA3 register.
9.2.13
R/W
R
R/W
R
High-Speed On-Chip Oscillator Control Register 3 (FRA3)
Address 002Fh
Bit
b7
b6
Symbol
—
—
After Reset When shipping
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Bit
Function
b7-b0 The frequency of the high-speed on-chip oscillator can be adjusted by setting as follows:
40 MHz:
FRA3 = value after reset
36.864 MHz: Transfer the value in the FRA4 register to the FRA1 register and the value in
the FRA5 register to the FRA3 register.
32 MHz:
Transfer the value in the FRA6 register to the FRA1 register and the value in
the FRA7 register to the FRA3 register.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the FRA3 register.
REJ09B0458-0010 Rev.0.10
Page 98 of 572
Apr 01, 2008
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.2.14
9. Clock Generation Circuit
Voltage Detect Register 2 (VCA2)
Address 0034h
Bit
b7
b6
b5
b4
b3
Symbol VCA27
VCA26
VCA25
VCA24
VCA23
After Reset The LVDAS bit in the OFS register is set to 1.
0
0
0
0
0
After Reset The LVDAS bit in the OFS register is set to 0.
0
0
1
0
0
Bit
b0
b5
Symbol
Bit Name
VCA20 Internal power low consumption
enable bit (1)
VCA21 Comparator A1 reference voltage
input select bit
VCA22 LVCMP1 comparison voltage
external input select bit
VCA23 Comparator A2 reference voltage
input select bit
VCA24 LVCMP2 comparison voltage
external input select bit
VCA25 Voltage detection 0 enable bit (3)
b6
VCA26
b7
VCA27
b1
b2
b3
b4
Voltage detection 1/comparator A1
enable bit (4)
Voltage detection 2/comparator A2
enable bit (5)
b2
VCA22
b1
VCA21
b0
VCA20
0
0
0
0
0
0
Function
0: Low consumption disabled
1: Low consumption enabled (2)
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
1: LVCMP1 pin input voltage
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
(Vdet2_0)
1: LVCMP2 pin input voltage (Vdet2_EXT)
0: Voltage detection 0 circuit disabled
1: Voltage detection 0 circuit enabled
0: Voltage detection 1/comparator A1 circuit disabled
1: Voltage detection 1/comparator A1 circuit enabled
0: Voltage detection 2/comparator A2 circuit disabled
1: Voltage detection 2/comparator A2 circuit enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in
Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit.
2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
3. To use voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation.
4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit
to 1.
After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit
starts operation.
5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27
bit to 1.
After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit
starts operation.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register.
REJ09B0458-0010 Rev.0.10
Page 99 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
Exit wait mode by interrupt
Procedure for enabling reduced internal
power consumption using VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (5)
VCA20 ← 0
(internal power low consumption disabled) (2)
(This is automatically set when exiting wait mode)
Step (2)
Stop XIN clock and
high-speed on-chip oscillator clock
Step (6)
Start XIN clock
or high-speed on-chip oscillator clock
Step (3)
VCA20 ← 1
(internal power low consumption enabled) (2, 3)
Step (7)
(Wait until XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Step (4)
Enter wait mode (4)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (5)
VCA20 ← 0
(internal power low consumption disabled) (2)
Start XIN clock or
high-speed on-chip oscillator clock
Step (1)
Step (6)
(Wait until XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Step (2)
Step (7)
Stop XIN clock and
high-speed on-chip oscillator clock
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (3)
Step (8)
VCA20 ← 1
(internal power low consumption enabled) (2, 3)
If it is necessary to start
the high-speed clock or
high-speed on-chip oscillator
during the interrupt routine,
execute steps (6) to (7)
in the routine.
Interrupt handling
Enter low-speed clock mode or
low-speed on-chip oscillator mode
If the high-speed clock or
high-speed on-chip oscillator
starts during the interrupt
routine, execute steps (1) to
(3) at the end of the routine.
Interrupt handling completed
Notes:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When the MCU enters wait mode, follow 9.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 9.3
Procedure for Reducing Internal Power Consumption Using VCA20 bit
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R8C/32A Group
9. Clock Generation Circuit
The clocks generated by the clock generation circuits are described below.
9.3
XIN Clock
The XIN clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU
and peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between
pins XIN and XOUT. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XOUT pin.
Figure 9.4 shows Examples of XIN Clock Connection Circuit.
During and after a reset, the XIN clock stops.
After setting the CM13 bit in the CM1 register to 1 (XIN-XOUT pin), the XIN clock starts oscillating when the
CM05 bit in the CM0 register is set to 0 (XIN clock oscillates). After the XIN clock oscillation stabilizes, the XIN
clock is used as the CPU clock source when the OCD2 bit in the OCD register is set to 0 (XIN clock selected).
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the
OCD2 bit is set to 1 (on-chip oscillator clock selected).
When an externally generated clock is input to the XOUT pin, the XIN clock does not stop even if the CM05 bit is
set to 1. If necessary, use an external circuit to stop the clock.
In stop mode, all clocks including the XIN clock stop. Refer to 9.7 Power Control for details.
• When CM05 bit in CM0 register
is set to 0 (XIN clock oscillates)
and CM13 bit in CM1 register is
set to 1 (XIN-XOUT pin)
• When CM05 bit in CM0 register
is set to 1 (XIN clock stops),
CM11 bit in CM1 register is set
to 1 (internal feedback resistor
disabled), and the CM13 bit is
set to 1 (XIN-XOUT pin)
MCU
(on-chip feedback resistor)
MCU
(on-chip feedback resistor)
XIN
XIN
XOUT
XOUT
Open
Rf
CIN
(1)
Rd (1)
COUT
Externally generated clock
VCC
VSS
Ceramic resonator external circuit
External clock input circuit
Note:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity settings. Use the values recommended by the oscillator manufacturer.
If the oscillator manufacturer's datasheet specifies that a feedback resistor be added to the chip
externally, insert a feedback resistor between XIN and XOUT following the instructions.
Figure 9.4
Examples of XIN Clock Connection Circuit
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.4
9. Clock Generation Circuit
On-Chip Oscillator Clock
The on-chip oscillator clock is supplied by the on-chip oscillator (high-speed on-chip oscillator or low-speed onchip oscillator). This clock is selected by the FRA01 bit in the FRA0 register.
9.4.1
Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-S, and fOCO128.
After a reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 1 (no
division) is selected as the CPU clock.
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating and supplies the necessary clock for the MCU.
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
9.4.2
High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-F, fOCO40M, and fOCO128.
To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:
• All division mode can be set when VCC = 3.0 V to 5.5 V
000b to 111b
• Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V
010b to 111b (divide by 4 or more)
• Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V
110b to 111b (divide by 8 or more)
After a reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on).
Frequency correction data is stored in registers FRA4 to FRA7.
To adjust the frequency of the high-speed on-chip oscillator clock to 36.864 MHz, first transfer the correction
value in the FRA4 register to the FRA1 register and the correction value in the FRA5 register to the FRA3
register before using the values. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be
0% when the serial interface is used in UART mode (refer to Table 21.8 and Table 22.8 Bit Rate Setting
Example in UART Mode).
To adjust the frequency of the high-speed on-chip oscillator clock to 32 MHz, first transfer the correction value
in the FRA6 register to the FRA1 register and the correction value in the FRA7 register to the FRA3 register
before using the values.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.5
9. Clock Generation Circuit
XCIN Clock
The XCIN clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the
CPU and peripheral function clocks. The XCIN clock oscillation circuit is configured by connecting a resonator
between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor,
which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed
by the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to
the XCIN pin.
Figure 9.5 shows Examples of XCIN Clock Connection Circuits.
During and after a reset, the XCIN clock stops.
After setting the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin), the XCIN clock starts oscillating when
the CM03 bit in the CM0 register is set to 1 (XCIN clock oscillates). After the XCIN clock oscillation stabilizes,
the XCIN clock is used as the CPU clock source when the CM07 bit in the CM0 register is set to 1 (XCIN clock).
To input an externally generated clock to the XCIN pin, also set the CM04 bit in the CM0 register to 1 (XCINXCOUT pin). Leave the XCOUT pin open at this time.
This MCU has an on-chip feedback resistor, which can be disabled/enabled by the CM12 bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 9.7 Power Control for details.
• When CM03 bit in CM0 register is set
to 0 (XCIN clock oscillates) and CM04
bit is set to 1 (XCIN-XCOUT pin)
• When CM03 bit in CM0 register is set
to 1 (XCIN clock stops) and CM04 bit
is set to 1 (XCIN-XCOUT pin)
MCU
(on-chip feedback resistor)
MCU
(on-chip feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
Rf (1)
CIN
Rd (1)
COUT
Externally generated clock
VCC
VSS
External crystal oscillator circuit
External clock input circuit
Note:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on
the oscillator and the oscillation drive capacity setting. Use the value recommended by the oscillator
manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable. If the oscillator
manufacturer's datasheet specifies that a feedback resistor be added to the chip externally,
insert a feedback resistor between XCIN and XCOUT following the instructions.
Figure 9.5
Examples of XCIN Clock Connection Circuits
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.6
9. Clock Generation Circuit
CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 9.1 Clock Generation Circuit (With XIN and XCIN Pins Shared).
9.6.1
System Clock
The system clock is the clock source for the CPU and peripheral function clocks. The XIN clock, the XCIN
clock, or the on-chip oscillator clock can be selected.
9.6.2
CPU Clock
The CPU clock is an operating clock for the CPU and the watchdog timer.
The system clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. Use the CM06 bit in the
CM0 register and bits CM16 and CM17 in the CM1 register to select the value of the division.
Also, use the XCIN clock while the XCIN clock oscillation stabilizes.
After a reset, the low-speed on-chip oscillator clock divided by 1 (no division) is used as the CPU clock.
When the MCU enters stop mode, the CM06 bit is set to 1 (divide-by-8 mode). To enter stop mode, set the
CM35 bit in the CM3 register to 0 (settings of CM06 in CM0 register and bits CM16 and CM17 in CM1
register enabled).
9.6.3
Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is an operating clock for the peripheral functions.
The fi (i = 1, 2, 4, 8, and 32) clock is generated by the system clock divided by i. It is used for timers RA, RB,
RC, RE, the serial interface, and the A/D converter.
If the MCU enters wait mode after the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops
in wait mode), the fi clock stops.
9.6.4
fOCO
fOCO is an operating clock for the peripheral functions.
This clock runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer
RA.
In wait mode, the fOCO clock does not stop.
9.6.5
fOCO40M
fOCO40M is used as the count source for timer RC.
This clock is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1.
In wait mode, the fOCO40M clock does not stop.
This clock can be used with supply voltage VCC = 3.0 to 5.5 V.
9.6.6
fOCO-F
fOCO-F is used as the count source for timer RC and the A/D converter.
fOCO-F is a clock generated by the high-speed on-chip oscillator and divided by i (i = 2, 3, 4, 5, 6, 7, 8, and 9;
divide ratio selected by the FRA2 register). This clock is supplied by setting the FRA00 bit to 1.
In wait mode, the fOCO-F clock does not stop.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.6.7
9. Clock Generation Circuit
fOCO-S
fOCO-S is an operating clock for the voltage detection circuit.
This clock is generated by the low-speed on-chip oscillator and supplied by setting the CM14 bit to 0 (lowspeed on-chip oscillator on).
In wait mode, the fOCO-S clock does not stop.
9.6.8
fOCO128
fOCO128 is a clock generated by dividing fOCO-S or fOCO-F by 128. When the FRA03 bit is set to 0, fOCOS divided by 128 is selected. When this bit is set to 1, fOCO-F divided by 128 is selected.
fOCO128 is configured as the capture signal used in the TRCGRA register for timer RC.
9.6.9
fC, fC2, fC4, and fC32
fC, fC2, fC4, and fC32 are used for timers RA, RE, and the serial interface.
Use theses clocks while the XCIN clock oscillation stabilizes.
9.6.10
fOCO-WDT
fOCO-WDT is an operating clock for the watchdog timer.
This clock is generated by the low-speed on-chip oscillator for the watchdog timer and supplied by setting the
CSPRO bit in the CSPR register to 1 (count source protect mode enabled).
In count source protection mode for the watchdog timer, the fOCO-WDT clock does not stop.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.7
9. Clock Generation Circuit
Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
9.7.1
Standard Operating Mode
Standard operating mode is further separated into four modes.
In standard operating mode, the CPU and peripheral function clocks are supplied to operate the CPU and the
peripheral functions. Power consumption control is enabled by controlling the CPU clock frequency. The
higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the
more power consumption decreases. If unnecessary oscillator circuits stop, power consumption is further
reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation stabilizes before the MCU exits.
Table 9.2
Settings and Modes of Clock Associated Bits
Modes
OCD
Register
OCD2
High-speed
clock mode
Low-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
0
0
0
0
0
−
−
−
−
−
1
1
1
1
1
1
1
1
1
1
CM1 Register
FRA0 Register
CM17,
CM14 CM13 CM07 CM06 CM05 CM04 CM03 FRA01 FRA00
CM16
00b
−
1
0
0
0
−
−
−
−
01b
−
1
0
0
0
−
−
−
−
10b
−
1
0
0
0
−
−
−
−
−
−
1
0
1
0
−
−
−
−
11b
−
1
0
0
0
−
−
−
−
00b
−
−
1
0
−
1
0
−
−
01b
−
−
1
0
−
1
0
−
−
10b
−
−
1
0
−
1
0
−
−
−
−
−
1
1
−
1
0
−
−
11b
−
−
1
0
−
1
0
−
−
00b
−
−
0
0
−
−
−
1
1
01b
−
−
0
0
−
−
−
1
1
10b
−
−
0
0
−
−
−
1
1
−
−
−
0
1
−
−
−
1
1
11b
−
−
0
0
−
−
−
1
1
00b
0
−
0
0
−
−
−
0
−
01b
0
−
0
0
−
−
−
0
−
10b
0
−
0
0
−
−
−
0
−
−
0
−
0
1
−
−
−
0
−
11b
0
−
0
0
−
−
−
0
−
−: Indicates that either 0 or 1 can be set.
REJ09B0458-0010 Rev.0.10
Page 106 of 572
CM0 Register
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.7.1.1
9. Clock Generation Circuit
High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the CM14 bit is set to 0
(low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip
oscillator on), fOCO can be used for timer RA.
Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC.
If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection
circuit.
9.7.1.2
Low-Speed Clock Mode
The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock.
In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip
oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read
mode enabled).
Also, if the FRA00 bit is set to 1, fOCO40M can be used for timer RC.
If the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection
circuit.
To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting
the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled).
To reduce the power consumption, refer to 31. Reducing Power Consumption.
9.7.1.3
High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 is used as the CPU clock. If the FRA00 bit is set to 1,
fOCO40M can be used for timer RC.
Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection
circuit.
9.7.1.4
Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) and the FRA01 bit in the FRA0
register is set to 0, the low-speed on-chip oscillator is used as the on-chip oscillator clock. At this time, the onchip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 is used as the CPU clock. The on-chip oscillator
clock is also the clock source for the peripheral function clocks. If the FRA00 bit is set to 1, fOCO40M can be
used for timer RC.
Also, if the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the voltage detection
circuit.
In this mode, low consumption operation is enabled by stopping the XIN clock and the high-speed on-chip
oscillator, and by setting the FMR27 bit in the FMR2 register to 1 (flash memory low-consumption-current read
mode enabled).
To enter wait mode from low-speed clock mode, lower consumption current in wait mode is enabled by setting
the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled).
To reduce the power consumption, refer to 31. Reducing Power Consumption.
REJ09B0458-0010 Rev.0.10
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.7.2
9. Clock Generation Circuit
Wait Mode
Since the CPU clock stops in wait mode, the CPU operating with the CPU clock and the watchdog timer when
count source protection mode is disabled stop. Since the XIN clock, XCIN clock, and on-chip oscillator clock
do not stop, the peripheral functions using these clocks continue operating.
9.7.2.1
Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop
in wait mode. This reduces power consumption.
9.7.2.2
Entering Wait Mode
The MCU enters wait mode by executing the WAIT instruction or setting the CM30 bit in the CM3 register to 1
(MCU enters wait mode).
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction or setting the CM30 bit in the CM3 register to 1(MCU enters wait mode).
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),
current consumption is not reduced because the CPU clock does not stop.
9.7.2.3
Pin Status in Wait Mode
The I/O port retains the status immediately before the MCU enters wait mode.
REJ09B0458-0010 Rev.0.10
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Under development
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R8C/32A Group
9.7.2.4
9. Clock Generation Circuit
Exiting Wait Mode
The MCU exits wait mode by a reset or peripheral function interrupt.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), the peripheral function interrupts other than A/D conversion
interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait
mode), the peripheral functions using the peripheral function clock stop and the peripheral functions operating
with external signals or the on-chip oscillator clock can be used to exit wait mode.
Table 9.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 9.3
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt
Serial interface interrupt
CM02 = 0
CM02 = 1
Usable when operating with internal Usable when operating with external
or external clock
clock
Usable in all modes
(Do not use)
Synchronous serial
communication unit interrupt
/ I2C bus interface interrupt
Key input interrupt
A/D conversion interrupt
Timer RA interrupt
Usable
(Do not use)
Usable in all modes
Timer RB interrupt
Timer RC interrupt
Timer RE interrupt
Usable in all modes
Usable in all modes
Usable in all modes
INT interrupt
Usable
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Oscillation stop detection
interrupt
Comparator A1 interrupt
Comparator A2 interrupt
Usable
Usable
Usable
Usable (INT0, INT1, INT3 can be
used if there is no filter.)
Usable
Usable
(Do not use)
Usable
Usable
Usable
Usable
REJ09B0458-0010 Rev.0.10
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Usable
(Do not use)
Usable if there is no filter in event
counter mode.
Usable by selecting fOCO, fC, or
fC32 as count source.
(Do not use)
(Do not use)
Usable when operating in real time
clock mode
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
Figure 9.6 shows the Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register is
Set to 1 (MCU Enters Wait Mode).
To use a peripheral function interrupt to exit wait mode, set up the following before setting the CM30 bit to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
(2) Operate the peripheral function to be used for exiting wait mode.
When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the VCA20 bit in the VCA2 register, as shown in Figure 9.6.
The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU
exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits
CM16 and CM17 in the CM1 register automatically change.
FMR0 Register
VCA2 Register
FMSTP Bit
VCA20 Bit
0
(flash memory
operates)
1
(flash memory
stops)
Internal Power
Stabilization Time
(T0)
0
(internal power
low consumption disabled)
0 µs
1
(internal power
low consumption enabled)
100 µs (max.)
0
(internal power
low consumption disabled
0 µs
1
(internal power
low consumption enabled)
100 µs (max.)
Wait mode
Time until
Flash Memory
Activation (T1)
Time until
CPU Clock
Supply (T2)
Time for
Interrupt
Sequence (T3)
Remarks
Period of system clock Period of CPU clock Period of CPU clock
× 1 cycle + 60 µs
× 2 cycles
× 20 cycles
(max.)
The total of T0
to T3 is the time
from wait mode to
interrupt routine
execution.
Period of system clock
× 1 cycle
Same as above
Same as above
T0
T1
T2
T3
Internal power
stabilization time
Flash memory
activation sequence
CPU clock
restart sequence
Interrupt sequence
100 µs (max.)
Interrupt request generation
Figure 9.6
Time from Wait Mode to Interrupt Routine Execution after CM30 Bit in CM3 Register
is Set to 1 (MCU Enters Wait Mode)
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R8C/32A Group
9. Clock Generation Circuit
Figure 9.7 shows the Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is Executed.
To use a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
When the MCU exits by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the VCA20 bit in the VCA2 register, as shown in Figure 9.7.
The clock set by bits CM35, CM36, and CM37 in the CM3 register is used as the CPU clock when the MCU
exits wait mode by a peripheral function interrupt. At this time, the CM06 bit in the CM0 register and bits
CM16 and CM17 in the CM1 register automatically change.
FMR0 Register
VCA2 Register
FMSTP Bit
VCA20 Bit
0
(flash memory
operates)
1
(flash memory
stops)
Internal Power
Stabilization Time
(T0)
0
(internal power
low consumption disabled)
0 µs
1
(internal power
low consumption enabled)
100 µs (max.)
0
(internal power
low consumption disabled
0 µs
1
(internal power
low consumption enabled)
Wait mode
Time until
Flash Memory
Activation (T1)
Time until
CPU Clock
Supply (T2)
Time for
Interrupt
Sequence (T3)
Remarks
Period of system clock Period of CPU clock Period of CPU clock
× 1 cycle + 60 µs
× 2 cycles
× 20 cycles
(max.)
The total of T0
to T3 is the time
from wait mode to
interrupt routine
execution.
Period of system clock
× 1 cycle
Same as above
Same as above
T0
T1
T2
T3
Internal power
stabilization time
Flash memory
activation sequence
100 µs (max.)
CPU clock
restart sequence
Interrupt sequence
100 µs (max.)
Interrupt request generation
Figure 9.7
Time from Wait Mode to Interrupt Routine Execution after WAIT instruction is
Executed
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.7.3
9. Clock Generation Circuit
Stop Mode
Since all oscillator circuits except fOCO-WDT stop in stop mode, the CPU and peripheral function clocks stop
and the CPU and the peripheral functions operating with these clocks also stop. The least power required to
operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of
internal RAM is retained.
The peripheral functions clocked by external signals continue operating.
Table 9.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 9.4
Interrupts to Exit Stop Mode and Usage Conditions
Interrupt
Key input interrupt
Usage Conditions
−
INT0, INT1, INT3 interrupt Usable if there is no filter
Timer RA interrupt
Usable if there is no filter when external pulse is counted in event counter
mode
Serial interface interrupt
When external clock selected
Voltage monitor 1 interrupt Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1)
Voltage monitor 2 interrupt Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1)
Comparator A1 interrupt
Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1)
Comparator A2 interrupt
Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1)
9.7.3.1
Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode).
To use stop mode, set the following before the MCU enters stop mode:
• Bits OCD1 to OCD0 in the OCD register = 00b
• CM35 bit in CM3 register = 0 (settings of CM06 bit in CM0 register and bits CM16 and CM17 in CM1
register enabled)
9.7.3.2
Pin Status in Stop Mode
The I/O port retains the status before the MCU enters wait mode.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pin), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in an input status.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.7.3.3
9. Clock Generation Circuit
Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 9.8 shows the Time from Stop Mode to Interrupt Routine Execution.
To use a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for
exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting stop mode.
When the MCU exits stop mode by a peripheral function interrupt, the interrupt sequence is executed when
an interrupt request is generated and the CPU clock supply starts.
The clock used immediately before stop mode divided by 8 is used as the CPU clock when the MCU exits stop
mode by a peripheral function interrupt. To enter stop mode, set the CM35 bit in the CM3 register to 0 (settings
of CM06 bit in CM0 register and bits CM16 and CM17 in CM1 register enabled)
FMR0 Register
Internal Power
Stabilization Time (T0)
FMSTP Bit
0
(flash memory operates)
100 µs (max.)
1
(flash memory stops)
100 µs (max.)
Stop mode
Time until
Flash Memory
Activation (T2)
Time until
CPU Clock
Supply (T3)
T0
T1
T2
T3
T4
Internal power
stabilization time
Oscillation time of CPU clock
source used immediately
before stop mode
Flash memory
activation sequence
CPU clock
restart sequence
Interrupt sequence
Time from Stop Mode to Interrupt Routine Execution
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Remarks
Period of system clock Period of CPU clock Period of CPU clock
The total of T0
× 1 cycle + 60 µs
× 2 cycles
× 20 cycles
to T4 is the time
(max.)
from wait mode to
interrupt routine
Period of system clock
Same as above
Same as above
execution.
× 1 cycle
100 ms (max.)
Interrupt request generation
Figure 9.8
Time for
Interrupt
Sequence (T4)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
Figure 9.9 shows the State Transitions in Power Control Mode.
State Transitions in Power Control Mode
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
CM03 = 0
CM04 = 1
CM07 = 1
FRA00 = 1
FRA01 = 1
CM03 = 0
CM04 = 1
CM07 = 1
High-speed clock mode
Low-speed clock mode
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
CM14 = 0
FRA01 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
Interrupt
High-speed on-chip oscillator mode
WAIT instruction
CM10 = 1
Interrupt
Wait mode
Stop mode
CPU operation stops
All oscillators stop
(except fOCO-WDT)
CM03, CM04, CM05, CM07: Bits in CM0 register
CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
State Transitions in Power Control Mode
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CM04 = 1
CM07 = 1
CM03 = 0
CM03 = 0
CM04 = 1
CM07 = 1
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
Figure 9.9
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
Apr 01, 2008
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.8
9. Clock Generation Circuit
Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit.
The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 9.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the MCU is placed in the
following state if the XIN clock stops.
• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated
Table 9.5
Specifications of Oscillation Stop Detection Function
Item
Oscillation stop detection clock and
frequency bandwidth
Enabled condition for oscillation stop
detection function
Operation at oscillation stop detection
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Specification
f(XIN) ≥ 2 MHz
Bits OCD1 to OCD0 set to 11b
Oscillation stop detection interrupt generated
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.8.1
9. Clock Generation Circuit
How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
•
•
•
•
•
monitor 2 interrupt, and the watchdog timer interrupt. To use the oscillation stop detection interrupt and
watchdog timer interrupt, the interrupt source needs to be determined.
Table 9.6 lists the Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, or Voltage Monitor 2 Interrupt. Figure 9.11 shows an Example of Determining Interrupt
Sources for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.
When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source for the CPU clock
and the peripheral functions by a program.
Figure 9.10 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock.
To enter wait mode while the oscillation stop detection function is used, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 to 00b to stop or start the XIN clock by a program (select stop mode or
change the CM05 bit).
This function cannot be used when the XIN clock frequency is below 2 MHz. In this case, set bits OCD1 to
OCD0 to 00b.
To use the low-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral
functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip
oscillator selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chip oscillator clock as the clock source for the CPU clock and the peripheral
functions after detecting the oscillation stop, first set the FRA00 bit to 1 (high-speed on-chip oscillator
oscillates) and the FRA01 bit to 1 (high-speed on-chip oscillator selected). Then set bits OCD1 to OCD0 to
11b.
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 9.6
9. Clock Generation Circuit
Determination of Interrupt Sources for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, or Voltage Monitor 2 Interrupt
Generated Interrupt Source
Bit Indicating Interrupt Source
Oscillation stop detection
(a) OCD3 bit in OCD register = 1
((a) or (b))
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer
VW2C3 bit in VW2C register = 1
Voltage monitor 1
VW1C2 bit in VW1C register = 1
Voltage monitor 2
VW2C2 bit in VW2C register = 1
Switch to XIN clock
NO
Check several times
whether OCD3 bit is set to 0
(XIN clock oscillates)
YES
Set bits OCD1 to OCD0 to 00b
Set OCD2 bit to 0
(XIN clock selected)
End
OCD3 to OCD0: Bits in OCD register
Figure 9.10
Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
9. Clock Generation Circuit
Determination of
Interrupt sources
OCD3 = 1?
(XIN clock stops)
YES
NO
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock
selected as system clock)?
NO
YES
VW2C3 = 1?
(watchdog timer underflow)
NO
YES
VW2C2 = 1?
(Vdet2 passed)
NO
YES
Set OCD1 bit to 0
(oscillation stop detection
interrupt disabled) (1)
To oscillation stop detection
interrupt routine
To watchdog timer
interrupt routine
To voltage monitor 2
interrupt routine
To voltage monitor 1
interrupt routine
Note:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C2, VW2C3: Bits in VW2C register
Figure 9.11
Example of Determining Interrupt Sources for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
9.9
9. Clock Generation Circuit
Notes on Clock Generation Circuit
9.9.1
Stop Mode
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10
bit to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001:
NOP
NOP
NOP
NOP
9.9.2
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
Wait Mode
To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode
disabled) and then execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT
instruction and the program stops. Insert at least four NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
1,FMR0
FSET
I
WAIT
NOP
NOP
NOP
NOP
9.9.3
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is below 2 MHz, set bits
OCD1 to OCD0 to 00b.
9.9.4
Oscillation Circuit Constants
Consult the oscillator manufacturer to determine the optimal oscillation circuit constants for the user system.
To use the MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled) and connect the feedback resistor to the chip externally.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
10. Protection
10. Protection
The protection function protects important registers from being easily overwritten if a program runs out of control.
The registers protected by the PRCR register are as follows:
• Registers protected by PRC0 bit: Registers CM0, CM1, CM3, OCD, FRA0, FRA1, FRA2, and FRA3
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC3 bit: Registers OCVREFCR, VCA2, VD1LS, VW0C, VW1C, and VW2C
10.1
10.1.1
Register
Protect Register (PRCR)
Address 000Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b6
—
0
b5
—
0
Symbol
Bit Name
PRC0 Protect bit 0
b4
—
0
b3
PRC3
0
b2
—
0
b1
PRC1
0
b0
PRC0
0
b1
PRC1
Protect bit 1
b2
b3
—
PRC3
Reserved bit
Protect bit 3
b4
b5
b6
b7
—
—
—
—
Reserved bits
Function
Enables writing to registers CM0, CM1, CM3, OCD, FRA0,
FRA1, FRA2, and FRA3.
0: Write disabled
1: Write enabled
Enables writing to registers PM0 and PM1.
0: Write disabled
1: Write enabled
Set to 0.
Enables writing to registers OCVREFCR, VCA2, VD1LS,
VW0C, VW1C, and VW2C.
0: Write disabled
1: Write enabled
Set to 0.
Reserved bits
When read, the content is 0.
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Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11. Interrupts
11. Interrupts
11.1
Overview
11.1.1
Types of Interrupts
Figure 11.1 shows the Types of Interrupts.
Software
(non-maskable interrupts)
Interrupts
Special
(non-maskable interrupts)
Hardware
Peripheral function (1)
(maskable interrupts)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage monitor 1/comparator A1 (3)
Voltage monitor 2/comparator A2 (3)
Single step (2)
Address break (2)
Address match
Notes:
1. Peripheral function interrupts are generated by the peripheral functions in the MCU.
2. Do not use these interrupts. This is provided exclusively for use by development tools.
3. A non-maskable or maskable interrupt can be selected by bits IRQ1SEL and IRQ2SEL in the CMPA register.
Figure 11.1
Types of Interrupts
• Maskable interrupts:
• Non-maskable interrupts:
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These interrupts are enabled or disabled by the interrupt enable flag (I flag).
The interrupt priority can be changed based on the interrupt priority level.
These interrupts are not enabled or disabled by the interrupt enable flag (I flag).
The interrupt priority cannot be changed based on the interrupt priority level.
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.1.2
11. Interrupts
Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
11.1.2.1
Undefined Instruction Interrupt
An undefined instruction interrupt is generated when the UND instruction is executed.
11.1.2.2
Overflow Interrupt
An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are as follows:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.
11.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
11.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to
63 can be specified with the INT instruction. Because some software interrupt numbers are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by
executing the INT instruction.
For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and the U
flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack
when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change
state during instruction execution, and the selected SP is used.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.1.3
11. Interrupts
Special Interrupts
Special interrupts are non-maskable.
11.1.3.1
Watchdog Timer Interrupt
A watchdog timer interrupt is generated by the watchdog timer. For details, refer to 14. Watchdog Timer.
11.1.3.2
Oscillation Stop Detection Interrupt
An oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 9. Clock Generation Circuit.
11.1.3.3
Voltage Monitor 1/Comparator A1 Interrupt
A voltage monitor 1/comparator A1 interrupt is generated by the voltage detection circuit or the comparator A.
A non-maskable or maskable interrupt can be selected by IRQ1SEL bit in the CMPA register. For details of the
voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28.
Comparator A.
11.1.3.4
Voltage Monitor 2/Comparator A2 Interrupt
A voltage monitor 2/comparator A2 interrupt is generated by the voltage detection circuit or the comparator A.
A non-maskable or maskable interrupt can be selected by IRQ2SEL bit in the CMPA register. For details of the
voltage detection circuit, refer to 6. Voltage Detection Circuit and for details of the comparator A, refer to 28.
Comparator A.
11.1.3.5
Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are provided exclusively for use by development tools.
11.1.3.6
Address Match Interrupt
An address match interrupt is generated immediately before executing an instruction that is stored at an address
indicated by registers RMAD0 to RMAD1 if the AIER0 bit in the AIER0 register or the AIER1 bit in the
AIER1 register is set to 1 (address match interrupt enabled).
For details of the address match interrupt, refer to 11.6 Address Match Interrupt.
11.1.4
Peripheral Function Interrupts
A peripheral function interrupt is generated by a peripheral function in the MCU. Peripheral function interrupts
are maskable. Refer to Table 11.2 Relocatable Vector Tables for sources of the corresponding peripheral
function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral
functions.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.1.5
11. Interrupts
Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 11.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low-order address
Middle-order address
Vector address (H)
Figure 11.2
11.1.5.1
0000
High-order address
0000
0000
Interrupt Vector
Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 11.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 30.3 Functions to Prevent Flash Memory from being Rewritten.
Table 11.1
Fixed Vector Tables
Interrupt Source
Undefined instruction
Overflow
BRK instruction
Address match
Vector Addresses
Remarks
Reference
Address (L) to (H)
0FFDCh to 0FFDFh Interrupt with
R8C/Tiny Series
UND instruction
Software Manual
0FFE0h to 0FFE3h Interrupt with
INTO instruction
0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
0FFE8h to 0FFEBh
11.6 Address Match
Interrupt
0FFECh to 0FFEFh
Single step (1)
0FFF0h to 0FFF3h
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1/comparator A1,
Voltage monitor 2/comparator A2
0FFF4h to 0FFF7h
Address break (1)
(Reserved)
Reset
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
14. Watchdog Timer
9. Clock Generation Circuit
6. Voltage Detection Circuit
28. Comparator A
5. Resets
Note:
1. Do not use these interrupts. They are provided exclusively for use by development tools.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.1.5.2
11. Interrupts
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 11.2 lists the Relocatable Vector Tables.
Table 11.2
Relocatable Vector Tables
Interrupt Source
Vector Addresses (1)
Address (L) to Address (H)
BRK instruction (3)
+0 to +3 (0000h to 0003h)
Flash memory ready
(Reserved)
(Reserved)
Timer RC
(Reserved)
(Reserved)
Timer RE
UART2 transmit/NACK2
UART2 receive/ACK2
Key input
A/D conversion
Synchronous serial
communication unit / I2C
bus interface (2)
+4 to +7 (0004h to 0007h)
(Reserved)
UART0 transmit
UART0 receive
(Reserved)
(Reserved)
(Reserved)
Timer RA
(Reserved)
Timer RB
INT1
INT3
(Reserved)
(Reserved)
+24 to +27 (0018h to 001Bh)
+28 to +31 (001Ch to 001Fh)
+32 to +35 (0020h to 0023h)
+36 to +39 (0024h to 0027h)
+40 to +43 (0028h to 002Bh)
+44 to +47 (002Ch to 002Fh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
13
14
15
KUPIC
ADIC
SSUIC/IICIC
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
16
17
18
19
20
21
22
23
24
25
−
S0TIC
S0RIC
−
−
−
TRAIC
−
TRBIC
INT1IC
+104 to +107 (0068h to 006Bh)
26
INT3IC
27
28
29
−
−
INT0IC
30
U2BCNIC
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+84 to +87 (0054h to 0057h)
+88 to +91 (0058h to 005Bh)
+116 to +119 (0074h to 0077h)
INT0
UART2 bus collision detection +120 to +123 (0078h to 007Bh)
(Reserved)
Software
(3)
(Reserved)
Voltage monitor 1/
comparator A1
Voltage monitor 2/
comparator A2
(Reserved)
Software (3)
−
−
31
+128 to +131 (0080h to 0083h) to 32 to 41
+164 to +167 (00A4h to 00A7h)
42 to 49
+200 to +203 (00C8h to 00CBh)
50
−
VCMP1IC
+204 to +207 (00CCh to 00CFh)
VCMP2IC
51
52 to 55
+224 to +227 (00E0h to 00E3h) to 56 to 63
+252 to +255 (00FCh to 00FFh)
Notes:
1. These addresses are relative to those in the INTB register.
2. Selectable by the IICSEL bit in the SSUIICSR register.
3. These interrupts are not disabled by the I flag.
REJ09B0458-0010 Rev.0.10
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Software
Interrupt Control
Reference
Interrupt
Register
Number
0
−
R8C/Tiny Series
Software Manual
1
FMRDYIC
30. Flash Memory
2 to 5
−
−
6
−
−
7
TRCIC
19. Timer RC
8
−
−
9
−
−
10
TREIC
20. Timer RE
11
S2TIC
22. Serial Interface
(UART2)
12
S2RIC
Apr 01, 2008
−
−
11.5 Key Input Interrupt
27. A/D Converter
24. Synchronous Serial
Communication Unit
(SSU),
25. I2C bus Interface
−
21. Serial Interface
(UART0)
−
−
−
17. Timer RA
−
18. Timer RB
11.4 INT Interrupt
−
−
11.4 INT Interrupt
22. Serial Interface
(UART2)
−
R8C/Tiny Series
Software Manual
−
6. Voltage Detection
Circuit
28. Comparator A
−
R8C/Tiny Series
Software Manual
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.2
11. Interrupts
Registers
11.2.1
Interrupt Control Register
(TREIC, S2TIC, S2RIC, KUPIC, ADIC, S0TIC, S0RIC, TRAIC, TRBIC,
U2BCNIC, VCMP1IC, VCMP2IC)
Address 004Ah (TREIC), 004Bh (S2TIC), 004Ch (S2RIC), 004Dh (KUPIC), 004Eh (ADIC),
0051h (S0TIC), 0052h (S0RIC), 0056h (TRAIC), 0058h (TRBIC), 005Eh (U2BCNIC),
0072h (VCMP1IC), 0073h (VCMP2IC),
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
—
—
—
—
IR
ILVL2
ILVL1
ILVL0
After Reset
X
X
X
X
X
0
0
0
Bit
b0
b1
b2
Symbol
Bit Name
ILVL0 Interrupt priority level select bit
ILVL1
ILVL2
b3
IR
b4
b5
b6
b7
—
—
—
—
Function
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
Interrupt request bit
0: No interrupt requested
1: Interrupt requested
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
R/W
R/W
R/W
R/W
R/W
(1)
—
Note:
1. Only 0 can be written to the IR bit. Do not write 1 to this bit.
Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.
Refer to 11.8.5 Rewriting Interrupt Control Register.
REJ09B0458-0010 Rev.0.10
Page 126 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.2.2
11. Interrupts
Interrupt Control Register (FMRDYIC TRCIC, SSUIC/IICIC)
Address 0041h (FMRDYIC), 0047h (TRCIC), 004Fh (SSUIC/IICIC (1))
Bit
Symbol
After Reset
Bit
b0
b1
b2
b7
—
X
b6
—
X
b5
—
X
Symbol
Bit Name
ILVL0 Interrupt priority level select bit
ILVL1
ILVL2
b3
IR
b4
b5
b6
b7
—
—
—
—
b4
—
X
b3
IR
X
b2
ILVL2
0
b1
ILVL1
0
Function
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
Interrupt request bit
0: No interrupt requested
1: Interrupt requested
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
b0
ILVL0
0
R/W
R/W
R/W
R/W
R
—
Note:
1. Selectable by the IICSEL bit in the SSUIICSR register.
Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.
Refer to 11.8.5 Rewriting Interrupt Control Register.
REJ09B0458-0010 Rev.0.10
Page 127 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.2.3
11. Interrupts
INTi Interrupt Control Register (INTiIC) (i = 0, 1, 3)
Address 0059h (INT1IC), 005Ah (INT3IC), 005Dh (INT0IC)
Bit
b7
b6
b5
b4
b3
Symbol
—
—
—
POL
IR
After Reset
X
X
0
0
X
Bit
b0
b1
b2
b3
Symbol
Bit Name
ILVL0 Interrupt priority level select bit
ILVL1
ILVL2
IR
b4
POL
b5
b6
b7
—
—
—
b2
ILVL2
0
b1
ILVL1
0
Function
b2 b1 b0
0 0 0: Level 0 (interrupt disabled)
0 0 1: Level 1
0 1 0: Level 2
0 1 1: Level 3
1 0 0: Level 4
1 0 1: Level 5
1 1 0: Level 6
1 1 1: Level 7
Interrupt request bit
0: No interrupt requested
1: Interrupt requested
0: Falling edge selected
Polarity switch bit (3)
1: Rising edge selected (2)
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
b0
ILVL0
0
R/W
R/W
R/W
R/W
R/W
(1)
R/W
R/W
—
Notes:
1. Only 0 can be written to the IR bit. Do not write 1 to this bit.
2. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (falling edge selected).
3. The IR bit may be set to 1 (interrupt requested) when the POL bit is rewritten. Refer to 11.8.4 Changing
Interrupt Sources.
Rewrite the interrupt control register when an interrupt request corresponding to the register is not generated.
Refer to 11.8.5 Rewriting Interrupt Control Register.
REJ09B0458-0010 Rev.0.10
Page 128 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.3
11. Interrupts
Interrupt Control
The following describes enabling and disabling maskable interrupts and setting the acknowledgement priority.
This description does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in the corresponding interrupt control register
to enable or disable a maskable interrupt. Whether an interrupt is requested or not is indicated by the IR bit in
the corresponding interrupt control register.
11.3.1
I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
11.3.2
IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. After the interrupt request is
acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (no interrupt
requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC interrupt, the synchronous serial communication unit interrupt,
the I2C bus interface interrupt, and the flash memory interrupt are different. Refer to 11.7 Timer RC Interrupt,
Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory
Interrupt (Interrupts with Multiple Interrupt Request Sources).
11.3.3
Bits ILVL2 to ILVL0, IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are the conditions when an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 11.3
Bits ILVL2 to ILVL0
000b
001b
010b
011b
100b
101b
110b
111b
Settings of Interrupt Priority
Levels
Interrupt Priority Level
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
REJ09B0458-0010 Rev.0.10
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Priority
−
Low
Apr 01, 2008
High
Table 11.4
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Interrupt Priority Levels Enabled by
IPL
Enabled Interrupt Priority Level
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.3.4
11. Interrupts
Interrupt Sequence
The following describes an interrupt sequence which is performed from when an interrupt request is
acknowledged until the interrupt routine is executed.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 11.3 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested). (2)
(2) The FLG register is saved to a temporary register (1) in the CPU immediately before entering the interrupt
sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is
executed.
(4) The CPU internal temporary register (1) is saved on the stack.
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
1
2
3
4
5
6
7
8
9
10
11
SP-2
SP-1
SP-4
12
13
14
15
16
17
18
19
20
CPU Clock
Address Bus
Data Bus
Address
0000h
Interrupt
information
RD
Undefined
Undefined
SP-2
SP-1
SP-4
contents contents contents
SP-3
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
PC
VEC+2
contents
Undefined
WR
Note:
The indeterminate state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.
Figure 11.3
Time Required for Executing Interrupt Sequence
Notes:
1. These registers cannot be accessed by the user.
2. Refer to 11.7 Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I2C bus
Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request
Sources) for the IR bit operations of the timer RC Interrupt, the Synchronous Serial Communication
unit Interrupt, and the I2C bus Interface Interrupt.
REJ09B0458-0010 Rev.0.10
Page 130 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.3.5
11. Interrupts
Interrupt Response Time
Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an
interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt
response time includes the period from when an interrupt request is generated until the currently executing
instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence
(20 cycles, refer to (b) in Figure 11.4).
Interrupt request generation
Interrupt request acknowledgement
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
20 cycles (b)
Interrupt response time
(a) The period from when an interrupt request is generated until the currently executing instruction is completed.
The length of time varies depending on the instruction being executed. The DIVX instruction requires
the longest time, 30 cycles (no wait states if the divisor is a register).
(b) 21 cycles for address match and single-step interrupts.
Figure 11.4
11.3.6
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt
is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in
the IPL.
Table 11.5 lists the IPL Value When Software or Special Interrupt is Acknowledged.
Table 11.5
IPL Value When Software or Special Interrupt is Acknowledged
Interrupt Source without Interrupt Priority Level
Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1,
voltage monitor 2/comparator A2, address break
Software, address match, single-step
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Value Set in IPL
7
Not changed
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.3.7
11. Interrupts
Saving Registers
In the interrupt sequence, the FLG register and PC are saved on the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved on the stack, the 16 low-order bits in the PC are saved.
Figure 11.5 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers should be saved by a program at the beginning of the interrupt routine. The
PUSHM instruction can save several registers in the register bank being currently used (1) with a single
instruction.
Note:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Stack
Address
MSB
Stack
Address
LSB
MSB
LSB
m−4
m−4
PCL
m−3
m−3
PCM
m−2
m−2
FLGL
m−1
m−1
m
Previous stack contents
m+1
Previous stack contents
[SP]
SP value before
interrupt request
acknowledgement (1)
m
m+1
Stack state before interrupt request acknowledgement
FLGH
[SP]
New SP value (1)
PCH
Previous stack contents
Previous stack contents
PCL
PCM
PCH
FLGL
FLGH
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
Stack state after interrupt request acknowledgement
Note:
1.When an INT instruction for software numbers 32 to 63 has been executed,
this SP is indicated by the U flag. Otherwise it is ISP.
Figure 11.5
Stack State Before and After Acknowledgement of Interrupt Request
REJ09B0458-0010 Rev.0.10
Page 132 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11. Interrupts
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 11.6 shows the Register Saving Operation.
Stack
Address
Sequence in which registers are saved
[SP]−5
[SP]−4
PCL
(3)
[SP]−3
PCM
(4)
[SP]−2
FLGL
(1)
Saved, 8 bits at a time
[SP]−1
FLGH
PCH
(2)
[SP]
Completed saving registers
in four operations
PCL
PCM
PCH
FLGL
FLGH
: 8 low-order bits of PC
: 8 middle-order bits of PC
: 4 high-order bits of PC
: 8 low-order bits of FLG
: 4 high-order bits of FLG
Note:
1.[SP] indicates the SP initial value when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
When an INT instruction for software numbers 32 to 63 has been executed,
this SP is indicated by the U flag. Otherwise it is ISP.
Figure 11.6
Register Saving Operation
REJ09B0458-0010 Rev.0.10
Page 133 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.3.8
11. Interrupts
Returning from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved on the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Registers saved by a program in an interrupt routine should be saved using the POPM instruction or a similar
instruction before executing the REIT instruction.
11.3.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select any priority level for maskable interrupts (peripheral function). However, if
two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware,
with the higher priority interrupts acknowledged.
The priority of watchdog timer and other special interrupts is set by hardware.
Figure 11.7 shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, the MCU executes the
interrupt routine.
Reset
High
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1/comparator A1
Voltage monitor 2/comparator A2
Peripheral function
Single step
Address match
Figure 11.7
Hardware Interrupt Priority
REJ09B0458-0010 Rev.0.10
Page 134 of 572
Apr 01, 2008
Low
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11. Interrupts
11.3.10 Interrupt Priority Level Selection Circuit
The interrupt priority level selection circuit is used to select the highest priority interrupt.
Figure 11.8 shows the Interrupt Priority Level Selection Circuit.
Highest
Priority level of interrupts
Level 0 (initial value)
Voltage monitor 1/comparator A1
UART2 bus collision detection
Voltage monitor 2/comparator A2
INT3
Timer RB
Timer RA
INT0
INT1
Timer RC
Peripheral function interrupt priority
(if the priority levels are same)
UART0 receive
A/D conversion
UART2 receive/ACK2
Timer RE
UART0 transmit
SSU / I2C bus (1)
Key input
UART2 transmit/NACK2
Flash memory ready
IPL
Lowest
Interrupt request level
selection output signal
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage monitor 1/comparator A1
Voltage monitor 2/comparator A2
Note:
1. Selectable by the IICSEL bit in the SSUIICSR register.
Figure 11.8
Interrupt Priority Level Selection Circuit
REJ09B0458-0010 Rev.0.10
Page 135 of 572
Apr 01, 2008
Interrupt request
acknowledgement
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.4
11. Interrupts
INT Interrupt
11.4.1
INTi Interrupt (i = 0, 1, 3)
The INTi interrupt is generated by an INTi input. To use the INTi interrupt, set the INTiEN bit in the INTEN
register is to 1 (enabled). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL
bit in the INTiIC register. The input pins used as the INT1 input can be selected.
Also, inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff input of timer RC, and the external trigger input of
timer RB.
Table 11.6 lists the Pin Configuration of INT Interrupt.
Pin Configuration of INT Interrupt
Table 11.6
Pin Name
Assigned Pin
I/O
Function
INT0
P4_5
Input
INT0 interrupt input, timer RB external
trigger input, timer RC pulse output forced
cutoff input
INT1
P1_5 or P1_7
Input
INT1 interrupt input
INT3
P3_3
Input
INT3 interrupt input
11.4.2
INT Interrupt Input Pin Select Register (INTSR)
Address 018Eh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
INT1SEL0
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
INT1SEL0 INT1 pin select bit
0: P1_7 assigned
1: P1_5 assigned
—
Reserved bits
Set to 0.
—
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
Reserved bits
Set to 0.
—
b0
—
0
R/W
—
R/W
R/W
—
R/W
The INTSR register selects which pin is assigned to the INT1 input. To use INT1, set this register.
Set the INTSR register before setting the INT1 associated registers. Also, do not change the setting values in
this register during INT1 operation.
REJ09B0458-0010 Rev.0.10
Page 136 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.4.3
11. Interrupts
External Input Enable Register 0 (INTEN)
Address 01FAh
Bit
b7
Symbol INT3PL
After Reset
0
b6
INT3EN
0
b5
—
0
b4
—
0
Bit
b0
Symbol
Bit Name
INT0EN INT0 input enable bit
b1
INT0PL INT0 input polarity select bit (1, 2)
b2
INT1EN INT1 input enable bit
b3
INT1PL INT1 input polarity select bit (1, 2)
b4
b5
b6
—
Reserved bits
—
INT3EN INT3 input enable bit
b7
INT3PL INT3 input polarity select bit (1, 2)
b3
INT1PL
0
b2
INT1EN
0
b1
INT0PL
0
b0
INT0EN
0
Function
R/W
R/W
0: Disabled
1: Enabled
0: One edge
1: Both edges
0: Disabled
1: Enabled
0: One edge
1: Both edges
Set to 0.
R/W
R/W
R/W
R/W
0: Disabled
1: Enabled
0: One edge
1: Both edges
R/W
R/W
Notes:
1. To set the INTiPL bit (i = 0, 1, 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge
selected).
2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 11.8.4
Changing Interrupt Sources.
11.4.4
INT Input Filter Select Register 0 (INTF)
Address 01FCh
Bit
b7
Symbol INT3F1
After Reset
0
b6
INT3F0
0
b5
—
0
Bit
b0
b1
Symbol
Bit Name
INT0F0 INT0 input filter select bit
INT0F1
b2
b3
INT1F0 INT1 input filter select bit
INT1F1
b4
b5
b6
b7
—
Reserved bits
—
INT3F0 INT3 input filter select bit
INT3F1
REJ09B0458-0010 Rev.0.10
Page 137 of 572
Apr 01, 2008
b4
—
0
b3
INT1F1
0
b2
INT1F0
0
b1
INT0F1
0
Function
b1 b0
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
b3 b2
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
Set to 0.
b7 b6
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
b0
INT0F0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.4.5
11. Interrupts
INTi Input Filter (i = 0, 1, 3)
The INTi input contains a digital filter. The sampling clock is selected using bits INTiF1 and INTiF0 in the
INTF register. The INTi level is sampled every sampling clock cycle and if the sampled input level matches
three times, the IR bit in the INTiIC register is set to 1 (interrupt requested).
Figure 11.9 shows the INTi Input Filter Configuration. Figure 11.10 shows an Operating Example of INTi Input
Filter.
INTiF1 to INTiF0
f1
f8
f32
= 01b
= 10b
Sampling clock
= 11b
INTi
INTiEN
Digital filter
(input level
matches
3 times)
Port direction
register (1)
Other than
INTiF1 to INTiF0
= 00b
= 00b
INTi interrupt
INTiPL = 0
Both edges
detection
INTiPL = 1
circuit
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0, 1, 3
Note:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when P1_5 pin used
Port P1_7 direction register when P1_7 pin used
INT3: Port P3_3 direction register when P3_3 pin used
Figure 11.9
INTi Input Filter Configuration
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 by a program.
Note:
This is an operating example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter enabled).
i = 0, 1, 3
Figure 11.10
Operating Example of INTi Input Filter
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R8C/32A Group
11.5
11. Interrupts
Key Input Interrupt
A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can
be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register is be used to select whether or not the pins are used as the KIi input.
The KIiPL bit in the KIEN register is also be used to select the input polarity.
When inputting “L” to the KIi pin, which sets the KIiPL bit to 0 (falling edge), the input to the other pins K10 to
K13 is not detected as interrupts. When inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the
input to the other pins K10 to K13 is not also detected as interrupts.
Figure 11.11 shows a Block Diagram of Key Input Interrupt. Table 11.7 lists the Pin Configuration of Key Input
Interrupt.
PU02 bit in PUR0 register
KUPIC register
Pull-up
transistor
PD1_3 bit in PD1 register
KI3EN bit
PD1_3 bit
KI3PL = 0
KI3
KI3PL = 1
Pull-up
transistor
KI2EN bit
PD1_2 bit
KI2PL = 0
Interrupt control circuit
KI2
KI2PL = 1
Pull-up
transistor
Key input
interrupt request
KI1EN bit
PD1_1 bit
KI1PL = 0
KI1
KI1PL = 1
Pull-up
transistor
KI0EN bit
PD1_0 bit
KI0PL = 0
KI0
KI0PL = 1
Figure 11.11
Table 11.7
Pin Name
Block Diagram of Key Input Interrupt
Pin Configuration of Key Input Interrupt
KI0
I/O
Input
KI0 interrupt input
KI1
Input
KI1 interrupt input
KI2
Input
KI2 interrupt input
KI3
Input
KI3 interrupt input
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Function
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KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.5.1
11. Interrupts
Key Input Enable Register 0 (KIEN)
Address 01FEh
Bit
b7
Symbol KI3PL
After Reset
0
Bit
b0
b6
KI3EN
0
b5
KI2PL
0
Symbol
Bit Name
KI0EN KI0 input enable bit
b1
KI0PL
KI0 input polarity select bit
b2
KI1EN
KI1 input enable bit
b3
KI1PL
KI1 input polarity select bit
b4
KI2EN
KI2 input enable bit
b5
KI2PL
KI2 input polarity select bit
b6
KI3EN
KI3 input enable bit
b7
KI3PL
KI3 input polarity select bit
b4
KI2EN
0
b3
KI1PL
0
b2
KI1EN
0
b1
KI0PL
0
Function
0: Disabled
1: Enabled
0: Falling edge
1: Rising edge
0: Disabled
1: Enabled
0: Falling edge
1: Rising edge
0: Disabled
1: Enabled
0: Falling edge
1: Rising edge
0: Disabled
1: Enabled
0: Falling edge
1: Rising edge
b0
KI0EN
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The IR bit in the KUPIC register may be set to 1 (interrupt requested) when the KIEN register is rewritten.
Refer to 11.8.4 Changing Interrupt Sources.
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R8C/32A Group
11.6
11. Interrupts
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When the
on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1,
and fixed vector tables) in the user system.
Set the starting address of any instruction in the RMADi register (i = 0 or 1). The AIERi bit in the AIERi register
can be used to select enable or disable the interrupt. The address match interrupt is not affected by the I flag and
IPL.
The PC value (Refer to 11.3.7 Saving Registers) which is saved on the stack when an address match interrupt
request is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The
appropriate return address is not saved on the stack.) When returning from the address match interrupt, follow one
of the following means:
• Rewrite the contents of the stack and use the REIT instruction to return.
• Use an instruction such as POP to restore the stack to its previous state before the interrupt request was
acknowledged. Then use a jump instruction to return.
Table 11.8 lists the PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged and Table
11.9 lists the Correspondence Between Address Match Interrupt Sources and Associated Registers.
Table 11.8
PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1)
• Instruction with 2-byte operation code (2)
• Instruction with 1-byte operation code (2)
ADD.B:S
#IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest
STNZ
#IMM8,dest STZX
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest PUSHM src
POPM
dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (however, dest = A0 or A1)
• Instructions other than above
PC Value Saved (1)
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
Notes:
1. Refer to the 11.3.7 Saving Registers.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 11.9
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
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R8C/32A Group
11.6.1
11. Interrupts
Address Match Interrupt Enable Register i (AIERi) (i = 0 or 1)
Address 01C3h (AIER0), 01C7h (AIER1)
Bit
b7
b6
b5
Symbol
—
—
—
After Reset
0
0
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
AIER0
0
Symbol
After Reset
—
0
—
0
—
0
—
0
AIER1
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
11.6.2
—
0
—
0
—
0
AIER0 register
AIER1 register
Symbol
Bit Name
AIERi Address match interrupt i enable bit
—
—
—
—
—
—
—
Function
0: Disabled
1: Enabled
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
—
Address Match Interrupt Register i (RMADi) (i = 0 or 1)
Address 01C2h to 01C0h (RMAD0), 01C6h to 01C4h (RMAD1)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
After Reset
—
X
—
X
—
X
—
X
—
X
—
X
—
X
—
X
Bit
Symbol
After Reset
b15
—
X
b14
—
X
b13
—
X
b12
—
X
b11
—
X
b10
—
X
b9
—
X
b8
—
X
Bit
Symbol
After Reset
b23
—
0
b22
—
0
b21
—
0
b20
—
0
b19
—
X
b18
—
X
b17
—
X
b16
—
X
Bit
Symbol
Function
Setting Range
b19 to b0
—
Address setting register for address match interrupt
00000h to FFFFFh
b20
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b21
—
b22
—
b23
—
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R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
11.7
11. Interrupts
Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I2C
bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple
Interrupt Request Sources)
The timer RC interrupt, synchronous serial communication unit interrupt, I2C bus interface interrupt, and flash
memory interrupt each have multiple interrupt request sources. An interrupt request is generated by the logical OR
of several interrupt request sources and is reflected in the IR bit in the corresponding interrupt control register.
Therefore, each of these peripheral functions has its own interrupt request source status register (status register) and
interrupt request source enable register (enable register) to control the generation of interrupt requests (change of
the IR bit in the interrupt control register). Table 11.10 lists the Registers Associated with Timer RC Interrupt,
Synchronous Serial Communication Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt.
Table 11.10
Registers Associated with Timer RC Interrupt, Synchronous Serial Communication
Unit Interrupt, I2C bus Interface Interrupt, and Flash Memory Interrupt
Peripheral Function
Name
Timer RC
Synchronous serial
communication unit
Status Register of
Enable Register of
Interrupt Control
Interrupt Request Source Interrupt Request Source
Register
TRCSR
TRCIER
TRCIC
SSSR
SSER
SSUIC
I2C bus interface
Flash memory
ICSR
ICIER
IICIC
RDYSTI
BSYAEI
RDYSTIE
BSYAEIE
CMDERIE
FMRDYIC
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R8C/32A Group
11. Interrupts
As with other maskable interrupts, the timer RC interrupt, synchronous serial communication unit interrupt, I2C
bus interface interrupt, and flash memory interrupt are controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple
interrupt request sources, the following differences from other maskable interrupts apply:
• When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR
bit is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, the IR bit is not set to 0 even if 0 is written to this bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
to 1, the IR bit remains 1.
• When multiple bits in the enable register are set to 1, use the status register to determine which request source
causes an interrupt.
Refer to chapters of the individual peripheral functions (19. Timer RC, 24. Synchronous Serial Communication
Unit (SSU), 25. I2C bus Interface, and 30. Flash Memory) for the status register and enable register.
For the interrupt control register, refer to 11.3 Interrupt Control.
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R8C/32A Group
11.8
11. Interrupts
Notes on Interrupts
11.8.1
Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the IR bit for the acknowledged interrupt is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
11.8.2
SP Setting
Set a value in the SP before an interrupt is acknowledged. The SP is set to 0000h after a reset. If an interrupt is
acknowledged before setting a value in the SP, the program may run out of control.
11.8.3
External Interrupt and Key Input Interrupt
Either the “L” level width or “H” level width shown in the Electrical Characteristics is required for the signal
input to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 32.22 (VCC = 5V), Table 32.28 (VCC = 3V), Table 32.34 (VCC = 2.2V) External
Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3).
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R8C/32A Group
11.8.4
11. Interrupts
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. To use an interrupt, set the IR bit to 0 (no interrupt requested) after changing interrupt sources.
Changing interrupt sources as referred to here includes all factors that change the source, polarity, or timing of
the interrupt assigned to a software interrupt number. Therefore, if a mode change of a peripheral function
involves the source, polarity, or timing of an interrupt, set the IR bit to 0 (no interrupt requested) after making
these changes. Refer to the descriptions of the individual peripheral functions for related interrupts.
Figure 11.12 shows a Procedure Example for Changing Interrupt Sources.
Interrupt source change
Disable interrupts
(2, 3)
Change interrupt sources
(including mode of peripheral function)
Set the IR bit to 0 (no interrupt request)
using the MOV instruction (3)
Enable interrupts
(2, 3)
Change completed
IR bit: The interrupt control register bit for the interrupt whose source is to be changed
Notes:
1. The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
2. To prevent interrupt requests from being generated disable the peripheral function
before changing the interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled.
If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 for the interrupt
whose source is to be changed.
3. Refer to 11.8.5 Rewriting Interrupt Control Register for the instructions to use and
related notes.
Figure 11.12
Procedure Example for Changing Interrupt Sources
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R8C/32A Group
11.8.5
11. Interrupts
Rewriting Interrupt Control Register
(a) The contents of the interrupt control register can be rewritten only while no interrupt requests
corresponding to that register are generated. If an interrupt request may be generated, disable the interrupt
before rewriting the contents of the interrupt control register.
(b) When rewriting the contents of the interrupt control register after disabling the interrupt, be careful to
choose appropriate instructions.
Changing any bit other than the IR bit
If an interrupt request corresponding to the register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt may be ignored. If this causes a problem, use one
of the following instructions to rewrite the contents of the register: AND, OR, BCLR, and BSET.
Changing the IR bit
Depending on the instruction used, the IR bit may not be set to 0 (no interrupt requested).
Use the MOV instruction to set the IR bit to 0.
(c) When using the I flag to disable an interrupt, set the I flag as shown in the sample programs below. Refer to
(b) regarding rewriting the contents of interrupt control registers using the sample programs.
Examples 1 to 3 shows how to prevent the I flag from being set to 1 (interrupts enabled) before the contents of
the interrupt control register are rewritten for the effects of the internal bus and the instruction queue buffer.
Example 1: Use the NOP instructions to pause program until the interrupt control register is rewritten
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set the TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2: Use a dummy read to delay the FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set the TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use the POPC instruction to change the I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set the TRAIC register to 00h
POPC
FLG
; Enable interrupts
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R8C/32A Group
12. ID Code Areas
12. ID Code Areas
The ID code areas are used to implement a function that prevents the flash memory from being rewritten in standard
serial I/O mode. This function prevents the flash memory from being read, rewritten, or erased.
12.1
Overview
The ID code areas are assigned to 0FFDFh, 0FFE3h, 0FFEBh, 0FFEFh, 0FFF3h, 0FFF7h, and 0FFFBh of the
respective vector highest-order addresses of the fixed vector table. Figure 12.1 shows the ID Code Areas.
ID code areas
Address
0FFDFh to 0FFDCh
ID1
Undefined instruction vector
0FFE3h to 0FFE0h
ID2
Overflow vector
BRK instruction vector
0FFE7h to 0FFE4h
0FFEBh to 0FFE8h
ID3
Address match vector
0FFEFh to 0FFECh
ID4
Single step vector
0FFF3h to 0FFF0h
ID5
Watchdog timer, oscillation stop detection,
voltage monitor 1, voltage monitor 2
0FFF7h to 0FFF4h
ID6
Address break vector
0FFFBh to 0FFF8h
ID7
0FFFFh to 0FFFCh
OFS
(Reserved)
Reset vector
4 bytes
Figure 12.1
ID Code Areas
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R8C/32A Group
12.2
12. ID Code Areas
Functions
The ID code areas are used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset
vector are set to FFFFFFh, the ID codes stored in the ID code areas and the ID codes sent from the serial
programmer or the on-chip debugging emulator are checked to see if they match. If the ID codes match, the
commands sent from the serial programmer or the on-chip debugging emulator are acknowledged. If the ID codes
do not match, the commands are not acknowledged. To use the serial programmer or the on-chip debugging
emulator, first write predetermined ID codes to the ID code areas.
If 3 bytes (addresses 0FFFCh to 0FFFEh) of the reset vector are set to FFFFFFh, the ID codes are not checked and
all commands are accepted.
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing an
instruction. Write appropriate values when creating a program.
The character sequence of the ASCII codes “ALeRASE” is the reserved word used for the forced erase function.
The character sequence of the ASCII codes “Protect” is the reserved word used for the standard serial I/O mode
disabled function. Table 12.1 shows the ID Code Reserved Word. The reserved word is a set of reserved characters
when all the addresses and data in the ID code storage addresses sequentially match Table 12.1. When the forced
erase function or standard serial I/O mode disabled function is not used, use another character sequence of the
ASCII codes.
Table 12.1
ID Code Reserved Word
ID Code Storage Address
0FFDFh
0FFE3h
0FFEBh
0FFEFh
0FFF3h
0FFF7h
0FFFBh
ID1
ID2
ID3
ID4
ID5
ID6
ID7
lD Code Reserved Word (ASCII) (1)
ALeRASE
Protect
41h (upper-case “A”)
50h (upper-case “P”)
4Ch (upper-case “L”)
72h (lower-case “r”)
65h (lower-case “e”)
6Fh (lower-case “o”)
52h (upper-case “R”)
74h (lower-case “t”)
41h (upper-case “A”)
65h (lower-case “e”)
53h (upper-case “S”)
63h (lower-case “c”)
45h (upper-case “E”)
74h (lower-case “t”)
Note:
1. Reserve word:A set of characters when all the addresses and data in the ID code storage addresses
sequentially match Table 12.1.
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R8C/32A Group
12.3
12. ID Code Areas
Forced Erase Function
This function is used in standard serial I/O mode. When the ID codes sent from the serial programmer or the onchip debugging emulator are “ALeRASE” in ASCII code, the content of the user ROM area will be erased at once.
However, if the contents of the ID code addresses are set to other than “ALeRASE” (other than Table 12.1 ID
Code Reserved Word) when the ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM
code protect enabled), forced erasure is not executed and the ID codes are checked with the ID code check function.
Table 12.2 lists the Conditions and Operations of Forced Erase Function.
Also, when the contents of the ID code addresses are set to “ALeRASE” in ASCII code, if the ID codes sent from
the serial programmer or the on-chip debugging emulator are “ALeRASE”, the content of the user ROM area will
be erased. If the ID codes sent from the serial programmer are other than “ALeRASE”, the ID codes do not match
and no command is acknowledged, thus the user ROM area remains protected.
Table 12.2
Conditions and Operations of Forced Erase Function
Condition
ID code from serial
programmer or the
on-chip debugging
emulator
ALeRASE
ID code in
ID code storage
address
ALeRASE
Other than
ALeRASE (1)
Other than ALeRASE ALeRASE
Bits ROMCP1 and
ROMCR
in OFS register
–
Other than 01b
(ROM code protect disabled)
01b
(ROM code protect enabled)
–
Other than ALeRASE (1) –
Operation
All erasure of user ROM
area (forced erase function)
ID code check
(ID code check function)
ID code check
(ID code check function.
No ID code match.)
ID code check
(ID code check function)
Note:
1. For “Protect”, refer to 12.4 Standard Serial II/O Mode Disabled Function.
12.4
Standard Serial II/O Mode Disabled Function
This function is used in standard serial I/O mode. When the I/D codes in the ID code storage addresses are set to the
reserved character sequence of the ASCII codes “Protect” (refer to Table 12.1 ID Code Reserved Word),
communication with the serial programmer or the on-chip debugging emulator is not performed. This does not
allow the flash memory to be read, rewritten, or erased using the serial programmer or the on-chip debugging
emulator.
Also, if the ID codes are also set to the reserved character sequence of the ASCII codes “Protect” when the
ROMCR bit in the OFS register is set to 1 and the ROMCP1 bit is set to 0 (ROM code protect enabled), ROM code
protection cannot be disabled using the serial programmer or the on-chip debugging emulator. This prevents the
flash memory from being read, rewritten, or erased using the serial programmer, the on-chip debugging emulator,
or parallel programmer.
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R8C/32A Group
12.5
12. ID Code Areas
Notes on ID Code Areas
12.5.1
Setting Example of ID Code Areas
As the ID code areas are allocated in the flash memory (not in the SFRs), they cannot be rewritten by executing
an instruction. Write appropriate values when creating a program. The following shows a setting example.
• To set 55h in all of the ID code areas
.org 00FFDCH
.lword dummy | (55000000h) ; UND
.lword dummy | (55000000h) ; INTO
.lword dummy ; BREAK
.lword dummy | (55000000h) ; ADDRESS MATCH
.lword dummy | (55000000h) ; SET SINGLE STEP
.lword dummy | (55000000h) ; WDT
.lword dummy | (55000000h) ; ADDRESS BREAK
.lword dummy | (55000000h) ; RESERVE
(Programming formats vary depending on the compiler. Check the compiler manual.)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
13. Option Function Select Area
13. Option Function Select Area
13.1
Overview
The option function select area is used to select the MCU state after a reset, the function to prevent rewriting in
parallel I/O mode, or the watchdog timer operation. The reset vector highest-order-address, 0FFFFh and 0FFDBh,
are assigned as the option function select area. Figure 13.1 shows the Option Function Select Area.
Option function select area
Address
0FFDBh to 0FFD8h
OFS2
Reserved area
0FFFFh to 0FFFCh
OFS
Reset vector
4 bytes
Figure 13.1
Option Function Select Area
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
13.2
13. Option Function Select Area
Registers
Registers OFS and OFS2 are used to select the MCU state after a reset, the function to prevent rewriting in parallel
I/O mode, or the watchdog timer operation.
13.2.1
Option Function Select Register (OFS)
Address 0FFFFh
Bit
b7
Symbol CSPROINI
When shipping
1
b6
LVDAS
1
b5
b4
b3
b2
VDSEL1 VDSEL0 ROMCP1 ROMCR
1
1
1
1
Bit
b0
Symbol
Bit Name
WDTON Watchdog timer start select bit
b1
b2
—
Reserved bit
ROMCR ROM code protect disable bit
b3
ROMCP1 ROM code protect bit
b4
b5
VDSEL0 Voltage detection 0 level select bit (2)
VDSEL1
b6
b7
LVDAS
Voltage detection 0 circuit start bit (3)
CSPROINI Count source protection mode
after reset select bit
b1
—
1
b0
WDTON
1
(Note 1)
Function
0: Watchdog timer automatically starts after reset.
1: Watchdog timer is stopped after reset.
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
R/W
R/W
b5 b4
R/W
R/W
0 0: 3.80 V selected (Vdet0_3)
0 1: 2.85 V selected (Vdet0_2)
1 0: 2.35 V selected (Vdet0_1)
1 1: 1.90 V selected (Vdet0_0)
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
R/W
R/W
R/W
R/W
R/W
Notes:
1. If the block including the OFS register is erased, the OFS register value is set to FFh.
2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of
voltage monitor 0 reset and power-on reset.
3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset).
The OFS register is allocated in the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
LVDAS Bit (Voltage Detection 0 Circuit Start Bit)
The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
13.2.2
13. Option Function Select Area
Option Function Select Register 2 (OFS2)
Address 0FFDBh
Bit
b7
Symbol
—
When shipping
1
b6
—
1
b5
—
1
b4
—
1
b3
b2
b1
b0
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
1
1
1
1
(Note 1)
Bit
b0
b1
Symbol
Bit Name
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
b2
b3
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1 set bit
b4
b5
b6
b7
—
—
—
—
Reserved bits
Function
b1 b0
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
b3 b2
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
Set to 1.
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh.
The OFS2 register is located on the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 14.3.1.1 Refresh Acknowledgment Period.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
13.3
13. Option Function Select Area
Notes on Option Function Select Area
13.3.1
Setting Example of Option Function Select Area
As the option function select area is allocated in the flash memory (not in the SFRs), they cannot be rewritten by
executing an instruction. Write appropriate values when creating a program. The following shows a setting
example.
• To set FFh in the OFS register
.org 00FFFCH
.lword reset | (0FF000000h)
; RESET
(Programming formats vary depending on the compiler. Check the compiler manual.)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14. Watchdog Timer
14. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system.
14.1
Overview
The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or
disable.
Table 14.1 lists the Watchdog Timer Specifications.
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 14.1 shows a Watchdog Timer Block Diagram.
Table 14.1
Watchdog Timer Specifications
Item
Count source
Count operation
Count start condition
Count stop condition
Watchdog timer
initialization conditions
Operations at underflow
Selectable functions
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Count Source Protection Mode
Disabled
CPU clock
Count Source Protection Mode
Enabled
Low-speed on-chip oscillator clock
for the watchdog timer
Decrement
Either of the following can be selected:
• After a reset, count starts automatically.
• Count starts by writing to the WDTS register.
Stop mode, wait mode
None
• Reset
• Write 00h and then FFh to the WDTR register (with acknowledgement period
setting).
• Underflow
Watchdog timer reset
Watchdog timer interrupt
or watchdog timer reset
• Division ratio of the prescaler
Selected by the WDTC7 bit in the WDTC register or the CM07 bit in
the CM0 register.
• Count source protection mode
Whether count source protection mode is enabled or disabled after a reset
can be selected by the CSPROINI bit in the OFS register (flash memory).
If count source protection mode is disabled after a reset, it can be enabled or
disabled by the CSPRO bit in the CSPR register (program).
• Start or stop of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
• Initial value of the watchdog timer
Selectable by bits WDTUFS0 and WDTUFS1 in the OFS2 register.
• Refresh acknowledgement period for the watchdog timer
Selectable by bits WDTRCS0 and WDTRCS1 in the OFS2 register.
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14. Watchdog Timer
Prescaler
1/16
CM07 = 0,
WDTC7 = 0
CSPRO = 0
1/128
CPU clock
CM07 = 0,
WDTC7 = 1
PM12 = 0
Watchdog timer
interrupt request
Watchdog timer
1/2
CM07 = 1
(Note 1)
CSPRO = 1
PM12 = 1
Watchdog
timer reset
Low-speed on-chip oscillator
for watchdog timer
Oscillation starts
when CSPRO = 1
Internal reset signal
(Low active)
Bits WDTRCS0 and WDTRCS1
Write to WDTR register
Refresh period
control circuit
CSPRO: Bit in CSPR register
WDTC7: Bit in WDTC register
PM12: Bit in PM1 register
CM07: Bit in CM0 register
WDTUFS0, WDTUFS1, WDTRCS0, WDTRCS1: Bits in OFS2 register
Note:
1. A value set by bits WDTUFS0 and WDTUFS1 is set in the watchdog timer (value when shipping: 3FFFh).
Figure 14.1
Watchdog Timer Block Diagram
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.2
14. Watchdog Timer
Registers
14.2.1
Processor Mode Register 1 (PM1)
Address 0005h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b6
—
0
b5
—
0
b4
—
0
Symbol
Bit Name
—
Reserved bits
—
PM12 WDT interrupt/reset switch bit
b3
b4
b5
b6
b7
—
—
—
—
—
b3
—
0
b2
PM12
0
b1
—
0
b0
—
0
Function
R/W
R/W
Set to 0.
0: Watchdog timer interrupt
1: Watchdog timer reset (1)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
Reserved bit
R/W
—
Set to 0.
Note:
1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it).
This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection
mode enabled).
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.
14.2.2
Watchdog Timer Reset Register (WDTR)
Address 000Dh
Bit
b7
Symbol
—
After Reset
X
b6
—
X
b5
—
X
b4
—
X
b3
—
X
b2
—
X
b1
—
X
b0
—
X
Bit
Function
b7 to b0 Writing 00h and then FFh to this register initializes the watchdog timer.
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2
register.
14.2.3
R/W
W
Watchdog Timer Start Register (WDTS)
Address 000Eh
Bit
b7
Symbol
—
After Reset
X
b6
—
X
b5
—
X
b4
—
X
b3
—
X
Bit
Function
b7 to b0 A write instruction to this register starts the watchdog timer.
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b2
—
X
b1
—
X
b0
—
X
R/W
W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.2.4
14. Watchdog Timer
Watchdog Timer Control Register (WDTC)
Address 000Fh
Bit
b7
Symbol WDTC7
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
14.2.5
Symbol
—
—
—
—
—
—
—
WDTC7
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Bit Name
Function
When read, b6 to b10 of the watchdog timer can be read.
R/W
R
When read, b11 of the watchdog timer can be read.
Reserved bit
When read, the content is 0.
Prescaler select bit
0: Divided-by-16
1: Divided-by-128
R
R
R/W
Count Source Protection Mode Register (CSPR)
Address 001Ch
Bit
b7
Symbol CSPRO
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
—
0
(Note 1)
Symbol
Bit Name
Function
—
Reserved bits
Set to 0.
—
—
—
—
—
—
CSPRO Count source protection mode select bit (2) 0: Count source protection mode disabled
1: Count source protection mode enabled
Notes:
1. When 0 is written to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. To set the CSPRO bit to 1, write 0 and then 1 to it. This bit cannot be set to 0 by a program.
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R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.2.6
14. Watchdog Timer
Option Function Select Register (OFS)
Address 0FFFFh
Bit
b7
Symbol CSPROINI
When shipping
1
b6
LVDAS
1
b5
b4
b3
b2
VDSEL1 VDSEL0 ROMCP1 ROMCR
1
1
1
1
Bit
b0
Symbol
Bit Name
WDTON Watchdog timer start select bit
b1
b2
—
Reserved bit
ROMCR ROM code protect disable bit
b3
ROMCP1 ROM code protect bit
b4
b5
VDSEL0 Voltage detection 0 level select bit (2)
VDSEL1
b6
b7
LVDAS
Voltage detection 0 circuit start bit (3)
CSPROINI Count source protection mode
after reset select bit
b1
—
1
b0
WDTON
1
(Note 1)
Function
0: Watchdog timer automatically starts after reset.
1: Watchdog timer is stopped after reset.
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
R/W
R/W
b5 b4
R/W
R/W
0 0: 3.80 V selected (Vdet0_3)
0 1: 2.85 V selected (Vdet0_2)
1 0: 2.35 V selected (Vdet0_1)
1 1: 1.90 V selected (Vdet0_0)
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
R/W
R/W
R/W
R/W
R/W
Notes:
1. If the block including the OFS register is erased, the OFS register value is set to FFh.
2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of
voltage monitor 0 reset and power-on reset.
3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset).
The OFS register is allocated in the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
LVDAS Bit (Voltage Detection 0 Circuit Start Bit)
The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.2.7
14. Watchdog Timer
Option Function Select Register 2 (OFS2)
Address 0FFDBh
Bit
b7
Symbol
—
When shipping
1
b6
—
1
b5
—
1
b4
—
1
b3
b2
b1
b0
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
1
1
1
1
(Note 1)
Bit
b0
b1
Symbol
Bit Name
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
b2
b3
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1 set bit
b4
b5
b6
b7
—
—
—
—
Reserved bits
Function
b1 b0
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
b3 b2
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
Set to 1.
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. If the block including the OFS2 register is erased, the OFS2 register value is set to FFh.
The OFS2 register is located on the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 14.3.1.1 Refresh Acknowledgment Period.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.3
14. Watchdog Timer
Functional Description
14.3.1
Common Items for Multiple Modes
14.3.1.1
Refresh Acknowledgment Period
The period for acknowledging refreshment operation to the watchdog timer (write to the WDTR register) can
be selected by bits WDTRCS0 and WDTRCS1 in the OFS2 register. Figure 14.2 shows the Refresh
Acknowledgement Period for Watchdog Timer.
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, a refresh
operation executed during the refresh acknowledgement period is acknowledged. Any refresh operation
executed during the period other than the above is processed as an incorrect write, and a watchdog timer
interrupt or watchdog timer reset (selectable by the PM12 bit in the PM1 register) is generated.
Watchdog timer period
Count starts
Underflow
Refresh can be acknowledged
Processed as
incorrect write (1)
Refresh acknowledge period
100% (WDTRCS1 to WDTRCS0 = 11b)
Refresh can be acknowledged
75% (WDTRCS1 to WDTRCS0 = 10b)
Processed as incorrect write (1) Refresh can be acknowledged
50% (WDTRCS1 to WDTRCS0 = 01b)
Refresh can be
acknowledged
25% (WDTRCS1 to WDTRCS0 = 00b)
Processed as incorrect write (1)
0%
25%
50%
75%
100%
WDTRCS0, WDTRCS1: Bits in OFS2 register
Note:
1. A watchdog timer interrupt or watchdog timer reset is generated.
Figure 14.2
Refresh Acknowledgement Period for Watchdog Timer
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.3.2
14. Watchdog Timer
Count Source Protection Mode Disabled
The count source for the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 14.2 lists the Watchdog Timer Specifications (Count Source Protection Mode Disabled).
Table 14.2
Watchdog Timer Specifications (Count Source Protection Mode Disabled)
Item
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operations at underflow
Specification
CPU clock
Decrement
Division ratio of prescaler (n) × count value of watchdog timer (m) (1)
CPU clock
n: 16 or 128 (selected by the WDTC7 bit in the WDTC register), or
2 when selecting the low-speed clock (CM07 bit in CM0 register = 1)
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Example:
The period is approximately 13.1 ms when:
- The CPU clock frequency is set to 20 MHz.
- The prescaler is divided by 16.
- Bits WDTUFS1 to WDTUFS0 are set to 11b (3FFFh).
• Reset
• Write 00h and then FFh to the WDTR register.
• Underflow
The operation of the watchdog timer after a reset is selected by
the WDTON bit (2) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).
The watchdog timer and prescaler are stopped after a reset and
start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after
reset).
The watchdog timer and prescaler start counting automatically after a reset.
Stop mode, wait mode (Count resumes from the retained value after exiting.)
• When the PM12 bit in the PM1 register is set to 0.
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1.
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
Notes:
1. The watchdog timer is initialized when 00h and then FFh is written to the WDTR register. The
prescaler is initialized after a reset. This may cause some errors due to the prescaler during the
watchdog timer period.
2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh
with a flash programmer.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
14.3.3
14. Watchdog Timer
Count Source Protection Mode Enabled
The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when
count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can
still be supplied to the watchdog timer.
Table 14.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled).
Table 14.3
Watchdog Timer Specifications (Count Source Protection Mode Enabled)
Item
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operation at underflow
Registers, bits
Specification
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (m)
Low-speed on-chip oscillator clock for the watchdog timer
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Example:
The period is approximately 8.2 ms when:
- The on-chip oscillator clock for the watchdog timer is set to 125 kHz.
- Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh).
• Reset
• Write 00h and then FFh to the WDTR register.
• Underflow
The operation of the watchdog timer after a reset is selected by
the WDTON bit (1) in the OFS register (address 0FFFFh).
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).
The watchdog timer and prescaler are stopped after a reset and
start counting when the WDTS register is written to.
• When the WDTON bit is set to 0 (watchdog timer starts automatically after
reset).
The watchdog timer and prescaler start counting automatically after a reset.
None (Count does not stop even in wait mode once it starts. The MCU does
not enter stop mode.)
Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset.)
• When the CSPPRO bit in the CSPR register is set to 1 (count source
protection mode enabled) (2), the following are set automatically:
- The low-speed on-chip oscillator for the watchdog timer is on.
- The PM12 bit in the PM1 register is set to 1 (watchdog timer reset when the
watchdog timer underflows).
Notes:
1. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh
with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh
with a flash programmer.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15. DTC
15. DTC
The DTC (data transfer controller) is a function that transfers data between the SFR and on-chip memory without using
the CPU. This chip incorporates one DTC channel. The DTC is activated by a peripheral function interrupt to perform
data transfers. The DTC and CPU use the same bus, and the DTC takes priority over the CPU in using the bus.
To control DTC data transfers, control data comprised of a transfer source address, a transfer destination address, and
operating modes are allocated in the DTC control data area. Each time the DTC is activated, the DTC reads control
data to perform data transfers.
15.1
Overview
Table 15.1 shows the DTC Specifications.
Table 15.1
DTC Specifications
Item
Activation sources
Allocatable control data
Address space which can be transferred
Maximum number of transfer Normal mode
times
Repeat mode
Maximum size of block to be Normal mode
transferred
Repeat mode
Unit of transfers
Transfer mode
Normal mode
Repeat mode
Address control
Normal mode
Repeat mode
Priority of activation sources
Interrupt request
Normal mode
Repeat mode
Transfer start
Transfer stop
Normal mode
Repeat mode
i = 0 to 3, 5, 6
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Specification
21 sources
24 sets
64 Kbytes (00000h to 0FFFFh)
256 times
255 times
256 bytes
255 bytes
Byte
Transfers end on completion of the transfer causing the DTCCT
register value to change from 1 to 0.
On completion of the transfer causing the DTCCT register value to
change from 1 to 0, the repeat area address is initialized and the
DTRLD register value is reloaded to the DTCCT register to continue
transfers.
Fixed or incremented
Addresses of the area not selected as the repeat area are fixed or
incremented.
See Table 15.6 DTC Activation Sources and DTC Vector
Addresses.
On completion of the data transfer causing the DTCCT register value
to change from 1 to 0, the activation source interrupt request is
generated for the CPU.
When the RPTINT bit in the DTCCR register is 1 (interrupt generation
enabled), the activation source interrupt request is generated for the
CPU on completion of the data transfer causing the DTCCT register
value to change from 1 to 0.
When bits DTCENi0 to DTCENi1 and bits DTCENi3 to DTCENi7 in
the DTCENi registers are 1 (activation enabled), data transfer is
started each time the corresponding DTC activation sources are
generated.
• When bits DTCENi0 to DTCENi1 and bits DTCENi3 to DTCENi7
are set to 0 (activation disabled).
• When the data transfer causing the DTCCT register value to
change from 1 to 0 is completed.
• When bits DTCENi0 to DTCENi1 and bits DTCENi3 to DTCENi7
are set to 0 (activation disabled).
• When the data transfer causing the DTCCT register value to
change from 1 to 0 is completed while the RPTINT bit is 1 (interrupt
generation enabled).
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15. DTC
DTBLS
DTCCT
DTRLD
DTSAR
DTDAR
ROM
Peripheral interrupt
request
RAM
DTCTL
DTCCR: DTC control register
DTBLS: DTC block size register
DTCCT: DTC transfer count register
DTRLD: DTC transfer count reload register
DTSAR: DTC source address register
DTDAR: DTC destination address register
DTCTL: DTC activation control register
DTCEN0 to DTCEN6:
DTC activation enable registers 0 to 6
Bus interface
Interrupt controller
Peripheral
functions
DTC activation
request
DTCCR
Internal bus
DTCENi
(i = 0 to 3, 5, 6)
Control circuit
Peripheral interrupt request
CPU
Peripheral bus
Figure 15.1
15.2
DTC Block Diagram
Registers
Table 15.2 shows the Register Configuration and Table 15.3 shows the Correspondences between Bits DTCENi0
to DTCENi1, Bits DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) and Interrupt Sources.
Table 15.2
Register Configuration
Register Name
DTC control register
Symbol
DTCCR
R/W
After Reset
00h
Address
—
DTC block size register
DTBLS
— (1)
00h
— (2)
DTCCT
—
(1)
DTC transfer count register
00h
— (2)
DTC transfer count reload register
DTRLD
— (1)
00h
— (2)
DTC source address register
DTSAR
—
(1)
00h
— (2)
DTC destination address register
DTDAR
00h
DTC activation control register
DTC activation enable register 0
DTC activation enable register 1
DTC activation enable register 2
DTC activation enable register 3
DTC activation enable register 5
DTC activation enable register 6
DTCTL
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN5
DTCEN6
— (1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
— (2)
0080h
0088h
0089h
008Ah
008Bh
008Dh
008Eh
(1)
00h
00h
00h
00h
00h
00h
00h
— (2)
Notes:
1. The registers in the DTC cannot be directly read or written to.
2. Allocated as control data at addresses from 2C40h to 2CFFh in the DTC control data area.
REJ09B0458-0010 Rev.0.10
Page 166 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.2.1
15. DTC
DTC Control Register (DTCCR)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
b2
b1
Symbol
—
—
RPTINT
CHNE DAMOD SAMOD RPTSEL
After Reset
0
0
0
0
0
0
0
Bit
b0
Symbol
MODE
b1
RPTSEL Repeat area select bit (1)
b2
SAMOD Source address control bit (2)
b3
DAMOD Destination address control bit (2)
b4
b5
CHNE
Bit Name
Transfer mode select bit
Chain transfer enable bit
RPTINT Repeat mode interrupt enable bit (1)
b6
b7
—
—
Reserved bits
b0
MODE
0
Function
0: Normal mode
1: Repeat mode
0: Transfer destination is the repeat area.
1: Transfer source is the repeat area.
0: Fixed
1: Incremented
0: Fixed
1: Incremented
0: Chain transfers disabled
1: Chain transfers enabled
0: Interrupt generation disabled
1: Interrupt generation enabled
Set to 0.
R/W
—
—
—
—
—
—
R/W
Notes:
1. This bit is valid when the MODE bit is 1 (repeat mode).
2. Settings of bits SAMOD and DAMOD are invalid for the repeat area.
15.2.2
DTC Block Size Register (DTBLS)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
Symbol
After Reset
Bit
b7 to b0
—
0
—
0
—
0
—
0
—
0
b2
b1
b0
—
0
—
0
—
0
Function
These bits specify the size of the data block to be transferred by one
activation.
Note:
1. When the DTBLS register is set to 00h, the block size is 256 bytes.
REJ09B0458-0010 Rev.0.10
Page 167 of 572
Apr 01, 2008
Setting Range
00h to FFh (1)
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.2.3
15. DTC
DTC Transfer Count Register (DTCCT)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
Symbol
—
—
—
—
—
After Reset
0
0
0
0
0
b2
—
0
b1
—
0
Bit
Function
b7 to b0 These bits specify the number of times of DTC data transfers.
b0
—
0
Setting Range
00h to FFh (1)
R/W
—
Note:
1. When the DTCCT register is set to 00h, the number of transfer times is 256. Each time the DTC is activated, the
DTCCT register is decremented by 1.
15.2.4
DTC Transfer Count Reload Register (DTRLD)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
Symbol
—
—
—
—
—
After Reset
0
0
0
0
0
b2
—
0
b1
—
0
Bit
Function
b7 to b0 This register value is reloaded to the DTCCT register in repeat mode.
b0
—
0
Setting Range
00h to FFh (1)
R/W
—
Note:
1. Set the initial value for the DTCCT register.
15.2.5
DTC Source Address Register (DTSAR)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
Symbol
—
—
—
—
—
After Reset
0
0
0
0
0
b2
—
0
b1
—
0
b0
—
0
Bit
Symbol
After Reset
b10
—
0
b9
—
0
b8
—
0
Bit
b15 to b0
15.2.6
b15
—
0
b14
—
0
b13
—
0
b12
—
0
b11
—
0
Function
These bits specify a transfer source address for data transfer.
Setting Range
0000h to FFFFh
DTC Destination Register (DTDAR)
Address See Table 15.5 Control Data Allocation Addresses.
Bit
b7
b6
b5
b4
b3
Symbol
—
—
—
—
—
After Reset
0
0
0
0
0
b2
—
0
b1
—
0
b0
—
0
Bit
Symbol
After Reset
b10
—
0
b9
—
0
b8
—
0
Bit
b15 to b0
R/W
—
b15
—
0
b14
—
0
b13
—
0
b12
—
0
b11
—
0
Function
These bits specify a transfer destination address for data transfer.
REJ09B0458-0010 Rev.0.10
Page 168 of 572
Apr 01, 2008
Setting Range
0000h to FFFFh
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.2.7
15. DTC
DTC Activation Enable Registers (DTCENi) (i = 0 to 3, 5, 6)
Address 0088h (DTCEN0), 0089h (DTCEN1), 008Ah (DTCEN2), 008Bh (DTCEN3),
008Dh (DTCEN5), 008Eh (DTCEN6)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol DTCENi7 DTCENi6 DTCENi5 DTCENi4 DTCENi3
—
DTCENi1 DTCENi0
After Reset
0
0
0
0
0
0
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
Bit Name
DTCENi0 DTC activation enable bit
DTCENi1
—
Reserved bit
DTCENi3 DTC activation enable bit
DTCENi4
DTCENi5
DTCENi6
DTCENi7
Function
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0: Activation disabled
1: Activation enabled
Set to 0.
0: Activation disabled
1: Activation enabled
i = 0 to 3, 5, 6
The DTCENi registers enable/disable DTC activation by interrupt sources. Table 15.3 shows Correspondences
between Bits DTCENi0 to DTCENi1, Bits DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) and Interrupt Sources.
Table 15.3
Correspondences between Bits DTCENi0 to DTCENi1, Bits DTCENi3 to DTCENi7 (i =
0 to 3, 5, 6) and Interrupt Sources
Register
DTCENi7
Bit
DTCENi6
Bit
DTCENi5
Bit
DTCENi4
Bit
DTCENi3
Bit
DTCEN0
INT0
INT1
—
INT3
UART0
transmission
—
DTCENi1
Bit
DTCENi0
Bit
—
—
UART2
reception
Timer RC
input-capture/
comparematch A
UART2
transmission
Timer RC
input-capture/
comparematch B
DTCEN1
Key input
A/D conversion
UART0
reception
DTCEN2
I2C bus/SSU
receive data
full
I2C bus/SSU
transmit data
empty
Voltage
monitor 2/
comparator A2
Voltage
monitor 1/
comparator A1
—
DTCEN3
Timer RC
input-capture/
comparematch C
Timer RC
input-capture/
comparematch D
—
—
—
—
—
DTCEN5
—
—
Timer RE
—
—
—
—
Timer RB
Flash memory
ready status
—
—
DTCEN6
—
REJ09B0458-0010 Rev.0.10
Page 169 of 572
Timer RA
Apr 01, 2008
—
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.2.8
15. DTC
DTC Activation Control Register (DTCTL)
Address 0080h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
Symbol
—
NMIF
b2
b3
b4
b5
b6
b7
—
—
—
—
—
—
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
NMIF
0
b0
—
0
Bit Name
Function
Reserved bit
Set to 0.
Non-maskable interrupt generation 0: Non-maskable interrupts not generated
1: Non-maskable interrupts generated
bit (1)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
—
Note:
1. This bit is set to 0 when the read result is 1 and 0 is written to the same bit. This bit remains
unchanged even if the read result is 0 and 0 is written to the same bit. This bit remains unchanged if
1 is written to it.
The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog
timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated.
NMIF Bit (Non-Maskable Interrupt Generation Bit)
The NMIF bit is set to 1 when a watchdog timer interrupt, an oscillation stop detection interrupt, a voltage
monitor 1 interrupt, or a voltage monitor 2 interrupt is generated.
When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is
generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed.
REJ09B0458-0010 Rev.0.10
Page 170 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3
15. DTC
Function Description
15.3.1
Overview
When the DTC is activated, control data is read from the DTC control data area to perform data transfers and
control data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can
be stored in the DTC control data area, which allows 24 types of data transfers to be performed.
There are two transfer modes: normal mode and repeat mode. In addition, multiple transfers can be performed
by one activation source (chain transfers) when the CHNE bit in the DTCCR register is set to 1 (chain transfers
enabled).
A transfer source address is specified by the 16-bit register DTSAR, and a transfer destination address is
specified by the 16-bit register DTDAR. The values in the registers DTSAR and DTDAR are separately fixed
or incremented according to the control data on completion of the data transfer.
15.3.2
Activation Sources
The DTC is activated by an interrupt source. Figure 15.2 is a Block Diagram Showing Control of DTC
Activation Sources.
The interrupt sources to activate the DTC are selected with the DTCENi registers (i = 0 to 3, 5, 6). After one
data transfer is completed (after the first transfer is completed in chain transfers), set 0 (activation disabled) to
either of the following: the interrupt source flag in the status register for the peripheral function which generates
the activation source or the corresponding bit among bits DTCENi0 to DTCENi1, and bits DTCENi3 to
DTCENi7 in the DTCENi register.
Table 15.4 shows the DTC Activation Sources and Interrupt Source Flags for Setting to 0 at Data Transfer
Completion.
If multiple activation sources are simultaneously generated, the DTC activation will be performed according to
the DTC activation source priority.
DTC activation is not affected by the I flag or interrupt control register, unlike with interrupt request operation.
Therefore, even if interrupt requests cannot be acknowledged because interrupts are disabled, DTC activation
requests can be acknowledged. The IR bit in the interrupt control register does not change when a DTC
activation request is acknowledged.
Interrupt controller
Interrupt request
Peripheral function 1
Peripheral function 2
bus/SSU, timer RC,
flash memory)
(I2C
Peripheral interrupt
request
Peripheral interrupt
request
Select interrupt source or
DTC activation source
DTC activation
request
DTC
Select DTC activation or
interrupt generation.
DTCENi
Set the interrupt source flag
in the status register to 0.
Set the bit among bits DTCENi0 to DTCENi1,
DTCENi3 to DTCENi7 (i = 0 to 3, 5, 6) to 0.
Clear control
Figure 15.2
Block Diagram Showing Control of DTC Activation Sources
REJ09B0458-0010 Rev.0.10
Page 171 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 15.4
15. DTC
DTC Activation Sources and Interrupt Source Flags for Setting to 0 at Data Transfer
Completion
DTC activation source generation
I2C
bus/SSU receive data full
I2C bus/SSU transmit data empty
Timer RC input-capture/compare-match A
Timer RC input-capture/compare-match B
Timer RC input-capture/compare-match C
Timer RC input-capture/compare-match D
Flash memory ready status
REJ09B0458-0010 Rev.0.10
Page 172 of 572
Interrupt Source Flag for Setting to 0
ICSR register/RDRF bit in SSSR register
Apr 01, 2008
ICSR register/TDRE bit in SSSR register
IMFA bit in TRCSR register
IMFB bit in TRCSR register
IMFC bit in TRCSR register
IMFD bit in TRCSR register
RDYSTI bit in FST register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.3
15. DTC
Control Data Allocation and DTC Vector Table
Control data is allocated in the order: Registers DTCCR, DTBLS, DTCCT, DTRLD, DTSAR, and DTDAR.
Table 15.5 shows the Control Data Allocation Addresses.
Table 15.5
Control Data Allocation Addresses
Register Control
Symbol Data No.
Address
Control
Data 0
Control
Data 1
Control
Data 2
Control
Data 3
Control
Data 4
Control
Data 5
Control
Data 6
Control
Data 7
Control
Data 8
Control
Data 9
Control
Data 10
Control
Data 11
Control
Data 12
Control
Data 13
Control
Data 14
Control
Data 15
Control
Data 16
Control
Data 17
Control
Data 18
Control
Data 19
Control
Data 20
Control
Data 21
Control
Data 22
Control
Data 23
2C40h to
2C47h
2C48h to
2C4Fh
2C50h to
2C57h
2C58h to
2C5Fh
2C60h to
2C67h
2C68h to
2C6Fh
2C70h to
2C77h
2C78h to
2C7Fh
2C80h to
2C87h
2C88h to
2C8Fh
2C90h to
2C97h
2C98h to
2C9Fh
2CA0h to
2CA7h
2CA8h to
2CAFh
2CB0h to
2CB7h
2CB8h to
2CBFh
2CC0h to
2CC7h
2CC8h to
2CCFh
2CD0h to
2CD7h
2CD8h to
2CDFh
2CE0h to
2CE7h
2CE8h to
2CEFh
2CF0h to
2CF7h
2CF8h to
2CFFh
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
DTCD22
DTCD23
REJ09B0458-0010 Rev.0.10
Page 173 of 572
DTCCR
Register
DTBLS
Register
DTCCT
Register
DTRLD
Register
DTSAR
Register
(Lower
8 Bits)
DTSAR
Register
(Higher
8 Bits)
DTDAR
Register
(Lower
8 Bits)
DTDAR
Register
(Higher
8 Bits)
2C40h
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
2C70h
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
2CB0h
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15. DTC
When the DTC is activated, one control data is selected according to the data read from the vector table which
has been assigned to each activation source, and the selected control data is read from the DTC control data
area.
Table 15.6 shows the DTC Activation Sources and DTC Vector Addresses. A one-byte vector table area is
assigned to each activation source and one value from 00000000b to 00010111b is stored in each area to select
one of the 24 control data sets.
Figure 15.3 shows a DTC Internal Operation Flowchart.
Table 15.6
DTC Activation Sources and DTC Vector Addresses
Interrupt Request Source
External input
Key input
A/D
UART0
(Reserved)
UART2
I2C bus/SSU
Voltage detection circuit
Timer RC
(Reserved)
Timer RE
Timer RA
Timer RB
Flash memory
REJ09B0458-0010 Rev.0.10
Page 174 of 572
Interrupt Name
Source No.
DTC Vector Address
Priority
INT0
0
2C00h
High
INT1
(Reserved)
1
2C01h
2
2C02h
3
2C03h
4
8
9
10
11
12
13
14
15
16
17
18
19
22
23
24
25
26
27
28
29
30
31
32
33
42
49
51
52
2C04h
2C08h
2C09h
2C0Ah
2C0Bh
2C0Ch
2C0Dh
2C0Eh
2C0Fh
2C10h
2C11h
2C12h
2C13h
2C16h
2C17h
2C18h
2C19h
2C1Ah
2C1Bh
2C1Ch
2C1Dh
2C1Eh
2C1Fh
2C20h
2C21h
2C2Ah
2C31h
2C33h
2C34h
INT3
(Reserved)
Key input
A/D conversion
UART0 reception
UART0 transmission
—
—
UART2 reception
UART2 transmission
Receive data full
Transmit data empty
Voltage monitor 2/comparator A2
Voltage monitor 1/comparator A1
Input-capture/compare-match A
Input-capture/compare-match B
Input-capture/compare-match C
Input-capture/compare-match D
—
—
—
—
—
—
—
—
Timer RE
Timer RA
Timer RB
Flash memory ready status
Apr 01, 2008
Low
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15. DTC
DTC activation source
generation
Yes
NMIF = 1?
No
Read DTC vector
Read control data
Transfer data
Branch 1
On completion of DTC transfer (on completion of the first DTC
transfer in chain transfers), 0 is written to the bit among bits
DTCENi0 to DTCENi1, DTCENi3 to DTCENi7 and an
interrupt request is generated in either of the following:
- When the DTCCT register value changes to 0 in normal
mode
- When the RPTINT bit is 1 and the DTCCT register value
changes to 0 in repeat mode
Branch 2
0 is written to the interrupt source flag in the peripheral status
register when the DTC activation source is either of the
following:
- I2C bus/SSU receive data full
- I2C bus/SSU transmit data empty
- timer RC input-capture/compare-match A to D
- Flash memory ready status
DTCENi0 to DTCENi1, DTCENi3 to DTCENi7:
Bits in DTCENi registers (i = 0 to 3, 5, 6)
RPTINT: Bit in DTCCR register
Figure 15.3
DTC Internal Operation Flowchart
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Write back control data
Yes
CHNE = 1?
No
Branch 1
Yes
No
Branch 2
No
Write 0 to the bit among
DTCENi0 to DTCENi1,
DTCENi3 to DTCENi7
Yes
Write 0 to the interrupt source
flag in the status register
Generate an interrupt request
for the CPU
End
Interrupt handling
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.4
15. DTC
Normal Mode
One to 256 bytes of data are transferred by one activation. The number of transfer times can be 1 to 256. When
the specified number of transfer times is completed, an interrupt request is generated for the CPU.
Table 15.7 shows Register Functions in Normal Mode.
Figure 15.4 shows Data Transfers in Normal Mode.
Table 15.7
Register Functions in Normal Mode
Register
DTC block size register
DTC transfer count register
DTC transfer count reload
register
DTC source address register
DTC destination address
register
Symbol
DTBLS
DTCCT
DTRLD
Function
Size of the data block to be transferred by one activation
Number of times of data transfers
Not used
DTSAR
DTDAR
Data transfer source address
Data transfer destination address
Transfer source
Transfer destination
SRC
DST
Size of the data block to be transferred
by one activation (N bytes)
Transfer
DTBLS = N
DTSAR = SRC
DTDAR = DST
Bits b3 to b0 in
DTCCR register
00X0b
01X0b
10X0b
11X0b
Source address Destination address
control
control
Fixed
Incremented
Fixed
Incremented
Fixed
Fixed
Incremented
Incremented
X: 0 or 1
Figure 15.4
Data Transfers in Normal Mode
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Source address
after transfer
Destination address
after transfer
SRC
SRC+N
SRC
SRC+N
DST
DST
DST+N
DST+N
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.5
15. DTC
Repeat Mode
One to 255 bytes of data are transferred by one activation. Either of the transfer source or destination should be
specified as the repeat area. The number of transfer times can be 1 to 255. On completion of the specified
number of transfer times, the DTCCT register and the address specified for the repeat area are initialized to
continue transfers. When the RPTINT bit in the DTCCR register is 1 to enable the interrupt generation, an
interrupt request is generated for the CPU after the specified number of transfer times.
The lower 8 bits of the initial value for the repeat area address must be 00h. The size of data to be transferred
must be set to 255 bytes or less before the specified number of transfer times is completed.
Table 15.8 shows Register Functions in Repeat Mode.
Figure 15.5 shows Data Transfers in Repeat Mode.
Table 15.8
Register Functions in Repeat Mode
Register
DTC block size register
DTC transfer count register
DTC transfer count reload
register
DTC source address register
DTC destination address
register
Symbol
DTBLS
DTCCT
DTRLD
Function
Size of the data block to be transferred by one activation
Number of times of data transfers
This register value is reloaded to the DTCCT register. (Data
transfer count is initialized.)
Data transfer source address
Data transfer destination address
DTSAR
DTDAR
DTCCT register ≠ 1
Transfer source
Transfer destination
SRC
DST
Size of the data block to be transferred by
one activation (N bytes)
Transfer
DTBLS = N
DTCCT ≠ 1
DTSAR = SRC
DTDAR = DST
Bits b3 to b0 in
DTCCR register
0X11b
1X11b
X001b
X101b
Source address Destination address
control
control
Repeat area
Repeat area
Fixed
Incremented
Fixed
Incremented
Repeat area
Repeat area
Source address
after transfer
Destination address
after transfer
SRC+N
SRC+N
SRC
SRC+N
DST
DST+N
DST+N
DST+N
X: 0 or 1
DTCCT register = 1
Repeat area
SRC0/DST0
Address of the repeat area is initialized
after a transfer.
…
SRC/DST
Bits b3 to b0 in
DTCCR register
0X11b
1X11b
X001b
X101b
Source address Destination address
control
control
Repeat area
Repeat area
Fixed
Incremented
Fixed
Incremented
Repeat area
Repeat area
SRC0: Initial source address value
DST0: Initial destination address value
X: 0 or 1
Figure 15.5
Data Transfers in Repeat Mode
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DTBLS = N
DTCCT = 1
DTSAR = SRC
DTDAR = DST
Source address
after transfer
Destination address
after transfer
SRC0
SRC0
SRC
SRC+N
DST
DST+N
DST0
DST0
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.6
15. DTC
Chain Transfers
When the CHNE bit in the DTCCR register is 1 (chain transfers enabled), multiple data transfers can be
continuously performed by one activation source. Figure 15.6 shows a Flow of Chain Transfers.
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area.
When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately
following the current control data is read and transferred after the current transfer is completed. This operation
is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is
completed.
DTC activation source
generation
Read DTC vector
Read control data 1
DTC control data area
Control data 1
CHNE = 1
Control data 2
CHNE = 0
Transfer data
Write back control data 1
Read control data 2
Data transfer
Write back control data 2
CHNE: Bit in DTCCR register
Figure 15.6
15.3.7
End of DTC transfers
Flow of Chain Transfers
Interrupt Sources
When the specified number of times of data transfers is completed in normal mode or when completed while
the PRTINT bit in the DTCCR register is 1 (interrupt generation enabled) in repeat mode, the interrupt request
corresponding to the activation source is generated for the CPU. Interrupt requests for the CPU are affected by
the I flag or interrupt control register. In chain transfers, whether the interrupt request is generated or not is
determined either by the number of transfer times specified for the first type of the transfer or the RPTINT bit.
When an interrupt request is generated for the CPU, the bit among bits DTCENi0 to DTCENi1, and bits
DTCENi3 to DTCENi7 in the DTCENi registers (i = 0 to 3, 5, 6) corresponding to the activation source are set
to 0 (activation disabled).
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.8
15. DTC
Operation Timings
The DTC requires four clock cycles to read control data allocated in the DTC control data area. The number of
clock cycles required to write back control data differs depending on the control data settings.
Figure 15.7 shows an Example of DTC Operation Timings and Figure 15.8 shows an Example of DTC
Operation Timings in Chain Transfers.
Table 15.9 shows the Specifications of Control Data Write-Back Operation.
CPU clock
Read vector
Address
Used by CPU
Read
Read control data
Figure 15.7
Write
Transfer data
Used by CPU
Write back control data
Example of DTC Operation Timings
CPU clock
Read vector
Address
Used by CPU
Read
Read control data
Figure 15.8
Table 15.9
Bits b3 to b0
in DTCCR
Register
Address Control
Operating
Mode
Normal
mode
11X0b
Source
Destination
Fixed
Fixed
Incremented
Fixed
Fixed
Incremented
Incremented Incremented
0X11b
X001b
X101b
Write back control data
Read control data
Write
Used by CPU
Transfer data Write back control data
Specifications of Control Data Write-Back Operation
10X0b
1X11b
Transfer data
Read
Example of DTC Operation Timings in Chain Transfers
00X0b
01X0b
Write
Repeat area
Fixed
Incremented
Repeat
mode
Fixed
Repeat area
Incremented
X: 0 or 1
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Control Data to be Written Back
DTRLD
DTSAR
DTDAR
Register
Register
Register
Not written
Not written
Written back Written back
back
back
Not written
Written back Written back Written back
back
Not written
Written back Written back
Written back
back
Written back Written back Written back Written back
Not written
Written back Written back Written back
back
Written back Written back Written back Written back
Not written
Written back Written back
Written back
back
Written back Written back Written back Written back
DTCCT
Register
Number of
Clock
Cycles
1
2
2
3
2
3
2
3
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.3.9
15. DTC
Number of DTC Execution Cycles
Table 15.10 shows the Operations Following DTC Activation and Required Number of Cycles for each
operation.
Table 15.11 shows the Number of Clock Cycles Required for Data Transfers.
Table 15.10
Operations Following DTC Activation and Required Number of Cycles
Vector Read
Control Data Read
Write (J)
1
5 to 7
1
5 to 7
Data Read
Data Write
Internal Operation
(Note 1)
(Note 1)
(Note 1)
(Note 1)
2
2
Note:
1. For the number of clock cycles required for data read/write, see Table 15.11 Number of Clock
Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLS register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte
transfer.
Table 15.11
Operation
Data read
Data write
Number of Clock Cycles Required for Data Transfers
Unit of
Transfers
1-byte SK1
2-byte SK2
1-byte SL1
2-byte SL2
On-Chip RAM
(During DTC Transfers)
Even
Odd
Address
Address
1
1
2
1
1
2
On-Chip
ROM
(User Area)
On-Chip
ROM
(Data Area)
1
2
2
4
—
—
—
—
SFR
(Word Access)
Even
Odd
Address
Address
2
2
4
2
2
SFR
(Byte
Access)
2
4
2
4
4
From Tables 15.10 and 15.11, the total number of required execution cycles can be obtained by the following
formula:
Number of required execution cycles = 1 + Σ[formula A] + 2
Σ: Sum of the cycles for the number of transfer times performed by one activation source ([the number of
transfer times for which CHNE is set to 1] + 1)
(1) For N = 2n (even)
Formula A = J + n • SK2 + n • SL2
(2) For N = 2n+1 (odd)
Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1
J: Number of cycles required to read or write back control data
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
15.4
15. DTC
Notes on DTC
15.4.1
DTC activation source
• Do not generate any DTC activation sources before entering wait mode or during wait mode.
• Do not generate any DTC activation sources before entering stop mode or during stop mode.
15.4.2
DTCENi Registers (i = 0 to 3, 5, 6)
• Modify bits DTCENi0 to DTCENi1, and bits DTCENi3 to DTCENi7 only while an interrupt request
corresponding to the bit is not generated.
• When the interrupt source flag in the status register for the peripheral function is 1, do not modify the
corresponding activation source bit among bits DTCENi0 to DTCENi1, and bits DTCENi3 to DTCENi7.
• Do not access the DTCENi registers using DTC transfers.
15.4.3
Peripheral Modules
• Do not set the status register bit for the peripheral function to 0 using a DTC transfer.
• When the DTC activation source is I2C bus/SSU receive data full, read the SSRDR register/the ICDRR
register using a DTC transfer.
• When the DTC activation source is I2C bus/SSU transmit data empty, write to the SSTDR register/the ICDRT
register using a DTC transfer.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
16. General Overview of Timers
16. General Overview of Timers
The MCU has two 8-bit timers with 8-bit prescalers, a 16-bit timer, and a timer with a 4-bit counter and an 8-bit
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The 16-bit timers are timer RC, and have input capture and output compare
functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate
independently.
Table 16.1 lists Functional Comparison of Timers.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
16. General Overview of Timers
Table 16.1
Functional Comparison of Timers
Item
Count
Count sources
Timer RA
8-bit timer with 8-bit
prescaler (with reload
register)
Decrement
• f1
• f2
• f8
• fOCO
• fC32
• fC
Timer RB
8-bit timer with 8-bit
prescaler (with reload
register)
Decrement
• f1
• f2
• f8
• Timer RA underflow
Function
Timer mode
Timer mode
Event counter mode
—
Pulse width
measurement mode,
pulse period
measurement mode
Pulse output mode (1),
Event counter
mode (1)
—
One-shot waveform
output
—
Three-phase
waveforms output
Timer
—
Configuration
Count of the internal
count source
Count of the external
count source
External pulse width/
period measurement
Timer RE
4-bit counter
8-bit counter
Increment
• f4
• f8
• f32
• fC4
—
—
—
Output compare
mode (1)
Programmable oneshot generation
mode,
Programmable wait
one-shot generation
mode
—
Timer mode (output
compare function;
4 pins) (1),
PWM mode (3 pins),
PWM2 mode (1 pin)
PWM mode (3 pins)
—
—
Timer mode
(only fC32 count)
TRAIO
—
—
Real-time clock mode
INT0
—
Output pin
TRAO
TRAIO
TRBO
Related interrupt
Timer RA interrupt
Timer RB interrupt,
INT0 interrupt
Timer stop
Provided
Provided
INT0, TRCCLK,
TRCTRG, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD
TRCIOA,
TRCIOB, TRCIOC,
TRCIOD
Compare match/input
capture A to D
interrupt,
Overflow interrupt,
INT0 interrupt
Provided
PWM output
Input pin
Programmable
waveform generation
mode
Timer RC
16-bit timer (with input
capture and output
compare)
Increment
• f1
• f2
• f4
• f8
• f32
• fOCO40M
• fOCO-F
• TRCCLK
Timer mode (output
compare function)
Timer mode (output
compare function)
Timer mode (input
capture function;
4 pins)
—
—
Timer RE interrupt
Provided
Note:
1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of
the pulses are the same.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17. Timer RA
17. Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
17.1
Overview
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at
the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 17.2 to 17.6 the
Specification of Each Modes).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and
reloading.
Figure 17.1 shows a Timer RA Block Diagram. Table 17.1 lists Pin Configuration of Timer RA.
Timer RA contains the following five operating modes:
• Timer mode:
The timer counts the internal count source.
• Pulse output mode:
The timer counts the internal count source and outputs pulses which invert the
polarity by underflow of the timer.
• Event counter mode:
The timer counts external pulses.
• Pulse width measurement mode:
The timer measures the pulse width of an external pulse.
• Pulse period measurement mode:
The timer measures the pulse period of an external pulse.
TCK2 to TCK0 bit
f1
f8
fOCO
f2
fC32
fC
= 000b
= 001b
= 010b
= 011b
= 100b
TMOD2 to TMOD0
= other than 010b
= 110b
Data bus
TIOGT1 to TIOGT0 bits
= 00b
TCKCUT
bit
Event input always enabled
= 01b
Do not set
Event enabled for “H” period of
TRCIOD (timer RC compare match signal)
TCSTF
bit
Reload
register
Reload
register
= 10b
Underflow signal
Counter
TRA register
(timer)
Counter
TRAPRE register
(prescaler)
TMOD2 to TMOD0
= 010b
Timer RA interrupt
TIPF1 to TIPF0 bits
= 01b
f1
= 10b
f8
= 11b
f32
Digital
filter
TIPF1 to TIPF0 bits
= other than
000b
TMOD2 to TMOD0
= 011b or 100b
Count control
circle
Polarity
switching
= 00b
TRAIO pin
TMOD2 to TMOD0 = 001b
TEDGSEL = 1
TOPCR bit
Q
(1)
Q
TOENA bit
TEDGSEL = 0
Measurement
completion signal
Toggle
flip-flop
CK
CLR
Write to TRAMR register
Write 1 to TSTOP bit
TRAO pin
TCSTF, TSTOP: TRACR register
TEDGSEL, TOPCR, TOENA, TIPF1, TIPF0, TIOGT1, TIOGT0: TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register
Note:
1. Bits TRAIOSEL0 and TRAIOSEL1 in the TRASR register are used to select which pin is assigned.
Figure 17.1
Table 17.1
Pin Name
Timer RA Block Diagram
Pin Configuration of Timer RA
Assigned Pin
TRAIO
P1_5 or P1_7
TRAO
P3_7
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I/O
I/O
Output
Apr 01, 2008
Function
Function differs according to the mode.
Refer to descriptions of individual modes
for details
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.2
17. Timer RA
Registers
17.2.1
Timer RA Control Register (TRACR)
Address 0100h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
TUNDF
0
Bit
b0
Symbol
Bit Name
TSTART Timer RA count start bit (1)
b1
TCSTF
b2
TSTOP
b3
b4
—
TEDGF
b5
TUNDF
b6
b7
—
—
b4
TEDGF
0
b3
—
0
b2
TSTOP
0
b1
TCSTF
0
b0
TSTART
0
Function
0: Count stops
1: Count starts
0: Count stops
Timer RA count status flag (1)
1: During count
(2)
When this bit is set to 1, the count is forcibly stopped.
Timer RA count forcible stop bit
When read, its content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
0: Active edge not received
Active edge judgment flag (3, 4)
1: Active edge received (end of measurement period)
0: No underflow
Timer RA underflow flag (3, 4)
1: Underflow
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R
R/W
—
R/W
R/W
—
Notes:
1. Refer to 17.8 Notes on Timer RA for precautions regarding bits TSTART and TCSTF.
2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values
after a reset.
3. Bits TEDGF and TUNDF can be set to 0 by writing 0 to these bits by a program. However, their value remains
unchanged when 1 is written.
4. Set to 0 in timer mode, pulse output mode, and event counter mode.
In pulse width measurement mode and pulse period measurement mode, use the MOV instruction to set the
TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, write 1 to them.
17.2.2
Timer RA I/O Control Register (TRAIOC)
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
TIOGT0
b5
TIPF1
b4
TIPF0
b3
TIOSEL
b2
TOENA
0
0
0
0
0
0
Symbol
TEDGSEL
TOPCR
TOENA
TIOSEL
TIPF0
TIPF1
TIOGT0
TIOGT1
Bit Name
TRAIO polarity switch bit
TRAIO output control bit
TRAO output enable bit
Hardware LIN function select bit
TRAIO input filter select bit
TRAIO event input control bit
REJ09B0458-0010 Rev.0.10
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b1
b0
TOPCR TEDGSEL
0
0
Function
R/W
Function varies according to the operating mode. R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.2.3
Timer RA Mode Register (TRAMR)
Address 0102h
Bit
b7
Symbol TCKCUT
After Reset
0
Bit
b0
b1
b2
17. Timer RA
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
Symbol
Bit Name
TMOD0 Timer RA operating mode select bit
TMOD1
TMOD2
b3
—
0
b2
TMOD2
0
b1
TMOD1
0
b0
TMOD0
0
Function
R/W
R/W
R/W
R/W
b2 b1 b0
0 0 0: Timer mode
0 0 1: Pulse output mode
0 1 0: Event counter mode
0 1 1: Pulse width measurement mode
1 0 0: Pulse period measurement mode
1 0 1: Do not set.
1 1 0: Do not set.
1 1 1: Do not set.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b6 b5 b4
TCK0 Timer RA count source select bit
0 0 0: f1
TCK1
0 0 1: f8
TCK2
0 1 0: fOCO
0 1 1: f2
1 0 0: fC32
1 0 1: Do not set.
1 1 0: fC
1 1 1: Do not set.
TCKCUT Timer RA count source cutoff bit
0: Provides count source
1: Cuts off count source
b3
b4
b5
b6
b7
—
R/W
R/W
R/W
R/W
When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rewrite this register.
17.2.4
Timer RA Prescaler Register (TRAPRE)
Address 0103h
Bit
b7
Symbol
—
After Reset
1
b6
—
1
b5
—
1
Bit
Mode
b7 to b0 Timer mode
Pulse output mode
Event counter mode
Pulse width measurement mode
b4
—
1
b3
—
1
b2
—
1
b1
—
1
Function
Counts an internal count source
Counts an external count source
Measure pulse width of input pulses from
external (counts internal count source)
Pulse period measurement mode Measure pulse period of input pulses from
external (counts internal count source)
b0
—
1
Setting Range
00h to FFh
00h to FFh
00h to FFh
00h to FFh
R/W
R/W
R/W
R/W
R/W
00h to FFh
R/W
Note:
1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
REJ09B0458-0010 Rev.0.10
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(Note 1)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.2.5
17. Timer RA
Timer RA Register (TRA)
Address 0104h
Bit
b7
Symbol
—
After Reset
1
b6
—
1
Bit
Mode
b7 to b0 All modes
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
Function
Counts on underflow of TRAPRE register
b0
—
1
(Note 1)
Setting Range
00h to FFh
R/W
R/W
Note:
1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
17.2.6
Timer RA Pin Select Register (TRASR)
Address 0180h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
Symbol
Bit Name
TRAIOSEL0 TRAIO pin select bit
TRAIOSEL1
—
—
—
—
—
—
Reserved bits
b4
—
0
b3
—
0
b2
—
0
b1
b0
TRAIOSEL1 TRAIOSEL0
0
0
Function
b1 b0
0 0: TRAIO pin not used
0 1: P1_7 assigned
1 0: P1_5 assigned
1 1: Do not set.
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
R/W
—
The TRASR register selects which pin is assigned to the timer RA I/O. To use the I/O pin for timer RA, set this
register.
Set the TRASR register before setting the timer RA associated registers. Also, do not change the setting value
in this register during timer RA operation.
REJ09B0458-0010 Rev.0.10
Page 187 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.3
17. Timer RA
Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 17.2 Timer Mode
Specifications).
Table 17.2
Timer Mode Specifications
Item
Count sources
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
TRAIO pin function
TRAO pin function
Read from timer
Write to timer
17.3.1
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
Programmable I/O port
Programmable I/O port
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.3.2 Timer Write Control
during Count Operation).
Timer RA I/O Control Register (TRAIOC) in Timer Mode
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
0
Bit
b0
b1
b2
b3
Symbol
TEDGSEL
TOPCR
TOENA
TIOSEL
b4
b5
b6
b7
TIPF0
TIPF1
TIOGT0
TIOGT1
b6
TIOGT0
0
b5
TIPF1
0
b4
TIPF0
0
Bit Name
TRAIO polarity switch bit
TRAIO output control bit
TRAO output enable bit
Hardware LIN function select bit
TRAIO input filter select bit
TRAIO event input control bit
REJ09B0458-0010 Rev.0.10
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b3
TIOSEL
0
b2
TOENA
0
b1
b0
TOPCR TEDGSEL
0
0
Function
Set to 0 in timer mode.
Set to 0. However, set to 1 when the hardware
LIN function is used.
Set to 0 in timer mode.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.3.2
17. Timer RA
Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 17.2 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
Count source
After writing, the reload register is
written to at the first count source.
Reload register of
timer RA prescaler
Previous value
New value (01h)
Reload at
second count
source
Counter of
timer RA prescaler
06h
05h
04h
01h
00h
Reload at
underflow
01h
00h
01h
00h
01h
00h
After writing, the reload register is
written to at the first underflow.
Reload register of
timer RA
Previous value
New value (25h)
Reload at the second underflow
Counter of timer RA
IR bit in TRAIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow is
generated by a new value.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (during count).
Figure 17.2
Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
REJ09B0458-0010 Rev.0.10
Page 189 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.4
17. Timer RA
Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 17.3 Pulse Output Mode
Specifications).
Table 17.3
Pulse Output Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
Interrupt request
generation timing
TRAIO pin function
Pulse output, programmable output port
TRAO pin function
Programmable I/O port or inverted output of TRAIO
Read from timer
The count value can be read by reading registers TRA and TRAPRE.
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.3.2 Timer Write Control
during Count Operation).
Selectable functions
• TRAIO signal polarity switch function
The level when the pulse output starts is selected by the TEDGSEL bit in the
TRAIOC register. (1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO pin
(selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
• TRAIO pin select function
P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR
register.
Note:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
REJ09B0458-0010 Rev.0.10
Page 190 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.4.1
17. Timer RA
Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
0
Bit
b0
b6
TIOGT0
0
b5
TIPF1
0
b4
TIPF0
0
Symbol
Bit Name
TEDGSEL TRAIO polarity switch bit
b1
TOPCR
TRAIO output control bit
b2
TOENA
TRAO output enable bit
b3
b4
b5
b6
b7
TIOSEL
TIPF0
TIPF1
TIOGT0
TIOGT1
Hardware LIN function select bit
TRAIO input filter select bit
TRAIO event input control bit
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
b3
TIOSEL
0
b2
TOENA
0
b1
b0
TOPCR TEDGSEL
0
0
Function
0: TRAIO output starts at “H”
1: TRAIO output starts at “L”
0: TRAIO output
1: Port P1_7 or P1_5
0: Port P3_7
1: TRAO output (inverted TRAIO output from P3_7)
Set to 0.
Set to 0 in pulse output mode.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.5
17. Timer RA
Event Counter Mode
In event counter mode, external signal inputs to the TRAIO pin are counted (refer to Table 17.4 Event
Counter Mode Specifications).
Table 17.4
Event Counter Mode Specifications
Item
Count source
Count operations
Specification
External signal which is input to TRAIO pin (active edge selectable by a program)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
Interrupt request
generation timing
TRAIO pin function
Count source input
TRAO pin function
Programmable I/O port or pulse output (1)
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.3.2 Timer Write Control
during Count Operation).
Selectable functions
• INT1 input polarity switch function
The active edge of the count source is selected by the TEDGSEL bit in the
TRAIOC register.
• Count source input pin select function
P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR
register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register). (1)
• Digital filter function
Whether enabling or disabling the digital filter and the sampling frequency is
selected by bits TIPF0 and TIPF1 in the TRAIOC register.
• Event input control function
The enabled period for the event input to the TRAIO pin is selected by bits
TIOGT0 and TIOGT1 in the TRAIOC register.
Note:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
REJ09B0458-0010 Rev.0.10
Page 192 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.5.1
17. Timer RA
Timer RA I/O Control Register (TRAIOC) in Event Counter Mode
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
0
Bit
b0
b6
TIOGT0
0
b5
TIPF1
0
b4
TIPF0
0
b3
TIOSEL
0
b2
TOENA
0
b1
b0
TOPCR TEDGSEL
0
0
Symbol
Bit Name
TEDGSEL TRAIO polarity switch bit
b1
b2
TOPCR
TOENA
b3
b4
b5
TIOSEL
TIPF0
TIPF1
b6
b7
TIOGT0
TIOGT1
Function
0: Starts counting at rising edge of the TRAIO input
and TRAO starts output at “L”
1: Starts counting at falling edge of the TRAIO input
and TRAO starts output at “H”
TRAIO output control bit
Set to 0 in event counter mode.
TRAO output enable bit
0: Port P3_7
1: TRAO output
Hardware LIN function select bit Set to 0.
b5 b4
TRAIO input filter select bit (1)
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
b7 b6
TRAIO event input control bit
0 0: Event input always enabled
0 1: Do not set.
1 0: Event enabled for “H” period of timer RC
compare match signal
1 1: Do not set.
Note:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
REJ09B0458-0010 Rev.0.10
Page 193 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.6
17. Timer RA
Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the TRAIO pin is measured
(refer to Table 17.5 Pulse Width Measurement Mode Specifications).
Figure 17.3 shows an Operating Example of Pulse Width Measurement Mode.
Table 17.5
Pulse Width Measurement Mode Specifications
Item
Count sources
Count operations
Count start condition
Count stop conditions
Interrupt request
generation timing
TRAIO pin function
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
Measured pulse input
TRAO pin function
Read from timer
Write to timer
Programmable I/O port
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.3.2 Timer Write
Control during Count Operation).
Selectable functions
• Measurement level setting
The “H” level or “L” level period is selected by the TEDGSEL bit in the
TRAIOC register.
• Measured pulse input pin select function
P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR
register.
• Digital filter function
Whether enabling or disabling the digital filter and the sampling frequency is
selected by bits TIPF0 and TIPF1 in the TRAIOC register.
REJ09B0458-0010 Rev.0.10
Page 194 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.6.1
17. Timer RA
Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement
Mode
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
0
Bit
b0
b6
TIOGT0
0
b5
TIPF1
0
b4
TIPF0
0
Symbol
Bit Name
TEDGSEL TRAIO polarity switch bit
b1
b2
b3
TOPCR
TOENA
TIOSEL
TRAIO output control bit
TRAO output enable bit
Hardware LIN function select bit
b4
b5
TIPF0
TIPF1
TRAIO input filter select bit (1)
b6
b7
TIOGT0
TIOGT1
TRAIO event input control bit
b3
TIOSEL
0
b2
TOENA
0
b1
b0
TOPCR TEDGSEL
0
0
Function
0: TRAIO input starts at “L”
1: TRAIO input starts at “H”
Set to 0 in pulse width measurement mode.
Set to 0. However, set to 1 when the hardware
LIN function is used.
b5 b4
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
Set to 0 in pulse width measurement mode.
Note:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
REJ09B0458-0010 Rev.0.10
Page 195 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.6.2
17. Timer RA
Operating Example
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
FFFFh
Count start
Underflow
Content of counter (hex)
n
Count stop
Count stop
Count start
0000h
Count start
Period
Set to 1 by program
TSTART bit in
TRACR register
1
Measured pulse
(TRAIO pin input)
1
0
0
Set to 0 when interrupt request is acknowledged, or set by program
IR bit in TRAIC
register
1
0
Set to 0 by program
TEDGF bit in
TRACR register
1
0
Set to 0 by program
TUNDF bit in
TRACR register
1
0
The above applies under the following conditions.
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Figure 17.3
Operating Example of Pulse Width Measurement Mode
REJ09B0458-0010 Rev.0.10
Page 196 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.7
17. Timer RA
Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the TRAIO pin is measured
(refer to Table 17.6 Pulse Period Measurement Mode Specifications).
Figure 17.4 shows an Operating Example of Pulse Period Measurement Mode.
Table 17.6
Pulse Period Measurement Mode Specifications
Item
Count sources
Count operations
Count start condition
Count stop conditions
Interrupt request
generation timing
TRAIO pin function
TRAO pin function
Read from timer
Write to timer
Selectable functions
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
Measured pulse input (1)
Programmable I/O port
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 17.3.2 Timer Write
Control during Count Operation).
• Measurement period selection
The measurement period of the input pulse is selected by the TEDGSEL in
the TRAIOC register.
• Measured pulse input pin select function
P1_5 or P1_7 is selected by bits TRAIOSEL0 to TRAIOSEL1 in the TRASR
register.
• Digital filter function
Whether enabling or disabling the digital filter and the sampling frequency is
selected by bits TIPF0 and TIPF1 in the TRAIOC register.
Note:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input
to the TRAIO pin, the input may be ignored.
REJ09B0458-0010 Rev.0.10
Page 197 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.7.1
17. Timer RA
Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement
Mode
Address 0101h
Bit
b7
Symbol TIOGT1
After Reset
0
Bit
b0
b6
TIOGT0
0
b5
TIPF1
0
b4
TIPF0
0
Symbol
Bit Name
TEDGSEL TRAIO polarity switch bit
b1
b2
b3
b4
b5
TOPCR
TOENA
TIOSEL
TIPF0
TIPF1
TRAIO output control bit
TRAO output enable bit
Hardware LIN function select bit
TRAIO input filter select bit (1)
b6
b7
TIOGT0
TIOGT1
TRAIO event input control bit
b3
TIOSEL
0
b2
TOENA
0
b1
b0
TOPCR TEDGSEL
0
0
Function
0: Measures measurement pulse from one rising
edge to next rising edge
1: Measures measurement pulse from one falling
edge to next falling edge
Set to 0 in pulse period measurement mode.
Set to 0.
b5 b4
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
Set to 0 in pulse period measurement mode.
Note:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
REJ09B0458-0010 Rev.0.10
Page 198 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.7.2
17. Timer RA
Operating Example
Underflow signal of
timer RA prescaler
Set to 1 by program
TSTART bit in
TRACR register
1
0
Count start
Measurement pulse
(TRAIO pin input)
1
0
TRA reloaded
TRA reloaded
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
Contents of TRA
01h 00h 0Fh 0Eh
Underflow
Retained
Contents of read-out
buffer (1)
0Fh
0Eh
Retained
0Bh 0Ah
0Dh
09h
0Dh
01h 00h 0Fh 0Eh
TRA read (3)
(Note 2)
TEDGF bit in
TRACR register
(Note 2)
1
0
Set to 0 by program
(Note 4)
(Note 6)
TUNDF bit in
TRACR register
1
0
Set to 0 by program
IR bit in TRAIC
register
(Note 5)
1
0
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
Notes:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge received) when the
timer RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge received).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 17.4
Operating Example of Pulse Period Measurement Mode
REJ09B0458-0010 Rev.0.10
Page 199 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
17.8
17. Timer RA
Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count
starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0
to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READMODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these
bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is
not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF
are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count
starts) while the count is stopped.
During this time, do not access registers associated with timer RA (1) other than the TCSTF bit. Timer RA starts
counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops)
while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA (1) other than the TCSTF bit.
Note:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or
more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or
more cycles of the prescaler underflow for each write interval.
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18. Timer RB
18. Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
18.1
Overview
The prescaler and timer each consist of a reload register and counter (refer to Tables 18.2 to 18.5 the
Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 18.1 shows a Timer RB Block Diagram. Table 18.1 lists Pin Configuration of Timer RB.
Timer RB has four operation modes listed as follows:
• Timer mode:
The timer counts an internal count source (peripheral
function clock or timer RA underflows).
The timer outputs pulses of a given width successively.
The timer outputs a one-shot pulse.
The timer outputs a delayed one-shot pulse.
• Programmable waveform generation mode:
• Programmable one-shot generation mode:
• Programmable wait one-shot generation mode:
Data bus
TRBSC
register
Reload
register
Reload
register
Bits TCK1 to TCK0
f1
f8
= 00b
Timer RA underflow
= 10b
= 11b
f2
TRBPR
register
Reload
register
TCKCUT bit
= 01b
Counter
TRBPRE register
(prescaler)
Timer RB interrupt
Counter (timer RB)
(Timer)
TMOD1 to TMOD0 bits
= 10b or 11b
TSTART bit
TOSSTF bit
INT0 interrupt
Input polarity
selected to be one
edge or both edges
Digital filter
INT0 pin
INT0PL bit
Bits TMOD1 to TMOD0
= 01b, 10b, 11b
Polarity
select
INOSEG bit
INT0EN bit
INOSTG bit
TOPL = 1
TOCNT = 0
TRBO pin
P1_3 bit in P1 register
TOCNT = 1
TOPL = 0
Q
Toggle
flip-flop
Q
CLR
CK
TCSTF bit
Bits TMOD1 to TMOD0
= 01b, 10b, 11b
TSTART, TCSTF: Bits in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
Figure 18.1
Table 18.1
Pin Name
TRBO
Timer RB Block Diagram
Pin Configuration of Timer RB
Assigned Pin
P1_3
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I/O
Function
Output
Pulse output (Programmable waveform
generation mode, Programmable one-shot
generation mode, Programmable wait oneshot generation mode)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.2
18. Timer RB
Registers
18.2.1
Timer RB Control Register (TRBCR)
Address 0108h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
Bit
b0
Symbol
Bit Name
TSTART Timer RB count start bit (1)
b1
TCSTF
b2
TSTOP
b3
b4
b5
b6
b7
—
—
—
—
—
b4
—
0
b3
—
0
b2
TSTOP
0
b1
TCSTF
0
b0
TSTART
0
Function
0: Count stops
1: Count starts
0: Count stops
Timer RB count status flag (1)
1: During count (3)
(1,
2)
When this bit is set to 1, the count is forcibly
Timer RB count forcible stop bit
stopped. When read, the content is 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R
R/W
—
Notes:
1. Refer to 18.7 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP.
2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the
TOSSTF bit in the TRBOCR register are set to values after a reset.
3. Indicates that count operation is in progress in timer mode or programmable waveform mode. In programmable
one-shot generation mode or programmable wait one-shot generation mode, indicates that a one-shot pulse
trigger has been acknowledged.
18.2.2
Timer RB One-Shot Control Register (TRBOCR)
Address 0109h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
TOSST
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
TOSSTF
0
b1
TOSSP
0
Bit Name
Timer RB one-shot start bit
b0
TOSST
0
Function
When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
TOSSP Timer RB one-shot stop bit
When this bit is set to 1, counting of one-shot
pulses (including programmable wait one-shot
pulses) stops. When read, the content is 0.
TOSSTF Timer RB one-shot status flag (1)
0: One-shot stopped
1: One-shot operating (Including wait period)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
—
R/W
R/W
R/W
R
—
Note:
1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
This register is enabled when bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable oneshot generation mode) or 11b (programmable wait one-shot generation mode).
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.2.3
18. Timer RB
Timer RB I/O Control Register (TRBIOC)
Address 010Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
18.2.4
Symbol
TOPL
TOCNT
INOSTG
INOSEG
—
—
—
—
b2
b3
b4
b5
b6
b7
b5
—
0
b4
—
0
b3
b2
INOSEG INOSTG
0
0
b1
TOCNT
0
b0
TOPL
0
Bit Name
Function
Timer RB output level select bit
Function varies according to the operating mode.
Timer RB output switch bit
One-shot trigger control bit
One-shot trigger polarity select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
R/W
R/W
—
Timer RB Mode Register (TRBMR)
Address 010Bh
Bit
b7
Symbol TCKCUT
After Reset
0
Bit
b0
b1
b6
—
0
b6
—
0
b5
TCK1
0
b4
TCK0
0
b3
TWRC
0
b2
—
0
b1
TMOD1
0
b0
TMOD0
0
Symbol
Bit Name
Function
TMOD0 Timer RB operating mode select bit (1) b1 b0
0 0: Timer mode
TMOD1
0 1: Programmable waveform generation mode
1 0: Programmable one-shot generation mode
1 1: Programmable wait one-shot generation
mode
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
TWRC Timer RB write control bit (2)
0: Write to reload register and counter
1: Write to reload register only
b5 b4
TCK0 Timer RB count source select bit (1)
0 0: f1
TCK1
0 1: f8
1 0: Timer RA underflow
1 1: f2
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
TCKCUT Timer RB count source cutoff bit (1)
0: Provides count source
1: Cuts off count source
R/W
R/W
R/W
—
R/W
R/W
R/W
—
R/W
Notes:
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT when both the TSTART and TCSTF bits in the
TRBCR register set to 0 (count stops).
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode,
programmable one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must
be set to 1 (write to reload register only).
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.2.5
18. Timer RB
Timer RB Prescaler Register (TRBPRE)
Address 010Ch
Bit
b7
Symbol
—
After Reset
1
b6
—
1
b5
—
1
Bit
Mode
b7 to b0 Timer mode
Programmable waveform generation
mode
Programmable one-shot generation
mode
Programmable wait one-shot
generation mode
b4
—
1
b3
—
1
b2
—
1
b1
—
1
Function
Counts an internal count source or
timer RA underflows
b0
—
1
Setting Range
00h to FFh
00h to FFh
R/W
R/W
R/W
00h to FFh
R/W
00h to FFh
R/W
When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
18.2.6
Timer RB Secondary Register (TRBSC)
Address 010Dh
Bit
b7
Symbol
—
After Reset
1
b6
—
1
b5
—
1
Bit
Mode
b7 to b0 Timer mode
Programmable waveform generation
mode
Programmable one-shot generation
mode
Programmable wait one-shot
generation mode
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Function
Setting Range
Disabled
00h to FFh
Counts timer RB prescaler underflows (1) 00h to FFh
R/W
—
W (2)
Disabled
00h to FFh
—
Counts timer RB prescaler underflows
(one-shot width is counted)
00h to FFh
W (2)
Notes:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. The count value can be read out by reading the TRBPR register even when the secondary period is being
counted.
When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
To write to the TRBSC register, perform the following steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, write the same value second time.)
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.2.7
18. Timer RB
Timer RB Primary Register (TRBPR)
Address 010Eh
Bit
b7
Symbol
—
After Reset
1
b6
—
1
b5
—
1
Bit
Mode
b7 to b0 Timer mode
Programmable waveform generation
mode
Programmable one-shot generation
mode
Programmable wait one-shot
generation mode
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Function
Setting Range
Counts timer RB prescaler underflows
00h to FFh
Counts timer RB prescaler underflows (1) 00h to FFh
R/W
R/W
R/W
Counts timer RB prescaler underflows
(one-shot width is counted)
Counts timer RB prescaler underflows
(wait period width is counted)
00h to FFh
R/W
00h to FFh
R/W
Note:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.3
18. Timer RB
Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
18.2 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Table 18.2
Timer Mode Specifications
Item
Count sources
Count operations
Specification
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
TRBO pin function
INT0 pin function
Read from timer
Write to timer
18.3.1
Programmable I/O port
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 18.3.2 Timer Write Control during Count Operation.)
Timer RB I/O Control Register (TRBIOC) in Timer Mode
Address 010Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
1 (count starts) is written to the TSTART bit in the TRBCR register.
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
When timer RB underflows [timer RB interrupt].
Symbol
TOPL
TOCNT
INOSTG
INOSEG
—
—
—
—
b6
—
0
b5
—
0
b4
—
0
b3
b2
INOSEG INOSTG
0
0
b1
TOCNT
0
Bit Name
Function
Timer RB output level select bit
Set to 0 in timer mode.
Timer RB output switch bit
One-shot trigger control bit
One-shot trigger polarity select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
REJ09B0458-0010 Rev.0.10
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b0
TOPL
0
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.3.2
18. Timer RB
Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload register.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 18.2 shows an Operating Example of Timer RB when Counter
Value is Rewritten during Count Operation.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18. Timer RB
When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
Counter of
timer RB prescaler
06h
05h
New value (01h)
04h
Reload with
the second
count source
Reload on
underflow
01h
01h
00h
00h
01h
00h
01h
00h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on the second
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
New value (01h)
Reload on
underflow
Counter of
timer RB prescaler
06h
05h
04h
03h
02h
01h
00h
01h
00h
01h
00h
01h
00h
01h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
01h
00h
25h
0
Only the prescaler values are updated,
extending the duration until timer RB underflow.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 18.2
Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.4
18. Timer RB
Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 18.3
Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the
TRBPR register. The TRBOCR register is unused in this mode.
Figure 18.3 shows an Operating Example of Timer RB in Programmable Waveform Generation Mode.
Table 18.3
Programmable Waveform Generation Mode Specifications
Item
Count sources
Count operations
Width and period of
output waveform
Count start condition
Count stop conditions
Interrupt request
generation timing
TRBO pin function
INT0 pin function
Read from timer
Write to timer
Selectable functions
Specification
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the contents of the primary reload and secondary
reload registers alternately before the count continues.
Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
1 (count start) is written to the TSTART bit in the TRBCR register.
• 0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
In half a cycle of the count source, after timer RB underflows during the secondary period
(at the same time as the TRBO output change) [timer RB interrupt]
Programmable output port or pulse output
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE (1).
• When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation,
values are written to the reload registers only. (2)
• Output level select function
The output level during primary and secondary periods is selected by the TOPL bit in the
TRBIOC register.
• TRBO pin output switch function
Timer RB pulse output or P1_3 latch output is selected by the TOCNT bit in the TRBIOC
register. (3)
Notes:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after writing to
the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
• When counting starts.
• When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following primary period.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.4.1
18. Timer RB
Timer RB I/O Control Register (TRBIOC) in Programmable Waveform
Generation Mode
Address 010Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
TOPL
b6
—
0
b5
—
0
b4
—
0
Bit Name
Timer RB output level select bit
b3
b2
INOSEG INOSTG
0
0
b1
TOCNT
0
b0
TOPL
0
Function
0: Outputs “H” for primary period
Outputs “L” for secondary period
Outputs “L” when the timer is stopped
1: Outputs “L” for primary period
Outputs “H” for secondary period
Outputs “H” when the timer is stopped
TOCNT Timer RB output switch bit
0: Outputs timer RB waveform
1: Outputs value in P1_3 port register
INOSTG One-shot trigger control bit
Set to 0 in programmable waveform generation
mode.
INOSEG One-shot trigger polarity select bit
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
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R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.4.2
18. Timer RB
Operating Example
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads
01h
Counter of timer RB
00h
02h
01h
Timer RB primary reloads
00h
01h
00h
02h
Set to 0 when interrupt
request is acknowledged,
or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in TRBIO
register
1
0
Waveform
output starts
Waveform output inverted
Waveform output starts
1
TRBO pin output
0
Initial output is the same level
as during secondary period.
Primary period
Secondary period
Primary period
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 18.3
Operating Example of Timer RB in Programmable Waveform Generation Mode
REJ09B0458-0010 Rev.0.10
Page 211 of 572
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.5
18. Timer RB
Programmable One-shot Generation Mode
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 18.4 Programmable One-Shot Generation Mode
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given period
equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 18.4 shows an Operating Example of Programmable One-Shot Generation Mode.
Table 18.4
Programmable One-Shot Generation Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
(n+1)(m+1)/fi
output time
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)
Interrupt request
In half a cycle of the count source, after the timer underflows (at the same time as
generation timing
the TRBO output ends) [timer RB interrupt]
TRBO pin function
Pulse output
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
INT0 pin functions
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer
The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload) (1).
Selectable functions • Output level select function
The output level of the one-shot pulse waveform is selected by the TOPL bit in
the TRBIOC register.
• One-shot trigger select function
Refer to 18.5.3 One-Shot Trigger Selection.
Note:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
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R8C/32A Group
18.5.1
18. Timer RB
Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot
Generation Mode
Address 010Ah
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
Bit
b0
Symbol
TOPL
b1
TOCNT Timer RB output switch bit
b2
INOSTG One-shot trigger control bit (1)
b3
b4
b5
b6
b7
b4
—
0
Bit Name
Timer RB output level select bit
b3
b2
INOSEG INOSTG
0
0
b1
TOCNT
0
b0
TOPL
0
Function
0: Outputs one-shot pulse “H”
Outputs “L” when the timer is stopped
1: Outputs one-shot pulse “L”
Outputs “H” when the timer is stopped
Set to 0 in programmable one-shot generation
mode.
0: INT0 pin one-shot trigger disabled
1: INT0 pin one-shot trigger enabled
INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger
1: Rising edge trigger
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
Note:
1. Refer to 18.5.3 One-Shot Trigger Selection.
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R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.5.2
18. Timer RB
Operating Example
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Set to 0 when
counting ends
Set to 1 by program
TOSSTF bit in TRBOCR
register
Set to 1 by INT0 pin
input trigger
1
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
01h
Counter of timer RB
Timer RB primary reloads
00h
Count starts
01h
Timer RB primary reloads
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Waveform output starts
Waveform output ends
Waveform output starts
1
TRBIO pin output
0
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 18.4
Operating Example of Programmable One-Shot Generation Mode
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Waveform output ends
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.5.3
18. Timer RB
One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 11. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG
bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value
of the IR bit in the INT0IC register changes.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.6
18. Timer RB
Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 18.5 Programmable Wait One-Shot Generation Mode
Specifications). When a trigger is generated from that point, the timer outputs a pulse only once for a given length
of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting
value in the TRBPR register.
Figure 18.5 shows an Operating Example of Programmable Wait One-Shot Generation Mode.
Table 18.5
Programmable Wait One-Shot Generation Mode Specifications
Item
Count sources
Count operations
Wait time
One-shot pulse output time
Count start conditions
Count stop conditions
Interrupt request generation
timing
TRBO pin function
INT0 pin functions
Read from timer
Write to timer
Selectable functions
Specification
f1, f2, f8, timer RA underflow
• Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the contents of
timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents
of timer RB primary before the count completes and the TOSSTF bit is set to 0
(one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it
stops.
(n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register
(n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger
is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).
In half a cycle of the count source after timer RB underflows during secondary period
(complete at the same time as waveform output from the TRBO pin) [timer RB
interrupt].
Pulse output
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only. (1)
• Output level select function
The output level of the one-shot pulse waveform is selected by the TOPL bit in the
TRBIOC register.
• One-shot trigger select function
Refer to 18.5.3 One-Shot Trigger Selection.
Note:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.6.1
18. Timer RB
Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot
Generation Mode
Address 010Ah
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
Bit
b0
Symbol
TOPL
b1
TOCNT Timer RB output switch bit
b2
INOSTG One-shot trigger control bit (1)
b3
b4
b5
b6
b7
b4
—
0
Bit Name
Timer RB output level select bit
b3
b2
INOSEG INOSTG
0
0
b1
TOCNT
0
b0
TOPL
0
Function
0: Outputs one-shot pulse “H”
Outputs “L” when the timer stops or during wait
1: Outputs one-shot pulse “L”
Outputs “H” when the timer stops or during wait
Set to 0 in programmable wait one-shot generation
mode.
0: INT0 pin one-shot trigger disabled
1: INT0 pin one-shot trigger enabled
INOSEG One-shot trigger polarity select bit (1) 0: Falling edge trigger
1: Rising edge trigger
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
Note:
1. Refer to 18.5.3 One-Shot Trigger Selection.
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R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.6.2
18. Timer RB
Operating Example
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
TOSSTF bit in TRBOCR
register
Set to 0 when
counting ends
1
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
01h
Counter of timer RB
Timer RB secondary reloads
00h
04h
Timer RB primary reloads
03h
02h
01h
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Wait starts
Waveform output starts
Waveform output ends
1
TRBIO pin output
0
Wait
(primary period)
One-shot pulse
(secondary period)
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 18.5
Operating Example of Programmable Wait One-Shot Generation Mode
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.7
18. Timer RB
Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count
starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU.
Consequently, the timer value may be updated during the period when these two registers are being read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the
TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the TRBOCR register to
1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot
generation mode and programmable wait one-shot generation mode, read the timer count value before the timer
stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RB (1) other than the TCSTF bit. Timer RB starts
counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops)
while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB (1) other than the TCSTF bit.
Note:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after
one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between
when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or
1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the
TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.
18.7.1
Timer Mode
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
18.7.2
Programmable Waveform Generation Mode
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
18.7.3
18. Timer RB
Programmable One-shot Generation Mode
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three
or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
18.7.4
Programmable Wait One-shot Generation Mode
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit in the TRBCR register is set to
1), note the following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for
each write interval.
REJ09B0458-0010 Rev.0.10
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19. Timer RC
Timer RC is a 16-bit timer with four I/O pins.
19.1
Overview
Timer RC uses either f1, fOCO40M or fOCO-F as its operation clock. Table 19.1 lists the Timer RC Operation
Clock.
Table 19.1
Timer RC Operation Clock
Condition
Timer RC Operation Clock
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in f1
TRCCR1 register are set to a value from 000b to 101b)
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set fOCO40M
to 110b)
Count source is fOCO-F (bits TCK2 to TCK0 in TRCCR1 register are set to fOCO-F
111b)
Table 19.2 lists the Pin Configuration of Timer RC, and Figure 19.1 shows a Timer RC Block Diagram.
Timer RC has three modes.
• Timer mode
- Input capture function
The counter value is captured to a register, using an external signal as the trigger.
- Output compare function
Matches between the counter and register values are detected. (Pin output state
changes when a match is detected.)
The following two modes use the output compare function.
• PWM mode
Pulses of a given width are output continuously.
• PWM2 mode
A one-shot waveform or PWM waveform is output following the trigger after the
wait time has elapsed.
Input capture function, output compare function, and PWM mode settings may be specified independently for each
pin.
In PWM2 mode waveforms are output based on a combination of the counter or the register.
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
f1, f2, f4, f8, f32,
fOCO40M, fOCO-F
TRCMR register
TRCCR1 register
TRCIER register
INT0
Count source
select circuit
TRCSR register
TRCCLK
TRCIOR0 register
TRCIOA/TRCTRG
TRCIOR1 register
TRCIOB
Timer RC control circuit
Data bus
TRC register
TRCIOC
TRCGRA register
TRCIOD
TRCGRB register
TRCGRC register
TRCGRD register
TRCCR2 register
TRCDF register
Timer RC interrupt
request
TRCOER register
TRCADCR register
Figure 19.1
Table 19.2
Timer RC Block Diagram
Pin Configuration of Timer RC
Pin Name
Assigned Pin
TRCIOA
P1_1
TRCIOB
P1_2
TRCIOC
P1_3 or P3_4
TRCIOD
P1_0 or P3_5
TRCCLK
TRCTRG
I/O
Function
I/O
Function differs according to the mode. Refer
to descriptions of individual modes for details
P1_4 or P3_3
Input
External clock input
P1_1
Input
PWM2 mode external trigger input
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2
19. Timer RC
Registers
Table 19.3 lists the Registers Associated with Timer RC.
Table 19.3
Registers Associated with Timer RC
Mode
Timer
Address Symbol
Input
Output
PWM
Capture Compare
Function Function
0008h
MSTCR Valid
Valid
Valid
0120h
TRCMR Valid
Valid
Valid
0121h
TRCCR1 Valid
Valid
Valid
Valid
Valid
Valid
0122h
0123h
0124h
TRCIER Valid
TRCSR
Valid
TRCIOR0 Valid
0125h
TRCIOR1
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
TRC
PWM2
Related Information
19.2.1 Module Standby Control Register (MSTCR)
19.2.2 Timer RC Mode Register (TRCMR)
Timer RC control register 1
19.2.3 Timer RC Control Register 1 (TRCCR1)
19.5.1 Timer RC Control Register 1 (TRCCR1) for
Output Compare Function
19.6.1 Timer RC Control Register 1 (TRCCR1) in
PWM Mode
19.7.1 Timer RC Control Register 1 (TRCCR1) in
PWM2 Mode
19.2.4 Timer RC Interrupt Enable Register (TRCIER)
19.2.5 Timer RC Status Register (TRCSR)
Timer RC I/O control register 0, timer RC I/O control
register 1
19.2.6 Timer RC I/O Control Register 0 (TRCIOR0)
19.2.7 Timer RC I/O Control Register 1 (TRCIOR1)
19.4.1 Timer RC I/O Control Register 0 (TRCIOR0)
for Input Capture Function
19.4.2 Timer RC I/O Control Register 1 (TRCIOR1)
for Input Capture Function
19.5.2 Timer RC I/O Control Register 0 (TRCIOR0)
for Output Compare Function
19.5.3 Timer RC I/O Control Register 1 (TRCIOR1)
for Output Compare Function
19.2.8 Timer RC Counter (TRC)
Valid
Valid
Valid
Valid
Valid
−
Valid
Valid
−
Valid
Valid
Valid
Valid
TRCGRA Valid
Valid
Valid
Valid
19.2.9 Timer RC General Registers A, B, C, and D
(TRCGRA, TRCGRB, TRCGRC, TRCGRD)
TRCCR2 −
TRCDF
Valid
−
−
−
−
Valid
Valid
0132h
TRCOER −
Valid
Valid
Valid
0133h
TRCADCR −
Valid
Valid
Valid
0181h
0182h
0183h
TRBRCSR Valid
TRCPSR0 Valid
TRCPSR1 Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
19.2.10 Timer RC Control Register 2 (TRCCR2)
19.2.11 Timer RC Digital Filter Function Select
Register (TRCDF)
19.2.12 Timer RC Output Master Enable Register
(TRCOER)
19.2.13 Timer RC Trigger Control Register
(TRCADCR)
19.2.14 Timer RC Pin Select Register (TRBRCSR)
19.2.15 Timer RC Pin Select Register 0 (TRCPSR0)
19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)
TRCGRB
TRCGRC
TRCGRD
−: Invalid
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2.1
19. Timer RC
Module Standby Control Register (MSTCR)
Address 0008h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b6
—
0
b5
b4
b3
MSTTRC MSTTRD MSTIIC
0
0
0
b2
—
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
MSTIIC SSU, I2C bus standby bit
0: Active
1: Standby (1)
MSTTRD Peripheral function power consumption
Set to 1.
reduce bit
The power consumption of the peripheral
functions can be reduced.
MSTTRC Timer RC standby bit
0: Active
1: Standby (2)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b4
b5
b6
b7
R/W
—
R/W
R/W
R/W
—
Notes:
1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses
0193h to 019Dh) is disabled.
2. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h
to 0133h) is disabled.
19.2.2
Timer RC Mode Register (TRCMR)
Address 0120h
Bit
b7
Symbol TSTART
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
PWMB
b6
—
1
b5
BFD
0
b4
BFC
0
b3
PWM2
1
b2
PWMD
0
b1
PWMC
0
Bit Name
PWM mode of TRCIOB select bit (1)
b0
PWMB
0
Function
0: Timer mode
1: PWM mode
PWMC PWM mode of TRCIOC select bit (1)
0: Timer mode
1: PWM mode
0: Timer mode
PWMD PWM mode of TRCIOD select bit (1)
1: PWM mode
PWM2 PWM2 mode select bit
0: PWM 2 mode
1: Timer mode or PWM mode
BFC
TRCGRC register function select bit (2) 0: General register
1: Buffer register of TRCGRA register
BFD
TRCGRD register function select bit
0: General register
1: Buffer register of TRCGRB register
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TSTART TRC count start bit
0: Count stops
1: Count starts
Notes:
1. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode).
2. Set the BFC bit to 0 (general register) in PWM2 mode.
For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
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R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2.3
19. Timer RC
Timer RC Control Register 1 (TRCCR1)
Address 0121h
Bit
b7
Symbol CCLR
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
Symbol
TOA
TOB
TOC
TOD
TCK0
TCK1
TCK2
b7
CCLR
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
Bit Name
TRCIOA output level select bit (1)
TRCIOB output level select bit (1)
TRCIOC output level select bit (1)
TRCIOD output level select bit (1)
Count source select bit (1)
TRC counter clear select bit
b3
TOD
0
b2
TOC
0
b1
TOB
0
b0
TOA
0
Function
Function varies according to the operating mode
(function).
b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F (2)
0: Disable clear (free-running operation)
1: Clear TRC counter by input capture or by compare
match in TRCGRA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
19.2.4
Timer RC Interrupt Enable Register (TRCIER)
Address 0122h
Bit
b7
Symbol
OVIE
After Reset
0
Bit
b0
Symbol
IMIEA
b1
IMIEB
b2
IMIEC
b3
IMIED
b4
b5
b6
b7
—
—
—
OVIE
b6
—
1
b5
—
1
b4
—
1
b3
IMIED
0
b2
IMIEC
0
b1
IMIEB
0
b0
IMIEA
0
Bit Name
Function
Input capture / compare match interrupt 0: Disable interrupt (IMIA) by the IMFA bit
enable bit A
1: Enable interrupt (IMIA) by the IMFA bit
Input capture / compare match interrupt 0: Disable interrupt (IMIB) by the IMFB bit
enable bit B
1: Enable interrupt (IMIB) by the IMFB bit
Input capture / compare match interrupt 0: Disable interrupt (IMIC) by the IMFC bit
enable bit C
1: Enable interrupt (IMIC) by the IMFC bit
Input capture / compare match interrupt 0: Disable interrupt (IMID) by the IMFD bit
enable bit D
1: Enable interrupt (IMID) by the IMFD bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
R/W
R/W
Overflow interrupt enable bit
R/W
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
0: Disable interrupt (OVI) by the OVF bit
1: Enable interrupt (OVI) by the OVF bit
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2.5
19. Timer RC
Timer RC Status Register (TRCSR)
Address 0123h
Bit
b7
Symbol
OVF
After Reset
0
Bit
b0
b1
b2
b3
Symbol
IMFA
IMFB
IMFC
IMFD
b4
b5
b6
b7
—
—
—
OVF
b6
—
1
b5
—
1
b4
—
1
b3
IMFD
0
b2
IMFC
0
b1
IMFB
0
b0
IMFA
0
Bit Name
Input capture / compare match flag A
Input capture / compare match flag B
Input capture / compare match flag C
Input capture / compare match flag D
Function
[Source for setting this bit to 0]
Write 0 after read (1).
[Source for setting this bit to 1]
Refer to Table 19.4 Source for Setting Bit of
Each Flag to 1.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
R/W
R/W
R/W
R/W
R/W
Overflow flag
R/W
[Source for setting this bit to 0]
Write 0 after read (1).
[Source for setting this bit to 1]
Refer to Table 19.4 Source for Setting Bit of
Each Flag to 1.
—
Note:
1. The writing results are as follows:
•This bit is set to 0 when the read result is 1 and 0 is written to the same bit.
•This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even
if it is set to 1 from 0 after reading, and writing 0.)
•This bit remains unchanged if 1 is written to it.
Table 19.4
Source for Setting Bit of Each Flag to 1
IMFA
Timer Mode
PWM Mode
PWM2 Mode
Input capture Function
Output Compare Function
When the values of the registers TRC and TRCGRA match.
TRCIOA pin input edge (1)
IMFB
TRCIOB pin input edge (1)
IMFC
TRCIOC pin input edge
(1)
IMFD
When the values of the registers TRC and TRCGRD match. (2)
TRCIOD pin input edge (1)
When the TRC register overflows.
Bit Symbol
OVF
When the values of the registers TRC and TRCGRB match.
When the values of the registers TRC and TRCGRC match. (2)
Notes:
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2.6
19. Timer RC
Timer RC I/O Control Register 0 (TRCIOR0)
Address 0124h
Bit
b7
Symbol
—
After Reset
1
Bit
b0
b1
b2
b6
IOB2
0
b5
IOB1
0
b4
IOB0
0
b3
IOA3
1
b2
IOA2
0
b1
IOA1
0
b0
IOA0
0
Symbol
Bit Name
IOA0 TRCGRA control bit
IOA1
IOA2 TRCGRA mode select bit (1)
b3
IOA3
b4
b5
b6
IOB0
IOB1
IOB2
b7
—
Function
Function varies according to the operating mode
(function).
0: Output compare function
1: Input capture function
TRCGRA input capture input switch
0: fOCO128 signal
1: TRCIOA pin input
bit (3)
TRCGRB control bit
Function varies according to the operating mode
(function).
(2)
0: Output compare function
TRCGRB mode select bit
1: Input capture function
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function).
The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
19.2.7
Timer RC I/O Control Register 1 (TRCIOR1)
Address 0125h
Bit
b7
Symbol
IOD3
After Reset
1
Bit
b0
b1
b2
b6
IOD2
0
b5
IOD1
0
b4
IOD0
0
Symbol
Bit Name
IOC0 TRCGRC control bit
IOC1
IOC2 TRCGRC mode select bit (1)
b3
IOC3
TRCGRC register function select bit
b4
b5
b6
IOD0
IOD1
IOD2
TRCGRD control bit
TRCGRD mode select bit (2)
b7
IOD3
TRCGRD register function select bit
b3
IOC3
1
b2
IOC2
0
b1
IOC1
0
b0
IOC0
0
Function
Function varies according to the operating mode
(function).
0: Output compare function
1: Input capture function
0: TRCIOA output register
1: General register or buffer register
Function varies according to the operating mode
(function).
0: Output compare function
1: Input capture function
0: TRCIOB output register
1: General register or buffer register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
REJ09B0458-0010 Rev.0.10
Page 227 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.2.8
19. Timer RC
Timer RC Counter (TRC)
Address 0127h to 0126h
Bit
b7
b6
Symbol
—
—
After Reset
0
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
—
0
Bit
Symbol
After Reset
b13
—
0
b12
—
0
b11
—
0
b10
—
0
b9
—
0
b8
—
0
b15
—
0
b14
—
0
Bit
Function
b15 to b0 Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRCSR register is set to 1.
Setting Range
0000h to FFFFh
R/W
R/W
Access the TRC register in 16-bit units. Do not access it in 8-bit units.
19.2.9
Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC,
TRCGRD)
Address 0129h to 0128h (TRCGRA), 012Bh to 012Ah (TRCGRB), 012Dh to 012Ch (TRCGRC),
012Fh to 012Eh (TRCGRD)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
—
—
—
—
—
—
—
—
After Reset
1
1
1
1
1
1
1
1
Bit
Symbol
After Reset
b15
—
1
b14
—
1
b13
—
1
b12
—
1
b11
—
1
b10
—
1
b9
—
1
b8
—
1
Bit
Function
b15 to b0 Function varies according to the operating mode.
Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.2.10 Timer RC Control Register 2 (TRCCR2)
Address 0130h
Bit
b7
Symbol TCEG1
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
TCEG0
0
b5
CSTP
0
b4
—
1
b3
—
1
b2
POLD
0
b1
POLC
0
b0
POLB
0
Symbol
Bit Name
Function
POLB PWM mode output level control
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
bit B (1)
POLC PWM mode output level control
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
bit C (1)
POLD PWM mode output level control
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
bit D (1)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
CSTP TRC count operation select bit (2)
0: Count continues at compare match with the
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
b7 b6
TCEG0 TRCTRG input edge select bit (3)
0 0: Disable the trigger input from the TRCTRG pin
TCEG1
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Notes:
1. Enabled when in PWM mode.
2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
3. In timer mode and PWM mode these bits are disabled.
19.2.11 Timer RC Digital Filter Function Select Register (TRCDF)
Address 0131h
Bit
b7
Symbol DFCK1
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
DFA
DFB
DFC
DFD
DFTRG
—
DFCK0
DFCK1
b6
DFCK0
0
b5
—
0
b4
DFTRG
0
b3
DFD
0
b2
DFC
0
b1
DFB
0
b0
DFA
0
Bit Name
Function
TRCIOA pin digital filter function select bit (1) 0: Function is not used
TRCIOB pin digital filter function select bit (1) 1: Function is used
TRCIOC pin digital filter function select bit (1)
TRCIOD pin digital filter function select bit (1)
TRCTRG pin digital filter function select bit (2)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Clock select bits for digital filter function (1, 2) b7 b6
0 0: f32
0 1: f8
1 0: f1
1 1: Count source (clock selected by bits
TCK2 to TCK0 in the TRCCR1
register)
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Notes:
1. These bits are enabled for the input capture function.
2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b,
10b, or 11b (TRCTRG trigger input enabled).
REJ09B0458-0010 Rev.0.10
Page 229 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.2.12 Timer RC Output Master Enable Register (TRCOER)
Address 0132h
Bit
b7
Symbol
PTO
After Reset
0
Bit
b0
b6
—
1
b5
—
1
b4
—
1
b3
ED
1
b2
EC
1
b1
EB
1
b0
EA
1
Symbol
Bit Name
EA
TRCIOA output disable bit (1)
b1
EB
b2
EC
b3
ED
b4
b5
b6
b7
—
—
—
PTO
Function
0: Enable output
1: Disable output (The TRCIOA pin is used as a
programmable I/O port.)
(1)
0:
Enable
output
TRCIOB output disable bit
1: Disable output (The TRCIOB pin is used as a
programmable I/O port.)
0: Enable output
TRCIOC output disable bit (1)
1: Disable output (The TRCIOC pin is used as a
programmable I/O port.)
(1)
0:
Enable
output
TRCIOD output disable bit
1: Disable output (The TRCIOD pin is used as a
programmable I/O port.)
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
INT0 of pulse output forced cutoff
signal input enabled bit
0: Pulse output forced cutoff input disabled
1: Pulse output forced cutoff input enabled
(Bits EA, EB, EC, and ED are set to 1 (disable
output) when “L” is applied to the INT0 pin)
R/W
R/W
R/W
R/W
R/W
—
R/W
Note:
1. These bits are disabled for input pins set to the input capture function.
19.2.13 Timer RC Trigger Control Register (TRCADCR)
Address 0133h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
Symbol
Bit Name
ADTRGAE A/D trigger A enable bit
b4
—
0
b3
b2
b1
b0
ADTRGDE ADTRGCE ADTRGBE ADTRGAE
0
0
0
0
Function
0: A/D trigger disabled
1: A/D trigger generated at compare match with
registers TRC and TRCGRA
ADTRGBE A/D trigger B enable bit
0: A/D trigger disabled
1: A/D trigger generated at compare match with
registers TRC and TRCGRB
ADTRGCE A/D trigger C enable bit
0: A/D trigger disabled
1: A/D trigger generated at compare match with
registers TRC and TRCGRC
ADTRGDE A/D trigger D enable bit
0: A/D trigger disabled
1: A/D trigger generated at compare match with
registers TRC and TRCGRD
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
REJ09B0458-0010 Rev.0.10
Page 230 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.2.14 Timer RC Pin Select Register (TRBRCSR)
Address 0181h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
TRCCLKSEL1 TRCCLKSEL0
0
0
b3
—
0
b2
—
0
b1
—
0
Symbol
Bit Name
Function
—
Reserved bits
Set to 0.
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b5 b4
TRCCLKSEL0 TRCCLK pin select bit
0 0: TRCCLK pin not used
TRCCLKSEL1
0 1: P1_4 assigned
1 0: P3_3 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b0
—
0
R/W
R/W
—
R/W
R/W
R/W
—
The TRBRCSR register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set bits TRCCLKSEL0 and TRCCLKSEL1 before setting the timer RC associated registers. Also, do not
change the setting values of bits TRCCLKSEL0 and TRCCLKSEL1 during timer RC operation.
REJ09B0458-0010 Rev.0.10
Page 231 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
19.2.15 Timer RC Pin Select Register 0 (TRCPSR0)
Address 0182h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
TRCIOBSEL0
0
b3
—
0
b2
—
0
b1
—
0
b0
TRCIOASEL0
0
Bit
b0
Symbol
Bit Name
TRCIOASEL0 TRCIOA/TRCTRG pin select bit
b1
b2
b3
b4
—
Reserved bits
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
TRCIOBSEL0 TRCIOB pin select bit
0: TRCIOB pin not used
1: P1_2 assigned
—
Reserved bits
Set to 0.
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5
b6
b7
Function
0: TRCIOA/TRCTRG pin not used
1: P1_1 assigned
Set to 0.
R/W
R/W
R/W
—
R/W
R/W
—
The TRCPSR0 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set the TRCPSR0 register before setting the timer RC associated registers. Also, do not change the setting value
in this register during timer RC operation.
19.2.16 Timer RC Pin Select Register 1 (TRCPSR1)
Address 0183h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
TRCIODSEL1 TRCIODSEL0
0
0
Symbol
Bit Name
TRCIOCSEL0 TRCIOC pin select bit
TRCIOCSEL1
b3
b2
—
0
—
0
b1
b0
TRCIOCSEL1 TRCIOCSEL0
0
0
Function
b1 b0
0 0: TRCIOC pin not used
0 1: P1_3 assigned
1 0: P3_4 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5 b4
TRCIODSEL0 TRCIOD pin select bit
0 0: TRCIOD pin not used
TRCIODSEL1
0 1: P1_0 assigned
1 0: P3_5 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
—
The TRCPSR1 register selects which pin is assigned to the timer RC I/O. To use the I/O pin for timer RC, set
this register.
Set the TRCPSR1 register before setting the timer RC associated registers. Also, do not change the setting value
in this register during timer RC operation.
REJ09B0458-0010 Rev.0.10
Page 232 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.3
19. Timer RC
Common Items for Multiple Modes
19.3.1
Count Source
The method of selecting the count source is common to all modes.
Table 19.5 lists the Count Source Selection, and Figure 19.2 shows a Count Source Block Diagram.
Table 19.5
Count Source Selection
Count Source
f1, f2, f4, f8, f32
fOCO40M
fOCO-F
Selection Method
Count source selected using bits TCK2 to TCK0 in TRCCR1 register
FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on)
Bits TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)
Bits TCK2 to TCK0 in TRCCR1 register are set to 111b (fOCO-F)
External signal input Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge
to TRCCLK pin
of external clock) and the corresponding direction bit in the corresponding direction
register is set is set to 0 (input mode)
TCK2 to TCK0
f1
= 000b
= 001b
f2
= 010b
f4
Count source
= 011b
f8
TRC register
= 100b
f32
= 101b
TRCCLK
= 110b
fOCO40M
= 111b
fOCO-F
TCK2 to TCK0: Bits in TRCCR1 register
Figure 19.2
Count Source Block Diagram
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC
operation clock (see Table 19.1 Timer RC Operation Clock).
To select fOCO40M or fOCO-F as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed
on-chip oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M) or 111b
(fOCO-F).
REJ09B0458-0010 Rev.0.10
Page 233 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.3.2
19. Timer RC
Buffer Operation
Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer
register for the TRCGRA or TRCGRB register.
• Buffer register for TRCGRA register: TRCGRC register
• Buffer register for TRCGRB register: TRCGRD register
Buffer operation differs depending on the mode.
Table 19.6 lists the Buffer Operation in Each Mode, Figure 19.3 shows the Buffer Operation for Input Capture
Function, and Figure 19.4 shows the Buffer Operation for Output Compare Function.
Table 19.6
Buffer Operation in Each Mode
Function, Mode
Input capture function
Transfer Timing
Input capture signal input
Transfer Destination Register
Contents of TRCGRA (TRCGRB)
register are transferred to buffer
register
Contents of buffer register are
transferred to TRCGRA (TRCGRB)
register
Contents of buffer register (TRCGRD)
are transferred to TRCGRB register
Output compare function Compare match between TRC
register and TRCGRA (TRCGRB)
PWM mode
register
PWM2 mode
• Compare match between TRC
register and TRCGRA register
• TRCTRG pin trigger input
TRCIOA input
(input capture signal)
TRCGRC
register
TRCGRA
register
TRC
TRCIOA input
TRC register
n
n-1
n+1
Transfer
TRCGRA register
m
n
Transfer
TRCGRC register
(buffer)
m
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).
Figure 19.3
Buffer Operation for Input Capture Function
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
Compare match signal
TRCGRC
register
TRC register
TRCGRA register
TRCGRA
register
Comparator
m
m-1
TRC
m+1
m
n
Transfer
TRCGRC register
(buffer)
n
TRCIOA output
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
Figure 19.4
Buffer Operation for Output Compare Function
Make the following settings in timer mode.
• To use the TRCGRC register as the buffer register for the TRCGRA register:
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
• To use the TRCGRD register as the buffer register for the TRCGRB register:
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
REJ09B0458-0010 Rev.0.10
Page 235 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.3.3
19. Timer RC
Digital Filter
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.
Figure 19.5 shows a Digital Filter Block Diagram.
TCK2 to TCK0
f1
f2
f4
f8
f32
TRCCLK
fOCO40M
DFCK1 to DFCK0
= 000b
= 00b
f32
= 001b
= 01b
f8
= 010b
= 10b
f1
= 011b
= 11b
Count source
= 100b
= 101b
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
(or TCEG1 to TCEG0)
= 110b
= 111b
fOCO-F
Sampling clock
DFj (or DFTRG)
C
TRCIOj input signal
(or TRCTRG input
signal)
D
C
Q
Latch
C
D
Q
Latch
D
1
C
Q
Latch
D
Q
Match detect
circuit
Edge detect
circuit
Latch
0
Timer RC operation clock
f1 or fOCO40M
C
D
Q
Latch
Clock cycle selected by
TCK2 to TCK0
(or DFCK1 to DFCK0)
Sampling clock
TRCIOj input signal
(or TRCTRG input signal)
Three matches occur and a
signal change is confirmed.
Input signal after passing
through digital filter
Maximum signal transmission
delay is five sampling clock
pulses.
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
j = A, B, C, or D
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0: Bits in TRCCR2 register
Figure 19.5
Digital Filter Block Diagram
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.3.4
19. Timer RC
Forced Cutoff of Pulse Output
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj output pin functions as the programmable I/O port). When one or two
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 19.1 Timer RC
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.
Make the following settings to use this function.
• Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H” output).
(Refer to 7. I/O Ports.)
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and
a change in the INT0 pin input (refer to 11.8 Notes on Interrupts).
For details on interrupts, refer to 11. Interrupts.
REJ09B0458-0010 Rev.0.10
Page 237 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
EA bit
write value
INT0 input
EA bit
D Q
S
Timer RC
output data
TRCIOA
Port P1_1
output data
PTO bit
Port P1_1
input data
EB bit
write value
EB bit
D Q
S
Timer RC
output data
TRCIOB
Port P1_2
output data
Port P1_2
input data
EC bit
write value
EC bit
D Q
S
Timer RC
output data
TRCIOC
Port P3_4
output data
Port P3_4
input data
ED bit
write value
ED bit
D Q
S
Timer RC
output data
Port P3_5
output data
Port P3_5
input data
EA, EB, EC, ED, PTO: Bits in TRCOER register
Figure 19.6
Forced Cutoff of Pulse Output
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
TRCIOD
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.4
19. Timer RC
Timer Mode (Input Capture Function)
This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A, B,
C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj register
(input capture). The input capture function, or any other mode or function, can be selected for each individual pin.
The TRCGRA register can also select fOCO128 signal as input-capture trigger input.
Table 19.7 lists the Specifications of Input Capture Function, Figure 19.7 shows a Block Diagram of Input Capture
Function, Table 19.8 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 19.8
shows an Operating Example of Input Capture Function.
Table 19.7
Specifications of Input Capture Function
Item
Count source
Count operation
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Specification
f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge)
input to TRCCLK pin
Increment
1/fk × 65,536 fk: Count source frequency
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The TRC register retains a value before count stops.
• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows.
Programmable I/O port or input capture input (selectable individually for
each pin)
Programmable I/O port or INT0 interrupt input
The count value can be read by reading TRC register.
The TRC register can be written to.
• Input capture input pin selection
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selection
Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Digital filter (Refer to 19.3.3 Digital Filter.)
• Timing for setting the TRC register to 0000h
Overflow or input capture
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRCGRA register.
j = A, B, C, or D
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
fOCO-S or
fOCO-F
19. Timer RC
Divided
by 128
fOCO128
IOA3 = 0
Input capture signal (3)
TRCIOA
Edge
selection
IOA3 = 1
(Note 1)
TRCGRA
register
TRC register
TRCGRC
register
TRCIOC
TRCIOB
Edge
selection
Input capture signal
Input capture signal
Edge
selection
(Note 2)
TRCGRB
register
TRCGRD
register
TRCIOD
Edge
selection
Input capture signal
IOA3: Bit in TRCIOR0 register
Notes:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.
Figure 19.7
Block Diagram of Input Capture Function
REJ09B0458-0010 Rev.0.10
Page 240 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.4.1
19. Timer RC
Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function
Address 0124h
Bit
b7
Symbol
—
After Reset
1
Bit
b0
b1
b6
IOB2
0
b5
IOB1
0
Symbol
Bit Name
IOA0 TRCGRA control bit
IOA1
b2
b3
IOA2
IOA3
b4
b5
IOB0
IOB1
b6
b7
IOB2
—
b4
IOB0
0
b3
IOA3
1
b2
IOA2
0
b1
IOA1
0
b0
IOA0
0
Function
b1 b0
0 0: Input capture to the TRCGRA register at the
rising edge
0 1: Input capture to the TRCGRA register at the
falling edge
1 0: Input capture to the TRCGRA register at both
edges
1 1: Do not set.
Set to 1 (input capture) in the input capture function.
TRCGRA mode select bit (1)
TRCGRA input capture input switch 0: fOCO128 signal
1: TRCIOA pin input
bit (3)
b5 b4
TRCGRB control bit
0 0: Input capture to the TRCGRB register at the
rising edge
0 1: Input capture to the TRCGRB register at the
falling edge
1 0: Input capture to the TRCGRB register at both
edges
1 1: Do not set.
Set to 1 (input capture) in the input capture function.
TRCGRB mode select bit (2)
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
3. The IOA3 bit is enabled when the IOA2 bit is set to 1 (input capture function).
REJ09B0458-0010 Rev.0.10
Page 241 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.4.2
19. Timer RC
Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function
Address 0125h
Bit
b7
Symbol
IOD3
After Reset
1
Bit
b0
b1
b6
IOD2
0
b5
IOD1
0
b4
IOD0
0
Symbol
Bit Name
IOC0 TRCGRC control bit
IOC1
b2
b3
IOC2
IOC3
b4
b5
IOD0
IOD1
b6
b7
IOD2
IOD3
TRCGRC mode select bit (1)
TRCGRC register function select
bit
TRCGRD control bit
TRCGRD mode select bit (2)
TRCGRD register function select
bit
b3
IOC3
1
b2
IOC2
0
b1
IOC1
0
b0
IOC0
0
Function
b1 b0
0 0: Input capture to the TRCGRC register at the rising
edge
0 1: Input capture to the TRCGRC register at the
falling edge
1 0: Input capture to the TRCGRC register at both
edges
1 1: Do not set.
Set to 1 (input capture) in the input capture function.
Set to 1.
b5 b4
0 0: Input capture to the TRCGRD register at the rising
edge
0 1: Input capture to the TRCGRD register at the
falling edge
1 0: Input capture to the TRCGRD register at both
edges
1 1: Do not set.
Set to 1 (input capture) in the input capture function.
Set to 1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Table 19.8
Functions of TRCGRj Register when Using Input Capture Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
−
BFC = 0
BFD = 0
BFC = 1
BFD = 1
Input Capture
Input Pin
General register. Can be used to read the TRC register value TRCIOA
at input capture.
TRCIOB
General register. Can be used to read the TRC register value TRCIOC
at input capture.
TRCIOD
Buffer registers. Can be used to hold transferred value from TRCIOA
the general register. (Refer to 19.3.2 Buffer Operation.)
TRCIOB
Register Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
REJ09B0458-0010 Rev.0.10
Page 242 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.4.3
19. Timer RC
Operating Example
TRCCLK input
count source
TRC register
count value
FFFFh
0009h
0006h
0000h
TSTART bit in
TRCMR register
1
0
65536
TRCIOA input
TRCGRA register
0006h
Transfer
TRCGRC register
0009h
Transfer
0006h
IMFA bit in
TRCSR register
1
OVF bit in
TRCSR register
1
0
Set to 0 by a program
0
The above applies under the following conditions:
• The CCLR bit in the TRCCR1 register is set to 1 (Clear TRC counter by input capture).
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
Figure 19.8
Operating Example of Input Capture Function
REJ09B0458-0010 Rev.0.10
Page 243 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5
19. Timer RC
Timer Mode (Output Compare Function)
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or D)
match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The output
compare function, or other mode or function, can be selected for each individual pin.
Table 19.9 lists the Specifications of Output Compare Function, Figure 19.9 shows a Block Diagram of Output
Compare Function, Table 19.10 lists the Functions of TRCGRj Register when Using Output Compare Function,
and Figure 19.10 shows an Operating Example of Output Compare Function.
Table 19.9
Specifications of Output Compare Function
Item
Count source
Count operation
Count period
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC, and
TRCIOD pin functions
Specification
f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge) input to
TRCCLK pin
Increment
• The CCLR bit in the TRCCR1 register is set to 0 (free running operation):
1/fk × 65,536
fk: Count source frequency
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to 0000h at
TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
Compare match
1 (count starts) is written to the TSTART bit in the TRCMR register.
• When the CSEL bit in the TRCCR2 register is set to 0 (count continues after
compare match with TRCGRA).
0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops, the TRC
register retains a value before count stops.
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare
match with TRCGRA register).
The count stops at the compare match with the TRCGRA register. The outputcompare output pin retains the level after the output is changed by the compare
match.
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port or output compare output (Selectable individually for
each pin)
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt
input
Read from timer
Write to timer
Select functions
The count value can be read by reading the TRC register.
The TRC register can be written to.
• Output compare output pin selection
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level selection
“L” output, “H” output, or toggle output
• Initial output level selection
Sets output level for period from count start to compare match
• Timing for setting the TRC register to 0000h
Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse
Output.)
• Can be used as an internal timer by disabling timer RC output
• Changing output pins for registers TRCGRC and TRCGRD
TRCGRC can be used for output control of the TRCIOA pin and TRCGRD can
be used for output control of the TRCIOB pin.
• A/D trigger generation
j = A, B, C, or D
REJ09B0458-0010 Rev.0.10
Page 244 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
TRC
TRCIOA
TRCIOC
TRCIOB
TRCIOD
Figure 19.9
Output
control
Output
control
Output
control
Output
control
Compare match signal
TRCGRA
Comparator
TRCGRC
Comparator
TRCGRB
Comparator
TRCGRD
Compare match signal
Compare match signal
Compare match signal
Block Diagram of Output Compare Function
REJ09B0458-0010 Rev.0.10
Page 245 of 572
Comparator
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5.1
19. Timer RC
Timer RC Control Register 1 (TRCCR1) for Output Compare Function
Address 0121h
Bit
b7
Symbol CCLR
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
Symbol
TOA
TOB
TOC
TOD
TCK0
TCK1
TCK2
b7
CCLR
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
b3
TOD
0
b2
TOC
0
b1
TOB
0
b0
TOA
0
Bit Name
Function
TRCIOA output level select bit (1, 2) 0: Initial output “L”
TRCIOB output level select bit (1, 2) 1: Initial output “H”
TRCIOC output level select bit (1, 2)
TRCIOD output level select bit (1, 2)
b6 b5 b4
Count source select bit (1)
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F (3)
TRC counter clear select bit
0: Disable clear (free-running operation)
1: Clear by compare match in the TRCGRA register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
TRCCR1 register is set.
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
Table 19.10
Functions of TRCGRj Register when Using Output Compare Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
Register Function
−
General register. Write a compare value to one of these
registers.
BFC = 0
BFD = 0
BFC = 1
BFD = 1
General register. Write a compare value to one of these
registers.
Buffer register. Write the next compare value to one of
these registers. (Refer to 19.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
REJ09B0458-0010 Rev.0.10
Page 246 of 572
Apr 01, 2008
Output Compare
Output Pin
TRCIOA
TRCIOB
TRCIOC
TRCIOD
TRCIOA
TRCIOB
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5.2
19. Timer RC
Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function
Address 0124h
Bit
b7
Symbol
—
After Reset
1
Bit
b0
b1
b6
IOB2
0
b5
IOB1
0
Symbol
Bit Name
IOA0 TRCGRA control bit
IOA1
b2
IOA2
TRCGRA mode select bit (1)
b3
IOA3
b4
b5
IOB0
IOB1
TRCGRA input capture input
switch bit
TRCGRB control bit
b6
IOB2
b7
—
b4
IOB0
0
b3
IOA3
1
b2
IOA2
0
b1
IOA1
0
b0
IOA0
0
Function
b1 b0
0 0: Disable pin output by compare match (TRCIOA pin
functions as the programmable I/O port)
0 1: “L” output by compare match in the TRCGRA
register
1 0: “H” output by compare match in the TRCGRA
register
1 1: Toggle output by compare match in the TRCGRA
register
Set to 0 (output compare) in the output compare
function.
Set to 1.
b5 b4
0 0: Disable pin output by compare match (TRCIOB pin
functions as the programmable I/O port)
0 1: “L” output by compare match in the TRCGRB
register
1 0: “H” output by compare match in the TRCGRB
register
1 1: Toggle output by compare match in the TRCGRB
register
(2)
Set
to
0 (output compare) in the output compare
TRCGRB mode select bit
function.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in
theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5.3
19. Timer RC
Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function
Address 0125h
Bit
b7
Symbol
IOD3
After Reset
1
Bit
b0
b1
b6
IOD2
0
b5
IOD1
0
b4
IOD0
0
Symbol
Bit Name
IOC0 TRCGRC control bit
IOC1
b2
IOC2
TRCGRC mode select bit (1)
b3
IOC3
b4
b5
IOD0
IOD1
TRCGRC register function select
bit
TRCGRD control bit
b6
IOD2
TRCGRD mode select bit (2)
b7
IOD3
TRCGRD register function select
bit
b3
IOC3
1
b2
IOC2
0
b1
IOC1
0
b0
IOC0
0
Function
b1 b0
0 0: Disable pin output by compare match
0 1: “L” output by compare match in the TRCGRC
register
1 0: “H” output by compare match in the TRCGRC
register
1 1: Toggle output by compare match in the TRCGRC
register
Set to 0 (output compare) in the output compare
function.
0: TRCIOA output register
1: General register or buffer register
b5 b4
0 0: Disable pin output by compare match
0 1: “L” output by compare match in the TRCGRD
register
1 0: “H” output by compare match in the TRCGRD
register
1 1: Toggle output by compare match in the TRCGRD
register
Set to 0 (output compare) in the output compare
function.
0: TRCIOB output register
1: General register or buffer register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in
theTRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in
theTRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5.4
19. Timer RC
Operating Example
Count source
TRC register value
m
n
p
Count
restarts
Count
stops
TSTART bit in
TRCMR register
1
0
m+1
m+1
Output level held
TRCIOA output
Output inverted at
compare match
Initial output “L”
IMFA bit in
TRCSR register
1
0
Set to 0 by a program
Output level held
n+1
TRCIOB output
“H” output at
compare match
Initial output “L”
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
P+1
Output level held
“L” output at compare match
TRCIOC output
Initial output “H”
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until
compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
• The CSEL bit in the TRCCR2 register is set to 0 (TRC count continues after TRCGRA compare match).
Figure 19.10
Operating Example of Output Compare Function
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.5.5
19. Timer RC
Changing Output Pins in Registers TRCGRC and TRCGRD
The TRCGRC register can be used for output control of the TRCIOA pin, and the TRCGRD register can be
used for output control of the TRCIOB pin. Therefore, each pin output can be controlled as follows:
• TRCIOA output is controlled by the values in registers TRCGRA and TRCGRC.
• TRCIOB output is controlled by the values in registers TRCGRB and TRCGRD.
Change output pins in registers TRCGRC and TRCGRD as follows:
• Set the IOC3 bit in the TRCIOR1 register to 0 (TRCIOA output register) and set the IOD3 bit to 0
(TRCIOB output register).
• Set bits BFC and BFD in the TRCMR register to 0 (general register).
• Set different values in registers TRCGRC and TRCGRA. Also, set different values in registers TRCGRD
and TRCGRB.
Figure 19.12 shows an Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin.
TRC
Compare match signal
TRCIOA
Output
control
IOC3 = 0 in
TRCIOR1 register
Comparator
TRCGRA
Comparator
TRCGRC
Comparator
TRCGRB
Comparator
TRCGRD
Compare match signal
TRCIOC
Output
control
IOC3 = 1
Compare match signal
TRCIOB
Output
control
IOD3 = 0 in
TRCIOR1 register
Compare match signal
TRCIOD
Figure 19.11
Output
control
IOD3 = 1
Changing Output Pins in Registers TRCGRC and TRCGRD
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
Count source
Value in TRC register
FFFFh
m
n
p
q
0000h
m+1
n+1
m-n
p+1
q+1
p-q
Initial output “L”
TRCIOA output
Output inverted by compare match
IMFA bit in
TRCSR register
1
0
Set to 0 by a program
IMFC bit in
TRCSR register
Set to 0 by a program
1
0
Initial output “L”
TRCIOB output
Output inverted by compare match
IMFB bit in
TRCSR register
1
IMFD bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
m: Value set in TRCGRA register
n: Value set in TRCGRC register
p: Value set in TRCGRB register
q: Value set in TRCGRD register
i = 0 or 1
The above applies under the following conditions:
Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD are not used as buffer register).
Bits EA and EB in the TRCOER register are set to 0 (enable TRCIOA and TRCIOB pin outputs).
The CCLR bit in the TRCCR1 register are set to 1 (set the TRC register to 0000h by compare match in the TRCGRA register).
Bits TOA and TOB in the TRCCR1 register are set to 0 (initial output “L” to compare match).
Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA register compare match).
Bits IOB2 to IOB0 in the TRCIOR0 register are set to 011b (TRCIOB output inverted at TRCGRB register compare match).
Bits IOC2 to IOC0 in the TRCIOR1 register are set to 011b (TRCIOA output inverted at TRCGRC register compare match).
The IOC3 bit in the TRCIOR1 register are set to 0 (TRCIOA output register).
Bits IOD2 to IOD0 in the TRCIOR1 register are set to 011b (TRCIOB output inverted at TRCGRD register compare match).
The IOD3 bit in the TRCIOR1 register are set to 0 (TRCIOB output register).
The CSEL bit in the TRCCR2 register are set to 0 (TRC continues counting after compare match).
Figure 19.12
Operating Example When TRCGRC Register is Used for Output Control of TRCIOA
Pin and TRCGRD Register is Used for Output Control of TRCIOB Pin
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.6
19. Timer RC
PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA register
is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer mode.)
Table 19.11 lists the Specifications of PWM Mode, Figure 19.13 shows a PWM Mode Block Diagram, Table 19.12
lists the Functions of TRCGRj Register in PWM Mode, and Figures 19.14 and 19.15 show Operating Examples of
PWM Mode.
Table 19.11
Specifications of PWM Mode
Item
Specification
f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge)
input to TRCCLK pin
Increment
PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count source
Count operation
PWM waveform
m+1
n+1
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA pin function
TRCIOB, TRCIOC, and
TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
(“L” is active level)
1 (count starts) is written to the TSTART bit in the TRCMR register.
• When the CSEL bit in the TRCCR2 register is set to 0 (count continues
after compare match with TRCGRA).
0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
• When the CSEL bit in the TRCCR2 register is set to 1 (count stops at
compare match with TRCGRA register).
The count stops at the compare match with the TRCGRA register. The
PWM output pin retains the level after the output is changed by the
compare match.
• Compare match (contents of registers TRC and TRCGRh match)
• The TRC register overflows.
Programmable I/O port
Programmable I/O port or PWM output (selectable individually for each
pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• One to three pins selectable as PWM output pins
One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable for each pin
• Initial level selectable for each pin
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff
of Pulse Output.)
• A/D trigger generation
j = B, C, or D
h = A, B, C, or D
REJ09B0458-0010 Rev.0.10
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m-n
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
TRC
Compare match signal
Comparator
TRCIOB
TRCGRA
Compare match signal
(Note 1)
TRCIOC
Output
control
Comparator
TRCGRB
Comparator
TRCGRC
Compare match signal
TRCIOD
(Note 2)
Compare match signal
Comparator
TRCGRD
Notes:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
Figure 19.13
PWM Mode Block Diagram
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.6.1
19. Timer RC
Timer RC Control Register 1 (TRCCR1) in PWM Mode
Address 0121h
Bit
b7
Symbol CCLR
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
Symbol
TOA
TOB
TOC
TOD
TCK0
TCK1
TCK2
b7
CCLR
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
Bit Name
TRCIOA output level select bit (1)
TRCIOB output level select bit (1, 2)
TRCIOC output level select bit (1, 2)
TRCIOD output level select bit (1, 2)
Count source select bit (1)
TRC counter clear select bit
b3
TOD
0
b2
TOC
0
b1
TOB
0
b0
TOA
0
Function
Disabled in PWM mode
0: Initial output selected as non-active level
1: Initial output selected as active level
b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F (3)
0: Disable clear (free-running operation)
1: Clear by compare match in the TRCGRA register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
j = B, C or D
Notes:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
TRCCR1 register is set.
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
19.6.2
Timer RC Control Register 2 (TRCCR2)
Address 0130h
Bit
b7
Symbol TCEG1
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
TCEG0
0
b5
CSTP
0
b4
—
1
b3
—
1
b2
POLD
0
b1
POLC
0
b0
POLB
0
Symbol
Bit Name
Function
POLB PWM mode output level control
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
bit B (1)
POLC PWM mode output level control
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
bit C (1)
0: TRCIOD output level selected as “L” active
POLD PWM mode output level control
1: TRCIOD output level selected as “H” active
bit D (1)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
CSTP TRC count operation select bit (2) 0: Count continues at compare match with the
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
TCEG0 TRCTRG input edge select bit (3) b7 b6
0 0: Disable the trigger input from the TRCTRG pin
TCEG1
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
Notes:
1. Enabled when in PWM mode.
2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
3. In timer mode and PWM mode these bits are disabled.
REJ09B0458-0010 Rev.0.10
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R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 19.12
19. Timer RC
Functions of TRCGRj Register in PWM Mode
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
Setting
−
−
BFC = 0
BFD = 0
BFC = 1
TRCGRD
BFD = 1
Register Function
General register. Set the PWM period.
General register. Set the PWM output change point.
General register. Set the PWM output change point.
PWM Output Pin
−
TRCIOB
TRCIOC
TRCIOD
Buffer register. Set the next PWM period. (Refer to 19.3.2 Buffer −
Operation.)
Buffer register. Set the next PWM output change point. (Refer to TRCIOB
19.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Note:
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.6.3
19. Timer RC
Operating Example
Count source
Value in TRC register
m
n
p
q
m+1
n+1
m-n
Active level “H”
Initial output “L”
to compare match
TRCIOB output
Inactive level “L”
p+1
TRCIOC output
Initial output “H”
to compare match
m-p
Inactive level “H”
q+1
m-q
Active level “L”
TRCIOD output
Initial output “L”
to compare match
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
IMFD bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• Bits TOB and TOC in the TRCCR1 register are set to 0 (inactive level), the TOD bit is set to 1 (active level).
• The POLB bit in the TRCCR2 register is set to 1 (“H” active), bits POLC and POLD are set to 0 (“L” active).
Figure 19.14
Operating Example of PWM Mode
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
TRC register value
p
m
q
n
0000h
1
TSTART bit in
TRCMR register
TRCIOB output does not switch to “L” because
no compare match with the TRCGRB register
has occurred
0
Duty 0%
TRCIOB output
TRCGRB register
n
q
p (p>m)
Rewritten by a program
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
TRC register value
m
p
n
0000h
1
TSTART bit in
TRCMR register
If compare matches occur simultaneously with registers TRCGRA and
TRCGRB, the compare match with the TRCGRB register has priority.
TRCIOB output switches to “L”. (In other words, no change).
0
Duty 100%
TRCIOB output
TRCIOB output switches to “L” at compare match with the
TRCGRB register. (In other words, no change).
n
TRCGRB register
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
m
p
Rewritten by
a program
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
The above applies under the following conditions:
• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).
• The POLB bit in the TRCCR2 register is set to 0 (“L” active).
Figure 19.15
Operating Example of PWM Mode (Duty 0% and Duty 100%)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.7
19. Timer RC
PWM2 Mode
This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the pin
output switches to active level. Then, after a given duration, the output switches back to inactive level.
Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use
PWM2 mode to output a programmable wait one-shot waveform.
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with it.
Figure 19.16 shows a PWM2 Mode Block Diagram, Table 19.13 lists the Specifications of PWM2 Mode, Table
19.14 lists the Functions of TRCGRj Register in PWM2 Mode, and Figures 19.17 to 19.19 show Operating
Examples of PWM2 Mode.
Trigger signal
Compare match signal
TRCTRG
TRCIOB
Input
control
Count clear signal
TRC
(Note 1)
Comparator
TRCGRA
Comparator
TRCGRB
Comparator
TRCGRC
TRCGRD
register
Output
control
Note:
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register).
Figure 19.16
PWM2 Mode Block Diagram
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 19.13
19. Timer RC
Specifications of PWM2 Mode
Item
Count source
Count operation
PWM waveform
Specification
f1, f2, f4, f8, f32, fOCO40M, fOCO-F, or external signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRCTRG input
m+1
n+1
n+1
p+1
p+1
TRCIOB output
n-p
n-p
(TRCTRG: Rising edge, active level is “H”)
Count start conditions
Count stop conditions
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
PWM output
TRCIOC and TRCIOD pin Programmable I/O port
functions
INT0 pin function
Read from timer
Write to timer
Select functions
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selection
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 19.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse
Output.)
• Digital filter (Refer to 19.3.3 Digital Filter.)
• A/D trigger generation
j = A, B, or C
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.7.1
19. Timer RC
Timer RC Control Register 1 (TRCCR1) in PWM2 Mode
Address 0121h
Bit
b7
Symbol CCLR
After Reset
0
Bit
b0
b1
b6
TCK2
0
b5
TCK1
0
b4
TCK0
0
Symbol
Bit Name
TOA
TRCIOA output level select bit (1)
TOB
TRCIOB output level select bit (1, 2)
b2
b3
b4
b5
b6
TOC
TOD
TCK0
TCK1
TCK2
TRCIOC output level select bit (1)
TRCIOD output level select bit (1)
Count source select bit (1)
b7
CCLR
TRC counter clear select bit
b3
TOD
0
b2
TOC
0
b1
TOB
0
b0
TOA
0
Function
Disabled in PWM2 mode
0: Active level “H”
(Initial output “L”
“H” output by compare match in the TRCGRC
register
“L” output by compare match in the TRCGRB
register
1: Active level “L”
(Initial output “H”
“L” output by compare match in the TRCGRC
register
“H” output by compare match in the TRCGRB
register
Disabled in PWM2 mode
b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
1 1 1: fOCO-F (3)
0: Disable clear (free-running operation)
1: Clear by compare match in the TRCGRA
register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
TRCCR1 register is set.
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.7.2
19. Timer RC
Timer RC Control Register 2 (TRCCR2) in PWM2 Mode
Address 0130h
Bit
b7
Symbol TCEG1
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
TCEG0
0
b5
CSTP
0
b4
—
1
b3
—
1
b2
POLD
0
b1
POLC
0
b0
POLB
0
Symbol
Bit Name
Function
POLB PWM mode output level control
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
bit B (1)
POLC PWM mode output level control
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
bit C (1)
POLD PWM mode output level control
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
bit D (1)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
CSTP TRC count operation select bit (2)
0: Count continues at compare match with the
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
b7 b6
TCEG0 TRCTRG input edge select bit (3)
0 0: Disable the trigger input from the TRCTRG pin
TCEG1
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Notes:
1. Enabled when in PWM mode.
2. For notes on PWM2 mode, refer to 19.9.6 TRCMR Register in PWM2 Mode.
3. In timer mode and PWM mode these bits are disabled.
19.7.3
Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode
Address 0131h
Bit
b7
Symbol DFCK1
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
DFA
DFB
DFC
DFD
DFTRG
—
DFCK0
DFCK1
b6
DFCK0
0
b5
—
0
b4
DFTRG
0
b3
DFD
0
b2
DFC
0
b1
DFB
0
b0
DFA
0
Bit Name
Function
TRCIOA pin digital filter function select bit (1) 0: Function is not used
TRCIOB pin digital filter function select bit (1) 1: Function is used
TRCIOC pin digital filter function select bit (1)
TRCIOD pin digital filter function select bit (1)
TRCTRG pin digital filter function select bit (2)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Clock select bits for digital filter function (1, 2) b7 b6
0 0: f32
0 1: f8
1 0: f1
1 1: Count source (clock selected by bits
TCK2 to TCK0 in the TRCCR1
register)
R/W
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
Notes:
1. These bits are enabled for the input capture function.
2. These bits are enabled when in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b,
10b, or 11b (TRCTRG trigger input enabled).
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 19.14
19. Timer RC
Functions of TRCGRj Register in PWM2 Mode
Register
TRCGRA
TRCGRB
TRCGRC
Setting
−
−
BFC = 0
TRCGRD
TRCGRD
BFD = 0
BFD = 1
Register Function
PWM2 Output Pin
General register. Set the PWM period.
TRCIOB pin
General register. Set the PWM output change point.
General register. Set the PWM output change point (wait time
after trigger).
(Not used in PWM2 mode)
−
Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin
19.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Note:
1. Do not set the TRCGRB and TRCGRC registers to the same value.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.7.4
19. Timer RC
Operating Example
Count source
TRC register value
FFFFh
TRC register cleared
at TRCGRA register
compare match
m
n
Previous value held if the
TSTART bit is set to 0
Set to 0000h
by a program
p
0000h
TSTART bit in
TRCMR register
Count stops
because the
CSEL bit is
set to 1
1
0
Set to 1 by
a program
CSEL bit in
TRCCR2 register
TSTART bit
is set to 0
1
0
m+1
n+1
p+1
p+1
“H” output at TRCGRC
register compare match
Return to initial output
if the TSTART bit is
set to 0
“L” initial output
TRCIOB output
“L” output at TRCGRB
register compare match
No change
No change
“H” output at TRCGRC register
compare match
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
0
Set to 0 by a program
Set to 0 by a program
0
TRCGRB register
n
Transfer
TRCGRD register
n
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 19.17
Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
Count source
TRC register value
TRC register cleared
at TRCGRA register
compare match
FFFFh
m
TRC register (counter)
cleared at TRCTRG pin
trigger input
Previous value
held if the
TSTART bit is
set to 0
n
Set to 0000h
by a program
p
0000h
TRCTRG input
Count starts at
TRCTRG pin
trigger input
Count starts
TSTART bit
is set to 1
TSTART bit in
TRCMR register
1
CSEL bit in
TRCCR2 register
1
Count stops
because the
CSEL bit is
set to 1
Changed by a program
The TSTART
bit is set to 0
0
Set to 1 by
a program
0
m+1
n+1
n+1
p+1
p+1
“H” output at
TRCGRC register
compare match
“L” output at
TRCGRB register
compare match
“L” initial output
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
TRCGRB register
p+1
Inactive level so
TRCTRG input is
enabled
Return to initial value if the
TSTART bit is set to 0
Active level so TRCTRG
input is disabled
0
Set to 0 by
a program
0
Set to 0 by
a program
Set to 0 by
a program
Set to 0 by
a program
0
n
n
Transfer
TRCGRD register
n
n
Transfer
n
Transfer from buffer register to general register
Transfer
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the
TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
Figure 19.18
Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
• TRCGRB register setting value greater than TRCGRA
register setting value
TRC register value
• TRCGRC register setting value greater than TRCGRA
register setting value
TRC register value
n
p
m
m
n
p
0000h
0000h
TSTART bit in
TRCMR register
1
TSTART bit in
TRCMR register
0
n+1
m+1
m+1
TRCIOB output
“H” output at TRCGRC register
compare match
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
0
p+1
No compare match with
TRCGRB register, so
“H” output continues
IMFA bit in
TRCSR register
1
“L” initial
output
0
0
1
No compare match
with TRCGRC register,
so “L” output continues
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
Set to 0 by a
program
0
“L” output at
TRCGRB register
compare match
with no change.
“L” initial
output
0
0
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 19.19
Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.8
19. Timer RC
Timer RC Interrupt
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single TRCIC
register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 19.15 lists the Registers Associated with Timer RC Interrupt, and Figure 19.20 is a Timer RC Interrupt Block
Diagram.
Table 19.15
Registers Associated with Timer RC Interrupt
Timer RC Status Register
TRCSR
Timer RC Interrupt Enable Register
TRCIER
Timer RC Interrupt Control Register
TRCIC
IMFA bit
IMIEA bit
Timer RC interrupt request
(IR bit in TRCIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
Figure 19.20
Timer RC Interrupt Block Diagram
Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.
• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to 1
and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt requested) when the bit in the TRCSR register or the corresponding bit in
the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained if
the IR bit is once set to 1 but the interrupt is not acknowledged.
• If another interrupt source is triggered after the IR bit is set to 1, the IR bit remains set to 1 and does not
change.
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
interrupt request.
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them to
0 within the interrupt routine. Refer to 19.2.5 Timer RC Status Register (TRCSR), for the procedure for
setting these bits to 0.
Refer to 19.2.4 Timer RC Interrupt Enable Register (TRCIER), for details of the TRCIER register.
Refer to 11.3 Interrupt Control, for details of the TRCIC register and 11.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
19.9
19. Timer RC
Notes on Timer RC
19.9.1
TRC Register
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is set
to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the write
value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.W
#XXXXh, TRC
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.W
TRC,DATA
;Read
19.9.2
TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.B
#XXh, TRCSR
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.B
TRCSR,DATA
;Read
19.9.3
TRCCR1 Register
To set bits TCK2 to TCK0 in the TRCCR1 register to 111b (fOCO-F), set fOCO-F to the clock frequency
higher than the CPU clock frequency.
19.9.4
Count Source Switching
• Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
19. Timer RC
• After switching the count source from fOCO-F to fOCO40M, allow a minimum of two cycles of fOCO-F to
elapse after changing the clock setting before stopping fOCO-F.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of fOCO-F.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
• After switching the count source from fOCO-F to a clock other than fOCO40M, allow a minimum of one
cycle of fOCO-F + fOCO40M to elapse after changing the clock setting before stopping fOCO-F.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of one cycle of fOCO-F + fOCO40M.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
19.9.5
Input Capture Function
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
(refer to Table 19.1 Timer RC Operation Clock).
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the digital
filter function is not used).
19.9.6
TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
19.9.7
Count Source fOCO40M
The count source fOCO40M can be used with supply voltage VCC = 2.7 to 5.5 V. For supply voltage other than
that, do not set bits TCK2 to TCK0 in the TRCCR1 register to 110b (select fOCO40M as the count source).
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
20. Timer RE
20. Timer RE
Timer RE has the 4-bit counter and 8-bit counter.
20.1
Overview
Timer RE has the following 2 modes:
• Real-time clock mode
Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
• Output compare mode
Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
REJ09B0458-0010 Rev.0.10
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2
20. Timer RE
Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 20.1 shows
a Block Diagram of Real-Time Clock Mode and Table 20.1 lists the Real-Time Clock Mode Specifications.
Table 20.2 lists the Interrupt Sources, Figure 20.2 shows the Definition of Time Representation and Figure 20.3
shows the Operating Example in Real-Time Clock Mode.
fC4
(8.192kHz)
1/2
(1/16)
(1/256)
4-bit counter
8-bit counter
(1s) Overflow
Data bus
Overflow
TRESEC
register
Overflow
TREMIN
register
Overflow
TREHR
register
H12_H24
bit
TREWK
register
000
PM
bit
WKIE
DYIE
Timing
control
HRIE
MNIE
SEIE
BSY
bit
H12_H24, PM, INT: Bits in TRECR1 register
SEIE, MNIE, HRIE, DYIE, WKIE: Bits in TRECR2 register
BSY: Bit in TRESEC, TREMIN, TREHR, TREWK register
Figure 20.1
Block Diagram of Real-Time Clock Mode
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INT
bit
Timer RE
interrupt
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 20.1
20. Timer RE
Real-Time Clock Mode Specifications
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request generation
timing
Read from timer
Write to timer
Select function
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Specification
fC4
Increment
1 (count starts) is written to TSTART bit in TRECR1 register
0 (count stops) is written to TSTART bit in TRECR1 register
Select any one of the following:
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
12-hour mode/24-hour mode switch function
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.1
Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode
Address 0118h
Bit
b7
Symbol
BSY
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
20.2.2
b6
SC12
0
b5
SC11
0
Symbol
Bit Name
SC00 1st digit of second count bit
SC01
SC02
SC03
SC10 2nd digit of second count bit
SC11
SC12
BSY
Timer RE busy flag
b4
SC10
0
b3
SC03
0
b2
SC02
0
b1
SC01
0
b0
SC00
0
Function
Setting Range
Count 0 to 9 every second. When the digit 0 to 9
moves up, 1 is added to the 2nd digit of (BCD code)
second.
When counting 0 to 5, 60 seconds are
counted.
0 to 5
(BCD code)
This bit is set to 1 while registers TRESEC, TREMIN,
TREHR, and TREWK are updated
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode
Address 0119h
Bit
b7
Symbol
BSY
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
20. Timer RE
b6
MN12
0
b5
MN11
0
Symbol
Bit Name
MN00 1st digit of minute count bit
MN01
MN02
MN03
MN10 2nd digit of minute count bit
MN11
MN12
BSY
Timer RE busy flag
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b4
MN10
0
b3
MN03
0
b2
MN02
0
b1
MN01
0
b0
MN00
0
Function
Setting Range
Count 0 to 9 every minute. When the digit 0 to 9
moves up, 1 is added to the 2nd digit of (BCD code)
minute.
When counting 0 to 5, 60 minutes are
counted.
0 to 5
(BCD code)
This bit is set to 1 while registers TRESEC, TREMIN,
TREHR, and TREWK are updated.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.3
20. Timer RE
Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode
Address 011Ah
Bit
b7
Symbol
BSY
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
20.2.4
b3
b4
b5
b6
b7
b5
HR11
0
Symbol
Bit Name
HR00 1st digit of hour count bit
HR01
HR02
HR03
HR10 2nd digit of hour count bit
HR11
—
BSY
b4
HR10
0
b3
HR03
0
b2
HR02
0
b1
HR01
0
Function
Count 0 to 9 every hour. When the digit
moves up, 1 is added to the 2nd digit of
hour.
b0
HR00
0
Setting Range
0 to 9
(BCD code)
Count 0 to 1 w hen the H12_H24 bit is set 0 to 2
to 0 (12-hour mode).
(BCD code)
Count 0 to 2 w hen the H12_H24 bit is set
to 1 (24-hour mode).
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Timer RE busy flag
This bit is set to 1 while registers TRESEC, TREMIN,
TREHR, and TREWK are updated.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
R
Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode
Address 011Bh
Bit
b7
Symbol
BSY
After Reset
0
Bit
b0
b1
b2
b6
—
0
b6
—
0
b5
—
0
Symbol
Bit Name
WK0
Day of week count bit
WK1
WK2
—
—
—
—
BSY
b4
—
0
b3
—
0
b2
WK2
0
b1
WK1
0
b0
WK0
0
Function
b2 b1 b0
0 0 0: Sunday
0 0 1: Monday
0 1 0: Tuesday
0 1 1: Wednesday
1 0 0: Thursday
1 0 1: Friday
1 1 0: Saturday
1 1 1: Do not set.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Timer RE busy flag
REJ09B0458-0010 Rev.0.10
Page 273 of 572
Apr 01, 2008
This bit is set to 1 while registers TRESEC, TREMIN,
TREHR, and TREWK are updated.
R/W
R/W
R/W
R/W
—
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.5
20. Timer RE
Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode
Address 011Ch
Bit
b7
b6
Symbol TSTART H12_H24
After Reset
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b5
PM
0
b4
TRERST
0
b3
INT
0
b2
—
0
b1
TCSTF
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
TCSTF Timer RE count status flag
0: Count stopped
1: Counting
—
Reserved bit
Set to 0.
INT
Interrupt request timing bit
Set to 1 in real-time clock mode.
TRERST Timer RE reset bit
When setting this bit to 0, after setting it to 1, the followings
will occur.
• Registers TRESEC, TREMIN, TREHR, TREWK, and
TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in the
TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit counter is set
to 0h.
PM
A.m./p.m. bit
When the H12_H24 bit is set to 0 (12-hour mode) (1)
0: a.m.
1: p.m.
When the H12_H24 bit is set to 1 (24-hour mode), its value
is undefined.
H12_H24 Operating mode select bit
0: 12-hour mode
1: 24-hour mode
TSTART Timer RE count start bit
0: Count stops
1: Count starts
Note:
1. This bit is automatically modified while timer RE counts.
Noon
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H12_H24 bit = 0
(12-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
0 (a.m.)
Contents of PM bit
1 (p.m.)
000 (Sunday)
Contents in TREWK register
Date changes
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
18
19
20
21
22
23
0
1
2
3
⋅⋅⋅
H12_H24 bit = 0
(12-hour mode)
6
7
8
9
10
11
0
1
2
3
⋅⋅⋅
Contents of PM bit
Contents in TREWK register
1 (p.m.)
0 (a.m.)
⋅⋅⋅
000 (Sunday)
001 (Monday)
⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 20.2
Definition of Time Representation
REJ09B0458-0010 Rev.0.10
Page 274 of 572
Apr 01, 2008
R/W
—
R
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.6
20. Timer RE
Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode
Address 011Dh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
COMIE
0
b4
WKIE
0
b3
DYIE
0
b2
HRIE
0
b1
MNIE
0
b0
SEIE
0
Symbol
Bit Name
Function
SEIE Periodic interrupt triggered every
0: Disable periodic interrupt triggered every second
1: Enable periodic interrupt triggered every second
second enable bit (1)
MNIE Periodic interrupt triggered every
0: Disable periodic interrupt triggered every minute
1: Enable periodic interrupt triggered every minute
minute enable bit (1)
HRIE Periodic interrupt triggered every
0: Disable periodic interrupt triggered every hour
1: Enable periodic interrupt triggered every hour
hour enable bit (1)
0: Disable periodic interrupt triggered every day
DYIE Periodic interrupt triggered every
1: Enable periodic interrupt triggered every day
day enable bit (1)
WKIE Periodic interrupt triggered every
0: Disable periodic interrupt triggered every week
1: Enable periodic interrupt triggered every week
week enable bit (1)
COMIE Compare match interrupt enable bit Set to 0 in real-time clock mode.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Note:
1. Do not set multiple enable bits to 1 (enable interrupt).
Table 20.2
Interrupt Sources
Factor
Periodic interrupt
triggered every week
Periodic interrupt
triggered every day
Periodic interrupt
triggered every hour
Periodic interrupt
triggered every minute
Periodic interrupt
triggered every second
REJ09B0458-0010 Rev.0.10
Page 275 of 572
Interrupt Source
Value in TREWK register is set to 000b (Sunday)
(1-week period)
TREWK register is updated (1-day period)
Interrupt Enable Bit
WKIE
DYIE
TREHR register is updated (1-hour period)
HRIE
TREMIN register is updated (1-minute period)
MNIE
TRESEC register is updated (1-second period)
SEIE
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.7
20. Timer RE
Timer RE Count Source Select Register (TRECSR) in Real-Time Clock
Mode
Address 011Eh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
RCS0
RCS1
RCS2
RCS3
—
—
—
—
b6
—
0
b5
—
0
b4
—
0
b3
RCS3
1
b2
RCS2
0
b1
RCS1
0
b0
RCS0
0
Bit Name
Count source select bit
Function
Set to 00b in real-time clock mode.
4-bit counter select bit
Real-time clock mode select bit
Reserved bits
Set to 0 in real-time clock mode.
Set to 1 in real-time clock mode.
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
REJ09B0458-0010 Rev.0.10
Page 276 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.2.8
20. Timer RE
Operating Example
1s
Approx.
62.5 ms
Approx.
62.5 ms
BSY bit
Bits SC12 to SC00 in
TRESEC register
58
59
Bits MN12 to MN00 in
TREMIN register
03
Bits HR11 to HR00 in
TREHR register
(Not changed)
PM bit in
TRECR1 register
IR bit in TREIC register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
IR bit in TREIC register
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
(Not changed)
0
(Not changed)
1
0
1
0
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 20.3
Operating Example in Real-Time Clock Mode
REJ09B0458-0010 Rev.0.10
Page 277 of 572
04
1
Bits WK2 to WK0 in
TREWK register
Apr 01, 2008
00
Set to 0 by acknowledgement
of interrupt request
or a program
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.3
20. Timer RE
Output Compare Mode
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and
compare value match is detected with the 8-bit counter. Figure 20.4 shows a Block Diagram of Output Compare
Mode and Table 20.3 lists the Output Compare Mode Specifications. Figure 20.5 shows the Operating Example
in Output Compare Mode.
RCS1 to RCS0
f4
f8
f32
fC4
= 00b
= 01b
= 10b
1/2
4-bit
counter
RCS2 = 1
8-bit
counter
= 11b
RCS2 = 0
Comparison
circuit
TRERST: Bit in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2: Bits in TRECSR register
COMIE
TRESEC
TREMIN
Data bus
Figure 20.4
Block Diagram of Output Compare Mode
REJ09B0458-0010 Rev.0.10
Page 278 of 572
Apr 01, 2008
Match
signal
Timer RE interrupt
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 20.3
20. Timer RE
Output Compare Mode Specifications
Item
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
Read from timer
Write to timer
Selectable functions
REJ09B0458-0010 Rev.0.10
Page 279 of 572
Specification
f4, f8, f32, fC4
• Increment
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues.
The count value is held while count stops.
• When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
1 (count starts) is written to the TSTART bit in the TRECR1 register
0 (count stops) is written to the TSTART bit in the TRECR1 register
When the 8-bit counter content matches with the TREMIN register content
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
• Select use of 4-bit counter
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.3.1
20. Timer RE
Timer RE Counter Data Register (TRESEC) in Output Compare Mode
Address 0118h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
—
0
Bit
Function
b7 to b0 8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
20.3.2
R/W
R
Timer RE Compare Data Register (TREMIN) in Output Compare Mode
Address 0119h
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
Bit
b7 to b0 8-bit compare data is stored.
REJ09B0458-0010 Rev.0.10
Page 280 of 572
Apr 01, 2008
b4
—
0
b3
—
0
Function
b2
—
0
b1
—
0
b0
—
0
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.3.3
20. Timer RE
Timer RE Control Register 1 (TRECR1) in Output Compare Mode
Address 011Ch
Bit
b7
b6
Symbol TSTART H12_H24
After Reset
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
20.3.4
b5
PM
0
b4
TRERST
0
b3
INT
0
b2
—
0
b1
TCSTF
0
b0
—
0
Symbol
—
TCSTF
Bit Name
Function
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Timer RE count status flag
0: Count stopped
1: Counting
—
Reserved bit
Set to 0.
INT
Interrupt request timing bit
Set to 0 in output compare mode.
TRERST Timer RE reset bit
When setting this bit to 0, after setting it to 1, the
following will occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART in
the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bit
counter is set to 0h.
PM
A.m./p.m. bit
Set to 0 in output compare mode.
H12_H24 Operating mode select bit
TSTART Timer RE count start bit
0: Count stops
1: Count starts
R/W
—
R
R/W
R/W
R/W
R/W
R/W
R/W
Timer RE Control Register 2 (TRECR2) in Output Compare Mode
Address 011Dh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
Symbol
SEIE
b1
MNIE
b2
HRIE
b3
DYIE
b4
WKIE
b5
COMIE
b6
b7
—
—
b6
—
0
b5
COMIE
0
b4
WKIE
0
b3
DYIE
0
b2
HRIE
0
b1
MNIE
0
b0
SEIE
0
Bit Name
Function
Periodic interrupt triggered every
Set to 0 in output compare mode.
second enable bit
Periodic interrupt triggered every
minute enable bit
Periodic interrupt triggered every hour
enable bit
Periodic interrupt triggered every day
enable bit
Periodic interrupt triggered every
week enable bit
Compare match interrupt enable bit
0: Disable compare match interrupt
1: Enable compare match interrupt
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
REJ09B0458-0010 Rev.0.10
Page 281 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.3.5
20. Timer RE
Timer RE Count Source Select Register (TRECSR) in Output Compare
Mode
Address 011Eh
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
—
0
Bit
b0
b1
Symbol
RCS0
RCS1
Bit Name
Count source select bit (1)
b2
RCS2
4-bit counter select bit
b3
b4
b5
b6
b7
RCS3
—
—
—
—
Real-time clock mode select bit
Reserved bits
b3
RCS3
1
b2
RCS2
0
b1
RCS1
0
b0
RCS0
0
Function
b1 b0
0 0: f4
0 1: f8
1 0: f32
1 1: fC4
0: Not used
1: Used
Set to 0 in output compare mode.
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Note:
1. Write to bits RCS0 to RCS1 when the TCSTF bit in the TRECR1 register is set to 0 (count stopped).
REJ09B0458-0010 Rev.0.10
Page 282 of 572
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.3.6
20. Timer RE
Operating Example
8-bit counter content
(hexadecimal number)
Count starts
Matched
TREMIN register
setting value
Matched
Matched
00h
Time
Set to 1 by a program
TSTART bit in
TRECR1 register
1
0
2 cycles of maximum count source
TCSTF bit in
TRECR1 register
1
0
Set to 0 by acknowledgement of interrupt request
or a program
IR bit in
TREIC register
1
0
The above applies under the following conditions.
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
Figure 20.5
Operating Example in Output Compare Mode
REJ09B0458-0010 Rev.0.10
Page 283 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.4
20. Timer RE
Notes on Timer RE
20.4.1
Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE (1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
Note:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
20.4.2
Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 20.6 shows a Setting Example in Real-Time Clock Mode.
REJ09B0458-0010 Rev.0.10
Page 284 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20. Timer RE
TSTART in TRECR1 = 0
Stop timer RE operation
TCSTF in TRECR1 = 0?
TREIC ← 00h
(disable timer RE interrupt)
TRERST in TRECR1 = 1
Timer RE register
and control circuit reset
TRERST in TRECR1 = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Setting of TREIC (IR bit ← 0,
select interrupt priority level)
TSTART in TRECR1 = 1
Start timer RE operation
TCSTF in TRECR1 = 1?
Figure 20.6
Setting Example in Real-Time Clock Mode
REJ09B0458-0010 Rev.0.10
Page 285 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
20.4.3
20. Timer RE
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register
is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit
is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
REJ09B0458-0010 Rev.0.10
Page 286 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
21. Serial Interface (UART0)
The serial interface consists of two channels, UART0, UART2. This chapter describes the UART0.
21.1
Overview
UART0 has a dedicated timer to generate a transfer clock and operate independently. UART0 supports clock
synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figure 21.1 shows a UART0 Block Diagram. Figure 21.2 shows a Block Diagram of UART0 Transmit/Receive Unit.
Table 21.1 lists the Pin Configuration of UART0.
UART0
RXD0
TXD0
CLK1 and CLK0 = 00b
f1
f8
f32
fC
= 01b
CKDIR = 0
Internal
1/16
Clock synchronous type
U0BRG register
= 10b
1/(n0+1)
1/16
External
CKDIR = 1
Reception control
circuit
UART transmission
Transmission
control circuit
= 11b
Receive clock
Transmit clock
Transmit/
receive
unit
Clock synchronous type
1/2
Clock synchronous type
(internal clock selected)
CLK0
UART reception
Clock synchronous type
(internal clock selected)
Clock synchronous type
(external clock selected)
CKDIR = 0
CKDIR = 1
CLK
polarity
switch
circuit
CKDIR: Bit in U0MR register
CLK0, CLK1: Bits in U0C0 register
Figure 21.1
UART0 Block Diagram
REJ09B0458-0010 Rev.0.10
Page 287 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
1SP
RXD0
SP
SP
Clock
synchronous
type
PRYE = 0
Clock
PAR
disabled synchronous
type
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART0 receive register
PAR
PAR enabled UART
PRYE = 1
2SP
UART (9 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0 U0RB register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D8
PRYE = 1
PAR enabled
2SP
SP
SP
UART (9 bits)
UART
Pin Name
D5
D4
D3
D2
D1
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
UART (7 bits)
UART (8 bits)
UART (7 bits)
UART0 transmit register
SP: Stop bit
PAR: Parity bit
Clock
synchronous
type
Block Diagram of UART0 Transmit/Receive Unit
Pin Configuration of UART0
Assigned Pin
I/O
TXD0
P1_4
Output
RXD0
P1_5
Input
CLK0
P1_6
I/O
REJ09B0458-0010 Rev.0.10
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D0 U0TB register
TXD0
Clock
PAR
disabled synchronous
PRYE = 0 type
0
Table 21.1
D6
PAR
1SP
Figure 21.2
D7
Apr 01, 2008
Function
Serial data output
Serial data input
Transfer clock I/O
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.2
21. Serial Interface (UART0)
Registers
21.2.1
UART0 Transmit/Receive Mode Register (U0MR)
Address 00A0h (U0MR)
Bit
b7
b6
Symbol
—
PRYE
After Reset
0
0
b5
PRY
0
b4
STPS
0
Bit
b0
b1
b2
Symbol
SMD0
SMD1
SMD2
Bit Name
Serial I/O mode select bit
b3
CKDIR
Internal/external clock select bit
b4
STPS
Stop bit length select bit
b5
PRY
Odd/even parity select bit
b6
PRYE
b7
—
21.2.2
b3
CKDIR
0
b2
SMD2
0
b1
SMD1
0
b0
SMD0
0
Function
b2 b1 b0
Parity enable bit
Reserved bit
0 0 0: Serial interface disabled
0 0 1: Clock synchronous serial I/O mode
1 0 0: UART mode, transfer data 7 bits long
1 0 1: UART mode, transfer data 8 bits long
1 1 0: UART mode, transfer data 9 bits long
Other than above: Do not set.
0: Internal clock
1: External clock
0: One stop bit
1: Two stop bits
Enabled when PRYE = 1
0: Odd parity
1: Even parity
0: Parity disabled
1: Parity enabled
Set to 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UART0 Bit Rate Register (U0BRG)
Address 00A1h (U0BRG)
Bit
b7
b6
Symbol
—
—
After Reset
X
X
b5
—
X
b4
—
X
b3
—
X
b2
—
X
Bit
Function
b7 to b0 If the setting value is n, U0BRG divides the count source by n+1.
b1
—
X
b0
—
X
Setting Range
00h to FFh
Write to the U0BRG register while transmission and reception stop.
Use the MOV instruction to write to this register.
Set bits CLK0 and CLK1 in the U0C0 register before writing to the U0BRG register.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.2.3
21. Serial Interface (UART0)
UART0 Transmit Buffer Register (U0TB)
Address 00A3h to 00A2h (U0TB)
Bit
b7
b6
b5
Symbol
—
—
—
After Reset
X
X
X
b4
—
X
b3
—
X
b2
—
X
b1
—
X
b0
—
X
Bit
Symbol
After Reset
b12
—
X
b11
—
X
b10
—
X
b9
—
X
b8
—
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b15
—
X
b14
—
X
b13
—
X
Symbol
Function
—
Transmit data
—
—
—
—
—
—
—
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
—
—
—
—
—
—
R/W
W
—
If the transfer data is 9 bits long, write data to the high-order byte first, then low-order byte of the U0TB
register.
Use the MOV instruction to write to this register.
REJ09B0458-0010 Rev.0.10
Page 290 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.2.4
21. Serial Interface (UART0)
UART0 Transmit/Receive Control Register 0 (U0C0)
Address 00A4h (U0C0)
Bit
b7
b6
Symbol UFORM CKPOL
After Reset
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
CLK0
CLK1
b5
NCH
0
b4
—
0
Bit Name
BRG count source select bit (1)
b3
TXEPT
1
b2
—
0
b1
CLK1
0
b0
CLK0
0
Function
b1 b0
0 0: f1 selected
0 1: f8 selected
1 0: f32 selected
1 1: fC selected
—
Reserved bit
Set to 0.
TXEPT Transmit register empty flag
0: Data present in the transmit register
(transmission in progress)
1: No data in the transmit register
(transmission completed)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NCH
Data output select bit
0: TXD0 pin set to CMOS output
1: TXD0 pin set to N-channel open-drain output
CKPOL CLK polarity select bit
0: Transmit data output at the falling edge and receive
data input at the rising edge of the transfer clock
1: Transmit data output at the rising edge and receive
data input at the falling edge of the transfer clock
UFORM Transfer format select bit
0: LSB first
1: MSB first
R/W
R/W
R/W
R/W
R
—
R/W
R/W
R/W
Note:
1. If the BRG count source is switched, set the U0BRG register again.
21.2.5
UART0 Transmit/Receive Control Register 1 (U0C1)
Address 00A5h (U0C1)
Bit
b7
b6
Symbol
—
—
After Reset
0
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Symbol
TE
b5
U0RRM
0
b4
U0IRS
0
b3
RI
0
b2
RE
0
Bit Name
Transmit enable bit
b1
TI
1
b0
TE
0
Function
0: Transmission disabled
1: Transmission enabled
TI
Transmit buffer empty flag
0: Data present in the U0TB register
1: No data in the U0TB register
RE
Receive enable bit
0: Reception disabled
1: Reception enabled
RI
0: No data in the U0RB register
Receive complete flag (1)
1: Data present in the U0RB register
U0IRS UART0 transmit interrupt source
0: Transmission buffer empty (TI = 1)
select bit
1: Transmission completed (TXEPT = 1)
U0RRM UART0 continuous receive mode
0: Continuous receive mode disabled
1: Continuous receive mode enabled
enable bit (2)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
Notes:
1. The RI bit is set to 0 when the higher byte of the U0RB register is read.
2. In UART mode, set the U0RRM bit to 0 (continuous receive mode disabled).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R
R/W
R
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.2.6
21. Serial Interface (UART0)
UART0 Receive Buffer Register (U0RB)
Address 00A7h to 00A6h (U0RB)
Bit
b7
b6
b5
Symbol
—
—
—
After Reset
X
X
X
Bit
Symbol
After Reset
b15
SUM
X
b14
PER
X
b13
FER
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
Symbol
—
—
—
—
—
—
—
—
—
—
—
—
OER
Overrun error flag (1)
b13
FER
Framing error flag (1)
b14
PER
Parity error flag (1)
b15
SUM
Error sum flag (1)
b4
—
X
b3
—
X
b2
—
X
b1
—
X
b0
—
X
b12
OER
X
b11
—
X
b10
—
X
b9
—
X
b8
—
X
Bit Name
—
Function
Receive data (D7 to D0)
—
Receive data (D8)
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
0: No overrun error
1: Overrun error
0: No framing error
1: Framing error
0: No parity error
1: Parity error
0: No error
1: Error
Note:
1. Bits SUM, PER, FER, and OER are set to 0 (no error) when either of the following is set:
- Bits SMD2 to SMD0 in the U0MR register are set to 000b (serial interface disabled), or
- The RE bit in the U0C1 register is set to 0 (reception disabled)
The SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error).
Bits PER and FER are also set to 0 when the high-order byte of the U0RB register is read.
Always read the U0RB register in 16-bit units.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R
R
—
R
R
R
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.2.7
UART0 Pin Select Register (U0SR)
Address 0188h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
21. Serial Interface (UART0)
b6
—
0
b5
—
0
Symbol
Bit Name
TXD0SEL0 TXD0 pin select bit
b4
CLK0SEL0
0
b3
—
0
b2
RXD0SEL0
0
b1
—
0
b0
TXD0SEL0
0
Function
0: TXD0 pin not used
1: P1_4 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
RXD0SEL0 RXD0 pin select bit
0: RXD0 pin not used
1: P1_5 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
CLK0SEL0 CLK0 pin select bit
0: CLK0 pin not used
1: P1_6 assigned
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
R/W
R/W
—
R/W
—
R/W
—
The U0SR register selects which pin is assigned to the UART0 I/O. To use the I/O pin for UART0, set this
register.
Set the U0SR register before setting the UART0 associated registers. Also, do not change the setting value in
this register during UART0 operation.
REJ09B0458-0010 Rev.0.10
Page 293 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.3
21. Serial Interface (UART0)
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 21.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 21.3 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode (1).
Table 21.2
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer data format
Transfer clocks
Specification
• Transfer data length: 8 bits
• The CKDIR bit in the U0MR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): Input from the CLK0 pin
Transmit start conditions
• To start transmission, the following requirements must be met: (1)
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
register).
Receive start conditions
• To start reception, the following requirements must be met: (1)
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
register).
• For transmission: One of the following can be selected.
- The U0IRS bit is set to 0 (transmit buffer empty):
When data is transferred from the U0TB register to the UART0 transmit
register (at start of transmission).
- The U0IRS bit is set to 1 (transmission completed):
When data transmission from the UART0 transmit register is completed.
• For reception:
When data is transferred from the UART0 receive register to the U0RB
register (at completion of reception).
Interrupt request
generation timing
Error detection
Selectable functions
• Overrun error (2)
This error occurs if the serial interface starts receiving the next unit of data
before reading the U0RB register and receives the 7th bit of the next unit of
data.
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Reception is enabled immediately by reading the U0RB register.
Notes:
1. When an external clock is selected, the requirements must be met in either of the following states:
- The external clock is held high when the CKPOL bit in the U0C0 register is set to 0 (transmit data
output at the falling edge and receive data input at the rising edge of the transfer clock)
- The external clock is held low when the CKPOL bit in the U0C0 register is set to 1 (transmit data
output at the rising edge and receive data input at the falling edge of the transfer clock)
2. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register will be undefined.
The IR bit in the S0RIC register remains unchanged.
REJ09B0458-0010 Rev.0.10
Page 294 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 21.3
Register
U0TB
U0RB
U0BRG
U0MR
U0C0
U0C1
21. Serial Interface (UART0)
Registers Used and Settings in Clock Synchronous Serial I/O Mode (1)
Bit
b0 to b7
b0 to b7
OER
b0 to b7
SMD2 to SMD0
CKDIR
CLK1, CLK0
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
U0IRS
U0RRM
Function
Set data transmission.
Receive data can be read.
Overrun error flag
Set a bit rate.
Set to 001b.
Select the internal clock or external clock.
Select the count source for the U0BRG register.
Transmit register empty flag
Select TXD0 pin output mode.
Select the transfer clock polarity.
Select LSB first or MSB first.
Set to 1 to enable transmission/reception
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Select the UART0 transmit interrupt source.
Set to 1 to use continuous receive mode.
Note:
1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
REJ09B0458-0010 Rev.0.10
Page 295 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
Table 21.4 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode.
After UART0 operating mode is selected, the TXD0 pin outputs a “H” level until transfer starts. (If the NCH bit is
set to 1 (N-channel open-drain output), this pin is in the high-impedance state.)
Table 21.4
Pin Name
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
I/O Pin Functions in Clock Synchronous Serial I/O Mode
Function
Serial data output
Selection Method
TXD0SEL0 bit in U0SR register = 1
For reception only:
P1_4 can be used as a port by setting TXD0SEL0 bit = 0.
Serial data input
RXD0SEL0 bit in U0SR register = 1
PD1_5 bit in PD1 register = 0
For transmission only:
P1_5 can be used as a port by setting RXD0SEL0 bit = 0.
Transfer clock output CLK0SEL0 bit in U0SR register = 1
CKDIR bit in U0MR register = 0
Transfer clock input CLK0SEL0 bit in U0SR register = 1
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
REJ09B0458-0010 Rev.0.10
Page 296 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
• Transmit Timing Example (Internal Clock Selected)
TC
Transfer clock
TE bit in
U0C1 register
1
0
TI bit in
U0C1 register
1
0
Data is set in U0TB register.
Data transfer from U0TB register to UART0 transmit register
TCLK
Pulsing stops because TE bit is set to 0.
CLK0
TXD0
D0
TXEPT bit in
U0C0 register
1
0
IR bit in
S0TIC register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0
(interrupt request generation when the transmit buffer is empty)
TC = TCLK = 2(n+1)/fi
fi: Frequency of U0BRG count source (f1, f8, f32, fC)
n: Setting value in U0BRG register
• Receive Timing Example (External Clock Selected)
RE bit in
U0C1 register
1
0
TE bit in
U0C1 register
1
0
TI bit in
U0C1 register
1
0
Dummy data is set in U0TB register.
Data transfer from U0TB register to UART0 transmit register
1/fEXT
CLK0
Receive data taken in
D0
RXD0
RI bit in
U0C1 register
1
0
IR bit in
S0RIC register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
Data transfer from UART0 receive register
to U0RB register
D3
D4
D5
Data read from U0RB register
Set to 0 by an interrupt request acknowledgement or by a program.
The above applies when:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
The following should be met when “H” is applied to the CLK0 pin before receiving data:
• TE bit in U0C1 register = 1 (transmission enabled)
• RE bit in U0C1 register = 1 (reception enabled)
• Dummy data is written to U0TB register
fEXT: Frequency of external clock
Figure 21.3
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
D7
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.3.1
21. Serial Interface (UART0)
Polarity Select Function
Figure 21.4 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer
clock polarity.
• CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
CLK0 (1)
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
• CKPOL bit in U0C0 register = 1 (transmit data output at the rising edge and
receive data input at the falling edge of the transfer clock)
CLK0 (2)
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
Notes:
1. The CLK0 pin level is high during no transfer.
2. The CLK0 pin level is low during no transfer.
Figure 21.4
21.3.2
Transfer Clock Polarity
LSB First/MSB First Select Function
Figure 21.5 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.
• UFORM bit in U0C0 register = 0 (LSB first) (1)
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
• UFORM bit in U0C0 register = 1 (MSB first) (1)
CLK0
TXD0
D7
D6
D5
D4
D3
D2
D1
D0
RXD0
D7
D6
D5
D4
D3
D2
D1
D0
Note:
1. The above applies when:
CKPOL bit in U0C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock).
Figure 21.5
Transfer Format
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.3.3
21. Serial Interface (UART0)
Continuous Receive Mode
Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (continuous receive
mode enabled). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data present in
the U0TB register). If the U0RRM bit is set to 1, do not write dummy data to the U0TB register by a program.
REJ09B0458-0010 Rev.0.10
Page 299 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.4
21. Serial Interface (UART0)
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 21.5 lists the UART Mode Specifications. Table 21.6 lists the Registers Used and Settings in UART Mode.
Table 21.5
UART Mode Specifications
Item
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Specification
• Character bits (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bits: Selectable among 1 or 2 bits
• The CKDIR bit in the U0MR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32, fC n = setting value in the U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from the CLK0 pin,
n = setting value in the U0BRG register: 00h to FFh
• To start transmission, the following requirements must be met:
- The TE bit in the U0C1 register is set to 1 (transmission enabled).
- The TI bit in the U0C1 register is set to 0 (data present in the U0TB
register).
• To start reception, the following requirements must be met:
- The RE bit in the U0C1 register is set to 1 (reception enabled).
- Start bit detection
• For transmission: One of the following can be selected.
- The U0IRS bit is set to 0 (transmit buffer empty):
When data is transferred from the U0TB register to the UART0 transmit
register (at start of transmission).
- The U0IRS bit is set to 1 (transfer completed):
When data transmission from the UART0 transmit register is completed.
• For reception:
When data is transferred from the UART0 receive register to the U0RB
register (at completion of reception).
• Overrun error (1)
This error occurs if the serial interface starts receiving the next unit of data
before reading the U0RB register and receive the bit one before the last
stop bit of the next unit of data.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in the
parity and character bits do not match the set number of 1’s.
• Error sum flag
This flag is set is set to 1 if an overrun, framing, or parity error occurs.
Note:
1. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register will be undefined.
The IR bit in the S0RIC register remains unchanged.
REJ09B0458-0010 Rev.0.10
Page 300 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 21.6
21. Serial Interface (UART0)
Registers Used and Settings in UART Mode
Register
U0TB
b0 to b8
Set transmit
U0RB
b0 to b8
U0BRG
U0MR
OER,FER,PER,SUM
b0 to b7
SMD2 to SMD0
Receive data can be read. (2)
Error flag
Set a bit rate.
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
Select the internal clock or external clock.
Select the stop bit.
Select whether parity is included and whether odd or even.
Select the count source for the U0BRG register.
Transmit register empty flag
Select TXD0 pin output mode.
Set to 0.
Select LSB first or MSB first when transfer data is 8 bits long.
Set to 0 when transfer data is 7 bits or 9 bits long.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Select the UART0 transmit interrupt source.
Set to 0.
U0C0
U0C1
Bit
CKDIR
STPS
PRY, PRYE
CLK0, CLK1
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
U0IRS
U0RRM
Function
data. (1)
Notes:
1. The bits used for transmission/receive data are as follows:
- Bits b0 to b6 when transfer data is 7 bits long
- Bits b0 to b7 when transfer data is 8 bits long
- Bits b0 to b8 when transfer data is 9 bits long
2. The contents of the following are undefined:
- Bits 7 and 8 when the transfer data is 7 bits long
- Bit 8 when the transfer data is 8 bits long
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
Table 21.7 lists the I/O Pin Functions in UART Mode.
After the UART0 operating mode is selected, the TXD0 pin outputs a “H” level until transfer starts. (If the NCH bit
is set to 1 (N-channel open-drain output), this pin is in the high-impedance state.)
Table 21.7
Pin name
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
I/O Pin Functions in UART Mode
Function
Serial data output
Selection Method
TXD0SEL0 bit in U0SR register = 1
For reception only:
P1_4 can be used as a port by setting TXD0SEL0 bit = 0.
Serial data input
RXD0SEL0 bit in U0SR register = 1
PD1_5 bit in PD1 register = 0
For transmission only:
P1_5 can be used as a port by setting RXD0SEL0 bit = 0.
Programmable I/O port CLK0SEL0 bit in U0SR register = 0 (CLK0 pin not used)
Transfer clock input
CLK0SEL0 bit in U0SR register = 1
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
REJ09B0458-0010 Rev.0.10
Page 302 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
• Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
TC
Transfer clock
TE bit in 1
U0C1 register 0
Data is set in U0TB register.
TI bit in 1
U0C1 register 0
Data transfer from U0TB register to
UART0 transmit register
Pulsing stops because TE bit is set to 0.
Start
bit
TXD0
ST
Parity Stop
bit
bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
TXEPT bit in 1
U0C0 register 0
IR bit in 1
S0TIC register 0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• PRYE bit in U0MR register = 1 (parity enabled)
• STPS bit in U0MR register = 0 (one stop bit)
• U0IRS bit in U0C1 register = 1
(interrupt request generation when transmission is completed)
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of U0BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U0BRG count source (external clock)
n: Setting value in U0BRG register
• Transmit Timing Example When Transfer Data is 9 Bits Long (Parity Disabled, Two Stop Bits)
TC
Transfer clock
TE bit in
U0C1 register
1
0
TI bit in
U0C1 register
1
0
Data is set in U0TB register.
Data transfer from U0TB register to
UART0 transmit register
Stop Stop
bit
bit
Start
bit
TXD0
TXEPT bit in
U0C0 register
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
1
0
IR bit in 1
S0TIC register 0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 1 (two stop bits)
• U0IRS bit in U0C1 register = 0
(interrupt request generation when the transmit buffer is empty)
Figure 21.6
Transmit Timing in UART Mode
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of U0BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U0BRG count source (external clock)
n: Setting value in U0BRG register
D1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21. Serial Interface (UART0)
• Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit)
U0BRG output
1
0
RE bit in
U0C1 register
Stop bit
Start bit
RXD0
“L” is determined.
D0
D1
D7
Receive data taken in
Transfer clock
Reception starts when a transfer clock is
generated at the falling edge of the start bit.
RI bit in
U0C1 register
1
0
IR bit in
S0RIC register
1
0
Data transfer from UART0 receive register to U0RB register
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when :
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 0 (one stop bit)
Figure 21.7
Receive Timing in UART Mode
REJ09B0458-0010 Rev.0.10
Page 304 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.4.1
21. Serial Interface (UART0)
Bit Rate
In UART mode, the bit rate is the frequency divided by the U0BRG register and divided by 16.
UART mode
• Internal clock selected
Setting value in U0BRG register =
fj
Bit Rate × 16
−1
fj: Count source frequency of U0BRG register (f1, f8, f32, or fC)
• External clock selected
Setting value in U0BRG register =
fEXT
Bit Rate × 16
−1
fEXT: Count source frequency of U0BRG register (external clock)
Figure 21.8
Formula for Calculating Setting Value in U0BRG Register
Table 21.8
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate
(bps)
U0BRG
Count
Source
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
System Clock = 20 MHz
U0BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
129 (81h)
1201.92
0.16
64 (40h)
2403.85
0.16
32 (20h)
4734.85
-1.36
129 (81h)
9615.38
0.16
86 (56h)
14367.82
-0.22
64 (40h)
19230.77
0.16
42 (2Ah)
29069.77
0.94
32 (20h)
37878.79
-1.36
21 (15h)
56818.18
-1.36
10 (0Ah) 113636.36
-1.36
System Clock = 18.432 MHz (1)
U0BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
119 (77h)
1200.00
0.00
59 (3Bh)
2400.00
0.00
29 (1Dh)
4800.00
0.00
119 (77h)
9600.00
0.00
79 (4Fh)
14400.00
0.00
59 (3Bh)
19200.00
0.00
39 (27h)
28800.00
0.00
29 (1Dh)
38400.00
0.00
19 (13h)
57600.00
0.00
9 (09h)
115200.00
0.00
System Clock = 8 MHz
U0BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
51 (33h)
1201.92
0.16
25 (19h)
2403.85
0.16
12 (0Ch)
4807.69
0.16
51 (33h)
9615.38
0.16
34 (22h)
14285.71
-0.79
25 (19h)
19230.77
0.16
16 (10h)
29411.76
2.12
12 (0Ch)
38461.54
0.16
8 (08h)
55555.56
-3.55
−
−
−
Note:
1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1
register and the correction value in the FRA5 register should be written into the FRA3 register.
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20
in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 32. Electrical Characteristics.
REJ09B0458-0010 Rev.0.10
Page 305 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
21.5
21. Serial Interface (UART0)
Notes on Serial Interface (UART0)
• When reading data from the U0RB register either in clock synchronous serial I/O mode or in clock asynchronous
serial I/O mode, always read data in 16-bit units.
When the high-order byte of the U0RB register is read, bits PER and FER in the U0RB register and the RI bit in
the U0C1 register are set to 0.
To check receive errors, read the U0RB register and then use the read data.
Program example to read the receive buffer register:
MOV.W
00A6H,R0
; Read the U0RB register
• When writing data to the U0TB register in clock asynchronous serial I/O mode with 9-bit transfer data length,
write data to the high-order byte first and then the low-order byte, in 8-bit units.
Program example to write to the transmit buffer register:
MOV.B
#XXH,00A3H ; Write to the high-order byte of the U0TB register
MOV.B
#XXH,00A2H ; Write to the low-order byte of the U0TB register
REJ09B0458-0010 Rev.0.10
Page 306 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
22. Serial Interface (UART2)
The serial interface consists of three channels, UART0 to UART2. This chapter describes the UART2.
22.1
Overview
UART2 has a dedicated timer to generate a transfer clock and operate independently.
Figure 22.1 shows a UART2 Block Diagram. Figure 22.2 shows a Block Diagram of UART2 Transmit/Receive
Unit. Table 22.1 lists the Pin Configuration of UART2.
UART2 has the following modes:
•
•
•
•
Clock synchronous serial I/O mode
Clock asynchronous serial I/O mode (UART mode)
Special mode 1 (I2C mode)
Multiprocessor communication function
DF2EN = 1
Digital filter
RXD2
DF2EN = 0
TXD
polarity
switching
circuit (1)
RXD polarity
switching circuit
= 010b, 100b, 101b, 110b
Clock source selection
= 001b
CLK1 to CLK0
CKDIR
CKDIR internal
=0
= 00b
f1 = 01b
f8 = 10b
f32 = 11b
fC
SMD2 to SMD0
UART reception
1/16
Reception
control circuit
Clock synchronous type
U2BRG
register
1/(n+1)
UART transmission
1/16
= 010b, 100b, 101b, 110b
CKDIR
=1
CKDIR
external
= 001b
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(internal clock selected)
CKDIR = 0
1/2
CKDIR = 1
CKPOL
Clock synchronous type
(internal clock selected)
Clock synchronous type
(external clock selected)
CLK
CLK2
polarity
switching
circuit
CTS/RTS disabled
CTS/RTS selected
CTS2/RTS2
RTS2
CRS = 1
CRS = 0
CRD = 0
CTS/RTS disabled
CTS2
CRD = 1
VSS
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
DF2EN: Bit in URXDF register
Figure 22.1
UART2 Block Diagram
REJ09B0458-0010 Rev.0.10
Page 307 of 572
Receive
clock
Apr 01, 2008
n: Setting value in U2BRG register
Transmit
clock
Transmit/
receive
unit
TXD2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Not inverted
RXD2
IOPOL = 0
RXD data
inversion circuit
IOPOL = 1
Inverted
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
I 2C
PAR
Clock
disabled
synchronous
PRYE = 0 type
1SP
STPS = 0
SP
SP
UART (7 bits)
UART2 receive register
PAR
PRYE = 1
PAR
enabled
STPS = 1
2SP
UART
I 2C
Clock
synchronous
type UART
I2C
UART
(9 bits)
(8 bits)
UART
(9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
U2RB
register
Logic inversion circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic inversion circuit + MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
U2TB
register
UART
(8 bits)
UART
(9 bits)
I 2C
PAR
enabled
UART
PRYE = 1 SMD = 1
2SP
STPS = 1
SP
SP
PAR
STPS = 0
1SP
UART
(9 bits)
SMD = 0
PRYE = 0
I 2C
PAR
Clock
disabled
synchronous
type
I 2C
Clock
synchronous type
UART2 transmit register
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in U2MR register
CLK1, CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
U2ERE: Bit in U2C1 register
Figure 22.2
Table 22.1
UART (7 bits)
Error signal output disabled
Not inverted
IOPOL = 0
U2ERE = 0
Error signal
output
circuit
U2ERE = 1
IOPOL = 1
Inverted
Error signal output enabled
TXD data
inversion
circuit
Block Diagram of UART2 Transmit/Receive Unit
Pin Configuration of UART2
Pin Name
Assigned Pin
TXD2
P3_4 or P3_7
RXD2
P3_4, P3_7, or P4_5
CLK2
P3_5
P3_3
CTS2
I/O
Output
Input
I/O
Input
Function
Serial data output
Serial data input
Transfer clock I/O
Transmit control input
Output
Receive control input
RTS2
SCL2
P3_3
P3_4, P3_7, or P4_5
I/O
I2C mode clock I/O
SDA2
P3_4 or P3_7
I/O
I2C mode data I/O
REJ09B0458-0010 Rev.0.10
Page 308 of 572
Apr 01, 2008
TXD2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2
22. Serial Interface (UART2)
Registers
22.2.1
UART2 Transmit/Receive Mode Register (U2MR)
Address 00A8h
Bit
b7
Symbol IOPOL
After Reset
0
b6
PRYE
0
b5
PRY
0
b4
STPS
0
Bit
b0
b1
b2
Symbol
SMD0
SMD1
SMD2
Bit Name
Serial I/O mode select bit
b3
CKDIR
Internal/external clock select bit
b4
STPS
Stop bit length select bit
b5
PRY
Odd/even parity select bit
b6
PRYE
Parity enable bit
b7
IOPOL
TXD, RXD I/O polarity switch bit
22.2.2
b3
CKDIR
0
b2
SMD2
0
b1
SMD1
0
b0
SMD0
0
Function
b2 b1 b0
0 0 0: Serial interface disabled
0 0 1: Clock synchronous serial I/O mode
0 1 0: I2C mode
1 0 0: UART mode, transfer data 7 bits long
1 0 1: UART mode, transfer data 8 bits long
1 1 0: UART mode, transfer data 9 bits long
Other than above: Do not set.
0: Internal clock
1: External clock
0: One stop bit
1: Two stop bits
Enabled when PRYE = 1
0: Odd parity
1: Even parity
0: Parity disabled
1: Parity enabled
0: Not inverted
1: Inverted
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UART2 Bit Rate Register (U2BRG)
Address 00A9h
Bit
b7
Symbol
—
After Reset
X
b6
—
X
b5
—
X
b4
—
X
b3
—
X
b2
—
X
Bit
Function
b7 to b0 If the setting value is n, U2BRG divides the count source by n+1.
b1
—
X
b0
—
X
Setting Range
00h to FFh
Write to the U2BRG register while transmission and reception stop.
Use the MOV instruction to write to this register.
Set bits CLK1 to CLK0 in the U2C0 register before writing to the U2BRG register.
REJ09B0458-0010 Rev.0.10
Page 309 of 572
Apr 01, 2008
R/W
W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.3
22. Serial Interface (UART2)
UART2 Transmit Buffer Register (U2TB)
Address 00ABh to 00AAh
Bit
b7
b6
Symbol
—
—
After Reset
X
X
b5
—
X
b4
—
X
b3
—
X
b2
—
X
b1
—
X
b0
—
X
Bit
Symbol
After Reset
b13
—
X
b12
—
X
b11
—
X
b10
—
X
b9
—
X
b8
MPTB
X
b15
—
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
Symbol
—
—
—
—
—
—
—
—
MPTB
b9
b10
b11
b12
b13
b14
b15
—
—
—
—
—
—
—
b14
—
X
Function
Transmit data (D7 to D0)
Transmit data (D8) (1)
[When the multiprocessor communication function is not used]
Transmit data (D8)
[When the multiprocessor communication function is used]
• To transfer an ID, set the MPTB bit to 1.
• To transfer data, set the MPTB bit to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Note:
1. Set bits b0 to b7 after setting the MPTB bit.
REJ09B0458-0010 Rev.0.10
Page 310 of 572
Apr 01, 2008
R/W
W
W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.4
22. Serial Interface (UART2)
UART2 Transmit/Receive Control Register 0 (U2C0)
Address 00ACh
Bit
b7
Symbol UFORM
After Reset
0
b6
CKPOL
0
b5
NCH
0
Bit
b0
b1
Symbol
CLK0
CLK1
Bit Name
U2BRG count source
select bit (1)
b2
CRS
CTS/RTS function select bit
b3
TXEPT
Transmit register empty flag
b4
CRD
CTS/RTS disable bit
b5
NCH
Data output select bit
b6
CKPOL CLK polarity select bit
b7
UFORM Transfer format select bit (2)
b4
CRD
0
b3
TXEPT
1
b2
CRS
0
b1
CLK1
0
b0
CLK0
0
Function
b1 b0
0 0: f1 selected
0 1: f8 selected
1 0: f32 selected
1 1: fC selected
Enabled when CRD = 0
0: CTS function selected
1: RTS function selected
0: Data present in the transmit register
(transmission in progress)
1: No data in the transmit register
(transmission completed)
0: CTS/RTS function enabled
1: CTS/RTS function disabled
0: Pins TXD2/SDA2, SCL2 set to CMOS output
1: Pins TXD2/SDA2, SCL2 set to N-channel open-drain
output
0: Transmit data output at the falling edge and receive
data input at the rising edge of the transfer clock
1: Transmit data output at the rising edge and receive
data input at the falling edge of the transfer clock
0: LSB first
1: MSB first
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Notes:
1. If bits CLK1 to CLK0 are switched, set the U2BRG register again.
2. The UFORM bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous
serial I/O mode), or set to 101b (UART mode, transfer data 8 bits long).
Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I2C mode), and to 0 when bits SMD2 to SMD0
are set to 100b (UART mode, transfer data 7 bits long) or 110b (UART mode, transfer data 9 bits long).
REJ09B0458-0010 Rev.0.10
Page 311 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.5
22. Serial Interface (UART2)
UART2 Transmit/Receive Control Register 1 (U2C1)
Address 00ADh
Bit
b7
Symbol U2ERE
After Reset
0
b6
U2LCH
0
b5
U2RRM
0
Bit
b0
Symbol
TE
b1
TI
Transmit buffer empty flag
b2
RE
Receive enable bit
b3
RI
Receive complete flag
b4
U2IRS
b4
U2IRS
0
Bit Name
Transmit enable bit
b6
UART2 transmit interrupt source
select bit
U2RRM UART2 continuous receive mode
enable bit
U2LCH Data logic select bit (1)
b7
U2ERE
b5
Error signal output enable bit
b3
RI
0
b2
RE
0
b1
TI
1
b0
TE
0
Function
0: Transmission disabled
1: Transmission enabled
0: Data present in the U2TB register
1: No data in the U2TB register
0: Reception disabled
1: Reception enabled
0: No data in the U2RB register
1: Data present in the U2RB register
0: Transmit buffer empty (TI = 1)
1: Transmission completed (TXEPT = 1)
0: Continuous receive mode disabled
1: Continuous receive mode enabled
0: Not inverted
1: Inverted
0: Output disabled
1: Output enabled
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
Note:
1. The U2LCH bit is enabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous
serial I/O mode), 100b (UART mode, transfer data 7 bits long), or 101b (UART mode, transfer data 8 bits long).
Set the U2LCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, transfer data
9 bits long).
REJ09B0458-0010 Rev.0.10
Page 312 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.6
22. Serial Interface (UART2)
UART2 Receive Buffer Register (U2RB)
Address 00AFh to 00AEh
Bit
b7
b6
Symbol
—
—
After Reset
X
X
Bit
Symbol
After Reset
b15
SUM
X
b14
PER
X
b5
—
X
b4
—
X
b3
—
X
b2
—
X
b1
—
X
b0
—
X
b13
FER
X
b12
OER
X
b11
ABT
X
b10
—
X
b9
—
X
b8
MPRB
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
Symbol
—
—
—
—
—
—
—
—
MPRB
Bit Name
b9
b10
b11
—
—
ABT
Arbitration lost detect flag (1)
b12
OER
Overrun error flag (2)
b13
FER
Framing error flag (2, 3)
b14
PER
Parity error flag (2, 3)
b15
SUM
Error sum flag (2, 3)
—
Function
Receive data (D7 to D0)
—
Receive data (D8) (2)
[When the multiprocessor communication function is
not used]
Receive data (D8)
[When the multiprocessor communication function is
used]
• When the MPRB bit is set to 0, received D0 to D7
are data fields.
• When the MPRB bit is set to 1, received D0 to D7
are ID fields.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
0: Not detected (Won)
1: Detected (Lost)
0: No overrun error
1: Overrun error
0: No framing error
1: Framing error
0: No parity error
1: Parity error
0: No error
1: Error
R/W
R
R
—
R
R
R
R
R
Notes:
1. The ABT bit is set to 0 by writing 0 by a program. (Writing 1 has no effect.)
2. When bits SMD2 to SMD0 in the U2MR register are set to 000b (serial interface disabled) or the RE bit in the
U2C1 register is set to 0 (reception disabled), all of bits SUM, PER, FER, and OER are set to 0 (no error). The
SUM bit is set to 0 (no error) when all of bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are
set to 0 by reading the lower byte of the U2RB register.
3. These error flags are disabled when bits SMD2 to SMD0 in the U2MR register are set to 001b (clock
synchronous serial I/O mode) or to 010b (I2C mode). When read, the content is undefined.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.7
UART2 Digital Filter Function Select Register (URXDF)
Address 00B0h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
22. Serial Interface (UART2)
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
DF2EN
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
DF2EN RXD2 digital filter enable bit (1)
0: RXD2 digital filter disabled
1: RXD2 digital filter enabled
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
—
R/W
—
R/W
—
Note:
1. The RXD2 digital filter can be used only in clock asynchronous serial I/O (UART) mode. When bits SMD2 to
SMD0 in the U2MR register are set to 001b (clock synchronous serial I/O mode) or 010b (I2C mode), set the
DF2EN bit to 0 (RXD2 digital filter disabled).
22.2.8
UART2 Special Mode Register 5 (U2SMR5)
Address 00BBh
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
MPIE
0
b3
—
0
b2
—
0
b1
—
0
b0
MP
0
Symbol
Bit Name
Function
MP
Multiprocessor communication
0: Multiprocessor communication disabled
enable bit
1: Multiprocessor communication enabled (1)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
MPIE Multiprocessor communication
This bit is enabled when the MP bit is set to 1
control bit
(multiprocessor communication enabled).
When the MPIE bit is set to 1, the following will
result:
• Receive data in which the multiprocessor bit is 0
is ignored. Setting of the RI bit in the U2C1
register and bits OER and FER in the U2RB
register to 1 is disabled.
• On receiving receive data in which the
multiprocessor bit is 1, the MPIE bit is set to 0 and
receive operation other than multiprocessor
communication is performed.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
Reserved bit
Set to 0.
R/W
R/W
—
R/W
—
R/W
Note:
1. When the MP bit is set to 1 (multiprocessor communication enabled), the settings of bits PRY and PRYE in the
U2MR register are disabled. If bits SMD2 to SMD0 in the U2MR register are set to 001b (clock synchronous
serial I/O mode), set the MP bit to 0 (multiprocessor communication disabled).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.2.9
22. Serial Interface (UART2)
UART2 Special Mode Register 4 (U2SMR4)
Address 00BCh
Bit
b7
Symbol SWC9
After Reset
0
Bit
b0
b1
b6
SCLHI
0
b5
ACKC
0
b4
ACKD
0
b3
b2
b1
b0
STSPSEL STPREQ RSTAREQ STAREQ
0
0
0
0
Symbol
Bit Name
STAREQ Start condition generate bit (1)
RSTAREQ Restart condition generate bit (1)
b2
STPREQ Stop condition generate bit (1)
b3
STSPSEL SCL, SDA output select bit
b4
ACKD
ACK data bit
b5
ACKC
ACK data output enable bit
b6
SCLHI
SCL output stop enable bit
b7
SWC9
SCL wait bit 3
Function
0: Clear
1: Start
0: Clear
1: Start
0: Clear
1: Start
0: Start and stop conditions not output
1: Start and stop conditions output
0: ACK
1: NACK
0: Serial interface data output
1: ACK data output
0: Disabled
1: Enabled
0: SCL “L” hold disabled
1: SCL “L” hold enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
1. This bit is set to 0 when each condition is generated.
22.2.10 UART2 Special Mode Register 3 (U2SMR3)
Address 00BDh
Bit
b7
Symbol
DL2
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
DL1
0
b5
DL0
0
b4
—
X
b3
NODC
0
b2
—
X
b1
CKPH
0
b0
—
X
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
CKPH Clock phase set bit
0: No clock delay
1: With clock delay
—
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
NODC Clock output select bit
0: CLK2 set to CMOS output
1: CLK2 set to N-channel open-drain output
—
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
b7 b6 b5
DL0
SDA2 digital delay setup bit (1, 2)
0 0 0: No delay
DL1
0 0 1: 1 to 2 cycle(s) of U2BRG count source
DL2
0 1 0: 2 to 3 cycles of U2BRG count source
0 1 1: 3 to 4 cycles of U2BRG count source
1 0 0: 4 to 5 cycles of U2BRG count source
1 0 1: 5 to 6 cycles of U2BRG count source
1 1 0: 6 to 7 cycles of U2BRG count source
1 1 1: 7 to 8 cycles of U2BRG count source
R/W
—
R/W
—
R/W
—
R/W
R/W
R/W
Notes:
1. Bits DL2 to DL0 are used to generate a delay in SDA2 output digitally in I2C mode. In other than I2C mode, set
these bits to 000b (no delay).
2. The amount of delay varies with the load on pins SCL2 and SDA2. When an external clock is used, the amount
of delay increases by about 100 ns.
REJ09B0458-0010 Rev.0.10
Page 315 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
22.2.11 UART2 Special Mode Register 2 (U2SMR2)
Address 00BEh
Bit
b7
Symbol
—
After Reset
X
Bit
b0
b1
b6
SDHI
0
b5
SWC2
0
b4
STAC
0
b3
ALS
0
b2
SWC
0
b1
CSC
0
b0
IICM2
0
Symbol
Bit Name
IICM2 I2C mode select bit 2
CSC
Clock synchronization bit
b2
SWC
b3
ALS
b4
STAC
b5
SWC2
b6
SDHI
b7
—
Function
Refer to Table 22.12 I2C Mode Functions.
0: Disabled
1: Enabled
SCL wait output bit
0: Disabled
1: Enabled
SDA output stop bit
0: Disabled
1: Enabled
UART2 initialization bit
0: Disabled
1: Enabled
SCL wait output bit 2
0: Transfer clock
1: “L” output
SDA output disable bit
0: Enabled
1: Disabled (high-impedance)
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
22.2.12 UART2 Special Mode Register (U2SMR)
Address 00BFh
Bit
b7
Symbol
—
After Reset
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
SSS
0
b5
ACSE
0
b4
ABSCS
0
b3
—
0
b2
BBS
0
Symbol
Bit Name
IICM
I2C mode select bit
b1
ABC
0
b0
IICM
0
Function
0: Other than I2C mode
1: I2C mode
ABC
Arbitration lost detect flag control bit 0: Update per bit
1: Update per byte
BBS
0: Stop condition detected
Bus busy flag (1)
1: Start condition detected (busy)
—
Reserved bit
Set to 0.
ABSCS Bus collision detect sampling clock
0: Rising edge of transfer clock
select bit
1: Underflow signal of Timer RA (2)
ACSE Auto clear function select bit of
0: No auto clear function
transmit enable bit
1: Auto clear at bus collision occurrence
SSS
Transmit start condition select bit
0: Not synchronized to RXD2
1: Synchronized to RXD2 (2)
—
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
Notes:
1. The BBS bit is set to 0 by writing 0 by a program (Writing 1 has no effect).
2. When a transfer begins, the SSS bit is set to 0 (not synchronized to RXD2).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
22.2.13 UART2 Pin Select Register 0 (U2SR0)
Address 018Ah
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
RXD2SEL1 RXD2SEL0
0
0
Symbol
Bit Name
TXD2SEL0 TXD2/SDA2 pin select bit
TXD2SEL1
b3
—
0
b2
—
0
b1
b0
TXD2SEL1 TXD2SEL0
0
0
Function
b1 b0
0 0: TXD2/SDA2 pin not used
0 1: P3_7 assigned
1 0: P3_4 assigned
1 1: Do not set.
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
b5 b4
RXD2SEL0 RXD2/SCL2 pin select bit
0 0: RXD2/SCL2 pin not used
RXD2SEL1
0 1: P3_4 assigned
1 0: P3_7 assigned
1 1: P4_5 assigned
—
Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
—
The U2SR0 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this
register.
Set the U2SR0 register before setting the UART2 associated registers. Also, do not change the setting value in
this register during UART2 operation.
22.2.14 UART2 Pin Select Register 1 (U2SR1)
Address 018Bh
Bit
b7
Symbol
—
After Reset
0
b6
—
0
b5
—
0
b4
CTS2SEL0
0
b3
—
0
b2
—
0
b1
—
0
b0
CLK2SEL0
0
Bit
b0
Symbol
Bit Name
CLK2SEL0 CLK2 pin select bit
R/W
R/W
b1
b2
b3
b4
—
—
—
CTS2SEL0 CTS2/RTS2 pin select bit
R/W
—
b5
b6
b7
Function
0: CLK2 pin not used
1: P3_5 assigned
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
0: CTS2/RTS2 pin not used
1: P3_3 assigned
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
Set to 0.
R/W
R/W
—
R/W
The U2SR1 register selects which pin is assigned to the UART2 I/O. To use the I/O pin for UART2, set this
register.
Set the U2SR1 register before setting the UART2 associated registers. Also, do not change the setting value in
this register during UART2 operation.
REJ09B0458-0010 Rev.0.10
Page 317 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.3
22. Serial Interface (UART2)
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 22.2 lists the Clock Synchronous Serial I/O Mode Specifications. Table 22.3 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
Table 22.2
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer data format
Transfer clock
Specification
Transfer data length: 8 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin
Transmit/receive control
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
Transmit start conditions
To start transmission, the following requirements must be met: (1)
• The TE bit in the U2C1 register is set to 1 (transmission enabled)
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register)
• If the CTS function is selected, input to the CTS2 pin = “L”.
Receive start conditions
To start reception, the following requirements must be met: (1)
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
• The U2IRS bit is set to 1 (transmission completed):
When data transmission from the UART2 transmit register is completed.
For reception
• When data is transferred from the UART2 receive register to the U2RB register
(at completion of reception).
Interrupt request generation
timing
Error detection
Selectable functions
Overrun error (2)
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 7th bit of the next unit of data.
• CLK polarity selection
Transfer data I/O can be selected to occur synchronously with the rising or falling
edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be
selected.
• Continuous receive mode selection
Reception is enabled immediately by reading the U2RB register.
• Serial data logic switching
This function inverts the logic value of the transmit/receive data.
Notes:
1. When an external clock is selected, the requirements must be met in either of the following states:
- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output
at the falling edge and receive data input at the rising edge of the transfer clock)
- The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data output
at the rising edge and receive data input at the falling edge of the transfer clock)
2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC
register does not change to 1 (interrupt requested).
REJ09B0458-0010 Rev.0.10
Page 318 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.3
22. Serial Interface (UART2)
Registers Used and Settings in Clock Synchronous Serial I/O Mode
Register
U2TB
(1)
U2RB (1)
U2BRG
U2MR (1)
U2C0
Bit
Set transmit data.
b0 to b7
OER
b0 to b7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
Receive data can be read.
Overrun error flag
Set a bit rate.
Set to 001b.
Select the internal clock or external clock.
Set to 0.
Select the count source for the U2BRG register.
TXEPT
CRD
U2C1
U2SMR
U2SMR2
U2SMR3
U2SMR4
URXDF
U2SMR5
Function
b0 to b7
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2RRM
U2LCH
U2ERE
b0 to b7
b0 to b7
b0 to b2
NODC
b4 to b7
b0 to b7
DF2EN
MP
Select either CTS or RTS to use functions.
Transmit register empty flag
Enable or disable the CTS or RTS function.
Select TXD2 pin output mode.
Select the transfer clock polarity.
Select LSB first or MSB first.
Set to 1 to enable transmission/reception.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Select the source of UART2 transmit interrupt.
Set to 1 to use continuous receive mode.
Set to 1 to use inverted data logic.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select clock output mode.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Note:
1. Set the bits not listed in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
REJ09B0458-0010 Rev.0.10
Page 319 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Table 22.4 lists the Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output Pin
Function Not Selected).
Note that for a period from when UART2 operating mode is selected to when transfer starts, the TXD2 pin outputs
a “H” level. (When N-channel open-drain output is selected, this pin is in the high-impedance state.)
Figure 22.3 shows the Transmit and Receive Timing in Clock Synchronous Serial I/O Mode.
Table 22.4
Pin Functions in Clock Synchronous Serial I/O Mode (Multiple Transfer Clock Output
Pin Function Not Selected)
Pin Name
Function
TXD2
Serial data output
(P3_4 or P3_7)
Selection Method
• When TXD2 (P3_4)
Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P3_4)
• When TXD2 (P3_7)
Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P3_7)
• For reception only:
P3_4 and P3_7 can be used as ports by setting TXD2SEL1 to
TXD2SEL0 to 00b.
RXD2
Serial data input
• When RXD2 (P3_4)
(P3_4, P3_7, or
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4)
P4_5)
PD3_4 bit in PD3 register = 0
• When RXD2 (P3_7)
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7)
PD3_7 bit in PD3 register = 0
• When RXD2 (P4_5)
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5)
PD4_5 bit in PD4 register = 0
• For transmission only:
P3_4, P3_7, and P4_5 can be used as ports by setting
RXD2SEL1 to RXD2SEL0 to 00b.
CLK2 (P3_5)
Transfer clock output CLK2SEL0 bit in U2SR1 register = 1
CKDIR bit in U2MR register = 0
Transfer clock input CLK2SEL0 bit in U2SR1 register = 1
CKDIR bit in U2MR register = 1
PD3_5 bit in PD3 register = 0
CTS2SEL0 bit in U2SR1 register = 1
CTS2/RTS2
CTS input
CRD bit in U2C0 register = 0
(P3_3)
CRS bit in U2C0 register = 0
PD3_3 bit in PD3 register = 0
CTS2SEL0 bit in U2SR1 register = 1
RTS output
CRD bit in U2C0 register = 0
CRS bit in U2C0 register = 1
I/O port
CTS2SEL0 bit in U2SR1 register = 0
REJ09B0458-0010 Rev.0.10
Page 320 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
(1) Transmit Timing Example (Internal Clock Selected)
TC
Transfer clock
TE bit in
U2C1 register
1
TI bit in
U2C1 register
1
CTS2
0
Data is set in U2TB register.
0
Data transfer from U2TB register to UART2 transmit register
“H”
TCLK
“L”
Pulsing stops because “H” is applied
to CTS2.
Pulsing stops because TE bit is set to 0.
CLK2
TXD2
D0 D1 D2 D3 D4 D5 D6 D7
TXEPT flag in
U2C0 register
1
IR bit in
S2TIC register
1
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
0
0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
TC = TCLK = 2(n+1)/fj
fj: Frequency of U2BRG count source
(f1, f8, f32, fC)
n: Setting value in U2BRG register
(2) Receive Timing Example (External Clock Selected)
RE bit in
U2C1 register
1
TE bit in
U2C1 register
1
TI bit in
U2C1 register
1
0
0
Dummy data is set in U2TB register.
0
Data transfer from U2TB register to UART2 transmit register
“H”
RTS2
“L”
1/fEXT
“L” is applied when U2RB register is read.
CLK2
Received data taken in
RXD2
RI bit in
U2C1 register
D0 D1 D2 D3 D4 D5 D6 D7
Data transfer from UART2 receive
1 register to U2RB register
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
D7
Data read from U2RB register
0
IR bit in
S2RIC register
1
OER flag in
U2RB register
1
0
Set to 0 when an interrupt request is acknowledged or by a program.
0
The above applies when:
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
Make sure the following conditions are met
when the CLK2 pin input before receiving data is high:
• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register
fEXT: Frequency of external clock
Figure 22.3
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.3.1
22. Serial Interface (UART2)
Measure for Dealing with Communication Errors
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow
the procedures below:
• Resetting the U2RB register
(1) Set the RE bit in the U2C1 register to 0 (reception disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(3) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(4) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register
(1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(2) Set bits SMD2 to SMD0 in the U2MR register to 001b (clock synchronous serial I/O mode).
(3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value in the
U2C2 register.
22.3.2
CLK Polarity Select Function
Use the CKPOL bit in the U2C0 register to select the transfer clock polarity. Figure 22.4 shows the Transfer
Clock Polarity.
(1) CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
CLK2
“H” output from CLK2 pin
during no transfer
TXD2
D0
D1
D2
D3
D4
D5
D6
D7
RXD2
D0
D1
D2
D3
D4
D5
D6
D7
(2) CKPOL bit in U2C0 register = 1 (transmit data output at the rising edge and
receive data input at the falling edge of the transfer clock)
“H” output from CLK2 pin
during no transfer
CLK2
TXD2
D0
D1
D2
D3
D4
D5
D6
D7
RXD2
D0
D1
D2
D3
D4
D5
D6
D7
The above applies when:
• UFORM bit in U2C0 register = 0 (LSB first)
• U2LCH bit in U2C1 register = 0 (not inverted)
Figure 22.4
Transfer Clock Polarity
REJ09B0458-0010 Rev.0.10
Page 322 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.3.3
22. Serial Interface (UART2)
LSB First/MSB First Select Function
Use the UFORM bit in the U2C0 register to select the transfer format. Figure 22.5 shows the Transfer Format.
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
CLK2
TXD2
D0
D1
D2
D3
D4
D5
D6
D7
RXD2
D0
D1
D2
D3
D4
D5
D6
D7
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
CLK2
TXD2
D7
D6
D5
D4
D3
D2
D1
D0
RXD2
D7
D6
D5
D4
D3
D2
D1
D0
The above applies when:
• CKPOL bit in U2C0 register = 0
(transmit data output at the falling edge and receive data input
at the rising edge of the transfer clock)
• U2LCH bit in U2C1 register = 0 (not inverted)
Figure 22.5
22.3.4
Transfer Format
Continuous Receive Mode
In continuous receive mode, receive operation is enabled when the receive buffer register is read. It is not
necessary to write dummy data to the transmit buffer register to enable receive operation in this mode.
However, a dummy read of the receive buffer register is required when starting the operating mode.
When the U2RRM bit in the U2C1 register is set to 1 (continuous receive mode), the TI bit in the U2C1 register
is set to 0 (data present in the U2TB register) by reading the U2RB register. If the U2RRM bit is set to 1, do not
write dummy data to the U2TB register by a program.
REJ09B0458-0010 Rev.0.10
Page 323 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.3.5
22. Serial Interface (UART2)
Serial Data Logic Switching Function
If the U2LCH bit in the U2C1 register is set to 1 (inverted), the data written to the U2TB register has its logic
inverted before being transmitted. Similarly, the received data has its logic inverted when read from the U2RB
register. Figure 22.6 shows the Serial Data Logic Switching.
(1) U2LCH Bit in U2C1 Register = 0 (not inverted)
Transfer Clock
“H”
“L”
TXD2
(not inverted)
“H”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
D4
D5
D6
D7
(2) U2LCH Bit in U2C1 Register = 1 (inverted)
Transfer Clock
“H”
“L”
TXD2
(inverted)
“H”
“L”
D0
D1
D2
D3
The above applies when:
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
Figure 22.6
22.3.6
Serial Data Logic Switching
CTS/RTS Function
The CTS function is used to start transmit and receive operation when “L” is applied to the CTS2/RTS2 pin.
Transmit and receive operation begins when the CTS2/RTS2 pin is held low. If the “L” signal is switched to
“H” during a transmit or receive operation, the operation stops before the next data.
For the RTS function, the CTS2/RTS2 pin outputs “L” when the MCU is ready for a receive operation. The
output level goes high at the first falling edge of the CLK2 pin.
• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled)
The CTS2/RTS2 pin operates as the programmable I/O function.
• The CRD bit = 0, CRS bit = 0 (CTS function selected)
The CTS2/RTS2 pin operates as the CTS function.
• The CRD bit = 0, CRS bit = 1 (RTS function selected)
The CTS2/RTS2 pin operates as the RTS function.
REJ09B0458-0010 Rev.0.10
Page 324 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.4
22. Serial Interface (UART2)
Clock Asynchronous Serial I/O (UART) Mode
In UART mode, data is transmitted and received after setting the desired bit rate and transfer data format. Table
22.5 lists the UART Mode Specifications. Table 22.6 lists the Registers Used and Settings in UART Mode.
Table 22.5
UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmit/receive control
Transmit start conditions
Receive start conditions
Interrupt request generation
timing
Error detection
Selectable functions
Specification
• Character bits (transfer data): Selectable from 7, 8, or 9 bits
• Start bit:1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bits: Selectable from 1 bit or 2 bits
• The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(16(n + 1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
fEXT: Input from CLK2 pin n: Setting value in the U2BRG register: 00h to FFh
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
To start transmission, the following requirements must be met:
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
• If the CTS function is selected, input to the CTS2 pin = “L”.
To start reception, the following requirements must be met:
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• Start bit detection
For transmission, one of the following conditions can be selected.
• The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
• The U2IRS bit is set to 1 (transmission completed):
When data transmission from the UART2 transmit register is completed.
For reception
• When data is transferred from the UART2 receive register to the U2RB register
(at completion of reception).
• Overrun error (1)
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the bit one before the last stop bit of the
next unit of data.
• Framing error (2)
This error occurs when the set number of stop bits is not detected.
• Parity error (2)
This error occurs when if parity is enabled, the number of 1’s in the parity and
character bits does not match the set number of 1’s.
• Error sum flag
This flag is set to 1 if an overrun, framing, or parity error occurs.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be
selected.
• Serial data logic switching
This function inverts the logic of the transmit/receive data. The start and stop bits
are not inverted.
• TXD, RXD I/O polarity switching
This function inverts the polarities of the TXD pin output and RXD pin input. The
logic levels of all I/O data are inverted.
• RXD2 digital filter selection
The RXD2 input signal can be enabled or disabled.
Notes:
1. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC
register remains unchanged.
2. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
from the UART2 receive register to the U2RB register.
REJ09B0458-0010 Rev.0.10
Page 325 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.6
22. Serial Interface (UART2)
Registers Used and Settings in UART Mode
Register
U2TB
b0 to b8
U2RB
b0 to b8
U2BRG
U2MR
U2C0
Bit
NCH
CKPOL
UFORM
U2SMR
U2SMR2
U2SMR3
U2SMR4
URXDF
U2SMR5
Set transmit data.
Receive data can be read. (1, 2)
OER, FER, PER, SUM Error flag
b0 to b7
Set a bit rate.
SMD2 to SMD0
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
CKDIR
Select the internal clock or external clock.
STPS
Select the stop bit.
PRY, PRYE
Select whether parity is included and whether odd or even.
IOPOL
Select the TXD/RXD I/O polarity.
CLK0, CLK1
Select the count source for the U2BRG register.
CRS
Select CTS or RTS to use functions.
TXEPT
CRD
U2C1
Function
(1)
TE
TI
RE
RI
U2IRS
U2RRM
U2LCH
U2ERE
b0 to b7
b0 to b7
b0 to b7
b0 to b7
DF2EN
MP
Transmit register empty flag
Enable or disable the CTS or RTS function.
Select TXD2 pin output mode.
Set to 0.
Select LSB first or MSB first when transfer data is 8 bits long.
Set to 0 when transfer data is 7 or 9 bits long.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Select the UART2 transmit interrupt source.
Set to 0.
Set to 1 to use inverted data logic.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select the digital filter disabled or enabled.
Set to 0.
Notes:
1. The bits used for transmit/receive data are as follows:
- Bits b0 to b6 when transfer data is 7 bits long
- Bits b0 to b7 when transfer data is 8 bits long
- Bits b0 to b8 when transfer data is 9 bits long
2. The contents of the following are undefined:
- Bits b7 and b8 when transfer data is 7 bits long
- Bit b8 when transfer data is 8 bits long
REJ09B0458-0010 Rev.0.10
Page 326 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Table 22.7 lists the I/O Pin Functions in UART Mode.
Note that for a period from when the UART2 operating mode is selected to when transfer starts, the TXD2 pin
outputs “H”. (When N-channel open-drain output is selected, this pin is in the high-impedance state.)
Figure 22.7 shows the Transmit Timing in UART Mode. Figure 22.8 shows the Receive Timing in UART Mode.
Table 22.7
I/O Pin Functions in UART Mode
Pin Name
Function
TXD2
Serial data output
(P3_4 or P3_7)
RXD2
Serial data input
(P3_4, P3_7, or
P4_5)
CLK2 (P3_5)
I/O port
Transfer clock input
CTS2/RTS2
(P3_3)
CTS input
RTS input
I/O port
REJ09B0458-0010 Rev.0.10
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Selection Method
• When TXD2 (P3_4)
Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 10b (P3_4)
• When TXD2 (P3_7)
Bits TXD2SEL1 to TXD2SEL0 in U2SR0 register = 01b (P3_7)
• For reception only:
P3_4 and P3_7 can be used as ports by setting TXD2SEL1 to
TXD2SEL0 to 00b.
• When RXD2 (P3_4)
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 01b (P3_4)
• When RXD2 (P3_7)
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 10b (P3_7)
PD3_7 bit in PD3 register = 0
• When RXD2 (P4_5)
Bits RXD2SEL1 to RXD2SEL0 in U2SR0 register = 11b (P4_5)
PD4_5 bit in PD4 register = 0
• For transmission only:
P3_4, P3_7, and P4_5 can be used as ports by setting
RXD2SEL1 to RXD2SEL0 to 00b.
CLK2SEL0 bit in U2SR1 register = 0
CLK2SEL0 bit in U2SR1 register = 1
CKDIR bit in U2MR register = 1
PD3_5 bit in PD3 register = 0
CTS2SEL0 bit in U2SR1 register = 1
CRD bit in U2C0 register = 0
CRS bit in U2C0 register = 0
PD3_3 bit in PD3 register = 0
CTS2SEL0 bit in U2SR1 register = 1
CRD bit in U2C0 register = 0
CRS bit in U2C0 register = 1
CTS2SEL0 bit in U2SR1 register = 0
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
(1) Transmit Timing Example When Transfer Data 8 Bits is Long (Parity Enabled, One Stop Bit)
The transfer clock stops once because “H” is applied to CTS pin when the stop bit is verified.
The transfer clock resumes running immediately after “L” is applied to CTS pin.
TC
Transfer clock
1
TE bit in
U2C1 register
0
Data is set in U2TB register.
1
TI bit in
U2C1 register
0
Data transfer from U2TB register
to UART2 transmit register
“H”
CTS2
“L”
Parity
bit
Start bit
TXD2
ST
TXEPT bit in
U2C0 register
1
IR bit in
S2TIC register
1
D0
D1
D2
D3
D4
D5
D6
D7
P
Pulsing stops because TE bit is set to 0.
Stop
bit
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
0
0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• PRYE bit in U2MR register = 1 (parity enabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
• U2IRS bit in U2C1 register = 1 (interrupt request generation when transmission is completed)
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Setting value in U2BRG
(2) Transmit Timing Example When Transfer Data 9 Bits is Long (Parity Disabled, Two Stop Bits)
TC
Transfer clock
TE bit in
U2C1 register
1
TI bit in
U2C1 register
1
0
Data is set in U2TB register.
0
Data transfer from U2TB register
to UART2 transmit register
Stop
bit
Start bit
TXD2
ST
TXEPT bit in
U2C0 register
1
IR bit in
S2TIC register
1
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
Stop
bit
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
0
0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 1 (two stop bits)
• CRD bit in U2C0 register = 1 (CTS/RTS function disabled)
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the transmit buffer is empty)
Figure 22.7
Transmit Timing in UART Mode
REJ09B0458-0010 Rev.0.10
Page 328 of 572
Apr 01, 2008
TC = 16(n + 1)/fj or 16(n + 1)/fEXT
fj: Frequency of U2BRG count source (f1, f8, f32, fC)
fEXT: Frequency of U2BRG count source (external clock)
n: Setting value in U2BRG
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Receive Timing Example When Transfer Data 8 Bits is Long (Parity Disabled, One Stop Bit)
U2BRG
count source
1
RE bit in
U2C1 register
0
Stop bit
Start bit
RXD2
D0
D1
D7
“L” is determined.
Receive data taken in
Transfer clock
RTS2
Reception starts when a transfer clock
is generated at the falling edge
of the start bit.
1
RI bit in
U2C1 register
0
Data transfer from UART2 receive register
to U2RB register
“H”
“L”
IR bit in
S2RIC register
1
0
Set to 0 when an interrupt request is acknowledged or by a program.
The above applies when:
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS2/RTS2 function enabled), CRS bit = 1 (RTS2 function selected)
Figure 22.8
22.4.1
Receive Timing in UART Mode
Bit Rate
In UART mode, the bit rate is the frequency divided by the U2BRG register divided by 16. Table 22.8 lists the
Bit Rate Setting Example in UART Mode (Internal Clock Selected).
Table 22.8
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate
(bps)
U2BRG
Count
Source
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
System Clock = 20 MHz
U2BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
129 (81h)
1201.92
0.16
64 (40h)
2403.85
0.16
32 (20h)
4734.85
-1.36
129 (81h)
9615.38
0.16
86 (56h)
14367.82
-0.22
64 (40h)
19230.77
0.16
42 (2Ah)
29069.77
0.94
32 (20h)
37878.79
-1.36
21 (15h)
56818.18
-1.36
10 (0Ah) 113636.36
-1.36
System Clock = 18.432 MHz (1)
U2BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
119 (77h)
1200.00
0.00
59 (3Bh)
2400.00
0.00
29 (1Dh)
4800.00
0.00
119 (77h)
9600.00
0.00
79 (4Fh)
14400.00
0.00
59 (3Bh)
19200.00
0.00
39 (27h)
28800.00
0.00
29 (1Dh)
38400.00
0.00
19 (13h)
57600.00
0.00
9 (09h)
115200.00
0.00
System Clock = 8 MHz
U2BRG
Actual
Setting
Setting
Time
Error
Value
(bps)
(%)
51 (33h)
1201.92
0.16
25 (19h)
2403.85
0.16
12 (0Ch)
4807.69
0.16
51 (33h)
9615.38
0.16
34 (22h)
14285.71
-0.79
25 (19h)
19230.77
0.16
16 (10h)
29411.76
2.12
12 (0Ch)
38461.54
0.16
8 (08h)
55555.56
-3.55
−
−
−
Note:
1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1
register and the correction value in the FRA5 register should be written into the FRA3 register.
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20
in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 32. Electrical Characteristics.
REJ09B0458-0010 Rev.0.10
Page 329 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.4.2
22. Serial Interface (UART2)
Measure for Dealing with Communication Errors
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below:
• Resetting the U2RB register
(1) Set the RE bit in the U2C1 register to 0 (reception disabled).
(2) Set the RE bit in the U2C1 register to 1 (reception enabled).
• Resetting the U2TB register
(1) Set bits SMD2 to SMD0 in the U2MR register to 000b (serial interface disabled).
(2) Reset bits SMD2 to SMD0 in the U2MR register to 001b, 101b, and 110b.
(3) Write 1 to the TE bit in the U2C1 register (transmission enabled), regardless of the TE bit value in the
U2C1 register.
22.4.3
LSB First/MSB First Select Function
As shown in Figure 22.9, use the UFORM bit in the U2C0 register to select the transfer format. This function is
enabled when transfer data is 8 bits long. Figure 22.9 shows the Transfer Format.
(1) UFORM Bit in U2C0 Register = 0 (LSB first)
CLK2
TXD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXD2
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) UFORM Bit in U2C0 Register = 1 (MSB first)
CLK2
TXD2
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXD2
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
ST: Start bit
P: Parity bit
SP: Stop bit
The above applies when:
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
receive data input at the rising edge of the transfer clock)
• U2LCH bit in U2C1 register = 0 (not inverted)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Figure 22.9
Transfer Format
REJ09B0458-0010 Rev.0.10
Page 330 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.4.4
22. Serial Interface (UART2)
Serial Data Logic Switching Function
The data written to the U2TB register has its logic inverted before being transmitted. Similarly, the received
data has its logic inverted when read from the U2RB register. Figure 22.10 shows the Serial Data Logic
Switching.
(1) U2LCH bit in U2C1 Register = 0 (not inverted)
Transfer clock
“H”
“L”
TXD2
(not inverted)
“H”
ST
“L”
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D5
D6
D7
P
SP
(2) U2LCH Bit in U2C1 Register = 1 (inverted)
Transfer clock
“H”
TXD2
(inverted)
“H”
“L”
ST
“L”
D0
D1
D2
D3
D4
ST: Start bit
P: Parity bit
SP: Stop bit
The above applies when:
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge of the transfer clock)
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Figure 22.10
22.4.5
Serial Data Logic Switching
TXD and RXD I/O Polarity Inverse Function
This function inverts the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all I/O data
(including bits for start, stop, and parity) are inverted. Figure 22.11 shows the TXD and RXD I/O Inversion.
(1) IOPOL Bit in U2MR Register = 0 (not inverted)
Transfer clock
“H”
TXD2
(not inverted)
“H”
RXD2
(not inverted)
“H”
“L”
“L”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) IOPOL Bit in U2MR Register = 1 (inverted)
Transfer clock
“H”
TXD2
(not inverted)
RXD2
(not inverted)
“H”
“L”
“L”
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
The above applies when:
• UFORM bit in U2C0 register = 0 (LSB first)
• STPS bit in U2MR register = 0 (one stop bit)
• PRYE bit in U2MR register = 1 (parity enabled)
Figure 22.11
TXD and RXD I/O Inversion
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ST: Start bit
P: Parity bit
SP: Stop bit
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.4.6
22. Serial Interface (UART2)
CTS/RTS Function
The CTS function is used to start transmit operation when “L” is applied to the CTS2/RTS2 pin. Transmit
operation begins when the CTS2/RTS2 pin is held low. If the “L” signal is switched to “H” during transmit
operation, the operation stops after the ongoing transmit/receive operation is completed.
When the RTS function is used, the CTS2/RTS2 pin outputs “L” when the MCU is ready for a receive
operation. The output level goes high at the first falling edge of the CLK2 pin.
• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled)
The CTS2/RTS2 pin operates as the programmable I/O function.
• The CRD bit = 0, CRS bit = 0 (CTS function selected)
The CTS2/RTS2 pin operates as the CTS function.
• The CRD bit = 0, CRS bit = 1 (RTS function selected)
The CTS2/RTS2 pin operates as the RTS function.
22.4.7
RXD2 Digital Filter Select Function
When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a
frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit
when three latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise.
Figure 22.12 shows a Block Diagram of RXD2 Digital Filter Circuit.
Sampling clock
C
RXD2
input signal
D
C
Q
Latch
D
C
Q
Latch
D
Q
Latch
Match
detection
circuit
URXDF
register
(DF2EN bit)
Internal basic clock
period (1)
Sampling
clock
Note:
1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1)
(fj = f1, f8, f32, fC; n = setting value in the U2BRG register).
When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1)
(fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).
Figure 22.12
Block Diagram of RXD2 Digital Filter Circuit
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Internal RXD2
input signal
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.5
22. Serial Interface (UART2)
Special Mode 1 (I2C Mode)
I2 C mode is provided for use as a simplified I2C interface compatible mode. Table 22.9 lists the I2C Mode
Specifications. Tables 22.10 and 22.11 list the registers used in I2C mode and the settings. Table 22.12 lists the I2C
Mode Functions, Figure 22.13 shows an I2C Mode Block Diagram, and Figure 22.14 shows the Transfer to U2RB
Register and Interrupt Timing.
As shown in Table 22.12, the MCU is placed in I2C mode by setting bits SMD2 to SMD0 to 010b and the IICM bit
to 1. Because SDA2 transmit output has a delay circuit attached, SDA2 output does not change state until SCL2
goes low and remains stably low.
Table 22.9
I2C Mode Specifications
Item
Transfer data format
Transfer clock
Specification
Transfer data length: 8 bits
• Master mode
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
• Slave mode
The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin
Transmit start conditions
To start transmission, the following requirements must be met: (1)
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
Receive start conditions
To start reception, the following requirements must be met: (1)
• The RE bit in the U2C1 register is set to 1 (reception enabled).
• The TE bit in the U2C1 register is set to 1 (transmission enabled).
• The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
Start/stop condition detection, no acknowledgement detection, or acknowledgement
detection
Interrupt request generation
timing
Error detection
Selectable functions
Overrun error (2)
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 8th bit of the next unit of data.
• Arbitration lost
Timing at which the ABT bit in the U2RB register is updated can be selected.
• SDA2 digital delay
No digital delay or a delay of 2 to 8 U2BRG count source clock cycles
can be selected.
• Clock phase setting
With or without clock delay can be selected.
Notes:
1. when an external clock is selected, the requirements must be met while the external clock is held high.
2. If an overrun error occurs, the received data in the U2RB register will be undefined. The IR bit in the S2RIC
register remains unchanged.
REJ09B0458-0010 Rev.0.10
Page 333 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
SDA2
Start/stop condition generation block
STSPSEL = 1
Delay
circuit
ACKC = 1
DTC request
(source number 15)
SDA (STSP)
SCL (STSP)
STSPSEL = 0
IICM2 = 1
UART2 transmit/NACK
interrupt request
Transmit
register
ACKC = 0
IICM = 1 and
IICM2 = 0
UART2
SDHI
ALS
ACKD bit
D Q
T
Arbitration
IICM2 = 1
Receive
register
UART2
IICM = 1 and
IICM2 = 0
Start condition
detection
S
R
Q
Bus
busy
Stop condition
detection
SCL2
NACK
D Q
T
Falling edge
detection
R
IICM = 0
I/O port
UART2 receive/ACK
interrupt request
DTC request
(source number 14)
D Q
T
Port register (1)
STSPSEL = 0
UART2
STSPSEL
IICM = 1
=1
ACK
9th bit
Q
Internal clock
SWC2
External
clock
R
S
Start/stop condition detection
interrupt request
CLK
control
UART2
9th bit falling edge
SWC
IICM: Bit in U2SMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in U2SMR2 register
STSPSEL, ACKD, ACKC: Bits in U2SMR4 register
The above applies when:
• Bits SMD2 to SMD0 in U2MR register = 010b
• IICM bit in U2SMR register = 1
Note:
If the IICM bit is set to 1, the pin can be read even when the port direction bit corresponding to the SCL2 pin is set to 1 (output mode).
Figure 22.13
I2C Mode Block Diagram
REJ09B0458-0010 Rev.0.10
Page 334 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.10
22. Serial Interface (UART2)
Registers Used and Settings in I2C Mode (1)
Register
U2TB
(1)
U2RB (1)
U2BRG
U2MR (1)
U2C0
Function
Bit
Master
Slave
b0 to b7
Set transmit data.
Set transmit data.
b0 to b7
b8
ABT
OER
b0 to b7
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
Receive data can be read.
ACK or NACK is set in this bit.
Arbitration lost detect flag
Overrun error flag
Set a bit rate.
Set to 010b.
Set to 0.
Set to 0.
Select the count source for the U2BRG
register.
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Disabled
Set to 0.
Receive data can be read.
ACK or NACK is set in this bit.
Disabled
Overrun error flag
Disabled
Set to 010b.
Set to 1.
Set to 0.
Disabled
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
U2C1
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
U2SMR
IICM
Set to 1.
ABC
Select the timing at which an arbitration
lost is detected.
BBS
Bus busy flag
b3 to b7
Set to 0.
U2SMR2 IICM2
Refer to Table 22.12 I2C Mode
Functions.
CSC
Set to 1 to enable clock synchronization.
SWC
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
ALS
Set to 1 to stop SDA2 output when an
arbitration lost is detected.
STAC
Set to 0.
SWC2
SDHI
b7
Set to 1 to forcibly pull SCL2 low.
Set to 1 to disable SDA2 output.
Set to 0.
Disabled because CRD = 1.
Transmit register empty flag
Set to 1.
Set to 1.
Set to 0.
Set to 1.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Disabled
Set to 0.
Set to 1.
Disabled
Bus busy flag
Set to 0.
Refer to Table 22.12 I2C Mode
Functions.
Set to 0.
Set to 1 to fix SCL2 output low at the falling
edge of the 9th bit of clock.
Set to 0.
Set to 1 to initialize UART2 at start
condition detection
Set to 1 to forcibly pull SCL2 output low.
Set to 1 to disable SDA2 output.
Set to 0.
Note:
1. Set the bits not listed in this table to 0 when writing to the above registers in I2C mode.
REJ09B0458-0010 Rev.0.10
Page 335 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.11
22. Serial Interface (UART2)
Registers Used and Settings in I2C Mode (2)
Register
Function
Bit
U2SMR3 b0, b2, b4, and
NODC
CKPH
DL2 to DL0
U2SMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
URXDF DF2EN
U2SMR5 MP
REJ09B0458-0010 Rev.0.10
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Master
Slave
Set to 0.
Set to 0.
Refer to Table 22.12 I2C Mode Functions.
Set the amount of SDA2 digital delay.
Set to 1 to generate a start condition.
Set to 1 to generate a restart condition.
Set to 1 to generate a stop condition.
Set to 1 to output each condition.
Select ACK or NACK.
Set to 1 to output ACK data.
Set to 1 to stop SCL2 output when a stop
condition is detected.
Set to 0.
Refer to Table 22.12 I2C Mode Functions.
Set the amount of SDA2 digital delay.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Select ACK or NACK.
Set to 1 to output ACK data.
Set to 0.
Set to 0.
Set to 0.
Apr 01, 2008
Set to 1 to hold SCL2 low at the falling
edge of the 9th bit of clock.
Set to 0.
Set to 0.
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.12
22. Serial Interface (UART2)
I2C Mode Functions
Function
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
Clock Synchronous
Serial I/O Mode
(SMD2 to SMD0 = 001b,
IICM = 0)
IICM2 = 0 (NACK/ACK interrupt)
CKPH = 0
(No Clock Delay)
CKPH = 1
(With Clock Delay)
IICM2 = 1 (UART transmit/receive interrupt)
CKPH = 0
(No Clock Delay)
Source of UART2 bus
collision interrupt (1, 5)
−
Start condition detection or stop condition detection
(Refer to Table 22.13 STSPSEL Bit Functions)
Source of UART2
transmit/NACK2 (1, 6)
UART2 transmission
Transmission started or
completed (selectable by
U2IRS bit)
No acknowledgment
detection (NACK)
Rising edge of SCL2 9th bit
Source of UART2
receive/ACK2 (1, 6)
UART2 reception
Acknowledgment detection (ACK)
When 8th bit received
Rising edge of SCL2 9th bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for transferring data CKPOL = 0 (rising edge) Rising edge of SCL2 9th bit
from UART reception shift CKPOL = 1 (falling edge)
register to U2RB register
UART2
transmission
Rising edge of
SCL2 9th bit
CKPH = 1
(With Clock Delay)
UART2 transmission
Falling edge of SCL2
next to 9th bit
UART2 reception
Falling edge of SCL2 9th bit
Falling edge of
SCL2 9th bit
Falling and rising edges
of SCL2 9th bit
UART2 transmission output
delay
No delay
With delay
TXD2/SDA2 functions
TXD2 output
SDA2 I/O
RXD2/SCL2 functions
RXD2 input
SCL2 I/O
CLK2 functions
CLK2 input or output port
selected
− (Cannot be used in I2C mode.)
Read of RXD2 and SCL2
pin levels
Possible when the
corresponding port
direction bit = 0
Possible regardless of the content of the corresponding port direction bit.
Initial value of TXD2 and
SDA2 outputs
CKPOL = 0 (“H”)
CKPOL = 1 (“L”)
The value set in the port register before setting I2C mode. (2)
Initial and end values of
SCL2
−
“H”
DTC source number 14 (6)
Acknowledgment detection (ACK)
UART2 reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
UART2 reception
Falling edge of SCL2 9th bit
DTC source number 15 (6)
UART2 transmission
Transmission started or
completed (selectable by
U2IRS bit)
UART2 transmission
Rising edge of SCL2
9th bit
UART2
transmission
Rising edge of
SCL2 9th bit
Storage of receive data
1st to 8th bits of the
received data are stored
in bits b0 to b7 in the
U2RB register.
1st to 8th bits of the received data are
stored in bits b7 to b0 in the U2RB register.
Read of receive data
Notes:
1.
2.
3.
4.
5.
6.
The U2RB register status is read.
“L”
UART2 transmission
Falling edge of SCL2
next to 9th bit
“H”
“L”
UART2 transmission
Falling edge of SCL2
next to 9th bit
1st to 7th bits of the received data are stored
in bits b6 to b0 in the U2RB register. 8th bit is
stored in bit b8 in the U2RB register.
1st to 8th bits are
stored in bits b7 to b0 in
the U2RB register. (3)
Bits b6 to b0 in the
U2RB register are read
as bits b7 to b1. Bit b8
in the U2RB register is
read as bit b0. (4)
If the source of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1
(interrupt requested). (Refer to 11.8 Notes on Interrupts.)
If one of the bits listed below is changed, the interrupt source, the interrupt timing, and others change. Therefore, always be sure to set the IR
bit to 0 (interrupt not requested) after changing these bits.
Bits SMD2 to SMD0 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2 register, and the CKPH bit in the
U2SMR3 register.
Set the initial value of SDA2 output while bits SMD2 to SMD0 in the U2MR register are 000b (serial interface disabled).
Second data transfer to the U2RB register (rising edge of SCL2 9th bit)
First data transfer to the U2RB register (falling edge of SCL2 9th bit)
Refer to Figure 22.16 STSPSEL Bit Functions.
Refer to Figure 22.14 Transfer to U2RB Register and Interrupt Timing.
REJ09B0458-0010 Rev.0.10
Page 337 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DTC source number 14 request),
NACK interrupt
Transfer to U2RB register
b15
b9
...
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
U2RB register contents
(2) IICM2 = 0, CKPH = 1 (with clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DTC source number 14 request),
NACK interrupt
Transfer to U2RB register
b15
b9
...
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
U2RB register contents
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DTC source number 14 request)
Transmit
interrupt
Transfer to U2RB register
b15
b9
...
b8
b7
D0
b0
D7
D6
D5
D4
D3
D2
D1
U2RB register contents
(4) IICM2 = 1, CKPH = 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCL2
SDA2
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DTC source number 14 request)
b15
b9
...
Transmit interrupt
Transfer to U2RB register
Transfer to U2RB register
b8
b15
D0
b7
b0
D7
D6
D5
D4
D3
D2
D1
U2RB register contents
The above applies when:
• CKDIR bit in U2MR register = 0 (master selected)
Figure 22.14
Transfer to U2RB Register and Interrupt Timing
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
b9
...
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
U2RB register contents
D0
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.5.1
22. Serial Interface (UART2)
Detection of Start and Stop Conditions
Whether a start or a stop condition has been detected is determined.
A start condition detect interrupt request is generated when the SDA2 pin changes state from high to low while
the SCL2 pin is in the high state. A stop condition detect interrupt request is generated when the SDA2 pin
changes state from low to high while the SCL2 pin is in the high state.
Because the start and stop condition detect interrupts share an interrupt control register and vector, check the
BBS bit in the U2SMR register to determine which interrupt source is requesting the interrupt.
Figure 22.15 shows the Detection of Start and Stop Conditions.
5 cycles of f1 < Setting up duration
5 cycles of f1 < Holding duration
Setting up
duration
SCL2
SDA2
(Start condition)
SDA2
(Stop condition)
Figure 22.15
Detection of Start and Stop Conditions
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Holding
duration
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.5.2
22. Serial Interface (UART2)
Output of Start and Stop Conditions
A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start).
A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start).
A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start).
The output procedure is as follows:
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start).
(2) Set the STSPSEL bit in the U2SMR4 register to 1 (output).
Table 22.13 lists the STSPSEL Bit Functions. Figure 22.16 shows the STSPSEL Bit Functions.
Table 22.13
STSPSEL Bit Functions
Function
Output of pins SCL2
and SDA2
STSPSEL = 0
Output of transfer clock and data
Output of start/stop conditions is
accomplished by a program using ports
(not automatically generated in
hardware)
Detection of start/stop conditions
Start/stop condition
interrupt request
generation timing
STSPSEL = 1
Output of start/stop conditions
according to bits STAREQ,
RSTAREQ, and STPREQ
Completion of start/stop condition
generation
(1) Slave Mode
CKDIR = 1 (external clock)
STSPSEL bit
0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCL2
SDA2
Start condition
detection interrupt
Stop condition
detection interrupt
(2) Master Mode
CKDIR = 0 (internal clock), CKPH = 1 (with clock delay)
STSPSEL bit
Set to 1 by Set to 0 by
a program. a program.
Set to 1 by
a program.
Set to 0 by
a program.
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCL2
SDA2
Set STAREQ = 1
(start)
Figure 22.16
Start condition detection
interrupt
STSPSEL Bit Functions
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Set STPREQ = 1
(start) Stop condition detection
interrupt
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.5.3
22. Serial Interface (UART2)
Arbitration
Unmatching of the transmit data and SDA2 pin input data is checked in synchronization with the rising edge of
SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the U2RB register is
updated. If the ABC bit is set to 0 (update per bit), the ABT bit is set to 1 at the same time unmatching is
detected during check, and is set to 0 when not detected. If the ABC bit is set to 1, if unmatching is ever
detected, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of the 9th bit. If the
ABT bit needs to be updated per byte, set the ABT bit to 0 (not detected) after detecting acknowledge for the
first byte, before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to 1 (SDA output stop enabled) causes an arbitration lost to occur,
in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit is set to 1
(unmatching detected).
22.5.4
Transfer Clock
The transfer clock is used to transmit and receive data as is shown in Figure 22.14 Transfer to U2RB Register
and Interrupt Timing.
The CSC bit in the U2SMR2 register is used to synchronize an internally generated clock (internal SCL2) and
an external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a
falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low. The value
in the U2BRG register is reloaded and counting of the low-level intervals starts. If the internal SCL2 changes
state from low to high while the SCL2 pin is low, counting stops. If the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is equivalent to AND of the internal SCL2 and the clock signal applied to
the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the internal SCL2 1st bit to
the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register determines whether the SCL2 pin is fixed low or freed from low-level
output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the highimpedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register to 1 (“L” output) makes it possible to forcibly output a low-level
signal from the SCL2 pin even while sending or receiving data. Setting the SWC2 bit to 0 (transfer clock)
allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to 1 (SCL “L” hold enabled) when the CKPH bit in the U2SMR3
register is 1, the SCL2 pin is fixed low at the falling edge of the clock pulse next to the 9th. Setting the SWC9
bit to 0 (SCL “L” hold disabled) frees the SCL2 pin from low-level output.
22.5.5
SDA Output
The data written to bits b7 to b0 (D7 to D0) in the U2TB register is output in descending order from D7.
The 9th bit (D8) is ACK or NACK.
Set the initial value of SDA2 transmit output when IICM is set to 1 (I2C mode) and bits SMD2 to SMD0 in the
U2MR register are set to 000b (serial interface disabled).
Bits DL2 to DL0 in the U2SMR3 register allow addition of no delays or a delay of 2 to 8 U2BRG count source
clock cycles to the SDA2 output.
Setting the SDHI bit in the U2SMR2 register to 1 (SDA output disabled) forcibly places the SDA2 pin in the
high-impedance state. Do not write to the SDHI bit at the rising edge of the UART2 transfer clock. This is
because the ABT bit may inadvertently be set to 1 (detected).
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.5.6
22. Serial Interface (UART2)
SDA Input
When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) of received data are stored in bits b7 to b0 in the
U2RB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) of received data are stored in bits b6 to b0 in the
U2RB register and the 8th bit (D0) is stored in bit b8 in the U2RB register. Even when the IICM2 bit is set to 1,
if the CKPH bit is 1, the same data as when the IICM2 bit is 0 can be read by reading the U2RB register after
the rising edge of 9th bit of the clock.
22.5.7
ACK and NACK
If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not output) and the ACKC bit
in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is
output from the SDA2 pin.
If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising
edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin is low at the
rising edge of the 9th bit of the transmit clock.
If ACK2 (UART2 reception) is selected to generate a DTC request source, a DTC transfer can be activated by
detection of an acknowledge.
22.5.8
Initialization of Transmission/Reception
If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial interface
operates as described below.
• The transmit shift register is initialized, and the contents of the U2TB register are transferred to the transmit
shift register. In this way, the serial interface starts sending data when the next clock pulse is applied.
However, the UART2 output value does not change state and remains the same as when a start condition was
detected until the first bit of data is output in synchronization with the input clock.
• The receive shift register is initialized, and the serial interface starts receiving data when the next clock pulse
is applied.
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the falling
edge of the 9th clock pulse.
Note that when UART2 transmission/reception is started using this function, the TI bit does not change state.
Select the external clock as the transfer clock to start UART2 transmission/reception with this setting.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.6
22. Serial Interface (UART2)
Multiprocessor Communication Function
When the multiprocessor communication function is used, data transmission/reception can be performed between a
number of processors sharing communication lines by asynchronous serial communication, in which a
multiprocessor bit is added to the data. For multiprocessor communication, each receiving station is addressed by a
unique ID code. The serial communication cycle consists of two component cycles; an ID transmission cycle for
specifying the receiving station, and a data transmission cycle for the specified receiving station. The
multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. When
the multiprocessor bit is set to 1, the cycle is an ID transmission cycle; when the multiprocessor bit is set to 0, the
cycle is a data transmission cycle. Figure 22.17 shows an Inter-Processor Communication Example Using
Multiprocessor Format (Data AAh Transmission to Receiving Station A).
The transmitting station first sends the ID code of the receiving station to perform communication as
communication data with a 1 multiprocessor bit added. It then sends transmit data as communication data with a 0
multiprocessor bit added.
When communication data in which the multiprocessor bit is 1 is received, the receiving station compares that data
with its own ID. If they match, the data to be sent next is received. If they do not match, the receive station
continues to skip communication data until data in which the multiprocessor bit is 1 is again received.
UART2 uses the MPIE bit in the U2SMR5 register to implement this function. When the MPIE bit is set to 1, data
transfer from the UART2 receive register to the U2RB register, receive error detection, and the settings of the
status flags, the RI bit in the U2C1 register, bits FER and OER in the U2RB register, are disabled until data in
which the multiprocessor bit is 1 is received. On receiving a receive character in which the multiprocessor bit is 1,
the MPRB bit in the U2RB register is set to 1 and the MPIE in the U2SMR5 register bit is set to 0, thus normal
reception is resumed.
When the multiprocessor format is specified, the parity bit specification is invalid. All other bit settings are the
same as those in normal asynchronous mode (UART mode). The clock used for multiprocessor communication is
the same as that in normal asynchronous mode (UART mode).
Figure 22.18 shows a Block Diagram of Multiprocessor Communication Function.
Table 22.14 lists the Registers and Settings in Multiprocessor Communication Function.
Transmitting
station
Communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial data
01h
AAh
(MPRB = 1)
(MPRB = 0)
ID transmission cycle
= receiving station
specification
Data transmission cycle
= data transmission to
receiving station
specified by ID
MPRB: Multiprocessor bit
Figure 22.17
Inter-Processor Communication Example Using Multiprocessor Format
(Data AAh Transmission to Receiving Station A)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Reception
(5)
1SP
DF2EN = 0
SP
SP
PRYE = 0 Clock
PAR
synchronous
disabled
type
PAR
enabled
PRYE = 1
Digital
filter
UART
UART
(9 bits)
(1)
(2)
RXD2
UART
(7 bits)
UART2 receive register
PAR
2SP
DF2EN = 1
Clock
synchronous type
UART (7 bits)
UART (8 bits)
0
0
0
0
0
0
0
MPRB
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
D7
D6
D5
D4
D3
D2
D1
D0 U2RB
register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
MPTB
Transmission
PAR
enabled
PRYE = 1
2SP
SP
SP
(4) UART
(9 bits)
UART
(3)
D7
D6
D5
(5)
D2
D1
U2TB
D0 register
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
Clock
PAR
synchronous
disabled
PRYE = 0 type
0
UART (7 bits)
UART
UART (8 bits)
(7 bits)
Clock
synchronous type
[Multiprocessor mode reception when MP = 1 (multiprocessor communication enabled)]
(1) Clock asynchronous (7 bits): Received D7 is transferred to b8 in the U2RB register.
(2) Clock asynchronous (8 bits): Received D8 is transferred to b8 in the U2RB register.
[Multiprocessor mode transmission when MP = 1 (multiprocessor communication enabled)]
(3) Clock asynchronous (7 bits): b8 in the U2TB register is transferred externally as transfer data D7.
(4) Clock asynchronous (8 bits): b8 in the U2TB register is transferred externally as transfer data D8.
[Multiprocessor mode transmission/reception]
(5) PAR is disabled.
Block Diagram of Multiprocessor Communication Function
REJ09B0458-0010 Rev.0.10
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D3
TXD2
PAR
1SP
Figure 22.18
D4
Apr 01, 2008
UART2 transmit register
SP: Stop bit
PAR: Parity bit
PRYE: Bit in U2MR register
DF2EN: Bit in URXDF register
MP: Bit in U2SMR5 register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 22.14
Register
U2TB
(1)
U2RB (2)
U2BRG
U2MR
U2C0
U2C1
U2SMR
U2SMR2
U2SMR3
U2SMR4
U2SMR5
URXDF
22. Serial Interface (UART2)
Registers and Settings in Multiprocessor Communication Function
Bit
b0 to b7
MPTB
b0 to b7
MPRB
OER, FER, SUM
b0 to b7
SMD2 to SMD0
CKDIR
STPS
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
TE
TI
RE
RI
U2IRS
U2LCH
U2ERE
b0 to b7
b0 to b7
b0 to b7
b0 to b7
MP
MPIE
DF2EN
Function
Set transmit data.
Set to 0 or 1.
Receive data can be read.
Multiprocessor bit
Error flag
Set the transfer rate.
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Select the internal clock or external clock.
Select the stop bit.
Parity detection function disabled
Set to 0.
Select the U2BRG count source.
CTS or RTS function disabled
Transmit register empty flag
Set to 0.
Select TXD2 pin output mode.
Set to 0.
Set to 0.
Set to 1 to enable transmission.
Transmit buffer empty flag
Set to 1 to enable reception.
Receive complete flag
Select the UART2 transmit interrupt source.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 0.
Set to 1.
Set to 1.
Select the digital filter enabled or disabled.
Notes:
1. Set the MPTB bit to 1 when the ID data frame is transmitted. Set this bit to 0 when the data frame is
transmitted.
2. If the MPRB bit is set to 1, received D7 to D0 are ID fields. If the MPRB bit is set to 0, received D7 to
D0 are data fields.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.6.1
22. Serial Interface (UART2)
Multiprocessor Transmission
Figure 22.19 shows a Sample Flowchart of Multiprocessor Data Transmission. Set the MPBT bit in the U2TB
register to 1 for ID transmission cycles. Set the MPBT bit in the U2TB register to 0 for data transmission cycles.
Other operations are the same as in universal asynchronous receiver/transmitter mode (UART mode).
Start
(1)
Read the TI bit in the U2C1 register
No
TI = 1?
(1) Read the U2C1 register to confirm that the TI bit is
set to 1. Then set the MPBT bit in the U2TB register
to 0 or 1 and write transmit data to the U2TB
register.
Writing data to the U2TB register sets the TI bit to 0
automatically.
(2) When transmission completes, the TXEPT bit is set
to 1 automatically.
Yes
Set the MPBT bit in the U2TB register
(3) To continue data transmission, read that the TI bit is 1
and write data tot the U2TB register. Writing data to
the U2TB register sets the TI bit to 0 automatically.
Write transmit data to
the U2TB register
Read the TXEPT bit
in the U2C0 register
No
TXEPT = 1?
(2)
Yes
Continue
data transmission?
(3)
Yes
No
Set the TE bit
in the U2C1 register to 0
End
Figure 22.19
Sample Flowchart of Multiprocessor Data Transmission
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.6.2
22. Serial Interface (UART2)
Multiprocessor Reception
Figure 22.20 shows a Sample Flowchart of Multiprocessor Data Reception. When the MPIE bit in the U2SMR5
register is set to 1, communication data is ignored until data in which the multiprocessor bit is 1 is received.
Communication data with a 1 multiprocessor bit added is transferred to the U2RB register as receive data. At this time,
a reception complete interrupt request is generated. Other operations are the same as in universal asynchronous
receiver/transmitter mode (UART mode). Figure 22.21 shows a Receive Operation Example during Multiprocessor
Communication (with 8-Bit Data/Multiprocessor Bit/One-Stop Bit).
Start
Set the MPIE bit
in the U2SMR5 register to 1
(1)
(1) Set the MPIE bit in the U2SMR5 register to 1.
Read the RI bit in the U2C1 register
No
RI = 1?
(2)
(3) When the data matches the own station ID, the
next data reception starts. When the data does
not match the ID, set the MPIE bit to 1 and the
MCU enters the idle state.
Yes
Read data
in the receive shift register
Yes
Own station ID?
(3)
No
(4) Read the U2C1 register to confirm that the RI
bit is set to 1. Then read data in the receive
shift register.
(5) To discontinue reception, set the RE bit in the
U2C0 register to 0 to complete reception.
To continue reception, restart the procedure
from step (1).
Read the RI bit in the U2C1 register
(4)
(2) When the MPRB bit is detected to be 1, the
MPIE bit is set to 0 and a reception complete
interrupt request can be generated.
Read the U2C1 register to confirm that the RI
bit is set to 1. If the RI bit is 1, read data in the
receive shift register and compare the data with
its own station ID. Reading data in the U2RB
register sets the RI bit to 0 automatically.
No
RI = 1?
Yes
Read receive data
in the U2RB register
(5)
Continue
data reception?
Yes
No
Set the RE bit
in the U2C1 register to 0
End
Figure 22.20
Sample Flowchart of Multiprocessor Data Reception
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22. Serial Interface (UART2)
Receive
data (ID1)
Start
bit
1
Serial data
0
D0
D1
MPRB
Stop
bit
1
1
D7
Receive
data (DATA1)
0
D0
1 frame
MP bit in
U2SMR5 register
1
MPIE bit in
U2SMR5 register
1
RI bit in
U2C1 register
1
D1
Marked state
(Idle state)
MPRB
D7
0
1
1
1 frame
0
0
ID1
U2RB register
Detect the MPRB bit and A reception complete
interrupt request is
set the MPIE bit to 0.
generated.
MCU operation
No reception complete
interrupt request is
generated.
The U2RB register retains
state.
Set the RI bit to 0.
Read data in the
U2RB register.
User processing
If data does not match
own station ID, set the
MPIE bit to 1 again.
(a) When Data Does Not Match Own Station ID
Receive
data (ID2)
Start
bit
1
Serial data
0
D0
D1
D7
MPRB
Stop
bit
1
1
Receive
data (DATA2)
0
D0
1 frame
MP bit in
U2SMR5 register
1
MPIE bit in
U2SMR5 register
1
RI bit in
U2C1 register
1
User processing
D7
0
1
1
1 frame
0
0
ID2
ID1
U2RB register
MCU operation
D1
Marked state
(Idle state)
MPRB
Detect the MPRB bit and A reception
complete
set the MPIE bit to 0.
interrupt request
is generated.
DATA2
Set the RI bit to 0.
A reception
Set the RI bit to 0.
complete
interrupt request
Read data in the If data matches own is generated.
Read data in the Set the MPIE bit
U2RB register.
station ID, continue
to 1 again.
U2RB register.
reception without any
setting changes.
(b) When Data Matches Own Station ID
MPRB: Bit in U2RB register
MPIE: Bit in U2SMR5 register
Figure 22.21
Receive Operation Example during Multiprocessor Communication (with 8-Bit
Data/Multiprocessor Bit/One-Stop Bit)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.6.3
22. Serial Interface (UART2)
RXD2 Digital Filter Select Function
When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a
frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit
when three latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise.
Figure 22.22 shows a Block Diagram of RXD2 Digital Filter Circuit.
Sampling clock
C
RXD2
input signal
D
C
Q
Latch
D
C
Q
Latch
D
Q
Latch
Match
detection
circuit
URXDF
register
(DF2EN bit)
Internal basic clock
period (1)
Sampling
clock
Note:
1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1)
(fj = f1, f8, f32, fC; n = setting value in the U2BRG register).
When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1)
(fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).
Figure 22.22
Block Diagram of RXD2 Digital Filter Circuit
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Internal RXD2
input signal
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.7
22. Serial Interface (UART2)
Notes on Serial Interface (UART2)
22.7.1
Clock Synchronous Serial I/O Mode
22.7.1.1
Transmission/Reception
When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the
transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs “H” when a receive
operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2
pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.
22.7.1.2
Transmission
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1
(transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input on the CTS2 pin = “L”
22.7.1.3
Reception
In clock synchronous serial I/O mode, the shift clock is generated by activating the transmitter. Set the UART2associated registers for transmit operation even if the MCU is used for receive operation only. Dummy data is
output from the TXD2 pin while receiving.
When an internal clock is selected, the shift clock is generated by setting the TE bit in the U2C1 register to 1
(transmission enabled) and placing dummy data in the U2TB register. When an external clock is selected, set
the TE bit to 1 (transmission enabled), place dummy data in the U2TB register, and input an external clock to
the CLK2 pin to generate the shift clock.
If data is received consecutively, an overrun error occurs when the RE bit in the U2C1 register is set to 1 (data
present in the U2RB register) and the next receive data is received in the UART2 receive register. Then, the
OER bit in the U2RB register is set to 1 (overrun error). At this time, the U2RB register value is undefined. If an
overrun error occurs, the IR bit in the S2RIC register remains unchanged.
To receive data consecutively, set dummy data in the low-order byte in the U2TB register per each receive
operation.
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit is set to 0, or while the external clock is held low when the CKPOL bit is set to 1.
• The RE bit in the U2C1 register = 1 (reception enabled)
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
22.7.2
22. Serial Interface (UART2)
Clock Asynchronous Serial I/O (UART) Mode
22.7.2.1
Transmission/Reception
When the RTS function is used with an external clock, the RTS2 pin outputs “L,” which informs the
transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs “H” when a receive
operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting the RTS2
pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is selected.
22.7.2.2
Transmission
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and receive data input at
the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set to 1
(transmit data output at the rising edge and receive data input at the falling edge of the transfer clock).
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
• If the CTS function is selected, input on the CTS2 pin = “L”
22.7.3
Special Mode 1 (I2C Mode)
When generating start, stop, and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0 and wait
for more than half cycle of the transfer clock before changing each condition generation bit (STAREQ,
RSTAREQ, and STPREQ) from 0 to 1.
REJ09B0458-0010 Rev.0.10
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
23. Clock Synchronous Serial Interface
23. Clock Synchronous Serial Interface
The clock synchronous serial interface is configured as follows.
Clock synchronous serial interface
Synchronous serial communication unit (SSU)
Clock synchronous communication mode
4-wire bus communication mode
I2C bus Interface
I2C bus interface mode
Clock synchronous serial mode
The clock synchronous serial interface uses the registers at addresses 0193h to 019Dh. Registers, bits, symbols, and
functions vary even for the same addresses depending on the mode. Refer to the registers of each function for details.
Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the
options of the transfer clock, clock output format, and data output format.
23.1
Mode Selection
The clock synchronous serial interface has four modes.
Table 23.1 lists the Mode Selections. Refer to 24. Synchronous Serial Communication Unit (SSU), 25. I2C bus
Interface and the sections that follow for details of each mode.
Table 23.1
Mode Selections
Bit 0 in 019Dh
IICSEL Bit in
Bit 7 in 0198h
(SSUMS Bit in SSMR2
SSUIICSR (ICE Bit in ICCR1
Function
Register, FS Bit in
Register
Register)
SAR Register)
0
0
0
Synchronous serial
communication unit
0
0
1
1
1
0
I2C bus interface
1
1
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1
Apr 01, 2008
Mode
Clock synchronous
communication mode
4-wire bus communication mode
I2C bus interface mode
Clock synchronous serial mode
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
24. Synchronous Serial Communication Unit (SSU)
Synchronous serial communication unit (SSU) supports clock synchronous serial data communication.
24.1
Overview
Table 24.1 lists a Synchronous Serial Communication Unit Specifications, Figure 24.1 shows a Block Diagram of
Synchronous Serial Communication Unit and Table 24.2 lists the Pin Configuration of Synchronous Serial
Communication Unit.
Table 24.1
Synchronous Serial Communication Unit Specifications
Item
Transfer data format
Specification
• Transfer data length: 8 to 16 bits
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Operating modes
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Master/slave device
Selectable
I/O pins
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
Transfer clocks
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
Receive error detection • Overrun error
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
Multimaster error
• Conflict error
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
detection
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Interrupt requests
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error) (1).
Select functions
• Data transfer direction
Selects MSB-first or LSB-first
• SSCK clock polarity
Selects “L” or “H” level when clock stops
• SSCK clock phase
Selects edge of data change and data download
Note:
1. Synchronous serial communication unit has only one interrupt vector table.
REJ09B0458-0010 Rev.0.10
Page 353 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
f1
Internal clock (f1/i)
Internal clock
generation
circuit
Multiplexer
SSCK
SSMR register
SSCRL register
SSCRH register
Transmit/receive
control circuit
SCS
SSER register
SSMR2 register
SSTDR register
SSO
Data bus
SSSR register
SSTRSR register
Selector
SSI
SSRDR register
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
i = 4, 8, 16, 32, 64, 128, or 256
Figure 24.1
Table 24.2
Block Diagram of Synchronous Serial Communication Unit
Pin Configuration of Synchronous Serial Communication Unit
Pin Name
Assigned Pin
I/O
Function
SSI
P3_3, P3_4, or P1_6
I/O
Data I/O pin
SCS
P3_3 or P3_4
I/O
Chip-select signal I/O pin
SSCK
P3_5
I/O
Clock I/O pin
SSO
P3_7
I/O
Data I/O pin
REJ09B0458-0010 Rev.0.10
Page 354 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2
24.2.1
24. Synchronous Serial Communication Unit (SSU)
Registers
Module Standby Control Register (MSTCR)
Address 0008h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
b3
MSTTRC MSTTRD MSTIIC
0
0
0
b2
—
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
0: Active
MSTIIC SSU, I2C bus standby bit
1: Standby (1)
MSTTRD Peripheral function power consumption
Set to 1.
reduce bit
The power consumption of the peripheral
functions can be reduced.
MSTTRC Timer RC standby bit
0: Active
1: Standby (2)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
R/W
—
R/W
R/W
R/W
—
Notes:
1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses
0193h to 019Dh) is disabled.
2. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h
to 0133h) is disabled.
24.2.2
SSU/IIC Pin Select Register (SSUIICSR)
Address 018Ch
Bit
b7
Symbol
—
After Reset
0
Bit
b0
Symbol
IICSEL
b1
b2
b3
b4
b5
b6
b7
—
—
—
—
—
—
—
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b1
—
0
b0
IICSEL
0
Function
0: SSU function selected
1: I2C bus function selected
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
—
Reserved bits
R/W
SSU/I2C
REJ09B0458-0010 Rev.0.10
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Bit Name
bus switch bit
b2
—
0
Apr 01, 2008
Set to 0.
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2.3
24. Synchronous Serial Communication Unit (SSU)
SS Bit Counter Register (SSBR)
Address 0193h
Bit
b7
Symbol
—
After Reset
1
Bit
b0
b1
b2
b3
b6
—
1
b5
—
1
b4
—
1
Symbol
Bit Name
BS0
SSU data transfer length set bit (1)
BS1
BS2
BS3
b4
b5
b6
b7
—
—
—
—
b3
BS3
1
b2
BS2
0
b1
BS1
0
b0
BS0
0
Function
R/W
R/W
R/W
R/W
R/W
b3 b2 b1 b0
0 0 0 0: 16 bits
1 0 0 0: 8 bits
1 0 0 1: 9 bits
1 0 1 0: 10 bits
1 0 1 1: 11 bits
1 1 0 0: 12 bits
1 1 0 1: 13 bits
1 1 1 0: 14 bits
1 1 1 1: 15 bits
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
—
—
—
Note:
1. Do not write to bits BS0 to BS3 during SSU operation. Write to these bits when the RE bit in the SSER register is
set to 0 (reception disabled) and the TE bit is set to 0 (transmission disabled).
To set the SSBR register, set the RE bit in the SSER register to 0 and the TE bit to 0.
Bits BS0 to BS3 (SSU Data Transfer Length Set Bit)
As the SSU data transfer length, 8 to 16 bits can be used.
24.2.4
SS Transmit Data Register (SSTDR)
Address 0195h to 0194h
Bit
b7
b6
Symbol
—
—
After Reset
1
1
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Bit
Symbol
After Reset
b13
—
1
b12
—
1
b11
—
1
b10
—
1
b9
—
1
b8
—
1
b15
—
1
b14
—
1
Bit
Symbol
Function
b15 to b0
—
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is
started when it is detected that the SSTRSR register is empty.
When the next transmit data is written to the SSTDR register during the data
transmission from the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data with LSB-first), the data
in which MSB and LSB are reversed is read, after writing to the SSTDR register.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2.5
24. Synchronous Serial Communication Unit (SSU)
SS Receive Data Register (SSRDR)
Address 0197h to 0196h
Bit
b7
b6
Symbol
—
—
After Reset
1
1
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Bit
Symbol
After Reset
b13
—
1
b12
—
1
b11
—
1
b10
—
1
b9
—
1
b8
—
1
b15
—
1
b14
—
1
Bit
Symbol
Function
(1)
b15 to b0
—
Store the receive data.
The receive data is transferred to the SSRDR register and the receive operation is
completed when 1 byte of data has been received by the SSTRSR register. At this time,
the next receive operation is possible.
Continuous reception is possible using registers SSTRSR and SSRDR.
R/W
R
Note:
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set
to 1 (overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
24.2.6
SS Control Register H (SSCRH)
Address 0198h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
RSSTP
0
b5
MSS
0
b4
—
0
Symbol
Bit Name
CKS0 Transfer clock select bit (1)
CKS1
CKS2
—
—
MSS
b3
—
0
b2
CKS2
0
b1
CKS1
0
b0
CKS0
0
Function
b2 b1 b0
0 0 0: f1/256
0 0 1: f1/128
0 1 0: f1/64
0 1 1: f1/32
1 0 0: f1/16
1 0 1: f1/8
1 1 0: f1/4
1 1 1: Do not set.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
0: Operates as slave device
1: Operates as master device
0: Maintains receive operation after receiving 1 byte of
RSSTP Receive single stop bit (3)
data
1: Completes receive operation after receiving 1 byte
of data
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Master/slave device select bit (2)
R/W
R/W
R/W
R/W
—
R/W
R/W
—
Notes:
1. The set clock is used when the internal clock is selected.
2. The SSCK pin functions as the transfer clock output pin when the MSS bit is set to 1 (operates as master
device). The MSS bit is set to 0 (operates as slave device) when the CE bit in the SSSR register is set to 1
(conflict error occurs).
3. The RSSTP bit is disabled when the MSS bit is set to 0 (operates as slave device).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2.7
SS Control Register L (SSCRL)
Address 0199h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
24. Synchronous Serial Communication Unit (SSU)
b6
—
1
b5
SOL
1
b4
SOLP
1
b3
—
1
b2
—
1
b1
SRES
0
b0
—
1
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SRES SSU control unit reset bit
Writing 1 to this bit resets the SSU control unit and the
SSTRSR register.
The value in the SSU internal register (1) is retained.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
The output level can be changed by the SOL bit when
SOLP SOL write protect bit (2)
this bit is set to 0.
The SOLP bit remains unchanged even if 1 is written
to it. When read, the content is 1.
SOL
Serial data output value setting bit When read
0: The serial data output is set to “L”.
1: The serial data output is set to “H”.
When written (2, 3)
0: The data output is “L” after the serial data output.
1: The data output is “H” after the serial data output.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
—
R/W
—
R/W
R/W
—
—
Notes:
1. Registers SSBR, SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
2. The data output after serial data is output can be changed by writing to the SOL bit before or after transfer. When
writing to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
3. Do not write to the SOL bit during data transfer.
REJ09B0458-0010 Rev.0.10
Page 358 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2.8
24. Synchronous Serial Communication Unit (SSU)
SS Mode Register (SSMR)
Address 019Ah
Bit
b7
Symbol
MLS
After Reset
0
b6
CPOS
0
b5
CPHS
0
Bit
b0
b1
b2
b3
Symbol
Bit Name
BC0
Bits counter 3 to 0
BC1
BC2
BC3
b4
b5
—
CPHS
b6
CPOS
b7
MLS
b4
—
1
b3
BC3
0
b2
BC2
0
b1
BC1
0
Function
b3 b2 b1 b0
0 0 0 0: 16 bits left
0 0 0 1: 1 bit left
0 0 1 0: 2 bits left
0 0 1 1: 3 bits left
0 1 0 0: 4 bits left
0 1 0 1: 5 bits left
0 1 1 0: 6 bits left
0 1 1 1: 7 bits left
1 0 0 0: 8 bits left
1 0 0 1: 9 bits left
1 0 1 0: 10 bits left
1 0 1 1: 11 bits left
1 1 0 0: 12 bits left
1 1 0 1: 13 bits left
1 1 1 0: 14 bits left
1 1 1 1: 15 bits left
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
0: Change data at odd edge
SSCK clock phase select bit (1)
(Download data at even edge)
1: Change data at even edge
(Download data at odd edge)
0: “H” when clock stops
SSCK clock polarity select bit (1)
1: “L” when clock stops
MSB first/LSB first select bit
0: Transfers data MSB first
1: Transfers data LSB first
b0
BC0
0
R/W
R
R
R
R
—
R/W
R/W
R/W
Note:
1. Refer to 24.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
and CPOS bits.
REJ09B0458-0010 Rev.0.10
Page 359 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.2.9
24. Synchronous Serial Communication Unit (SSU)
SS Enable Register (SSER)
Address 019Bh
Bit
b7
Symbol
TIE
After Reset
0
Bit
b0
b6
TEIE
0
b5
RIE
0
b4
TE
0
b3
RE
0
b2
—
0
b1
—
0
b0
CEIE
0
Symbol
Bit Name
CEIE Conflict error interrupt enable bit
Function
0: Disables conflict error interrupt request
1: Enables conflict error interrupt request
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
R/W
Receive enable bit
R/W
b1
b2
b3
—
—
RE
b4
TE
Transmit enable bit
b5
RIE
Receive interrupt enable bit
b6
TEIE
Transmit end interrupt enable bit
b7
TIE
Transmit interrupt enable bit
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
0: Disables receive
1: Enables receive
0: Disables transmit
1: Enables transmit
0: Disables receive data full and overrun error interrupt
request
1: Enables receive data full and overrun error interrupt
request
0: Disables transmit end interrupt request
1: Enables transmit end interrupt request
0: Disables transmit data empty interrupt request
1: Enables transmit data empty interrupt request
—
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
24.2.10 SS Status Register (SSSR)
Address 019Ch
Bit
b7
Symbol TDRE
After Reset
0
b6
TEND
0
b5
RDRF
0
b4
—
0
b3
—
0
b2
ORER
0
b1
—
0
b0
CE
0
Bit
b0
Symbol
Bit Name
CE
Conflict error flag (1)
R/W
R/W
b1
b2
—
ORER
—
R/W
b3
b4
b5
—
—
RDRF
Function
0: No conflict errors generated
1: Conflict errors generated (2)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
0: No overrun errors generated
Overrun error flag (1)
1: Overrun errors generated (3)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
b6
TEND
b7
TDRE
Receive data register full flag (1, 4) 0: No data in SSRDR register
1: Data in SSRDR register
0: The TDRE bit is set to 0 when transmitting the last
Transmit end flag (1, 5)
bit of transmit data
1: The TDRE bit is set to 1 when transmitting the last
bit of transmit data
0: Data is not transferred from registers SSTDR to
Transmit data empty flag (1, 5, 6)
SSTRSR
1: Data is transferred from registers SSTDR to
SSTRSR
—
R/W
R/W
Notes:
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits is invalid. To set any of these bits to 0, first read 1 then write
0.
2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit
is set to 1 if “L” is applied to the SCS pin input. Refer to 24.5.4 SCS Pin Control and Arbitration for more
information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H”
during transfer, the CE bit is set to 1.
3. Indicates when overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1.
After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1.
4. The RDRF bit is set to 0 when reading out the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register.
6. The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 (transmit enabled).
If the SSSR register is accessed continuously, insert one or more NOP instructions between the instructions
used for access.
REJ09B0458-0010 Rev.0.10
Page 361 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
24.2.11 SS Mode Register 2 (SSMR2)
Address 019Dh
Bit
b7
Symbol
BIDE
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
SCKS
0
b5
CSS1
0
b4
CSS0
0
Symbol
Bit Name
SSUMS SSU mode select bit (1)
CSOS
SCS pin open drain output select
bit
SOOS Serial data pin open output drain
select bit (1)
SCKOS SSCK pin open drain output select
bit
CSS0 SCS pin select bit (2)
CSS1
b6
SCKS
SSCK pin select bit
b7
BIDE
Bidirectional mode enable bit (1, 4)
b3
SCKOS
0
b2
SOOS
0
b1
CSOS
0
b0
SSUMS
0
Function
0: Clock synchronous communication mode
1: Four-wire bus communication mode
0: CMOS output
1: N-channel open-drain output
R/W
R/W
0: CMOS output (5)
1: N-channel open-drain output
0: CMOS output
1: N-channel open-drain output
R/W
b5 b4
R/W
R/W
0 0: Functions as port
0 1: Functions as SCS input pin
1 0: Functions as SCS output pin (3)
1 1: Functions as SCS output pin (3)
0: Functions as port
1: Functions as serial clock pin
0: Standard mode (communication using 2 pins of data
input and data output)
1: Bidirectional mode (communication using 1 pin of
data input and data output)
R/W
R/W
R/W
R/W
Notes:
1. Refer to 24.3.2.1 Association between Data I/O Pins and SS Shift Register for information on combinations of
data I/O pins.
2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 when the SSUMS bit is set to
0 (clock synchronous communication mode).
3. This bit functions as the SCS input pin before starting transfer.
4. The BIDE bit is disabled when the SSUMS bit is set to 0 (clock synchronous communication mode).
5. When the SOOS bit is set to 0 (CMOS output), set the port direction register bits corresponding to pins SSI and
SSO to 0 (input mode).
REJ09B0458-0010 Rev.0.10
Page 362 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.3
24. Synchronous Serial Communication Unit (SSU)
Common Items for Multiple Modes
24.3.1
Transfer Clock
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using synchronous serial communication unit, set the SCKS bit in the SSMR2 register to 1 and select the
SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
24.3.1.1
Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 24.2 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
REJ09B0458-0010 Rev.0.10
Page 363 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd
edge), and CPOS bit = 0 (“H” when clock stops)
SSCK
SSO, SSI
b1
b0
b2
b3
b4
b5
b6
b7
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
SCS
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
b0
SSO, SSI
b1
b2
b3
b4
b5
b6
b7
SCS
CPHS and CPOS: Bits in SSMR register, SSUMS: Bit in SSMR2 register
Figure 24.2
Association between Transfer Clock Polarity, Phase, and Transfer Data
REJ09B0458-0010 Rev.0.10
Page 364 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.3.2
24. Synchronous Serial Communication Unit (SSU)
SS Shift Register (SSTRSR)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
24.3.2.1
Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 24.3 shows the Association between Data I/O Pins and SSTRSR Register.
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
• SSUMS = 0
(clock synchronous communication mode)
SSTRSR register
SSO
SSTRSR register
SSI
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
SSTRSR register
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 1 (bidirectional mode)
SSTRSR register
SSI
Figure 24.3
Association between Data I/O Pins and SSTRSR Register
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SSO
SSO
SSI
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.3.3
24. Synchronous Serial Communication Unit (SSU)
Interrupt Requests
Synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive
data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial
communication unit interrupt vector table, determining interrupt sources by flags is required.
Table 24.3 lists the Synchronous Serial Communication Unit Interrupt Requests.
Table 24.3
Synchronous Serial Communication Unit Interrupt Requests
Interrupt Request
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
Abbreviation
TXI
TEI
RXI
OEI
CEI
Generation Condition
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation conditions in Table 24.3 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 by a synchronous serial communication unit interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.3.4
24. Synchronous Serial Communication Unit (SSU)
Communication Modes and Pin Functions
Synchronous serial communication unit switches the functions of the I/O pins in each communication mode
according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 24.4 lists the Association between Communication Modes and I/O Pins.
Table 24.4
Association between Communication Modes and I/O Pins
Communication Mode
Clock synchronous
communication mode
Bit Setting
SSUMS
BIDE
MSS
TE
0
Disabled 0
0
1
4-wire bus
communication mode
1
0
0
1
4-wire bus
1
(bidirectional)
communication mode (2)
1
0
1
RE
1
SSI
Input
− (1)
Input
Input
1
0
0
1
1
1
0
0
1
1
1
0
−
Output
0
1
1
Output
Input
1
0
0
1
1
−
Input
1
− (1)
Input
(1)
Pin State
SSO
− (1)
Output
Output
−
Output
(1)
Apr 01, 2008
Input
Input
Output
Output
Output
Input
Output
Input
− (1)
Input
Input
Input
Output
(1)
−
Output
(1)
Output
Input
Output
Input
0
− (1)
Output
Input
0
1
− (1)
Input
Output
1
0
− (1)
Output
Output
−
(1)
Notes:
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
REJ09B0458-0010 Rev.0.10
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SSCK
Input
Output
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.4
24. Synchronous Serial Communication Unit (SSU)
Clock Synchronous Communication Mode
24.4.1
Initialization in Clock Synchronous Communication Mode
Figure 24.4 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in the
SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or
reception.
Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format.
Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR
register.
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 0
SSMR2 register
SSMR register
CPHS bit ← 0
CPOS bit ← 0
Set MLS bit
SSCRH register
SCKS bit ← 1
Set SOOS bit
SSMR2 register
SSCRH register
Set bits CKS0 to CKS2
Set RSSTP bit
SSSR register
SSER register
Set MSS bit
ORER bit ← 0 (1)
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
Note:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 24.4
Initialization in Clock Synchronous Communication Mode
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.4.2
24. Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 24.5 shows an Example of Synchronous Serial Communication Unit Operation for Data Transmission
(Clock Synchronous Communication Mode). During data transmission, the synchronous serial communication
unit operates as described below.
When synchronous serial communication unit is set as a master device, it outputs a synchronous clock and data.
When synchronous serial communication unit is set as a slave device, it outputs data synchronized with the
input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)
and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 24.6 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at
odd numbers), CPOS = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
SSCK
SSO
b0
b1
b7
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b1
b7
1 frame
TEI interrupt request
generation
0
TXI interrupt request generation
0
Processing
by program
Figure 24.5
b0
Write data to SSTDR register
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
Example of Synchronous Serial Communication Unit Operation for Data
Transmission (Clock Synchronous Communication Mode)
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
Data
transmission
continues?
(2)
Yes
(2) Determine whether data transmission continues.
No
(3)
Read TEND bit in SSSR register
TEND = 1 ?
(3) When data transmission is completed, the TEND
bit is set to 1. Set the TEND bit to 0 and the TE bit
to 0 and complete transmit mode.
No
Yes
SSSR register
TEND bit ← 0 (1)
SSER register
TE bit ← 0
End
Note:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 24.6
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.4.3
24. Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 24.7 shows an Example of Synchronous Serial Communication Unit Operation for Data Reception
(Clock Synchronous Communication Mode).
During data reception, synchronous serial communication unit operates as described below. When the
synchronous serial communication unit is set as the master device, it outputs a synchronous clock and inputs
data. When synchronous serial communication unit is set as a slave device, it inputs data synchronized with the
input clock.
When synchronous serial communication unit is set as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Synchronous serial communication unit outputs a clock for receiving 8 bits of
data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to 0
(receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 24.8 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at
even edges), CPOS bit = 0 (“H” when clock stops), and BS3 to BS0 = 1000b (8 bits)
SSCK
b7
b0
SSI
b0
b7
1
RSSTP bit in
SSCRH register
1
Processing
by program
b7
1 frame
1 frame
RDRF bit in
SSSR register
b0
0
RXI interrupt request
generation
RXI interrupt request
generation
RXI interrupt request
generation
0
Dummy read in
SSRDR register
Read data in SSRDR
register
Set RSSTP bit to 1
Read data in
SSRDR register
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
SSUMS: Bit in SSMR2 register
Figure 24.7
Example of Synchronous Serial Communication Unit Operation for Data Reception
(Clock Synchronous Communication Mode)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
Start
Initialization
(1)
Dummy read of SSRDR register
(2)
Last data
received?
Yes
(1) After setting each register in the synchronous serial
communication unit register, a dummy read of the
SSRDR register is performed and the receive
operation is started.
(2) Determine whether it is the last 1 byte of data to be
received. If so, set to stop after the data is received.
No
Read ORER bit in SSSR register
Yes
(3)
(3) If a receive error occurs, perform error
(6) processing after reading the ORER bit. Then set
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
ORER = 1 ?
No
Read RDRF bit in SSSR register
(4)
No
(4) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
RDRF = 1 ?
Yes
Read receive data in SSRDR register
(5)
SSCRH register
RSSTP bit ← 1
(5) Before the last 1 byte of data is received, set the
RSSTP bit to 1 and stop after the data is
received.
Read ORER bit in SSSR register
ORER = 1 ?
(6)
Yes
No
Read RDRF in SSSR register
No
RDRF = 1 ?
(7)
Yes
SSCRH register
RSSTP bit ← 0
SSER register
RE bit ← 0
(7) Confirm that the RDRF bit is set to 1. When the
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
Overrun
error
processing
Read receive data in SSRDR register
End
Figure 24.8
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.4.3.1
24. Synchronous Serial Communication Unit (SSU)
Data Transmission/Reception
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (TE = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 24.9 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
(2)
Read RDRF bit in SSSR register
No
RDRF = 1 ?
(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
Yes
Read receive data in SSRDR register
(3)
Data
transmission (2)
continues?
Yes
(3) Determine whether the data transmission
continues
No
(4)
Read TEND bit in SSSR register
TEND = 1 ?
(4) When the data transmission is completed, the
TEND bit in the SSSR register is set to 1.
No
Yes
(5)
(6)
SSSR register
TEND bit ← 0 (1)
SSER register
RE bit ← 0
TE bit ← 0
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
receive mode.
End
Note:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 24.9
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Communication Mode)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.5
24. Synchronous Serial Communication Unit (SSU)
Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and
a chip select line is used for communication. This mode includes bidirectional mode in which the data input line
and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the
BIDE bit in the SSMR2 register. For details, refer to 24.3.2.1 Association between Data I/O Pins and SS Shift
Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in the
SSMR register. For details, refer to 24.3.1.1 Association between Transfer Clock Polarity, Phase, and Data.
When this MCU is set as the master device, the chip select line controls output. When synchronous serial
communication unit is set as a slave device, the chip select line controls input. When it is set as the master device,
the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the
CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as an
input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed
MSB-first.
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.5.1
24. Synchronous Serial Communication Unit (SSU)
Initialization in 4-Wire Bus Communication Mode
Figure 24.10 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the synchronous serial communication unit.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 1
SSMR2 register
(1)
SSMR register
Set bits CPHS and CPOS
MLS bits ← 0
SSCRH register
SSMR2 register
(2)
SSCRH register
SSSR register
SSER register
(1) The MLS bit is set to 0 for MSB-first transfer.
The clock polarity and phase are set by bits
CPHS and CPOS.
Set MSS bit
SCKS bit ← 1
Set bits SOOS, CSS0 to
CSS1, and BIDE
(2) Set the BIDE bit to 1 in bidirectional mode and
set the I/O of the SCS pin by bits CSS0 and
CSS1.
Set bits CKS0 to CKS2
Set RSSTP bit
ORER bit ← 0 (1)
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
Note:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 24.10
Initialization in 4-Wire Bus Communication Mode
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.5.2
24. Synchronous Serial Communication Unit (SSU)
Data Transmission
Figure 24.11 shows an Example of Synchronous Serial Communication Unit Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit operation, synchronous serial
communication unit operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”.
When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the
TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the
data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from
registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI
interrupt request is generated.
After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR
to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1,
TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set
to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests
enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is
held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the
SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in
high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 24.6
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
• CPHS bit = 0 (data change at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to
BS0 = 1000b (8 bits)
High-impedance
SCS
(output)
SSCK
b6
b7
SSO
b7
b0
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request is
generated
TXI interrupt request is
generated
0
Data write to SSTDR register
Processing
by program
• CPHS bit = 1 (data change at even edges). CPOS bit = 0 (“H” when clock stops), and BS3 to
BS0 = 1000b (8 bits)
High-impedance
SCS
(output)
SSCK
b7
SSO
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
b7
b6
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request is
generated
TXI interrupt request is
generated
0
Processing
by program
Data write to SSTDR register
BS0 to BS3: Bits in SSBR register
CPHS, CPOS: Bits in SSMR register
Figure 24.11
Example of Synchronous Serial Communication Unit Operation during Data
Transmission (4-Wire Bus Communication Mode)
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.5.3
24. Synchronous Serial Communication Unit (SSU)
Data Reception
Figure 24.12 shows an Example of Synchronous Serial Communication Unit Operation during Data Reception
(4-Wire Bus Communication Mode). During data reception, synchronous serial communication unit operates as
described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF
bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). Synchronous serial communication unit outputs a clock for receiving 8 bits of
data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to 0
(receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR register
is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 24.12 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some
point during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 24.8
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
The data transfer length can be set from 8 to 16 bits using the SSBR register.
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Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24. Synchronous Serial Communication Unit (SSU)
• CPHS bit = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3
to BS0 = 1000b (8 bits)
High-impedance
SCS
(output)
SSCK
b7
SSI
b7
b0
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
b7
b0
b0
1 frame
0
RXI interrupt request
is generated
RXI interrupt request
is generated
0
Dummy read in
SSRDR register
Processing
by program
Data read in SSRDR
register
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
• CPHS bit = 1 (data download at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to
BS0 = 1000b (8 bits)
High-impedance
SCS
(output)
SSCK
b7
SSI
b0
b7
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
Processing
by program
b0
b7
b0
1 frame
0
RXI interrupt request
is generated
RXI interrupt request
is generated
0
Dummy read in
SSRDR register
Data read in SSRDR
register
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
BS0 to BS3: Bits in SSBR register
CPHS and CPOS: Bits in SSMR register
Figure 24.12
Example of Synchronous Serial Communication Unit Operation during Data
Reception (4-Wire Bus Communication Mode)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.5.4
24. Synchronous Serial Communication Unit (SSU)
SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If synchronous serial
communication unit detects that the synchronized internal SCS signal is held “L” in this period, the CE bit in
the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 24.13 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
SCS input
Internal SCS
(synchronization)
MSS bit in
SSCRH register
1
0
Transfer start
Data write to
SSTDR register
CE
High-impedance
SCS output
Maximum time of SCS internal
synchronization
During arbitration detection
Figure 24.13
Arbitration Check Timing
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
24.6
24. Synchronous Serial Communication Unit (SSU)
Notes on Synchronous Serial Communication Unit
Set the IICSEL bit in the SSUIICSR register to 0 (select SSU function) to use the synchronous serial
communication unit function.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25. I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips
I2C bus.
25.1
Overview
Table 25.1 lists the I2C bus Interface Specifications, Figure 25.1 shows an I2C bus interface Block Diagram, and
Figure 25.2 shows the External Circuit Connection Example of Pins SCL and SDA, Table 25.2 lists the Pin
Configuration of I2C bus Interface.
* I2C bus is a trademark of Koninklijke Philips Electronics N. V.
Table 25.1
I2C bus Interface Specifications
Item
Specification
Communication formats • I2C bus format
- Selectable as master/slave device.
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent.)
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of the acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open-drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent.)
I/O pins
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks
• When the MST bit in the ICCR1 register is set to 0.
External clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1.
Internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next unit
of data is received while the RDRF bit in the ICSR register is set to 1 (data in
the ICDRR register), the AL bit is set to 1.
2
Interrupt sources
• I C bus format .................................. 6 sources (1)
Transmit data empty (including when slave address matches), end of
transmission, receive data full (including when slave address matches),
arbitration lost, NACK detection, and stop condition detection
• Clock synchronous serial format ...... 4 sources (1)
Transmit data empty, end of transmission, receive data full, and overrun error
2
Selectable functions
• I C bus format
- Selectable output level for the acknowledge signal during reception.
• Clock synchronous serial format
- MSB-first or LSB-first selectable as the data transfer direction.
Note:
1. All sources use one interrupt vector for I2C bus interface.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
f1
Transfer clock
generation
circuit
SCL
Output
control
ICCR1 register
Transmit/receive
control circuit
Noise
canceller
ICCR2 register
ICMR register
ICDRT register
SAR register
Output
control
ICDRS register
Noise
canceller
Address comparison
circuit
Data bus
SDA
ICDRR register
Bus state
check circuit
Arbitration
check circuit
ICSR register
ICIER register
Interrupt generation
circuit
Interrupt request
(TXI, TEI, RXI, STPI, NAKI)
Figure 25.1
Table 25.2
I2C bus interface Block Diagram
Pin Configuration of I2C bus Interface
Pin Name
SCL
SDA
Assigned Pin
P3_5
P3_7
REJ09B0458-0010 Rev.0.10
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Function
Clock I/O pin
Data I/O pin
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
VCC
VCC
SCL
SCL
SDA
SDA
SCL input
SCL output
SDA input
SDA output
SCL
(Master)
SCL
SCL input
SCL input
SCL output
SCL output
SDA
SDA input
SDA output
SDA output
(Slave 1)
Figure 25.2
SDA
SDA input
(Slave 2)
External Circuit Connection Example of Pins SCL and SDA
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2
25.2.1
Registers
Module Standby Control Register (MSTCR)
Address 0008h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
b4
b3
MSTTRC MSTTRD MSTIIC
0
0
0
b2
—
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
0: Active
MSTIIC SSU, I2C bus standby bit
1: Standby (1)
MSTTRD Peripheral function power consumption
Set to 1.
reduce bit
The power consumption of the peripheral
functions can be reduced.
MSTTRC Timer RC standby bit
0: Active
1: Standby (2)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
R/W
—
R/W
R/W
R/W
—
Notes:
1. When the MSTIIC bit is set to 1 (standby), any access to the SSU or the I2C bus associated registers (addresses
0193h to 019Dh) is disabled.
2. When the MSTTRC bit is set to 1 (standby), any access to the timer RC associated registers (addresses 0120h
to 0133h) is disabled.
25.2.2
SSU/IIC Pin Select Register (SSUIICSR)
Address 018Ch
Bit
b7
Symbol
—
After Reset
0
Bit
b0
Symbol
IICSEL
b1
b2
b3
b4
b5
b6
b7
—
—
—
—
—
—
—
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b1
—
0
b0
IICSEL
0
Function
0: SSU function selected
1: I2C bus function selected
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
R/W
—
Reserved bits
R/W
SSU/I2C
REJ09B0458-0010 Rev.0.10
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Bit Name
bus switch bit
b2
—
0
Apr 01, 2008
Set to 0.
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.3
IIC bus Transmit Data Register (ICDRT)
Address 0194h
Bit
b7
Symbol
—
After Reset
1
Bit
b7 to b0
25.2.4
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Function
This register stores transmit data.
When the ICDRS register is detected as empty, the stored transmit data item is transferred to the
ICDRS register and data transmission starts.
When the next unit of transmit data is written to the ICDRT register while data is transmitted to the
ICDRS register, continuous transmission is enabled.
When the MLS bit in the ICMR register is set to 1 (data transfer with LSB-first), the MSB-LSB
inverted data is read after the data is written to the ICDRT register.
R/W
R/W
IIC bus Receive Data Register (ICDRR)
Address 0196h
Bit
b7
Symbol
—
After Reset
1
Bit
b7 to b0
b6
—
1
b6
—
1
b5
—
1
b4
—
1
b3
—
1
b2
—
1
b1
—
1
b0
—
1
Function
This register stores receive data.
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
REJ09B0458-0010 Rev.0.10
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R/W
R
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.5
IIC bus Control Register 1 (ICCR1)
Address 0198h
Bit
b7
Symbol
ICE
After Reset
0
Bit
b0
b1
b2
b3
b6
RCVD
0
b5
MST
0
b4
TRS
0
Symbol
Bit Name
CKS0 Transmit clock select bits 3 to 0 (1)
CKS1
CKS2
CKS3
b4
b5
TRS
MST
b6
RCVD
b7
ICE
Transfer/receive select bit (2, 3, 6)
Master/slave select bit (5, 6)
Receive disable bit
I2C bus interface enable bit
b3
CKS3
0
b2
CKS2
0
b1
CKS1
0
b0
CKS0
0
Function
b3 b2 b1 b0
0 0 0 0: f1/28
0 0 0 1: f1/40
0 0 1 0: f1/48
0 0 1 1: f1/64
0 1 0 0: f1/80
0 1 0 1: f1/100
0 1 1 0: f1/112
0 1 1 1: f1/128
1 0 0 0: f1/56
1 0 0 1: f1/80
1 0 1 0: f1/96
1 0 1 1: f1/128
1 1 0 0: f1/160
1 1 0 1: f1/200
1 1 1 0: f1/224
1 1 1 1: f1/256
b5 b4
0 0: Slave Receive Mode (4)
0 1: Slave Transmit Mode
1 0: Master Receive Mode
1 1: Master Transmit Mode
After reading the ICDRR register while the TRS bit is
set to 0
0: Next receive operation continues
1: Next receive operation disabled
0: This module is halted
(Pins SCL and SDA are set to a port function)
1: This module is enabled for transfer operations
(Pins SCL and SDA are in a bus drive state)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Set according to the necessary transfer rate in master mode. Refer to Table 25.3 Transfer Rate Examples for
the transfer rate. This bit is used for maintaining the setup time in transmit mode of slave mode. The time is
10Tcyc when the CKS3 bit is set to 0 and 20Tcyc when the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
2. Rewrite the TRS bit between transfer frames.
3. When the first 7 bits after the start condition in slave receive mode match the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
4. In master mode with the I2C bus format, if arbitration is lost, bits MST and TRS are set to 0 and the IIC enters
slave receive mode.
5. When an overrun error occurs in master receive mode with the clock synchronous serial format, the MST bit is
set to 0 and the I2C bus enters slave receive mode.
6. In multimaster operation, use the MOV instruction to set bits TRS and MST.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.6
IIC bus Control Register 2 (ICCR2)
Address 0199h
Bit
b7
Symbol BBSY
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
SCP
1
b5
SDAO
1
b4
SDAOP
1
b3
SCLO
1
b2
—
1
b1
IICRST
0
b0
—
1
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
IICRST I2C bus control block reset bit When hang-up occurs due to communication failure during
I2C bus interface operation, writing 1 resets the control
block of the I2C bus interface without setting ports or
initializing registers.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SCLO SCL monitor flag
0: SCL pin is set to “L”
1: SCL pin is set to “H”
SDAOP SDAO write protect bit
When rewriting the SDAO bit, write 0 simultaneously (1).
When read, the content is 1.
SDAO SDA output value control bit
When read
0: SDA pin output is held “L”
1: SDA pin output is held “H”
When written (1, 2)
0: SDA pin output is changed to “L”
1: SDA pin output is changed to high-impedance
(“H” output via external pull-up resistor)
SCP
Start/stop condition generation When writing to the to BBSY bit, write 0 simultaneously (3).
disable bit
When read, the content is 1.
Writing 1 is invalid.
BBSY Bus busy bit (4)
When read:
0: Bus is released
(SDA signal changes from “L” to “H”
while SCL signal is held “H”)
1: Bus is occupied
(SDA signal changes from “H” to “L”
while SCL signal is held “H”)
When written (3):
0: Stop condition generated
1: Start condition generated
R/W
—
R/W
—
R
R/W
R/W
R/W
R/W
Notes:
1. When rewriting the SDAO bit, write 0 to the SDAOP bit simultaneously using the MOV instruction.
2. Do not write to the SDAO bit during a transfer operation.
3. Enabled in master mode. When writing to the BBSY bit, write 0 to the SCP bit simultaneously using the MOV
instruction. Execute the same way when a start condition is regenerated.
4. Disabled when the clock synchronous serial format is used.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.7
IIC bus Mode Register (ICMR)
Address 019Ah
Bit
b7
Symbol
MLS
After Reset
0
Bit
b0
b1
b2
b6
WAIT
0
Symbol
Bit Name
BC0
Bit counters 2 to 0
BC1
BC2
b5
—
0
b4
—
1
b3
BCWP
1
b2
BC2
0
b1
BC1
0
b0
BC0
0
Function
I2C bus format
(Read: Number of remaining transfer bits;
Write: Number of next transfer data bits) (1, 2).
R/W
R/W
R/W
R/W
b2 b1 b0
0 0 0: 9 bits (3)
0 0 1: 2 bits
0 1 0: 3 bits
0 1 1: 4 bits
1 0 0: 5 bits
1 0 1: 6 bits
1 1 0: 7 bits
1 1 1: 8 bits
Clock synchronous serial format
(Read: Number of remaining transfer bits;
Write: Always 000b).
b2 b1 b0
b3
BCWP
b4
b5
b6
—
—
WAIT
b7
MLS
0 0 0: 8 bits
0 0 1: 1 bit
0 1 0: 2 bits
0 1 1: 3 bits
1 0 0: 4 bits
1 0 1: 5 bits
1 1 0: 6 bits
1 1 1: 7 bits
BC write protect bit
When rewriting bits BC0 to BC2, write 0 simultaneously (2, 4).
When read, the content is 1.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Reserved bit
Set to 0.
0: No wait states
Wait insertion bit (5)
(Data and the acknowledge bit are transferred consecutively)
1: Wait state
(After the clock of the last data bit falls, a “L” period is
extended for two transfer clocks)
MSB-first/LSB-first
0: Data transfer with MSB-first (6)
select bit
1: Data transfer with LSB-first
R/W
—
R/W
R/W
R/W
Notes:
1. Rewrite between transfer frames. When writing values other than 000b, write when the SCL signal is “L”.
2. When writing to bits BC0 to BC2, write 0 to the BCWP bit simultaneously using the MOV instruction.
3. After data including the acknowledge bit is transferred, these bits are automatically set to 000b. When a start
condition is detected, these bits are automatically set to 000b.
4. Do not rewrite when the clock synchronous serial format is used.
5. The setting value is valid in master mode with the I2C bus format. It is invalid in slave mode with the I2C bus
format or when the clock synchronous serial format is used.
6. Set to 0 when the I2C bus format is used.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.8
IIC bus Interrupt Enable Register (ICIER)
Address 019Bh
Bit
b7
Symbol
TIE
After Reset
0
Bit
b0
b1
b6
TEIE
0
b5
RIE
0
Symbol
Bit Name
ACKBT Transmit acknowledge
select bit
ACKBR Receive acknowledge bit
b2
ACKE
Acknowledge bit detection
select bit
b3
STIE
b4
NAKIE
Stop condition detection
interrupt enable bit
NACK receive interrupt
enable bit
b5
RIE
Receive interrupt enable bit
b6
TEIE
b7
TIE
Transmit end interrupt
enable bit
Transmit interrupt enable bit
b4
NAKIE
0
b3
STIE
0
b2
ACKE
0
b1
ACKBR
0
b0
ACKBT
0
Function
0: In receive mode, 0 is transmitted as the acknowledge bit.
1: In receive mode, 1 is transmitted as the acknowledge bit.
0: In transmit mode, the acknowledge bit received from
receive device is set to 0.
1: In transmit mode, the acknowledge bit received from
receive device is set to 1.
0: Content of the receive acknowledge bit is ignored and
continuous transfer is performed.
1: When the receive acknowledge bit is set to 1,
continuous transfer is halted.
0: Stop condition detection interrupt request disabled
1: Stop condition detection interrupt request enabled (2)
0: NACK receive interrupt request and arbitration lost/
overrun error interrupt request disabled
1: NACK receive interrupt request and arbitration lost/
overrun error interrupt request (1)
0: Receive data full and overrun error interrupt request
disabled
1: Receive data full and overrun error interrupt request
enabled (1)
0: Transmit end interrupt request disabled
1: Transmit end interrupt request enabled
0: Transmit data empty interrupt request disabled
1: Transmit data empty interrupt request enabled
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. An overrun error interrupt request is generated when the clock synchronous format is used.
2. Set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit in the ICSR register
is set to 0.
REJ09B0458-0010 Rev.0.10
Page 391 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.9
IIC bus Status Register (ICSR)
Address 019Ch
Bit
b7
Symbol TDRE
After Reset
0
Bit
b0
b1
AL
b3
STOP
b5
b5
RDRF
0
b4
NACKF
0
Symbol
Bit Name
ADZ
General call address
recognition flag (1, 2)
AAS
Slave address
recognition flag (1)
b2
b4
b6
TEND
0
Arbitration lost flag/overrun
error flag (1)
Stop condition detection flag (1)
NACKF No acknowledge
detection flag (1, 4)
RDRF Receive data register full flag
(1, 5)
b6
TEND
Transmit end flag (1, 6)
b7
TDRE
Transmit data empty flag (1, 6)
b3
STOP
X
b2
AL
0
b1
AAS
0
b0
ADZ
0
Function
This flag is set to 1 when a general call address is
detected.
This flag is set to 1 when the first frame immediately after
the start condition matches bits SVA0 to SVA6 in the SAR
register in slave receive mode (slave address detection
and general call address detection)
I2C bus format:
This flag indicates that arbitration has been lost
in master mode.
This flag is set to 1 (3) when:
• The internal SDA signal and SDA pin level do not
match at the rising edge of the SCL signal in master
transmit mode
• The SDA pin is held “H” at start condition detection in
master transmit/receive mode
Clock synchronous format:
This flag indicates an overrun error.
This flag is set to 1 when:
• The last bit of the next unit of data is received
while the RDRF bit is set to 1
This flag is set to 1 when a stop condition is detected
after the frame is transferred.
This flag is set to 1 when no ACKnowledge is detected
from the receive device after transmission.
This flag is set to 1 when receive data is transferred from
registers ICDRS to ICDRR.
I2C bus format:
This flag is set to 1 at the rising edge of the 9th clock cycle
of the SCL signal while the TDRE bit is set to 1.
Clock synchronous format:
This flag is set to 1 when the last bit of the transmit frame
is transmitted.
This flag is set to 1 when:
• Data is transferred from registers ICDRT to ICDRS and
the CDRT register is empty
• The TRS bit in the ICCR1 register is set to 1 (transmit
mode)
• A start condition is generated (including retransmission)
• Slave receive mode is changed to slave transmit mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Each bit is set to 0 by reading 1 before writing 0.
2. This flag is enabled in slave receive mode with the I2C bus format.
3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface
monitors the SDA pin and the data which the I2C bus Interface transmits is different, the AL flag is set to 1 and
the bus is occupied by another master.
4. The NACKF bit is enabled when the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit
is set to 1, transfer is halted).
5. The RDRF bit is set to 0 when data is read from the ICDRR register.
6. Bits TEND and TDRE are set to 0 when data is written to the ICDRT register.
When accessing the ICSR register continuously, insert one or more NOP instructions between the instructions
to access it.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.2.10 Slave Address Register (SAR)
Address 019Dh
Bit
b7
Symbol SVA6
After Reset
0
Bit
b0
b6
SVA5
0
b5
SVA4
0
b4
SVA3
0
Symbol
Bit Name
FS
Format select bit
b1
b2
b3
b4
b5
b6
b7
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
b3
SVA2
0
b2
SVA1
0
b1
SVA0
0
b0
FS
0
Function
0: I2C bus format
1: Clock synchronous serial format
Set an address different from that of the other slave
devices connected to the I2C bus.
When the 7 high-order bits of the first frame
transmitted after the start condition match bits
SVA0 to SVA6 in slave mode of the I2C bus format,
the MCU operates as a slave device.
Slave addresses 6 to 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
25.2.11 IIC bus Shift Register (ICDRS)
Bit
Symbol
Bit
b7 to b0
b7
—
b6
—
b5
—
b4
—
b3
—
b2
—
b1
—
b0
—
Function
This register transmits and receives data.
During transmission, data is transferred from registers ICRDT to ICDRS and transmitted from the
SDA pin.
During reception, data is transferred from registers ICDRS to the ICDRR after 1 byte of data
reception ends.
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R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.3
Common Items for Multiple Modes
25.3.1
Transfer Clock
When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL
pin.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits CKS0
to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.
Table 25.3 lists the Transfer Rate Examples.
Table 25.3
Transfer Rate Examples
ICCR1 Register
Transfer
Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz
0
0
0
0
f1/28
179 kHz
286 kHz
357 kHz
571 kHz
714 kHz
1
f1/40
125 kHz
200 kHz
250 kHz
400 kHz
500 kHz
1
0
f1/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz
1
f1/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
1
0
0
f1/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
f1/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
1
0
f1/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
f1/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
1
0
0
0
f1/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
f1/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
0
f1/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
f1/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
1
0
0
f1/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
f1/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
1
0
f1/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
f1/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.3.2
Interrupt Requests
I 2C
The
bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests when
the clock synchronous serial format is used.
Table 25.4 lists the Interrupt Requests of I2C bus Interface.
Because these interrupt requests are allocated at the I2C bus interface interrupt vector table, the source must be
determined bit by bit.
Table 25.4
Interrupt Requests of I2C bus Interface
Format
Interrupt Request
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
Generation Condition
TXI
TEI
RXI
STPI
NAKI
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1
(or NAKIE = 1 and NACKF = 1)
I2C bus
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Clock
Synchronous
Serial
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When generation conditions listed in Table 25.4 are met, an I2C bus interface interrupt request is generated. Set
the interrupt generation conditions to 0 by the I2C bus interface interrupt routine.
Note that bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and
that the RDRF bit is automatically set to 0 by reading the ICDRR register. Especially, the TDRE bit is set to 0
when writing transmit data to the ICDRT register and set to 1 when transferring data from the ICDRT register to
the ICDRS register. If the TDRE bit is further set to 0, additional 1 byte may be transmitted.
Also, set the STIE bit to 1 (stop condition detection interrupt request enabled) when the STOP bit is set to 0.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
I2C bus Interface Mode
25.4
I2C bus Format
25.4.1
When the FS bit in the SAR register is set to 0, the I2C bus format is used for communication.
Figure 25.3 shows the I2C bus Format and Bus Timing. The first frame following the start condition consists of
8 bits.
(1) I2C bus format
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
Number of transfer bits (n = 1 to 8)
1
m
Number of transfer frames (m = 1 or more)
(b) I2C bus format When Start Condition is Retransmitted (FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
1
m1
m2
Upper: Number of transfer bits (n1, n2 = 1 to 8)
Lower: Number of transfer frames (m1, m2 = 1 or more)
(2) I2C bus timing
SDA
SCL
1 to 7
8
9
1 to 7
8
9
S
SLA
R/W
A
DATA
A
Legend:
S
: Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmission/reception
Data is transmitted when:
R/W value is 1: From the slave device to the master device
R/W value is 0: From the master device to the slave device
A
: Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit/receive data
P
: Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
Figure 25.3
I2C bus Format and Bus Timing
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1 to 7
8
DATA
9
A
P
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.4.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 25.4 and 25.5 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 for initialization, and set the ICE bit in the ICCR1 register to 1
(transfer operation enabled). Then, set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in
the ICCR1 register (initial setting).
(2) After confirming that the bus is released by reading the BBSY bit in the ICCR2 register, set bits TRS and
MST in the ICCR1 register to master transmit mode. Then, write 1 to the BBSY bit and 0 to the SCP bit
with the MOV instruction (start condition generated). This will generate a start condition.
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers ICDRT
to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W are indicated
in the 1st byte). At this time, the TDRE bit is automatically set to 0. When data is transferred from registers
ICDRT to ICDRS, the TDRE bit is set to 1 again.
(4) When 1 byte of data transmission is completed while the TDRE bit is set to 1, the TEND bit in the ICSR
register is set to 1 at the rising edge of the 9th clock cycle of the transmit clock. After confirming that the
slave device is selected by reading the ACKBR bit in the ICIER register, write the 2nd byte of data to the
ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to 1, generate a
stop condition. Stop condition generation is enabled by writing 0 to the BBSY bit and 0 to the SCP bit with
the MOV instruction. The SCL signal is fixed “L” until data is ready or a stop condition is generated.
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When the number of bytes to be transmitted is written to the ICDRT register, wait until the TEND bit is set
to 1 while the TDRE bit is set to 1. Or wait for NACK (NACKF bit in ICSR register = 1) from the receive
device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1,
transfer is halted). Then, generate a stop condition before setting the TEND bit or the NACKF bit to 0.
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
SCL
(master output)
1
2
3
4
5
6
7
8
SDA
(master output)
b7
b6
b5
b4
b3
b2
b1
b0
Slave address
9
2
b7
b6
R/W
SDA
(slave output)
TDRE bit in
ICSR register
1
A
1
0
TEND bit in
ICSR register
1
0
ICDRT register
Address + R/W
Address + R/W
ICDRS register
Program processing (2) Instruction for
start condition
generation
Figure 25.4
Data 1
(3) Write data to ICDRT register
(1st byte).
Data 2
Data 1
(4) Write data to ICDRT register
(2nd byte).
(5) Write data to ICDRT register
(3rd byte).
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)
SCL
(master output)
9
SDA
(master output)
SDA
(slave output)
TDRE bit in
ICSR register
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
A
9
A/A
1
0
TEND bit in
ICSR register
1
0
ICDRT register
Data n
ICDRS register
Program processing
Figure 25.5
Data n
(3) Write data to ICDRT register.
(6) Generate a stop condition
and set TEND bit to 0.
(7) Set to slave receive mode.
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)
REJ09B0458-0010 Rev.0.10
Page 398 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 25.6 and 25.7 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch
from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0.
(2) Dummy reading the ICDRR register starts receive operation. The receive clock is output in synchronization
with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in
the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock.
(3) When 1-frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising
edge of the 9th clock cycle of the receive clock. At this time, if the ICDRR register is read, the received
data can be read and the RDRF bit is set to 0 simultaneously.
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1.
If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF
bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (next receive
operation disabled) before reading the ICDRR register, stop condition generation is enabled after the next
receive operation.
(6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next
receive operation continues).
(8) Return to slave receive mode.
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Master transmit mode
SCL
(master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
1
A
SDA
(slave output)
TDRE bit in
ICSR register
9
A
b7
b6
b5
b4
b3
b2
b1
b0
b7
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
RDRF bit in
ICSR register
1
0
1
0
ICDRS register
Data 1
ICDRR register
Data 1
Program processing
Figure 25.6
(1) After setting bits TEND and TRS to 0,
set TDRE bit to 0.
(2) Read ICDRR register.
(3) Read ICDRR register.
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
SCL
(master output)
9
SDA
(master output)
A
1
RCVD bit in
ICCR1 register
3
4
5
6
7
8
9
A/A
SDA
(slave output)
RDRF bit in
ICSR register
2
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
Data n-1
ICDRS register
Data n
Data n-1
ICDRR register
Program processing
(5) Read ICDRR register
after setting RCVD bit to 1.
Data n
(6) Generate a stop condition.
(7) Set RCVD bit to 0
after reading ICDRR register.
(8) Set to slave receive mode.
Figure 25.7
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.4.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 25.8 and 25.9 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled), and set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Then, set bits TRS and MST
in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the first frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to
1, and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after the last transmit data is written to the ICDRT
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) Set the TRS bit to 0 and dummy read the ICDRR register to end the process. This will release the SCL
signal.
(5) Set the TDRE bit to 0.
REJ09B0458-0010 Rev.0.10
Page 402 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Slave receive mode
Slave transmit mode
SCL
(master output)
9
1
2
3
4
5
6
7
8
SDA
(master output)
9
1
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
A
b6
b7
b5
b4
b3
b2
b1
b0
b7
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
1
0
ICDRT register
Data 1
ICDRS register
Data 3
Data 2
Data 1
Data 2
ICDRR register
Program Processing
Figure 25.8
(1) Write data to ICDRT register
(data 1).
(2) Write data to ICDRT register
(data 2).
(2) Write Data to ICDRT register
(data 3).
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
REJ09B0458-0010 Rev.0.10
Page 403 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Slave receive
mode
Slave transmit mode
SCL
(master output)
9
SDA
(master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
b7
b6
b5
b4
b3
b2
b1
b0
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
1
0
ICDRT register
Data n
ICDRS register
Data n
ICDRR register
Program processing
Figure 25.9
(3) Set TEND bit to 0.
(4) Dummy read ICDRR register
after setting TRS bit to 0.
(5) Set TDRE bit to 0.
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 25.10 and 25.11 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled), and set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Then, set bits TRS and MST
in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the first frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, dummy read the ICDRR
register (the read data is unnecessary because it indicates the slave address and R/W).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the
acknowledge signal returned to the master device before reading the ICDRR register takes affect from the
following transfer frame.
(4) Reading the last byte is also performed by reading the ICDRR register.
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
SCL
(master output)
9
1
SDA
(master output)
2
3
b6
b7
4
5
b4
b5
6
7
b2
b3
8
9
b7
b0
b1
1
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Program processing
Figure 25.10
Data 1
(2) Read ICDRR register.
(2) Dummy read ICDRR register.
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1)
SCL
(master output)
1
9
SDA
(master output)
b7
2
3
b6
b5
4
b4
5
b3
6
b2
7
b1
8
9
b0
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Program processing
Figure 25.11
Data 1
(3) Set ACKBT bit to 1.
(3) Read ICDRR register.
(4) Read ICDRR register.
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2)
REJ09B0458-0010 Rev.0.10
Page 406 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.5
Clock Synchronous Serial Mode
25.5.1
Clock Synchronous Serial Format
When the FS bit in the SAR register is set to 1, the clock synchronous serial format is used for communication.
Figure 25.12 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin. When the
MST bit is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during transfer standby.
SCL
SDA
Figure 25.12
b0
b1
b2
b3
b4
b5
Transfer Format of Clock Synchronous Serial Format
REJ09B0458-0010 Rev.0.10
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b6
b7
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.5.2
Transmit Operation
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 25.13 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the
ICCR1 register and the MST bit (initial setting).
(2) Set the TRS bit in the ICCR1 register to 1 to select transmit mode. This will set the TDRE bit in the ICSR
register is to 1.
(3) After confirming that the TDRE bit is set to 1, write transmit data to the ICDRT register. Data is transferred
from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1. Continuous transmission is
enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. To switch from transmit
to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SCL
1
SDA
(output)
TRS bit in
ICCR1 register
TDRE bit in
ICSR register
b0
2
b1
7
b6
8
b7
1
b0
7
b6
8
1
b7
b0
1
0
1
0
ICDRT register
ICDRS register
Program processing
Data 2
Data 1
Data 1
(3) Write data to
ICDRT register.
Data 3
Data 3
Data 2
(3) Write data to
ICDRT register.
(3) Write data to
ICDRT register.
(3) Write data to
ICDRT register.
(2) Set TRS bit to 1.
Figure 25.13
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.5.3
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 25.14 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits CKS0 to CKS3 in the
ICCR1 register and the MST bit (initial setting).
(2) Set the MST bit to 1 while the transfer clock is being output. This will start the output of the receive clock.
(3) When the receive operation is completed, data is transferred from registers ICDRS to ICDRR and the
RDRF bit in the ICSR register is set to 1. When the MST bit is set to 1, the clock is output continuously
since the next byte of data is enabled for reception. Continuous reception is enabled by reading the ICDRR
register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, an
overrun is detected and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (next receive operation disabled)
and read the ICDRR register. The SCL signal is fixed “H” after the following byte of data reception is
completed.
SCL
1
SDA
(input)
b0
MST bit in
ICCR1 register
TRS bit in
ICCR1 register
2
b1
7
b6
8
b7
1
b0
7
b6
8
1
b7
2
b0
1
0
1
0
1
RDRF bit in
ICSR register
0
Data 1
ICDRS register
Data 1
ICDRR register
Program processing
Figure 25.14
Data 2
(2) Set MST bit to 1
(when transfer clock is output).
(3) Read ICDRR register.
Data 3
Data 2
(3) Read ICDRR register.
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.6
Examples of Register Setting
Figures 25.15 to 25.18 show Examples of Register Setting When Using I2C bus interface.
Start
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
• Set the MSTIIC bit in the MSTCR register to 0.
Initial setting
(1) Determine the state of the SCL and SDA lines.
Read BBSY bit in ICCR2 register
(2) Set to master transmit mode.
(1)
No
BBSY = 0?
(3) Generate a start condition.
Yes
(4) Set the transmit data of the 1st byte
(slave address + R/W).
ICCR1 register
ICCR2 register
TRS bit ← 1
MST bit ← 1
(2)
(5) Wait until 1 byte of data is transmitted.
SCP bit ← 0
BBSY bit ← 1
(3)
(6) Determine the ACKBR bit from the specified
slave device.
(4)
(7) Set the transmit data after 2nd byte
(except the last byte).
Write transmit data to ICDRT register
(8) Wait until the ICRDT register is empty.
Read TEND bit in ICSR register
(9) Set the transmit data of the last byte.
(5)
No
(10) Wait for end of transmission of the last byte.
TEND = 1?
(11) Set the TEND bit to 0.
Yes
Read ACKBR bit in ICIER register
ACKBR = 0?
No
(12) Set the STOP bit to 0.
(6)
(14) Wait until a stop condition is generated.
(15) Set to slave receive mode.
Set the TDRE bit to 0.
Yes
Transmit
mode?
(13) Generate a stop condition.
No
Master receive mode
Yes
Write transmit data to ICDRT register
(7)
Read TDRE bit in ICSR register
(8)
No
TDRE = 1?
Yes
No
Last byte?
(9)
Yes
Write transmit data to ICDRT register
Read TEND bit in ICSR register
(10)
No
TEND = 1?
Yes
ICSR register
TEND bit ← 0
(11)
ICSR register
STOP bit ← 0
(12)
ICCR2 register
SCP bit ← 0
BBSY bit ← 0
(13)
Read STOP bit in ICSR register
(14)
No
STOP = 1?
Yes
ICCR1 register
TRS bit ← 0
MST bit ← 0
(15)
ICSR register
TDRE bit ← 0
End
Figure 25.15
Register Setting Example in Master Transmit Mode (I2C bus Interface Mode)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Master receive mode
TEND bit ← 0
ICSR register
TRS bit ← 0
ICCR1 register
ICSR register
TDRE bit ← 0
ICIER register
ACKBT bit ← 0
Dummy read in ICDRR register
(1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0. (1,2)
(1)
(2) Set the ACKBT bit to the transmit device.
(1)
(3) Dummy read the ICDRR register. (1)
(2)
(3)
(4) Wait until 1 byte is received.
(5) Determine (last receive - 1).
(6) Read the receive data.
(7) Set the ACKBT bit of the last byte and set continuous
receive operation to disable (RCVD = 1). (2)
Read RDRF bit in ICSR register
(4)
No
(8) Read the receive data of (last byte - 1).
RDRF = 1?
(9) Wait until the last byte is received.
Yes
(10) Set the STOP bit to 0.
Yes
Last receive - 1?
(5)
(12) Wait until a stop condition is generated.
No
Read ICDRR register
(11) Generate a stop condition.
(6)
(13) Read the receive data of the last byte.
(14) Set the RCVD bit to 0.
ACKBT bit ← 1
ICIER register
(15) Set to slave receive mode.
(7)
ICCR1 register
RCVD bit ← 1
Read ICDRR register
(8)
Read RDRF bit in ICSR register
No
(9)
RDRF = 1?
Yes
STOP bit ← 0
ICSR register
SCP bit ← 0
BBSY bit ← 0
ICCR2 register
(10)
(11)
Read STOP bit in ICSR register
(12)
No
STOP = 1?
Yes
Read ICDRR register
(13)
ICCR1 register
RCVD bit ← 0
(14)
ICCR1 register
MST bit ← 0
(15)
End
Notes:
1. Do not generate interrupts while processing steps (1) to (3).
2. For 1 byte of data reception, skip steps (2) to (6) after step (1) and jump to process step (7).
Process step (8) is a dummy read from the ICDRR register.
Figure 25.16
Register Setting Example in Master Receive Mode (I2C bus Interface Mode)
REJ09B0458-0010 Rev.0.10
Page 411 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Slave transmit mode
AAS bit ← 0
ICSR register
(1) Set the AAS bit to 0.
(1)
(2) Set the transmit data (except the last byte).
Write transmit data to ICDRT register
(2)
(3) Wait until the ICRDT register is empty.
(4) Set the transmit data of the last byte.
Read TDRE bit in ICSR register
(5) Wait until the last byte is transmitted.
No
TDRE = 1?
(3)
(7) Set to slave receive mode.
Yes
No
(6) Set the TEND bit to 0.
(8) Dummy read the ICDRR register to release
the SCL signal.
Last byte?
(4)
Yes
(9) Set the TDRE bit to 0.
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
ICSR register
TEND = 1?
Yes
TEND bit ← 0
(6)
TRS bit ← 0
(7)
ICCR1 register
Dummy read ICDRR register
ICSR register
(5)
TDRE bit ← 0
(8)
(9)
End
Figure 25.17
Register Setting Example in Slave Transmit Mode (I2C bus Interface Mode)
REJ09B0458-0010 Rev.0.10
Page 412 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
Slave receive mode
AAS bit ← 0
(1)
ICIER register ACKBT bit ← 0
(2)
ICSR register
(1) Set the AAS bit to 0.
(1)
(2) Set the ACKBT bit to the transmit device.
(3) Dummy read the ICDRR register.
Dummy read ICDRR register
(3)
(4) Wait until 1 byte is received.
(5) Determine (last receive - 1).
Read RDRF bit in ICSR register
(6) Read the receive data.
(4)
No
(7) Set the ACKBT bit of the last byte. (1)
RDRF = 1?
(8) Read the receive data of (last byte - 1).
Yes
(9) Wait until the last byte is received.
Yes
Last receive - 1?
(5)
(10) Read the receive data of the last byte.
No
Read ICDRR register
ICIER register
ACKBT bit ← 1
Read ICDRR register
(6)
(7)
(8)
Read RDRF bit in ICSR register
No
(9)
RDRF = 1?
Yes
Read ICDRR register
(10)
End
Note:
1. For 1 byte of data reception, skip steps (2) to (6) after (1) and jump to process step (7).
Process step (8) is a dummy read from the ICDRR register.
Figure 25.18
Register Setting Example in Slave Receive Mode (I2C bus Interface Mode)
REJ09B0458-0010 Rev.0.10
Page 413 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.7
Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 25.19 shows a Noise Canceller Block Diagram.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or
SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit.
When they do not match, the former value is retained.
f1 (sampling clock)
C
SCL or SDA
input signal
D
C
Q
D
Latch
f1 period
f1 (sampling clock)
Figure 25.19
Noise Canceller Block Diagram
REJ09B0458-0010 Rev.0.10
Page 414 of 572
Apr 01, 2008
Q
Latch
Match
detection
circuit
Internal SCL
or SDA signal
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.8
Bit Synchronization Circuit
When the I2C bus interface is set to master mode, the high-level period may become shorter if:
• The SCL signal is driven L level by a slave device
• The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 25.20 shows the Bit Synchronization Circuit Timing and Table 25.5 lists the Time between Changing SCL
Signal from “L” Output to High-Impedance and Monitoring SCL Signal.
Reference clock of
SCL monitor timing
SCL
VIH
Internal SCL
Figure 25.20
Bit Synchronization Circuit Timing
Table 25.5
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring SCL Signal
ICCR1 Register
CKS3
0
1
CKS2
0
1
0
1
1Tcyc = 1/f1(s)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
SCL Monitoring Time
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
25. I2C bus Interface
R8C/32A Group
25.9
Notes on I2C bus Interface
To use the I2C bus interface, set the IICSEL bit in the SSUIICSR register to 1 (I2C bus interface function
selected).
REJ09B0458-0010 Rev.0.10
Page 416 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
26. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
26.1
Overview
The hardware LIN has the features listed below.
Figure 26.1 shows a Hardware LIN Block Diagram.
Master mode
• Synch Break generation
• Bus collision detection
Slave mode
• Synch Break detection
• Synch Field measurement
• Control function for Synch Break and Synch Field signal inputs to UART0
• Bus collision detection
Note:
1.The Wake up function is detected using INT1.
Hardware LIN
Synch Field
control
circuit
RXD0 pin
Timer RA
TIOSEL = 0
RXD data
LSTART bit
SBE bit
LINE bit
RXD0 input
control
circuit
Timer RA
underflow signal
TIOSEL = 1
Bus collision
detection
circuit
Timer RA
interrupt
Interrupt
control
circuit
UART0
Bits BCIE, SBIE,
and SFIE
UART0 transfer clock
UART0 TE bit
Timer RA output pulse
MST bit
UART0 TXD data
TXD0 pin
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
Figure 26.1
Hardware LIN Block Diagram
REJ09B0458-0010 Rev.0.10
Page 417 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.2
26. Hardware LIN
Input/Output Pins
The pin configuration for the hardware LIN is listed in Table 26.1.
Table 26.1
Hardware LIN Pin Configuration
Name
Pin Name
Assigned Pin
Input/Output
Receive data input
RXD0
P1_5 (1)
Input
Transmit data output
TXD0
P1_4 (1)
Output
Function
Receive data input pin for the
hardware LIN
Transmit data output pin for the
hardware LIN
Note:
1. To use the hardware LIN, set the TXD0SEL0 bit in the U0SR register to 1 and the RXD0SEL0 bit to
1.
REJ09B0458-0010 Rev.0.10
Page 418 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.3
26. Hardware LIN
Registers
The hardware LIN contains the following registers:
• LIN Control Register 2 (LINCR2)
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
26.3.1
LIN Control Register 2 (LINCR2)
Address 0105h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
BCE
0
Symbol
Bit Name
Function
BCE
Bus collision detection during Sync Break transmission 0: Bus collision detection disabled
enable bit
1: Bus collision detection enabled
—
Reserved bits
Set to 0.
—
—
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.3.2
LIN Control Register (LINCR)
Address 0106h
Bit
b7
Symbol
LINE
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
26. Hardware LIN
b6
MST
0
b5
SBE
0
b4
LSTART
0
b3
RXDSF
0
b2
BCIE
0
b1
SBIE
0
b0
SFIE
0
Symbol
Bit Name
Function
SFIE Synch Field measurement-completed 0: Synch Field measurement-completed interrupt
interrupt enable bit
disabled
1: Synch Field measurement-completed interrupt
enabled
SBIE Synch Break detection interrupt
0: Synch Break detection interrupt disabled
enable bit
1: Synch Break detection interrupt enabled
BCIE Bus collision detection interrupt
0: Bus collision detection interrupt disabled
enable bit
1: Bus collision detection interrupt enabled
RXDSF RXD0 input status flag
0: RXD0 input enabled
1: RXD0 input disabled
LSTART Synch Break detection start bit (1)
When this bit is set to 1, timer RA input is enabled
and RXD0 input is disabled.
When read, the content is 0.
0: Unmasked after Synch Break detected
SBE
RXD0 input unmasking timing
1: Unmasked after Synch Field measurement
select bit
completed
(effective only in slave mode)
(2)
MST
0:
Slave mode
LIN operation mode setting bit
(Synch Break detection circuit operation)
1: Master mode
(timer RA output OR’ed with TXD0)
LINE LIN operation start bit
0: LIN operation stops
1: LIN operation starts (3)
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Notes:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once.
3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts).
(Refer to Figure 26.3 Header Field Transmission Flowchart Example (1) and Figure 26.7 Header Field
Reception Flowchart Example (2).)
26.3.3
LIN Status Register (LINST)
Address 0107h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
B2CLR
0
b4
B1CLR
0
b3
B0CLR
0
b2
BCDCT
0
b1
SBDCT
0
b0
SFDCT
0
Symbol
Bit Name
Function
SFDCT Synch Field measurement-completed When this bit is set to 1, Synch Field measurement
flag
is completed.
SBDCT Synch Break detection flag
when this bit is set to 1, Synch Break is detected or
Synch Break generation is completed.
BCDCT Bus collision detection flag
When this bit is set to 1, bus collision is detected.
B0CLR SFDCT bit clear bit
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
B1CLR SBDCT bit clear bit
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
B2CLR BCDCT bit clear bit
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R
R
R
R/W
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.4
26. Hardware LIN
Function Description
26.4.1
Master Mode
Figure 26.2 shows an Operating Example during Header Field Transmission in master mode. Figures 26.3 and
26.4 show Examples of Header Field Transmission Flowchart.
During header field transmission, the hardware LIN operates as follows:
(1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a “L” level is output from the
TXD0 pin for the period set in registers TRAPRE and TRA for timer RA.
(2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is
set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
(3) The hardware LIN transmits “55h” via UART0.
(4) After the hardware LIN completes transmitting “55h”, it transmits an ID field via UART0.
(5) After the hardware LIN completes transmitting the ID field, it performs communication for a response
field.
Synch Break
TXD0 pin
1
0
SBDCT flag in
LINST register
1
0
Synch Field
IDENTIFIER
1 is written to B1CLR bit in LINST register.
Set to 0 when an interrupt request is acknowledged
or by a program.
IR bit in
TRAIC register
1
0
(1)
(2)
(3)
(4)
The above applies when:
LINE = 1, MST = 1, SBIE = 1
Figure 26.2
Operating Example during Header Field Transmission
REJ09B0458-0010 Rev.0.10
Page 421 of 572
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(5)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
Timer RA Set to timer mode
Bits TMOD2 to TMOD0 in TRAMR register ← 000b
(1)
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
(1)
Timer RA TRAIO pin assigned to P1_5
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b
UART0
RXD0 pin assigned to P1_5
RXD0SEL0 bit in U0SR register ← 1
INT1
INT1 pin assigned to P1_5
Bits INT1SEL2 to INT1SEL0 in INTSR register ← 001b
(1)
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Set the count source and
registers TRA and TRAPRE
as appropriate for the Synch
Break period.
Timer RA Set the Synch Break width
TRAPRE register
TRA register
UART0
Set to transmit/receive mode
(Transfer data 8 bits long, internal clock, 1 stop bit, parity
disabled)
U0MR register
(1)
UART0
Set the BRG count source (f1, f8, f32)
Bits CLK0 and CLK1 in U0C0 register
(1)
Set the bit rate
U0BRG register
(1)
UART0
Set the TIOSEL bit in the
TRAIOC register to 1 to select
the hardware LIN function.
If the wake-up function is not
necessary, the setting of the
INT1 pin can be omitted.
Hardware LIN Set the LIN operation to stop
LINE bit in LINCR register ← 0
(1)
Hardware LIN Set to master mode.
MST bit in LINCR register ← 1
(1)
Hardware LIN Set bus collision detection to enable
BCE bit in LINCR2 register ← 1
(1)
Set the BRG count source
and the U0BRG register as
appropriate for the bit rate.
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set interrupts to enable
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
(1)
In master mode, the Synch
Field measurement-completed
interrupt cannot be used.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
Note:
1. When the previous communication completes normally and header field transmission is
performed again with the same settings, the above settings can be omitted.
Figure 26.3
Header Field Transmission Flowchart Example (1)
REJ09B0458-0010 Rev.0.10
Page 422 of 572
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
A
Timer RA
Timer RA
Set the timer to start counting
TSTART bit in TRACR register ← 1
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 1?
NO
A Synch Break for timer RA is
generated.
After writing 1 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 1
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
SBDCT = 1?
NO
A timer RA interrupt can be used to
end Synch Break generation.
One or two cycles of the CPU clock
are required after Synch Break
generation ends before the SBDCT
flag is set to 1.
YES
Timer RA
Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0?
YES
NO
After a Synch Break for timer RA is
generated, stop the timer count.
After writing 0 to the TSTART bit,
if registers TRAPRE and TRA for
timer RA are not read or the register
settings are not changed, reading 0
from the TCSTF flag can be omitted.
Zero or one cycle of the timer RA
count source is required after timer
RA stops counting before the TCSTF
flag is set to 0.
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
The Synch Field is transmitted.
UART0 Communication via UART0
U0TB register ← ID field
The ID field is transmitted.
Figure 26.4
Header Field Transmission Flowchart Example (2)
REJ09B0458-0010 Rev.0.10
Page 423 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.4.2
26. Hardware LIN
Slave Mode
Figure 26.5 shows an Operating Example during Header Field Reception in slave mode. Figure 26.6 through
Figure 26.8 show examples of Header Field Reception Flowchart.
During header field reception, the hardware LIN operates as follows:
(1) When 1 is written to the LSTART bit in the LINCR register for the hardware LIN, Synch Break detection is
enabled.
(2) If a “L” level is input for a duration equal to or longer than the period set in timer RA, the hardware LIN
detected it as a Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. If the SBIE bit
in the LINCR register is set to 1, a timer RA interrupt is generated. Then the hardware LIN enters the Synch
Field measurement.
(3) The hardware LINA receives a Synch Field (55h) and measures the period of the start bit and bits 0 to 6 is
using timer RA. At this time, whether to input the Synch Field signal to RXD0 of UART0 can be selected
by the SBE bit in the LINCR register.
(4) When the Synch Field measurement is completed, the SFDCT flag in the LINST register is set to 1. If the
SFIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
(5) After the Synch Field measurement is completed, a transfer rate is calculated from the timer RA count
value. The rate is set in UART0 and registers TRAPRE and TRA for timer RA are set again. Then the
hardware LIN receives an ID field via UART0.
(6) After the hardware LIN completes receiving the ID field, it performs communication for a response field.
Synch Break
RXD0 pin
1
0
RXD0 input
for UART0
1
0
RXDSF flag in
LINCR register
SBDCT flag in
LINST register
Synch Field
IDENTIFIER
1 is written to LSTART bit
in LINCR register.
The flag is set to 0 after Synch Field
measurement is completed.
1
0
1 is written to B1CLR bit
in LINST register.
1
0
This period is measured.
SFDCT flag in
LINST register
1
0
IR bit in
TRAIC register
1
0
Set to 0 when an interrupt request is acknowledged
or by a program.
(1)
(2)
(3)
(4)
The above applies when:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 26.5
1 is written to B0CLR bit
in LINST register.
Operating Example during Header Field Reception
REJ09B0458-0010 Rev.0.10
Page 424 of 572
Apr 01, 2008
(5)
(6)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
(1)
Timer RA
Set to pulse width measurement mode
Bits TMOD2 to TMOD0 in TRAMR register ← 011b
Timer RA
Set the pulse width measurement level to low
TEDGSEL bit in TRAIOC register ← 0
(1)
Timer RA
TRAIO pin assigned to P1_5
Bits TRAIOSEL1 to TRAIOSEL0 in TRASR register ← 10b
RXD0 pin assigned to P1_5
RXD0SEL0 bit in U0SR register ← 1
INT1 pin assigned to P1_5
Bits INT1SEL2 to INT1SEL0 in INTSR register ← 001b
(1)
Timer RA
Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
(1)
Timer RA
Set the Synch Break width
TRAPRE register
TRA register
(1)
UART0
INT1
Hardware LIN
Set the LIN operation to stop
LINE bit in LINCR register ← 0
(1)
Hardware LIN
Set to slave mode
MST bit in LINCR register ← 0
(1)
Hardware LIN
Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN
Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch Field
measurement)
SBE bit in LINCR register
(1)
Hardware LIN
Set interrupts to enable
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
(1)
Set the TIOSEL bit in the
TRAIOC register to 1 to select the
hardware LIN function.
If the wake-up function is not
necessary, the setting of the INT1
pin can be omitted.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after Synch Break
detection, the Synch Field signal is
also input to UART0.
A
Note:
1. When the previous communication completes normally and header field reception is
performed again with the same settings, the above settings can be omitted.
Figure 26.6
Header Field Reception Flowchart Example (1)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
A
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST
register ← 1
Timer RA
Set pulse width measurement to start
TSTART bit in TRACR register ← 1
Timer RA
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 1?
NO
YES
Hardware LIN Set Synch Break detection to start
LSTART bit in LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in LINCR register
RXDSF = 1?
NO
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
SBDCT = 1?
NO
YES
B
Figure 26.7
Header Field Reception Flowchart Example (2)
REJ09B0458-0010 Rev.0.10
Page 426 of 572
Apr 01, 2008
Wait until timer RA starts counting.
Zero or one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set
to 1.
Wait until the RXD0 input to UART0 for
the hardware LIN is masked.
After writing 1 to the LSTART bit,
do not apply a “L” level to the RXD pin
until 1 is read from the RXDSF flag.
Otherwise, the signal applied during this
time will be input directly to UART0.
One or two cycles of the CPU clock and
zero or one cycle of the timer RA count
source are required after the LSTART bit
is set to 1 before the RXDSF flag is set
to 1. After this, input to timer RA and
UART0 is enabled.
A Synch Break for the hardware LIN is
detected.
A timer RA interrupt can be used.
When a Synch Break is detected, timer
RA is reloaded with the initially set count
value.
Even if the duration of the input “L” level
is shorter than the set period, timer RA is
reloaded with the initially set count value.
Wait until the next “L” level is input.
One or two cycles of the CPU clock are
required after Synch Break detection
before the SBDCT flag is
set to 1.
If the SBE bit in the LINCR register is set
to 0 (unmasked after Synch Break
detected), timer RA can be used in timer
mode after the SBDCT flag in the LINST
register is set to 1 and the RXDSF flag is
set to 0.
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26. Hardware LIN
B
YES
Hardware LIN
Read the Synch Field measurementcompleted flag
SFDCT flag in LINST register
SFDCT = 1?
NO
YES
UART0
Set the UART0 communication rate
U0BRG register
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
UART0
Figure 26.8
Communication via UART0
Clock asynchronous serial interface
(UART) mode ID field reception
Header Field Reception Flowchart Example (3)
REJ09B0458-0010 Rev.0.10
Page 427 of 572
Apr 01, 2008
A Synch Field for the hardware LIN
is measured.
A timer RA interrupt can be used.
(The SBDCT flag is set when
the timer RA counter underflows.)
If the SBE bit in the LINCR register
is set to 1 (unmasked after Synch
Field measurement completed),
timer RA can be used in timer mode
after the SFDCT flag in the LINST
register is set to 1 and the RXDSF
flag is set to 0.
Set a communication rate based on
the Synch Field measurement
result.
Communication is performed via
UART0.
(The SBDCT flag is set when
the timer RA counter underflows.)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.4.3
26. Hardware LIN
Bus Collision Detection Function
The bus collision detection function can be used if UART0 is enabled for transmission (TE bit in U0C1 register
= 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register to 1
(bus collision detection enabled).
Figure 26.9 shows an Operating Example When Bus Collision is Detected.
TXD0 pin
1
0
RXD0 pin
1
0
Transfer clock
1
0
LINE bit in
LINCR register
1
0
TE bit in
U0C1 register
1
0
BCDCT flag in
LINST register
1
0
IR bit in
TRAIC register
1
0
Set to 1 by a program.
Set to 1 by a program.
1 is written to B2CLR bit in LINST register.
Figure 26.9
Set to 0 when an interrupt request is acknowledged
or by a program.
Operating Example When Bus Collision is Detected
REJ09B0458-0010 Rev.0.10
Page 428 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.4.4
26. Hardware LIN
Hardware LIN End Processing
Figure 26.10 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
• If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA
Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0?
NO
YES
UART0
Transmission completes via UART0
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
Hardware LIN
Figure 26.10
Set the timer to stop counting.
Zero or one cycle of the timer RA
count source is required after
timer RA stops counting before
the TCSTF flag is set to 1.
If the bus collision detection
function is not used, UART0
transmission completion
processing is not required.
After clearing the hardware LIN
status flag, stop the hardware
LIN operation.
Set the LIN operation to stop
LINE bit in LINCR register ← 0
Example of Hardware LIN Communication Completion Flowchart
REJ09B0458-0010 Rev.0.10
Page 429 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.5
26. Hardware LIN
Interrupt Requests
There are four interrupt requests generated by the hardware LIN: Synch Break detection, Completion of Synch
Break generation, Completion of Synch Field measurement, and bus collision detection. These interrupts are
shared with timer RA.
Table 26.2 lists the Hardware LIN Interrupt Requests.
Table 26.2
Hardware LIN Interrupt Requests
Interrupt Request
Synch Break detection
Status Flag
Interrupt Source
SBDCT
Generated when timer RA underflows after the “L” level
duration for the RXD0 input is measured, or when a “L” level
is input for a duration longer than the Synch Break period
during communication.
Completion of Synch
Break generation
Generated when a “L” level output to TXD0 for the duration
set by timer RA is completed.
Completion of Synch
Field measurement
SFDCT
Generated when measurement for 6 bits of the Lynch Field
by timer RA is completed.
Bus collision detection
BCDCT
Generated when the RXD0 input and TXD0 output values
are different at data latch timing while UART0 is enabled for
transmission.
REJ09B0458-0010 Rev.0.10
Page 430 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
26.6
26. Hardware LIN
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
REJ09B0458-0010 Rev.0.10
Page 431 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
27. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins and P1_0 to P1_3.
27.1
Overview
Table 27.1 lists the A/D Converter Performance. Figure 27.1 shows a Block Diagram of A/D Converter.
Table 27.1
A/D Converter Performance
Item
A/D conversion method
Performance
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
Analog input voltage (1)
Operating clock φAD (2)
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
(φAD = fAD) (3)
fAD, fAD divided by 2, fAD divided by 4, fAD divided by 8
(fAD=f1 or fOCO-F)
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 20 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 16 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
AVCC = Vref = 3.0 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
AVCC = Vref = 2.2 V, φAD = 5 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
One-shot mode, repeat mode 0, repeat mode 1, single sweep mode,
and repeat sweep mode
4 pins (AN8 to AN11)
• Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition.)
Minimum 43 φAD cycles
Notes:
1. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 4.0 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 20 MHz or below.
When 3.2 V ≤ AVCC < 4.0 V, the frequency of φAD must be 16 MHz or below.
When 3.0 V ≤ AVCC < 3.2 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 3.0 V, the frequency of φAD must be 5 MHz or below.
The φAD frequency should be 2 MHz or above.
3. The conversion rate per pin is minimum 43 φAD cycles for 8-bit and 10-bit resolution.
REJ09B0458-0010 Rev.0.10
Page 432 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
CKS2 = 1
fOCO-F
fAD
f1
VREF
AVSS
Software trigger
Do not set.
Timer RC trigger
ADTRG
1/2
1/2
1/2
CKS2 = 0
ADSTBY = 0
CKS1 to CKS0
= 00b
= 01b
= 10b
= 11b
φAD
Analog circuit
ADSTBY = 1
ADCAP1 to ADCAP0
= 00b
= 01b
Successive conversion
register
Trigger
= 10b
SCAN1 to SCAN0
CH2 to CH0
AD0 register
= 11b
AD1 register
Vref
AD2 register
AD3 register
AD4 register
Decoder
Comparator
AD5 register
AD6 register
Vin
AD7 register
ADGSEL1 to ADGSEL0
Data bus
P1_0/AN8
P1_1/AN9
P1_2/AN10
P1_3/AN11
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
ADGSEL1 to ADGSEL0
= 01b
= 11b
ADEX0 = 0
OCVREFAN = 0
On-chip reference voltage
(OCVREF)
ADEX0 = 1
OCVREFAN = 1
(Note 1)
ADDDAEN=0
ADDDAEL
ADDDAEN=1
CKS0 to CKS2, ADCAP0 to ADCAP1: Bits in ADMOD register
CH0 to CH2, SCAN0 to SCAN1, ADGSEL0 to ADGSEL1: Bits in ADINSEL register
ADEX0, ADSTBY, ADDDAEN, ADDDAEL: Bits in ADCON1 register
OCVREFAN: Bit in OCVREFCR register
Note:
1. When on-chip reference voltage is used as analog input, first set the ADEX0
bit to 1 (on-chip reference voltage selected) and then set the OCVREFAN bit to
1 (on-chip reference voltage and analog input are connected).
When on-chip reference voltage is not used as analog input, first set the
OCVREFAN bit to 0 (on-chip reference voltage and analog input are cut off)
and then set the ADEX0 bit to 0 (extended analog input pin not selected).
Figure 27.1
Block Diagram of A/D Converter
REJ09B0458-0010 Rev.0.10
Page 433 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2
Registers
27.2.1
On-Chip Reference Voltage Control Register (OCVREFCR)
Address 0026h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
27. A/D Converter
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
b1
—
0
b0
OCVREFAN
0
Symbol
Bit Name
Function
R/W
OCVREFAN On-chip reference voltage to 0: On-chip reference voltage and analog input are cut off R/W
1: On-chip reference voltage and analog input are
analog input connect bit (1)
connected
—
Set
to 0.
R/W
Reserved bits
—
—
—
—
—
—
Note:
1. When on-chip reference voltage is used as analog input, first set the ADEX0 bit in the ADCON1 register to 1 (onchip reference voltage selected) and then set the OCVREFAN bit to 1 (on-chip reference voltage and analog
input are connected).
When on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference
voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected).
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the OCVREFCR register.
If the contents of the OCVREFCR register are rewritten during A/D conversion, the conversion result is
undefined.
REJ09B0458-0010 Rev.0.10
Page 434 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2.2
27. A/D Converter
A/D Register i (ADi) (i = 0 to 7)
Address 00C1h to 00C0h (AD0), 00C3h to 00C2h (AD1), 00C5h to 00C4h (AD2),
00C7h to 00C6h (AD3), 00C9h to 00C8h (AD4), 00CBh to 00CAh (AD5),
00CDh to 00CCh (AD6), 00CFh to 00CEh (AD7)
Bit
b7
b6
b5
b4
b3
b2
b1
Symbol
—
—
—
—
—
—
—
After Reset
X
X
X
X
X
X
X
b0
—
X
Bit
Symbol
After Reset
b8
—
X
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
b10
b11
b12
b13
b14
b15
b15
—
0
b14
—
0
b13
—
0
b12
—
0
10-Bit Mode
(BITS Bit in ADCON1 Register = 1)
8 low-order bits in A/D conversion result
2 high-order bits in A/D conversion result
b11
—
0
b10
—
0
b9
—
X
Function
8-Bit Mode
(BITS Bit in ADCON1 Register = 0)
A/D conversion result
When read, the content is 0.
R/W
R
R
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
Reserved bit
R
When read, the content is undefined.
If the contents of the ADCON1, ADMOD, ADINSEL, or OCVREFCR register are written during A/D
conversion, the conversion result is undefined.
When using the A/D converter in 10-bit mode, repeat mode 0, repeat mode 1, or repeat sweep mode, access the
ADi register in 16-bit units. Do not access it in 8-bit units.
REJ09B0458-0010 Rev.0.10
Page 435 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2.3
27. A/D Converter
A/D Mode Register (ADMOD)
Address 00D4h
Bit
b7
b6
Symbol ADCAP1 ADCAP0
After Reset
0
0
Bit
b0
b1
b5
MD2
0
b4
MD1
0
Symbol
Bit Name
CKS0 Division select bit
CKS1
b2
CKS2
Clock source select bit (1)
b3
b4
b5
MD0
MD1
MD2
A/D operating mode select bit
b6
b7
ADCAP0 A/D conversion trigger select
ADCAP1 bit
b3
MD0
0
b2
CKS2
0
b1
CKS1
0
b0
CKS0
0
Function
b1 b0
0 0: fAD divided by 8
0 1: fAD divided by 4
1 0: fAD divided by 2
1 1: fAD divided by 1 (no division)
0: Selects f1
1: Selects fOCO-F
b5 b4 b3
0 0 0: One-shot mode
0 0 1: Do not set.
0 1 0: Repeat mode 0
0 1 1: Repeat mode 1
1 0 0: Single sweep mode
1 0 1: Do not set.
1 1 0: Repeat sweep mode
1 1 1: Do not set.
b7 b6
0 0: A/D conversion starts by software trigger (ADST bit in
ADCON0 register)
0 1: Do not set.
1 0: A/D conversion starts by conversion trigger from timer
RC
1 1: A/D conversion starts by external trigger (ADTRG)
Note:
1. When the CKS2 bit is changed, wait for 3 φAD cycles or more before starting A/D conversion.
If the ADMOD register is rewritten during A/D conversion, the conversion result is undefined.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2.4
27. A/D Converter
A/D Input Select Register (ADINSEL)
Address 00D5h
Bit
b7
b6
Symbol ADGSEL1 ADGSEL0
After Reset
1
1
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b5
—
0
b4
SCAN0
0
Symbol
Bit Name
CH0
Analog input pin select bit
CH1
CH2
—
Reserved bit
SCAN0 A/D sweep pin count select bit
—
Reserved bit
ADGSEL0 A/D input group select bit
ADGSEL1
b3
—
0
b2
CH2
0
b1
CH1
0
b0
CH0
0
Function
Refer to Table 27.2 Analog Input Pin Selection
Set to 0.
0: 2 pins
1: 4 pins
Set to 0.
b7 b6
0 0: Do not set.
0 1: Port P1 group selected
1 0: Do not set.
1 1: Port group not selected
If the ADINSEL register is rewritten during A/D conversion, the conversion result is undefined.
Table 27.2
Analog Input Pin Selection
Bits CH2 to CH0
000b
001b
010b
011b
100b
101b
110b
111b
REJ09B0458-0010 Rev.0.10
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Bits ADGSEL1, ADGSEL0 = 01b
AN8
AN9
AN10
AN11
Do not set.
Apr 01, 2008
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2.5
27. A/D Converter
A/D Control Register 0 (ADCON0)
Address 00D6h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
—
0
Symbol
Bit Name
ADST A/D conversion start flag
—
—
—
—
—
—
—
b1
—
0
Function
0: Stop A/D conversion
1: Start A/D conversion
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
ADST Bit (A/D conversion start flag)
[Conditions for setting to 1]
When A/D conversion starts and while A/D conversion is in progress.
[Condition for setting to 0]
When A/D conversion stops.
REJ09B0458-0010 Rev.0.10
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b0
ADST
0
R/W
R/W
—
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.2.6
27. A/D Converter
A/D Control Register 1 (ADCON1)
Address 00D7h
Bit
b7
b6
b5
Symbol ADDDAEL ADDDAEN ADSTBY
After Reset
0
0
0
Bit
b0
Symbol
ADEX0
b1
b2
b3
b4
—
—
—
BITS
b5
b6
b7
b4
BITS
0
b3
—
0
b2
—
0
b1
—
0
b0
ADEX0
0
Bit Name
Function
Extended analog input pin select bit (1) 0: Extended analog input pin not selected
1: On-chip reference voltage selected (2)
Reserved bits
Set to 0.
R/W
R/W
8/10-bit mode select bit
R/W
ADSTBY A/D standby bit (3)
ADDDAEN A/D open-circuit detection assist
function enable bit (4)
ADDDAEL A/D open-circuit detection assist
method select bit (4)
0: 8-bit mode
1: 10-bit mode
0: A/D operation stops (standby)
1: A/D operation enabled
0: Disabled
1: Enabled
0: Discharge before conversion
1: Precharge before conversion
R/W
R/W
R/W
R/W
Notes:
1. When on-chip reference voltage is used as analog input, first set the ADEX0 bit to 1 (on-chip reference voltage
selected) and then set the OCVREFAN bit in the OCVREFCR register to 1 (on-chip reference voltage and analog
input are connected).
When on-chip reference voltage is not used as analog input, first set the OCVREFAN bit to 0 (on-chip reference
voltage and analog input are cut off) and then set the ADEX0 bit to 0 (extended analog input pin not selected).
2. Do not set to 1 (A/D conversion using comparison reference voltage as input) in single sweep mode or repeat
sweep mode.
3. When the ADSTBY bit is changed from 0 (A/D operation stops) to 1 (A/D operation enabled), wait for 1 φAD cycle
or more before starting A/D conversion.
4. To enable the A/D open-circuit detection assist function, select the conversion start state with the ADDDAEL bit
after setting the ADDDAEN bit to 1 (enabled).
The conversion result with an open circuit varies with external circuits. Careful evaluation should be performed
according to the system before using this function.
If the ADCON1 register is rewritten during A/D conversion, the conversion result is undefined.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.3
27. A/D Converter
Common Items for Multiple Modes
27.3.1
Input/Output Pins
The analog input shares pins P1_0 to P1_3 in AN8 to AN11.
When using the ANi (i = 8 to 11) pin as input, set the corresponding port direction bit to 0 (input mode).
After changing the A/D operating mode, select an analog input pin again.
27.3.2
A/D Conversion Cycles
Figure 27.2 shows a Timing Diagram of A/D Conversion. Figure 27.3 shows the A/D Conversion Cycles (φAD
= fAD).
A/D conversion execution time
Start process
Open-circuit
detection
Start
process
Open-circuit
detection
Charging time
Conversion time of 1st bit
Sampling time
15 φAD cycles
End process
2nd bit
Comparison
time
Comparison Comparison
time
time
……
Comparison
End process
time
* Repeat until conversion ends
Figure 27.2
Timing Diagram of A/D Conversion
A/D conversion execution time
Start process
Open-circuit
detection
Conversion time
(Minimum) (1)
Start process
(Minimum)
Open-circuit
detection
Charging time
43 φAD
1 φAD
Disabled: 0 φAD
Enabled: 2 φAD
Conversion time at the 1st bit
Sampling time
15 φAD
A/D Conversion Cycles (φAD = fAD)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
End process
Comparison
time
Comparison
time
End process
2.5 φAD
2.5 φAD
2 φAD
Note:
1. The conversion time (minimum) is 43 φAD for 8-bit and 10-bit resolution.
Figure 27.3
Conversion time
at the 2nd bit and
the follows
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
Table 27.3 shows the Number of Cycles for A/D Conversion Items. The A/D conversion time is defined as
follows.
The start process time varies depending on which φAD is selected.
When 1 (A/D conversion starts) is written to the ADST bit in the ADCON0 register, an A/D conversion starts
after the start process time has elapsed. Reading the ADST bit before the A/D conversion returns 0 (A/D
conversion stops).
In the modes where an A/D conversion is performed on multiple pins or multiple times, the between-execution
process time is inserted between the A/D conversion execution time for one pin and the next A/D conversion
time.
In one-shot mode and single sweep mode, the ADST bit is set to 0 during the end process time and the last A/D
conversion result is stored in the ADi register.
• In on-shot mode
Start process time + A/D conversion execution time + end process time
• When two pins are selected in single sweep mode
Start process time + (A/D conversion execution time + between-execution process time + A/D conversion
execution time) + end process time
Table 27.3
Number of Cycles for A/D Conversion Items
A/D Conversion Item
φAD = fAD
φAD = fAD divided by 2
φAD = fAD divided by 4
φAD = fAD divided by 8
A/D conversion
Open-circuit detection disabled
execution time
Open-circuit detection enabled
Between-execution process time
End process time
Start process time
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Number of Cycles
1 or 2 fAD cycles
2 or 3 fAD cycles
3 or 4 fAD cycles
5 or 6 fAD cycles
40 φAD cycles
42 φAD cycles
1 φAD cycle
2 or 3 fAD cycles
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.3.3
27. A/D Converter
A/D Conversion Start Condition
A software trigger, trigger from timer RC, and external trigger are used as A/D conversion start triggers.
Figure 27.4 shows the Block Diagram of A/D Conversion Start Control Unit.
ADCAP1 to ADCAP0 (1)
= 00b
IMFj
(TRCSR register)
ADTRG pin
PD4_5
ADST
ADTRGjE
= 10b
= 11b
A/D conversion start trigger
INT0EN
j = A, B, C, D k = 0 to 1
ADCAP1 to ADCAP0: Bits in ADMOD register
ADST: Bit in ADCON0 register
ADTRGjE: Bit in TRCADCR register
INT0EN: Bit in INTEN register
IMFj: Bit in TRCSR register
PD4_5: Bit in PD4 register
Note:
1. Do not set bits ADCAP1 to ADCAP0 to 01b.
Figure 27.4
27.3.3.1
Block Diagram of A/D Conversion Start Control Unit
Software Trigger
A software trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (software
trigger).
The A/D conversion starts when the ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
27.3.3.2
Trigger from Timer RC
This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC).
To use this function, make sure the following conditions are met.
• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 10b (timer RC).
• Timer RC is used in the output compare function (timer mode, PWM mode, PWM2 mode).
• The ADTRGjE bit (j = A, B, C, D) in the TRCADCR register is set to 1 (A/D trigger occurs at compare match
with TRCGRj register).
• The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
When the IMFj bit in the TRCSR register is changed from 0 to 1, A/D conversion starts.
Refer to 19. Timer RC, 19.5 Timer Mode (Output Compare Function), 19.6 PWM Mode, 19.7 PWM2
Mode for the details of timer RC and the output compare function (timer mode, PWM mode, and PWM2
mode).
27.3.3.3
External Trigger
This trigger is selected when bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger
(ADTRG)).
To use this function, make sure the following conditions are met.
• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 11b (external trigger (ADTRG)).
• The INT0EN bit in the INTEN register is set to 1 ((INT0 input enabled)).
• The PD4_5 bit in the PD4 register is set to 0 (input mode).
• The ADST bit in the ADCON0 register is set to 1 (A/D conversion starts).
When the ADTRG pin input is changed from “H” to “L” under the above conditions, A/D conversion starts.
REJ09B0458-0010 Rev.0.10
Page 442 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.3.4
27. A/D Converter
A/D Conversion Result
The A/D conversion result is stored in the ADi register (i = 0 to 7). The register where the result is stored varies
depending on the A/D operating mode used. The contents of the ADi register are undefined after a reset. Values
cannot be written to the ADi register.
In repeat mode 0, no interrupt request is generated. After the first AD conversion is completed, determine if the
A/D conversion time has elapsed by a program.
In one-shot mode, repeat mode 1, single sweep mode, and repeat sweep mode, an interrupt request is generated
at certain times, such as when an A/D conversion completes (the IR bit in the ADIC register is set to 1).
However, in repeat mode 1 and repeat sweep mode, A/D conversion continues after an interrupt request is
generated. Read the ADi register before the next A/D conversion is completed, since at completion the ADi
register is rewritten with the new value.
In one-shot mode and single sweep mode, when bits ADCAP1 to ADCAP0 in the ADMOD register is set to
00b (software trigger), the ADST bit in the ADCON0 register is used to determine whether the A/D conversion
or sweep has completed.
During an A/D conversion operation, if the ADST bit in the ADCON0 register is set to 0 (A/D conversion
stops) by a program to forcibly terminate A/D conversion, the conversion result of the A/D converter is
undefined and no interrupt is generated. If the ADST bit is set to 0 by a program, do not use the value of the
ADi register.
27.3.5
Low Current Consumption Function
When the A/D converter is not used, power consumption can be reduced by setting the ADSTBY bit in the
ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow.
To use the A/D converter, set the ADSTBY bit to 1 (A/D operation enabled) and wait for 1 φAD cycle or more
before setting the ADST bit in the ADCON0 register to 1 (A/D conversion starts). Do not write 1 to bits ADST
and ADSTBY at the same time.
Also, do not set the ADSTBY bit to 0 (A/D operation stops (standby)) during A/D conversion.
27.3.6
Extended Analog Input Pins
In one-shot mode, repeat mode 0, and repeat mode 1, the on-chip reference voltage (OCVREF) can be used as
analog input.
Any variation in VREF can be confirmed using the on-chip reference voltage. Use the ADEX0 bit in the
ADCON1 register and the OCVREFAN bit in the OCVREFCR register to select the on-chip reference voltage.
The A/D conversion result of the on-chip reference voltage in one-shot mode or in repeat mode 0 is stored in the
AD0 register.
27.3.7
A/D Open-Circuit Detection Assist Function
To suppress influences of the analog input voltage leakage from the previously converted channel during A/D
conversion operation, a function is incorporated to fix the electric charge on the chopper amp capacitor to the
predetermined state (AVCC or GND) before starting conversion.
This function enables more reliable detection of an open circuit in the wiring connected to the analog input pins.
Figure 27.5 shows the A/D Open-Circuit Detection Example on AVCC Side (Precharge before Conversion
Selected) and Figure 27.6 shows the A/D Open-Circuit Detection Example on AVSS Side (Discharge before
Conversion Selected).
REJ09B0458-0010 Rev.0.10
Page 443 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
Precharge
control signal
OFF
Discharge
control signal
Precharge
External circuit
example (1)
ADDDAEN
R
Analog input
ANi
Chopper amp
capacitor
i = 8 to 11
Open
ON
C
Note:
1. The conversion result for an open circuit varies with external circuits. Careful evaluation should be
performed before using this function.
Figure 27.5
A/D Open-Circuit Detection Example on AVCC Side (Precharge before Conversion
Selected)
ADDDAEN
External circuit
example (1)
Analog input
ANi
i = 8 to 11
Open
R
OFF
Precharge
control signal
ON
Discharge
control signal
Discharge
Chopper amp
capacitor
C
Note:
1. The conversion result for an open circuit varies with external circuits. Careful evaluation should be
performed before using this function.
Figure 27.6
A/D Open-Circuit Detection Example on AVSS Side (Discharge before Conversion
Selected)
REJ09B0458-0010 Rev.0.10
Page 444 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.4
27. A/D Converter
One-Shot Mode
In one-shot mode, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted
once.
Table 27.4 lists the One-Shot Mode Specifications.
Table 27.4
One-Shot Mode Specifications
Item
Function
Resolution
A/D conversion start condition
A/D conversion stop condition
Interrupt request generation
timing
Analog input pin
Storage resister for A/D
conversion result
Reading of result of A/D
converter
REJ09B0458-0010 Rev.0.10
Page 445 of 572
Specification
The input voltage to the pin selected by bits CH2 to CH0 and bits
ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in
the ADCON1 register is A/D converted once.
8 bits or 10 bits
• Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition)
• A/D conversion completes (If bits ADCAP1 to ADCAP0 in the
ADMOD register are set to 00b (software trigger), the ADST bit in the
ADCON0 register is set to 0.)
• Set the ADST bit to 0
When A/D conversion completes
One pin selectable from among AN8 to AN11, or OCVREF.
AD0 register: AN8, OCVREF
AD1 register: AN9
AD2 register: AN10
AD3 register: AN11
Read register AD0 to AD3 corresponding to the selected pin.
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.5
27. A/D Converter
Repeat Mode 0
In repeat mode 0, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted
repeatedly.
Table 27.5 lists the Repeat Mode 0 Specifications.
Table 27.5
Repeat Mode 0 Specifications
Item
Function
Resolution
A/D conversion start condition
A/D conversion stop condition
Interrupt request generation
timing
Analog input pin
Storage resister for A/D
conversion result
Reading of result of A/D
converter
REJ09B0458-0010 Rev.0.10
Page 446 of 572
Specification
The input voltage to the pin selected by bits CH2 to CH0 and bits
ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in
the ADCON1 register is A/D converted repeatedly.
8 bits or 10 bits
• Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition)
Set the ADST bit in the ADCON0 register to 0
Not generated
One pin selectable from among AN8 to AN11, or OCVREF.
AD0 register: AN8, OCVREF
AD1 register: AN9
AD2 register: AN10
AD3 register: AN11
Read register AD0 to AD3 corresponding to the selected pin.
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.6
27. A/D Converter
Repeat Mode 1
In repeat mode 1, the input voltage to one pin selected from among AN8 to AN11 or OCVREF is A/D converted
repeatedly.
Table 27.6 lists the Repeat Mode 1 Specifications. Figure 27.7 shows the Operating Example of Repeat Mode 1.
Table 27.6
Repeat Mode 1 Specifications
Item
Specification
Function
The input voltage to the pin selected by bits CH2 to CH0 and bits
ADGSEL1 to ADGSEL0 in the ADINSEL register or the ADEX0 bit in the
ADCON1 register is A/D converted repeatedly.
Resolution
8 bits or 10 bits
A/D conversion start condition • Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition)
A/D conversion stop condition Set the ADST bit in the ADCON0 register to 0
Interrupt request generation
When the A/D conversion result is stored in the AD7 register.
timing
Analog input pin
One pin selectable from among AN8 to AN11, or OCVREF.
Storage resister for A/D
AD0 register: 1st A/D conversion result, 9th A/D conversion result...
conversion result
AD1 register: 2nd A/D conversion result, 10th A/D conversion result...
AD2 register: 3rd A/D conversion result, 11th A/D conversion result...
AD3 register: 4th A/D conversion result, 12th A/D conversion result...
AD4 register: 5th A/D conversion result, 13th A/D conversion result...
AD5 register: 6th A/D conversion result, 14th A/D conversion result...
AD6 register: 7th A/D conversion result, 15th A/D conversion result...
AD7 register: 8th A/D conversion result, 16th A/D conversion result...
Reading of result of A/D
Read registers AD0 to AD7
converter
REJ09B0458-0010 Rev.0.10
Page 447 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
ADST bit in
ADCON0 register
“1”
“0”
Successive conversion
register
AD0 register
AD1 register
1st
2nd
3rd
Undefined
5th
AD3 register
AD4 register
AD5 register
6th
7th
8th
9th
1st A/D conversion result
Undefined
AD2 register
9th A/D conversion result
2nd A/D conversion result
Undefined
3rd A/D conversion result
Undefined
4th A/D conversion result
Undefined
5th A/D conversion result
Undefined
AD6 register
Undefined
Undefined
AD7 register
IR bit in
ADIC register
4th
6th A/D conversion result
7th A/D conversion result
8th A/D conversion result
Set to 0 when interrupt
request is acknowledged,
or set by a program.
“1”
“0”
The above applies under the following conditions:
Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (starts by software trigger).
Figure 27.7
Operating Example of Repeat Mode 1
REJ09B0458-0010 Rev.0.10
Page 448 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.7
27. A/D Converter
Single Sweep Mode
In single sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted
once.
Table 27.7 lists the Single Sweep Mode Specifications. Figure 27.8 shows the Operating Example of Single Sweep
Mode.
Table 27.7
Single Sweep Mode Specifications
Item
Specification
Function
The input voltage to the pins selected by bits ADGSEL1 to ADGSEL0 and
the SCAN0 bit in the ADINSEL register is A/D converted once.
Resolution
8 bits or 10 bits
A/D conversion start condition • Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition)
A/D conversion stop condition • If two pins are selected, when A/D conversion of the two selected pins
completes (the ADST bit in the ADCON0 register is set to 0).
• If four pins are selected, when A/D conversion of the four selected pins
completes (the ADST bit is set to 0).
• Set the ADST bit to 0.
Interrupt request generation
• If two pins are selected, when A/D conversion of the two selected pins
completes.
timing
• If four pins are selected, when A/D conversion of the four selected pins
completes.
Analog input pin
AN8 to AN9(2 pins), AN8 to AN11(4 pins),
(Selectable by the SCAN0 bit and bits ADGSEL1 to ADGSEL0.)
Storage resister for A/D
AD0 register: AN8
conversion result
AD1 register: AN9
AD2 register: AN10
AD3 register: AN11
Reading of result of A/D
Read the registers from AD0 to AD3 corresponding to the selected pin.
converter
REJ09B0458-0010 Rev.0.10
Page 449 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
ADST bit in
ADCON0 register
“1”
“0”
Successive conversion
register
AD0 register
AD1 register
AN8
AN10
Undefined
AD3 register
AN11
AN8 in A/D conversion result
Undefined
AD2 register
IR bit in
ADIC register
AN9
AN9 in A/D conversion result
Undefined
Undefined
“1”
AN10 in A/D conversion result
AN11 in A/D conversion result
Set to 0 when interrupt
request is acknowledged,
or set by a program.
“0”
The above applies under the following conditions:
• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b
(starts by software trigger).
• The SCAN0 bit in the ADINSEL register are set to 1 (4 pins),
bits ADGSEL1 to ADGSEL0 are set to 01b (AN8, AN9, AN10, AN11).
Figure 27.8
Operating Example of Single Sweep Mode
REJ09B0458-0010 Rev.0.10
Page 450 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.8
27. A/D Converter
Repeat Sweep Mode
In repeat sweep mode, the input voltage to two or four pins selected from among AN8 to AN11 are A/D converted
repeatedly.
Table 27.8 lists the Repeat Sweep Mode Specifications. Figure 27.9 shows the Operating Example of Repeat
Sweep Mode.
Table 27.8
Repeat Sweep Mode Specifications
Item
Specification
Function
The input voltage to the pins selected by bits ADGSEL1 to ADGSEL0 and
the SCAN0 bit in the ADINSEL register are A/D converted repeatedly.
Resolution
8 bits or 10 bits
A/D conversion start condition • Software trigger
• Timer RC
• External trigger
(Refer to 27.3.3 A/D Conversion Start Condition)
A/D conversion stop condition Set the ADST bit in the ADCON0 register to 0
Interrupt request generation
• If two pins are selected, when A/D conversion of the two selected pins
completes.
timing
• If four pins are selected, when A/D conversion of the four selected pins
completes.
Analog input pin
AN8 to AN9(2 pins), AN8 to AN11(4 pins),
(Selectable by the SCAN0 bit and bits ADGSEL1 to ADGSEL0.)
AD0 register: AN8
Storage resister for A/D
conversion result
AD1 register: AN9
AD2 register: AN10
AD3 register: AN11
Reading of result of A/D
Read the registers from AD0 to AD3 corresponding to the selected pin.
converter
REJ09B0458-0010 Rev.0.10
Page 451 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
ADST bit in
ADCON0 register
“1”
“0”
Successive conversion
register
AD0 register
AD1 register
AN8
Undefined
AD3 register
AN10
AN11
AN8
AN8 in A/D conversion result
Undefined
AD2 register
IR bit in
ADIC register
AN9
AN9
Undefined
AN11
AN8 in A/D conversion result
AN9 in A/D conversion result
AN10 in A/D conversion result
AN10 in A/D conversion result
AN11 in A/D conversion result
Set to 0 when interrupt
request is acknowledged,
or set by a program.
“1”
AN8
AN8 in A/D conversion result
AN9 in A/D conversion result
Undefined
AN10
AN11 in A/D conversion result
Set to 0 when interrupt
request is acknowledged,
or set by a program.
“0”
The above applies under the following conditions:
• Bits ADCAP1 to ADCAP0 in the ADMOD register are set to 00b (starts by software trigger).
• The SCAN0 bit in the ADINSEL register are set to 1 (4 pins),
bits ADGSEL1 to ADGSEL0 are set to 01b (AN8, AN9, AN10, and AN11).
Figure 27.9
Operating Example of Repeat Sweep Mode
REJ09B0458-0010 Rev.0.10
Page 452 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27.9
27. A/D Converter
Internal Equivalent Circuit of Analog Input
Figure 27.10 shows the Internal Equivalent Circuit of Analog Input.
VCC
VCC VSS
AVCC
ON Resistor
Wiring Resistor
TBD kΩ
TBD kΩ
Parasitic Diode
AN8
SW1
ON Resistor
TBD kΩ
Analog Input
Voltage
SW2
Parasitic Diode
i Ladder-type
Switches
i=4
AMP
VIN
ON Resistor
Approx. TBD kΩ
Sampling
Control Signal
VSS
C = Approx.TBD pF
SW3
SW4
i Ladder-type
Wiring Resistors
AVSS
ON Resistor
Wiring Resistor
TBD kΩ
TBD kΩ
Chopper-type
Amplifier
AN11
SW1
b6 b0 b4
b7 b1 b5
ADINSEL b2 ADINSEL
register
register
ADINSEL
register
A/D Successive
Conversion Register
Reference
Control Signal
Vref
VREF
Resistor
ladder
Comparison
voltage
ON Resistor
SW5
A/D Conversion
Interrupt Request
TBD kΩ
AVSS
Comparison reference voltage
(Vref) generator
Sampling Comparison
Connect to
Control signal
for SW2
SW1 conducts only on the ports selected for analog input.
SW2 and SW3 are open when A/D conversion is not in progress;
their status varies as shown by the waveforms in the diagrams on the left.
Connect to
SW4 conducts only when A/D conversion is not in progress.
Connect to
Control signal
for SW3
Connect to
SW5 conducts when compare operation is in progress.
Note:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 27.10
Internal Equivalent Circuit of Analog Input
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
27.10 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 27.11 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
VC is generally
And when t = T,
1
– -------------------------C ( R0 + R )

VC = VIN  1 – e

t



X
X
VC = VIN – ---- VIN = VIN  1 – ----

Y
Y
1
– --------------------------T
C
(
R0
+ R) = X
---e
Y
1
– -------------------------T = ln X
---C ( R0 + R )
Y
Hence,
T
R0 = – ------------------–R
X
C • ln ---Y
Figure 27.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN
and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
T = TBD µs when f(φAD) = TBD MHz. Output impedance R0 for sufficiently charging capacitor C within time T
is determined as follows.
T = TBD µs, R = TBD kΩ, C = TBD pF, X = 0.1, and Y = 1024. Hence,
TBD
R0 = – ------------------------------------ – TBD ≈ TBD
0.1
TBD • ln -----------1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately TBD kΩ. maximum.
MCU
Sensor equivalent
circuit
R0
R (TBD kΩ)
VIN
C (TBD pF)
VC
Note:
1. The capacity of the terminal is assumed to be TBD pF.
Figure 27.11
Analog Input Pin and External Sensor Equivalent Circuit
REJ09B0458-0010 Rev.0.10
Page 454 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
27. A/D Converter
27.11 Notes on A/D Converter
• Write to the ADMOD register, the ADINSEL register, the ADCON0 register (other than ADST bit), the
•
•
•
•
•
ADCON1 register, the OCVREFCR register when A/D conversion is stopped (before a trigger occurs).
To use the A/D converter in repeat mode 0, repeat mode 1, or repeat sweep mode, select the frequency of the A/D
converter operating clock φAD or more for the CPU clock during A/D conversion.
Do not select fOCO-F as φAD.
Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
Do not enter stop mode during A/D conversion.
Do not enter wait mode during A/D conversion regardless of the state of the CM02 bit in the CM0 register (1:
Peripheral function clock stops in wait mode or 0: Peripheral function clock does not stop in wait mode).
Do not set the FMSTP bit in the FMR0 register to 1 (flash memory stops) during A/D conversion.
REJ09B0458-0010 Rev.0.10
Page 455 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
28. Comparator A
Comparator A compares a reference input voltage and an analog input voltage. Comparator A1 and comparator A2 are
independent of each other. Note that these comparators share the voltage detection circuit with voltage monitor 1 and
voltage monitor 2. Either comparator A1 and comparator A2 or voltage monitor 1 and voltage monitor 2 can be
selected to use the voltage detection circuit.
28.1
Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
also can be output from the VCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pin can be selected as the
reference input voltage. Also, the comparator A1 interrupt and comparator A2 interrupt can be used.
Table 28.1 lists the Comparator A Specifications, Figure 28.1 shows a Comparator A Block Diagram, and Table
28.2 lists the Pin Configuration of Comparator A.
Table 28.1
Comparator A Specifications
Item
Analog input voltage
Reference input voltage
Comparison target
Comparison result
monitor
Interrupt
Digital Switching
Filter enable/disable
Sampling time
Comparison result
output
Comparator A1
Comparator A2
Input voltage to the LVCMP1 pin
Input voltage to the LVCMP2 pin
Input voltage to the LVREF pin
Whether passing thorough the reference input voltage by rising or falling.
The VW1C3 bit in the VW1C register
The VCA13 bit in the VCA1 register
Whether higher or lower than the reference input voltage.
Comparator A1 interrupt
Comparator A2 interrupt
(non-makable or maskable selectable)
(non-makable or maskable selectable)
Interrupt request at:
Interrupt request at:
Reference input voltage >
Reference input voltage >
input voltage to the LVCMP1 pin
input voltage to the LVCMP2 pin
and/or
and/or
Input voltage to the LVCMP1 pin >
Input voltage to the LVCMP2 pin >
reference input voltage
reference input voltage
Supported
(fOCO-S divided by n) × 2
n: 1, 2, 4, and 8
Output from the LVCOUT1 pin
(Whether the comparison result output is
inverted or not can be selected.)
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Output from the LVCOUT2 pin
(Whether the comparison result output is
inverted or not can be selected.)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
Shared with
voltage monitor 1
circuit
VW1F1 to VW1F0
= 00b
fOCO-S
VCA26
VCA22
0
LVCMP1
CM1POR
VW1C1
+
1
Sampling clock
= 01b
fOCO-S/2
= 10b
fOCO-S/4
= 11b
fOCO-S/8
CM1OE
0
-
Pin output
selection circuit
0
Digital filter
1
LVCOUT1
1
VW1C2
VW1C3
Edge
Non-maskable
interrupts
selection
circuit
Shared with
voltage monitor 2
circuit
VW2F1 to VW2F0
= 00b
fOCO-S
VCA27
VCA24
= 01b
fOCO-S/2
= 10b
fOCO-S/4
= 11b
fOCO-S/8
0
LVCMP2
Maskable
interrupts
VW1C0
IRQ1SEL
CM2POR
VW2C1
+
1
Sampling clock
0
-
CM2OE
0
Digital filter
1
1
VW2C2
VCA13
VCA23
Edge
Non-maskable
interrupts
selection
circuit
1
LVREF
Maskable
interrupts
0
VW2C0
IRQ2SEL
Internal reference voltage
VCA13: Bit in VCA1 register
VCA21, VCA22, VCA23, VCA24, VCA26, VCA27: Bits in VCA2 register
VW1C0 to VW1C3, VW1F0, VW1F1: Bits in VW1C register
VW2C0, VW2C2, VW2F0, VW2F1: Bits in VW2C register
CM1POR, CM2POR, CM1OE, CM2OE, IRQ1SEL, IRQ2SEL: Bits in CMPA register
Figure 28.1
Table 28.2
Comparator A Block Diagram
Pin Configuration of Comparator A
Pin Name
LVCMP1
LVCOUT1
LVCMP2
LVCOUT2
LVREF
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I/O
Input
Output
Input
Output
Input
Apr 01, 2008
Function
Comparator A1 analog pin
Comparator A1 comparison result output pin
Comparator A2 analog pin
Comparator A2 comparison result output pin
Comparator reference voltage pin
LVCOUT2
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.2
28.2.1
28. Comparator A
Registers
Voltage Monitor Circuit/Comparator A Control Register (CMPA)
Address 0030h
Bit
b7
Symbol COMPSEL
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
28.2.2
Symbol
CM1POR
b2
b3
b4
b5
b6
b7
b5
IRQ2SEL
0
b4
IRQ1SEL
0
b3
CM2OE
0
b2
CM1OE
0
b1
CM2POR
0
Bit Name
LVCOUT1 output polarity
select bit
b0
CM1POR
0
Function
0: Non-inverted comparator A1 comparison result is
output to LVCOUT1.
1: Inverted comparator A1 comparison result is
output to LVCOUT1.
0: Non-inverted Comparator A2 comparison result is
CM2POR LVCOUT2 output polarity
select bit
output to LVCOUT2.
1: Inverted comparator A2 comparison result is
output to LVCOUT2.
CM1OE LVCOUT1 output enable bit
0: Output disabled
1: Output enabled
CM2OE LVCOUT2 output enable bit
0: Output disabled
1: Output enabled
IRQ1SEL Voltage monitor 1/comparator A1 0: Non-maskable interrupt
interrupt type select bit
1: Maskable interrupt
IRQ2SEL Voltage monitor 2/comparator A2 0: Non-maskable interrupt
interrupt type select bit
1: Maskable interrupt
—
Reserved bit
Set to 0.
COMPSEL Voltage monitor/comparator A
0: Bits IRQ1SEL and IRQ2SEL disabled
interrupt type selection enable bit 1: Bits IRQ1SEL and IRQ2SEL enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Voltage Monitor Circuit Edge Select Register (VCAC)
Address 0031h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b6
—
0
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
VCAC2
0
b1
VCAC1
0
Symbol
Bit Name
Function
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
VCAC1 Comparator A1 circuit edge select bit (1) 0: One edge
1: Both edges
VCAC2 Comparator A2 circuit edge select bit (2) 0: One edge
1: Both edges
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
—
—
—
b0
—
0
R/W
—
R/W
R/W
—
Notes:
1. When the VCA1 bit is set tot 0 (one edge), the VW1C7 bit in the VW1C register is enabled. Set the VW1C7 bit
after setting the VCAC1 bit to 0.
2. When the VCA2 bit is set tot 0 (one edge), the VW2C7 bit in the VW2C register is enabled. Set the VW2C7 bit
after setting the VCAC2 bit to 0.
REJ09B0458-0010 Rev.0.10
Page 458 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.2.3
Voltage Detect Register (VCA1)
Address 0033h
Bit
b7
Symbol
—
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
28. Comparator A
b6
—
0
b5
—
0
b4
—
0
b3
VCA13
1
b2
—
0
b1
—
0
b0
—
0
Symbol
Bit Name
Function
—
Reserved bits
Set to 0.
—
—
VCA13 Comparator A2 signal monitor flag (1) 0: LVCMP2 < reference voltage
1: LVCMP2 ≥ reference voltage
or comparator A2 circuit disabled
—
Reserved bits
Set to 0.
—
—
—
R/W
R/W
R
R/W
Note:
1. When the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled), the VCA13 bit is enabled.
When the VCA27 bit in the VCA2 register is set to 0 (comparator A2 circuit disabled), the VCA13 bit is set to 1
(VCMP2 ≥ reference voltage).
REJ09B0458-0010 Rev.0.10
Page 459 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.2.4
28. Comparator A
Voltage Detect Register 2 (VCA2)
Address 0034h
Bit
b7
b6
b5
b4
b3
Symbol VCA27
VCA26
VCA25
VCA24
VCA23
After Reset The LVDAS bit in the OFS register is set to 1.
0
0
0
0
0
After Reset The LVDAS bit in the OFS register is set to 0.
0
0
1
0
0
Bit
b0
b5
Symbol
Bit Name
VCA20 Internal power low consumption
enable bit (1)
VCA21 Comparator A1 reference voltage
input select bit
VCA22 LVCMP1 comparison voltage
external input select bit
VCA23 Comparator A2 reference voltage
input select bit
VCA24 LVCMP2 comparison voltage
external input select bit
VCA25 Voltage detection 0 enable bit (3)
b6
VCA26
b7
VCA27
b1
b2
b3
b4
Voltage detection 1/comparator A1
enable bit (3)
Voltage detection 2/comparator A2
enable bit (5)
b2
VCA22
b1
VCA21
b0
VCA20
0
0
0
0
0
0
Function
0: Low consumption disabled
1: Low consumption enabled (2)
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
1: LVCMP1 pin input voltage
0: Internal reference voltage
1: LVREF pin input voltage
0: Supply voltage (VCC)
(Vdet2_0)
1: LVCMP2 pin input voltage (Vdet2_EXT)
0: Voltage detection 0 circuit disabled
1: Voltage detection 0 circuit enabled
0: Voltage detection 1/comparator A1 circuit disabled
1: Voltage detection 1/comparator A1 circuit enabled
0: Voltage detection 2/comparator A2 circuit disabled
1: Voltage detection 2/comparator A2 circuit enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. Use the VCA20 bit only when the MCU enters wait mode. To set the VCA20 bit, follow the procedure shown in
Figure 9.3 Procedure for Reducing Internal Power Consumption Using VCA20 bit.
2. When the VCA20 bit is set to 1 (low consumption enabled), do not set the CM10 bit in the CM1 register to 1 (stop
mode).
3. To use voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection circuit starts operation.
4. To use the voltage detection 1/comparator A1 interrupt or the VW1C3 bit in the VW1C register, set the VCA26 bit
to 1.
After the VCA26 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 1/comparator A1 circuit
starts operation.
5. To use the voltage detection 2/comparator A2 interrupt or the VCAC13 bit in the VCA1 register, set the VCA27
bit to 1.
After the VCA27 bit is set to 1 from 0, allow td(E-A) to elapse before the voltage detection 2/comparator A2 circuit
starts operation.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VCA2 register.
REJ09B0458-0010 Rev.0.10
Page 460 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.2.5
Voltage Monitor 1 Circuit Control Register (VW1C)
Address 0039h
Bit
b7
Symbol VW1C7
After Reset
1
Bit
b0
b1
b2
b3
b4
b5
b6
b7
28. Comparator A
b6
—
0
b5
VW1F1
0
b4
VW1F0
0
b3
VW1C3
1
b2
VW1C2
0
b1
VW1C1
1
b0
VW1C0
0
Symbol
Bit Name
Function
VW1C0 Comparator A1 interrupt enable bit (1) 0: Disabled
1: Enabled
0: Digital filter enable mode
VW1C1 Comparator A1 digital filter
(digital filter circuit enabled)
disable mode select bit (2)
1: Digital filter disable mode
(digital filter circuit disabled)
[Condition to set this bit to 0]
VW1C2 Comparator A1 interrupt flag (3, 4)
0 is written.
[Condition to set this bit to 1]
When an interrupt request is generated.
VW1C3 Comparator A1 signal monitor flag (3) 0: LVCMP1 < reference voltage
1: LVCMP1 ≥ reference voltage
or comparator A1 circuit disabled
b5 b4
VW1F0 Sampling clock select bit
0 0: fOCO-S divided by 1
VW1F1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
—
Reserved bit
Set to 0.
0: When LVCMP1 reaches reference voltage
VW1C7 Comparator A1 interrupt
or above.
generation condition select bit (5)
1: When LVCMP1 reaches reference voltage
or below.
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Notes:
1. The VW1C0 is enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit enabled).
Set the VW1C0 bit to 0 (disabled) when the VCA26 bit is set to 0 (comparator A1 circuit disabled). To set the
VW1C0 bit to 1 (enabled), follow the procedure shown in Table 28.3 Procedure for Setting Bits Associated
with Comparator A1 Interrupt.
2. To use the comparator A1 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW1C1 bit.
3. Bits VW1C2 and VW1C3 are enabled when the VCA26 bit in the VCA2 register is set to 1 (comparator A1 circuit
enabled).
4. Set the VW1C2 bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged
even if 1 is written to it).
5. The VW1C7 bit is enabled when the VCAC1 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC1 bit to 0, set the VW1C7 bit.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW1C register.
Rewriting the VW1C register may set the VW1C2 bit to 1. After rewriting this register, set the VW1C2 bit to 0.
REJ09B0458-0010 Rev.0.10
Page 461 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.2.6
28. Comparator A
Voltage Monitor 2 Circuit Control Register (VW2C)
Address 003Ah
Bit
b7
Symbol VW2C7
After Reset
1
b6
VW2C6
0
b5
VW2F1
0
b4
VW2F0
0
b3
VW2C3
0
b2
VW2C2
0
b1
VW2C1
1
b0
VW2C0
0
Bit
b0
Symbol
Bit Name
VW2C0 Comparator A2 interrupt enable bit (1)
Function
0: Disabled
1: Enabled
Comparator A2 digital filter disable mode 0: Digital filter enable mode
(digital filter circuit enabled)
select bit (2)
1: Digital filter disable mode
(digital filter circuit disabled)
[Condition to set this bit to 0]
Comparator A2 interrupt flag (3, 4)
0 is written.
[Condition to set this bit to 1]
When an interrupt request is generated.
0: Not detected
WDT detection monitor flag (4)
1: Detected
b5 b4
Sampling clock select bit
0 0: fOCO-S divided by 1
0 1: fOCO-S divided by 2
1 0: fOCO-S divided by 4
1 1: fOCO-S divided by 8
Reserved bit
Set to 0.
0: When LVCMP2 reaches reference voltage
Comparator A2 interrupt
or above.
generation condition select bit (5)
1: When LVCMP2 reaches reference voltage
or below.
R/W
R/W
b1
VW2C1
R/W
b2
VW2C2
b3
VW2C3
b4
b5
VW2F0
VW2F1
b6
b7
VW2C6
VW2C7
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. The VW2C0 is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled).
Set the VW2C0 bit to 0 (disabled) when the VCA27 bit is set to 0 (comparator A2 circuit disabled). To set the
VW1C0 bit to 1 (enabled), follow the procedure shown in Table 28.4 Procedure for Setting Bits Associated
Comparator A2 Interrupt.
2. To use the comparator A2 interrupt to exit stop mode and to return again, write 0 and then 1 to the VW2C1 bit.
3. The VW2C2 bit is enabled when the VCA27 bit in the VCA2 register is set to 1 (comparator A2 circuit enabled).
4. Set this bit to 0 by a program. When 0 is written by a program, this bit is set to 0 (and remains unchanged even if
1 is written to it).
5. The VW2C7 bit is enabled when the VCAC2 bit in the VCAC register is set to 0 (one edge). After setting the
VCAC2 bit to 0, set the VW2C7 bit.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting the VW2C register.
Rewriting the VW2C register may set the VW2C2 bit to 1. After rewriting this register, set the VW2C2 bit to 0.
REJ09B0458-0010 Rev.0.10
Page 462 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.3
28. Comparator A
Monitoring Comparison Results
28.3.1
Monitoring Comparator A1
Once the following settings are made, the comparison result of comparator A1 can be monitored by the VW1C3
bit in the VW1C register after td(E-A) has elapsed (refer to 32. Electrical Characteristics).
(1) Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage).
(2) Set the VCA22 bit in the VCA2 register to 1 (LVCMP1 pin input voltage).
(3) Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled).
28.3.2
Monitoring Comparator A2
Once the following settings are made, the comparison result of comparator A2 can be monitored by the VCA13
bit in the VCA1 register after td(E-A) has elapsed (refer to 32. Electrical Characteristics).
(1) Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage).
(2) Set the VCA24 bit in the VCA2 register to 1 (LVCMP2 pin input voltage).
(3) Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled).
REJ09B0458-0010 Rev.0.10
Page 463 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.4
28. Comparator A
Functional Description
Comparator A1 and comparator A2 operate independently.
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
can also be output from the LVCOUTi (i = 1 or 2) pin. An input voltage to the LVREF pin can be used as the
reference input voltage. The comparator A1 interrupt or the comparator A2 interrupt can be used by selecting nonmaskable or maskable for each interrupt type.
28.4.1
Comparator A1
Table 28.3 lists the Procedure for Setting Bits Associated with Comparator A1 Interrupt, Figure 28.2 shows a
Comparator A1 Operating Example (Digital Filter Enabled), and Figure 28.3 shows a Comparator A1
Operating Example (Digital Filter Disabled).
Table 28.3
Step
1
2
3
4
5
6
7 (1)
8
9
10
11
12
Procedure for Setting Bits Associated with Comparator A1 Interrupt
When Using Digital Filter
When Using No Digital Filter
Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled).
Set the VCA21 bit in the VCA2 register to 1 (LVREF pin input voltage) and
the VCA22 bit to 1 (LVCMP1 pin input voltage).
Set the VCA26 bit in the VCA2 register to 1 (comparator A1 circuit enabled).
Wait for td(E-A).
Select the interrupt type by the IRQ1SEL bit in the CMPA register.
Select the sampling clock of the digital filter by Set the VW1C1 bit in the VW1C register to 1
bits VW1F0 and VW1F1 in the VW1C register. (digital filter disabled).
Set the VW1C1 bit in the VW1C register to 0 −
(digital filter enabled).
Select the interrupt request timing by the VCAC1 bit in the VCAC register and
the VW1C7 bit in the VW1C register.
Set the VW1C2 bit in the VW1C register to 0.
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on).
Wait for 2 cycles of the sampling clock of
− (No wait time required)
the digital filter.
Set the VW1C0 bit in the VW1C register to 1 (comparator A1 interrupt enabled).
Note:
1. When the VW1C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one instruction).
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
LVCMP1
Reference voltage
(LVREF)
1
VW1C3 bit
0
Sampling clock of
digital filter × 2 cycles
Sampling clock of
digital filter × 2 cycles
1
VW1C2 bit
0
Set to 0 by a program.
VW1C1 bit is set to 0
(digital filter enabled)
and
VCAC1 bit is set to 1
(both edges)
Set to 0 when an interrupt request
is acknowledged or by a program.
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 0)
1
0
1
0
Set to 0 by a program.
1
VW1C2 bit
0
VW1C1 bit is set to 0
(digital filter enabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 0
(when LVCMP1 reaches
reference voltage or above)
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 0)
1
0
1
0
1
VW1C1 bit is set to 0
(digital filter enabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 1
(when LVCMP1 reaches
reference voltage or below)
Set to 0 when an interrupt request
is acknowledged or by a program.
Set to 0 by a program.
VW1C2 bit
0
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 1)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
CM1POR, IRQ1SEL: Bits in CMPA register
The above applies when:
• VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled)
• CM1OE bit in CMPA register = 1 (output enabled)
• VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled)
Figure 28.2
Comparator A1 Operating Example (Digital Filter Enabled)
REJ09B0458-0010 Rev.0.10
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
LVCMP1
Reference voltage
(LVREF)
1
VW1C3 bit
0
Set to 0 by a program.
1
VW1C2 bit
0
VW1C1 bit is set to 1
(digital filter disabled)
and
VCAC1 bit is set to 1
(both edges)
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 0)
Set to 0 when an interrupt request
is acknowledged or by a program.
1
0
1
0
Set to 0 by a program.
1
VW1C2 bit
VW1C1 bit is set to 1
(digital filter disabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 0
(when LVCMP1 reaches
reference voltage or above)
0
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 0)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
Set to 0 by a program.
1
VW1C1 bit is set to 1
(digital filter disabled),
VCAC1 bit is set to 0
(one edge),
and
VW1C7 bit is set to 1
(when LVCMP1 reaches
reference voltage or below)
VW1C2 bit
0
IR bit in
VCMP1IC register
(IRQ1SEL = 1)
LVCOUT1 output
(CM1POR = 1)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
VW1C1, VW1C2, VW1C3, VW1C7: Bits in VW1C register
VCAC1: Bit in VCAC register
CM1POR, IRQ1SEL: Bits in CMPA register
The above applies under when:
• VCA26 bit in VCA2 register = 1 (comparator A1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (comparator A1 interrupt enabled)
• CM1OE bit in CMPA register = 1 (output enabled)
• VCA22 bit in VCA2 register = 1 (LVCMP1 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled)
Figure 28.3
Comparator A1 Operating Example (Digital Filter Disabled)
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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.4.2
28. Comparator A
Comparator A2
Table 28.4 lists the Procedure for Setting Bits Associated Comparator A2 Interrupt, Figure 28.4 shows a
Comparator A2 Operating Example (Digital Filter Enabled), and Figure 28.5 shows a Comparator 2 Operating
Example (Digital Filter Disabled).
Table 28.4
Step
1
2
3
4
5
6
7 (1)
8
9
10
11
12
Procedure for Setting Bits Associated Comparator A2 Interrupt
When Using Digital Filter
When Using No Digital Filter
Set the COMPSEL bit in the CMPA register to 1 (bits IRQ1SEL and IRQ2SEL enabled).
Set the VCA23 bit in the VCA2 register to 1 (LVREF pin input voltage) and
the VCA24 bit to 1 (LVCMP2 pin input voltage).
Set the VCA27 bit in the VCA2 register to 1 (comparator A2 circuit enabled).
Wait for td(E-A).
Select the interrupt type by the IRQ2SEL bit in the CMPA register.
Select the sampling clock of the digital filter by Set the VW2C1 bit in the VW2C register to 1
bits VW2F0 and VW2F1 in the VW2C register. (digital filter disabled).
Set the VW2C1 bit in the VW2C register to 0 −
(digital filter enabled).
Select the interrupt request timing by the VCAC2 bit in the VCAC register and
the VW2C7 bit in the VW2C register.
Set the VW2C2 bit in the VW2C register to 0.
Set the CM14 bit in the CM1 register to 0 (low- −
speed on-chip oscillator on).
Wait for 2 cycles of the sampling clock of
− (No wait time required)
the digital filter.
Set the VW2C0 bit in the VW2C register to 1 (comparator A2 interrupt enabled).
Note:
1. When the VW2C0 bit is set to 0, steps 6 and 7 can be executed at the same time (with one
instruction).
REJ09B0458-0010 Rev.0.10
Page 467 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
LVCMP2
Reference voltage
(LVREF)
1
VCA13 bit
0
Sampling clock of
digital filter × 2 cycles
Sampling clock of
digital filter × 2 cycles
1
VW2C2 bit
0
Set to 0 by a program.
VW2C1 bit is set to 0
(digital filter enabled)
and
VCAC2 bit is set to 1
(both edges)
Set to 0 when an interrupt request
is acknowledged or by a program.
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 0)
1
0
1
0
Set to 0 by a program.
1
VW2C2 bit
0
VW2C1 bit is set to 0
(digital filter enabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 0
(when LVCMP2 reaches
reference voltage or above)
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 0)
1
0
1
0
1
VW2C1 bit is set to 0
(digital filter enabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 1
(when LVCMP2 reaches
reference voltage or below)
Set to 0 when an interrupt request
is acknowledged or by a program.
Set to 0 by a program.
VW2C2 bit
0
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 1)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
CM2POR, IRQ2SEL: Bits in CMPA register
The above applies when:
• VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled)
• CM2OE bit in CMPA register = 1 (output enabled)
• VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled)
Figure 28.4
Comparator A2 Operating Example (Digital Filter Enabled)
REJ09B0458-0010 Rev.0.10
Page 468 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28. Comparator A
VCMP2
Reference voltage
(LVREF)
1
VCA13 bit
0
Set to 0 by a program.
1
VW2C2 bit
0
VW2C1 bit is set to 1
(digital filter disabled)
and
VCAC2 bit is set to 1
(both edges)
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 0)
Set to 0 when an interrupt request
is acknowledged or by a program.
1
0
1
0
Set to 0 by a program.
1
VW2C2 bit
VW2C1 bit is set to 1
(digital filter disabled),
VCAC2 bit is set to 0
(one edge),
and
VW2C7 bit is set to 0
(when LVCMP2 reaches
reference voltage or above)
0
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 0)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
Set to 0 by a program.
1
VW2C2 bit
VW2C1 bit is set to 1
(digital filter disabled),
VCAC2 bit is set to 0
(one edge), and
VW2C7 bit is set to 1
(when LVCMP2 reaches
reference voltage or below)
0
IR bit in
VCMP2IC register
(IRQ2SEL = 1)
LVCOUT2 output
(CM2POR = 1)
1
Set to 0 when an interrupt request
is acknowledged or by a program.
0
1
0
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C7: Bits in VW2C register
VCAC2: Bit in VCAC register
CM2POR, IRQ2SEL: Bits in CMPA register
The above applies when:
• VCA27 bit in VCA2 register = 1 (comparator A2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (comparator A2 interrupt enabled)
• CM2OE bit in CMPA register = 1 (output enabled)
• VCA24 bit in VCA2 register = 1 (LVCMP2 pin input voltage)
• COMPSEL bit in CMPA register = 1 (bits IRQ1SEL and IRQ2SEL enabled)
Figure 28.5
Comparator 2 Operating Example (Digital Filter Disabled)
REJ09B0458-0010 Rev.0.10
Page 469 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
28.5
28. Comparator A
Comparator A1 and Comparator A2 Interrupts
Comparator A generates an interrupt request from two sources, comparator A1 and comparator A2. Non-maskable
or maskable can be selected for each interrupt type.
Refer to 11. Interrupts for details of interrupts.
28.5.1
Non-Maskable Interrupts
When the COMPSEL bit in the CMPA register is set to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the
IRQiSEL (i = 1 or 2) is set to 0, the comparator Ai interrupt functions as a non-maskable interrupt.
When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1. At this time,
a non-maskable interrupt request for comparator Ai is generated.
28.5.2
Maskable Interrupts
When the COMPSEL bit in the CMPA register is set to 1 (bits IRQ1SEL and IRQ2SEL enabled) and the
IRQiSEL (i = 1 or 2) is set to 1, the comparator Ai interrupt functions as a maskable interrupt.
The comparator Ai interrupt uses the corresponding VCMPiIC register (bits IR and ILVL0 to ILVL2) and a
single vector. When the selected interrupt request timing occurs, the VWiC2 bit in the VWiC register is set to 1.
At this time, the IR bit in the VCMPiIC register is set to 1 (interrupt requested).
Refer to 11.3 Interrupt Control for the VCMPiIC register and 11.1.5.2 Relocatable Vector Tables for
interrupt vectors.
REJ09B0458-0010 Rev.0.10
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Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29. Comparator B
29. Comparator B
Comparator B compares a reference input voltage and an analog input voltage. Comparator B1 and comparator B3 are
independent of each other.
29.1
Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. An input to
the IVREFi (i = 1 or 3) pin can be used as the reference input voltage.
Table 29.1 lists the Comparator B Specifications, Figure 29.1 shows a Comparator B Block Diagram, and Table
29.2 lists the I/O Pins.
Table 29.1
Comparator B Specifications
Item
Specification
Analog input voltage
Reference input voltage
Comparison result
Interrupt request
generation timing
Selectable functions
Input voltage to the IVCMPi pin
Input voltage to the IVREFi pin
Read from the INTiCOUT bit in the INTCMP register
When the comparison result changes.
• Digital filter function
Whether the digital filter is applied or not and the sampling frequency can
be selected.
i = 1 or 3
INT3F1 to INT3F0
f1 = 01b
Sampling clock
f8 = 10b
f32 = 11b
Port direction register
INT3EN
INT3
INT3CP0 = 0
Digital filter
(3 times match)
IVCMP3
+
IVREF3
-
IVCMP1
+
IVREF1
-
INT3CP0 = 1
INT3PL = 0
= 00b
INT3PL = 1
Both edge
detection
circuit
INT3COUT
INT1COUT
INT1EN
INT1CP0 = 1
Digital filter
(3 times match)
INT1CP0 = 0
INT1
INT1F1 to INT1F0
= other than 00b
INT1PL = 0
= 00b
INT1PL = 1
Port direction register
INT1F1 to INT1F0
f1 =01b
f8 =10b
Sampling clock
f32 =11b
INT1CP0, INT1COUT, INT3CP0, INT3COUT: Bits in INTCMP register
INT1EN, INT1PL, INT3EN, INT3PL: Bits in INTEN register
INT1F0, INT1F1, INT3F0, INT3F1: Bits in INTF register
Figure 29.1
Comparator B Block Diagram
REJ09B0458-0010 Rev.0.10
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To INT3 interrupt
INT3F1 to INT3F0
= other than 00b
Apr 01, 2008
Both edge
detection
circuit
To INT1 interrupt
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 29.2
29. Comparator B
I/O Pins
Pin Name
IVCMP1
IVREF1
IVCMP3
IVREF3
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I/O
Input
Input
Input
Input
Function
Comparator B1 analog pin
Comparator B1 reference voltage pin
Comparator B3 analog pin
Comparator B3 reference voltage pin
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29.2
29.2.1
29. Comparator B
Registers
Comparator B Control Register (INTCMP)
Address 01F8h
Bit
b7
Symbol INT3COUT
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
29.2.2
Symbol
INT1CP0
b6
—
0
b5
—
0
b4
b3
INT3CP0 INT1COUT
0
0
b2
—
0
b1
—
0
b0
INT1CP0
0
Bit Name
Function
Comparator B1 operation enable bit 0: Comparator B1 operation disabled
1: Comparator B1 operation enabled
Reserved bits
Set to 0.
—
—
INT1COUT Comparator B1 monitor flag
INT3CP0
0: IVCMP1 < IVREF1
or comparator B1 operation disabled
1: IVCMP1 > IVREF1
Comparator B3 operation enable bit 0: Comparator B3 operation disabled
1: Comparator B3 operation enabled
Reserved bits
Set to 0.
—
—
INT3COUT Comparator B3 monitor flag
0: IVCMP3 < IVREF3
or comparator B3 operation disabled
1: IVCMP3 > IVREF3
R/W
R/W
R/W
R
R/W
R/W
R
External Input Enable Register 0 (INTEN)
Address 01FAh
Bit
b7
Symbol INT3PL
After Reset
0
b6
INT3EN
0
b5
—
0
b4
—
0
Bit
b0
Symbol
Bit Name
INT0EN INT0 input enable bit
b1
INT0PL INT0 input polarity select bit (1, 2)
b2
INT1EN INT1 input enable bit
b3
INT1PL INT1 input polarity select bit (1, 2)
b4
b5
b6
—
Reserved bits
—
INT3EN INT3 input enable bit
b7
INT3PL INT3 input polarity select bit (1, 2)
b3
INT1PL
0
b2
INT1EN
0
b1
INT0PL
0
Function
0: Disabled
1: Enabled
0: One edge
1: Both edges
0: Disabled
1: Enabled
0: One edge
1: Both edges
Set to 0.
0: Disabled
1: Enabled
0: One edge
1: Both edges
b0
INT0EN
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. To set the INTiPL bit (i = 0, 1, 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge
selected).
2. The IR bit in the INTiIC register may be set to 1 (interrupt requested) if the INTiPL bit is rewritten. Refer to 11.8.4
Changing Interrupt Sources.
REJ09B0458-0010 Rev.0.10
Page 473 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29.2.3
29. Comparator B
INT Input Filter Select Register 0 (INTF)
Address 01FCh
Bit
b7
Symbol INT3F1
After Reset
0
b6
INT3F0
0
b5
—
0
Bit
b0
b1
Symbol
Bit Name
INT0F0 INT0 input filter select bit
INT0F1
b2
b3
INT1F0 INT1 input filter select bit
INT1F1
b4
b5
b6
b7
—
Reserved bits
—
INT3F0 INT3 input filter select bit
INT3F1
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b4
—
0
b3
INT1F1
0
b2
INT1F0
0
b1
INT0F1
0
Function
b1 b0
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
b3 b2
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
Set to 0.
b7 b6
0 0: No filter
0 1: Filter with f1 sampling
1 0: Filter with f8 sampling
1 1: Filter with f32 sampling
b0
INT0F0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29.3
29. Comparator B
Functional Description
Comparator B1 and comparator B3 operate independently. Their operations are the same.
Table 29.3 lists the Procedure for Setting Registers Associated with Comparator B.
Table 29.3
Procedure for Setting Registers Associated with Comparator B
Step Register
Bit
Setting Value
1
Select the function of pins IVCMPi and IVREFi. Refer to 7.5 Port Settings.
However, set registers and bits other than listed in step 2 and the following steps.
2
INTF
Select whether to enable or disable the filter.
Select the sampling clock.
3
INTCMP
INTiCP0
1 (operation enabled)
4
Wait for comparator stability time (TBD µs max.)
5
INTEN
INTiEN
When using an interrupt: 1 (interrupt enabled)
INTiPL
When using an interrupt: Select the input polarity.
6
INTiIC
ILVL2 to ILVL0
When using an interrupt: Select the interrupt priority level.
IR
When using an interrupt: 0 (no interrupt requested: initialization)
i = 1 or 3
Figure 29.2 shows an Operating Example of Comparator Bi (i = 1 or 3).
If the analog input voltage is higher than the reference input voltage, the INTiCOUT bit in the INTCMP register
is set to 1. If the analog input voltage is lower than the reference input voltage, the INTiCOUT bit is set to 0. To
use the comparator Bi interrupt, set the INTiEN bit in the INTEN register to 1 (interrupt enabled). If the
comparison result changes at this time, a comparator Bi interrupt request is generated. Refer to 29.4
Comparator B1 and Comparator B3 Interrupts for details of interrupts.
Analog input voltage (V)
Reference input voltage
0
INTiCOUT bit in
INTCMP register
1
0
Set to 0 by a program.
IR bit in
INTiIC register
1
0
The above applies when:
Bits INTiF1 to INTiF0 in INTF register = 00b (no filter)
INTiPL bit in the INTEN register = 0 (both edges)
i = 1 or 3
Figure 29.2
Operating Example of Comparator Bi (i = 1 or 3)
REJ09B0458-0010 Rev.0.10
Page 475 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29.3.1
29. Comparator B
Comparator Bi Digital Filter (i = 1 or 3)
Comparator Bi can use the same digital filter as the INTi input. The sampling clock can be selected by bits
INTiF1 and INTiF0 in the INTF register. The INTiCOUT signal output from comparator Bi is sampled every
sampling clock. When the level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt
requested).
Figure 29.3 shows a Configuration of Comparator Bi Digital Filter, and Figure 29.4 shows an Operating
Example of Comparator Bi Digital Filter.
INTiF1 to INTiF0
f1
f8
f32
= 01b
= 10b
Sampling clock
= 11b
INTiEN
INTiCP0 = 0
INTi
Digital filter
(match 3 times)
Port direction register
INTiCP0 = 1
INTiF1 to INTiF0
= other than 00b
= 00b
INTiCOUT
IVCMPi
+
IVREFi
-
To INTi interrupt
INTiPL = 0
Both edge
detection
circuit
INTiPL = 1
i = 1 or 3
INTiCP0, INTiCOUT: Bits in INTCMP register
INTiF0 to INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
Figure 29.3
Configuration of Comparator Bi Digital Filter
INTiCOUT signal
Sampling timing
IR bit in
INTiIC register
Set to 0 by a program.
Note:
The above applies when:
Bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter used).
i =1 or 3
Figure 29.4
Operating Example of Comparator Bi Digital Filter
REJ09B0458-0010 Rev.0.10
Page 476 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
29.4
29. Comparator B
Comparator B1 and Comparator B3 Interrupts
Comparator B generates an interrupt request from two sources, comparator B1 and comparator B3. The
comparator Bi (i = 1 or 3) interrupt uses the same INTiIC register (bits IR and ILVL0 to ILVL2) as the INTi (i
= 1 or 3) and a single vector.
To use the comparator Bi interrupt, set the INTiEN bit in the INTEN register to 1 (interrupt enabled). In
addition, the polarity can be selected by the INTiPL bit in the INTEN register and the POL bit in the INTiIC
register.
Inputs can also be passed through the digital filter with three different sampling clocks.
REJ09B0458-0010 Rev.0.10
Page 477 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30. Flash Memory
The flash memory can perform in the following three rewrite modes: CPU rewrite mode, standard serial I/O mode, and
parallel I/O mode.
30.1
Overview
Table 30.1 lists the Flash Memory Version Performance. (Refer to Table 1.1 and Table 1.2 R8C/32A Group
Specifications for items not listed in Table 30.1.)
Table 30.1
Flash Memory Version Performance
Item
Flash memory operating mode
Division of erase blocks
Programming method
Erasure method
Programming and erasure control method (1)
Rewrite control
Blocks 0 to 2
method
(Program ROM)
Blocks A, B, C, and D
(Data flash)
Number of commands
Blocks 0 to 2
Programming and
erasure endurance (2) (Program ROM)
Blocks A, B, C, and D
(Data flash)
ID code check function
ROM code protection
Specification
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Refer to Figure 30.1.
Byte units
Block erase
Program and erase control by software commands
Rewrite protect control in block units by the lock bit
Individual rewrite protect control on blocks A, B, C, and D
by bits FMR14, FMR15, FMR16, and FMR17 in the FMR1 register
8 commands
1,000 times
10,000 times
Standard serial I/O mode supported
Parallel I/O mode supported
Notes:
1. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
2. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When
performing 100 or more rewrites, the actual erase count can be reduced by executing program operations in
such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to
retain data on the erase count of each block and limit the number of erase operations to a certain number.
Table 30.2
Flash Memory Rewrite Mode
Flash Memory
Rewrite Mode
Function
CPU Rewrite Mode
User ROM area is rewritten by
executing software commands
from the CPU.
Rewritable area
User ROM
Rewrite programs User program
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Standard Serial I/O Mode
User ROM area is rewritten
using a dedicated serial
programmer.
User ROM
Standard boot program
Parallel I/O Mode
User ROM area is rewritten
using a dedicated parallel
programmer.
User ROM
–
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.2
30. Flash Memory
Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area).
Figure 30.1 show the R8C/32A Group Flash Memory Block Diagrams.
The user ROM area contains program ROM and data flash.
Program ROM: Flash memory mainly used for storing programs
Data flash:
Flash memory mainly used for storing data to be rewritten
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode,
standard serial I/O mode, or parallel I/O mode.
The rewrite control program (standard boot program) for standard serial I/O mode is stored in the boot ROM area
before shipment. The boot ROM area is allocated separately from the user ROM area.
ROM 8 KB product
ROM 4 KB product
03000h
Block A: 1 Kbyte
03000h
Block A: 1 Kbyte
ROM 16 KB product
03000h
Block A: 1 Kbyte
Block B: 1 Kbyte
Block B: 1 Kbyte
Block B: 1 Kbyte
Block C: 1 Kbyte
Block C: 1 Kbyte
Block C: 1 Kbyte
Data flash
03FFFh
Block D: 1 Kbyte
03FFFh
Block D: 1 Kbyte
03FFFh
Block D: 1 Kbyte
0C000h
0F000h
0F7FFh
0F800h
0FFFFh
Block 1: 2 Kbytes
Block 0: 2 Kbytes
User ROM area
Figure 30.1
0E000h
0EFFFh
0F000h
0F7FFh
0F800h
0FFFFh
Block 2: 8 Kbytes
Block 2: 4 Kbytes
Block 1: 2 Kbytes
Block 0: 2 Kbytes
0E000h
0F000h
0FFFFh
User ROM area
R8C/32A Group Flash Memory Block Diagram
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Block 1: 4 Kbytes
Block 0: 4 Kbytes
User ROM area
Program ROM
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.3
30. Flash Memory
Functions to Prevent Flash Memory from being Rewritten
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
30.3.1
ID Code Check Function
The ID code check function is used in standard serial I/O mode. Unless 3 bytes (addresses 0FFFCh to 0FFFEh)
of the reset vector are set to FFFFFFh, the ID codes sent from the serial programmer or the on-chip debugging
emulator and the 7-byte ID codes written in the flash memory are checked to see if they match. If the ID codes
do not match, the commands sent from the serial programmer or the on-chip debugging emulator are not
accepted. For details of the ID code check function, refer to 12. ID Code Areas.
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Under development
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.3.2
30. Flash Memory
ROM Code Protect Function
The ROM protect function prevents the contents of the flash memory from being read, rewritten, or erased
using the OFS register in parallel I/O mode.
Refer to 13. Option Function Select Area for details of the OFS register.
The ROM code protect function is enabled by writing 1 to the ROMCR bit and writing 0 to the ROMCP1 bit.
This prevents the contents of the on-chip flash memory from being read or rewritten.
Once ROM code protection is enabled, the content of the internal flash memory cannot be rewritten in parallel
I/O mode. To disable ROM code protection, erase the block including the OFS register using CPU rewrite
mode or standard serial I/O mode.
30.3.3
Option Function Select Register (OFS)
Address 0FFFFh
Bit
b7
Symbol CSPROINI
When shipping
1
b6
LVDAS
1
b5
b4
b3
b2
VDSEL1 VDSEL0 ROMCP1 ROMCR
1
1
1
1
Bit
b0
Symbol
Bit Name
WDTON Watchdog timer start select bit
b1
b2
—
Reserved bit
ROMCR ROM code protect disable bit
b3
ROMCP1 ROM code protect bit
b4
b5
VDSEL0 Voltage detection 0 level select bit (2)
VDSEL1
b6
b7
LVDAS
Voltage detection 0 circuit start bit (3)
CSPROINI Count source protection mode
after reset select bit
b1
—
1
b0
WDTON
1
(Note 1)
Function
0: Watchdog timer automatically starts after reset.
1: Watchdog timer is stopped after reset.
Set to 1.
0: ROM code protect disabled
1: ROMCP1 bit enabled
0: ROM code protect enabled
1: ROM code protect disabled
R/W
R/W
b5 b4
R/W
R/W
0 0: 3.80 V selected (Vdet0_3)
0 1: 2.85 V selected (Vdet0_2)
1 0: 2.35 V selected (Vdet0_1)
1 1: 1.90 V selected (Vdet0_0)
0: Voltage monitor 0 reset enabled after reset
1: Voltage monitor 0 reset disabled after reset
0: Count source protect mode enabled after reset
1: Count source protect mode disabled after reset
R/W
R/W
R/W
R/W
R/W
Notes:
1. If the block including the OFS register is erased, the OFS register value is set to FFh.
2. The same level of the voltage detection 0 level selected by bits VDSEL0 and VDESL1 is set in both functions of
voltage monitor 0 reset and power-on reset.
3. To use power-on reset, set the LVDAS bit to 0 (voltage monitor 0 reset enabled after reset).
The OFS register is allocated in the flash memory. Write to this register with a program.
After writing, do not write additions to this register.
LVDAS Bit (Voltage Detection 0 Circuit Start Bit)
The Vdet0 voltage to be monitored by the voltage detection 0 circuit is selected by bits VDSEL0 and VDSEL1.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4
30. Flash Memory
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
The flash module has an erase-suspend function which halts the erase operation temporarily during an erase
operation in CPU rewrite mode. During erase-suspend, the user ROM area can be read by a program.
Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode.
Table 30.3 lists the Differences between EW0 Mode and EW1 Mode.
Table 30.3
Differences between EW0 Mode and EW1 Mode
Item
Operating mode
Rewrite control program
allocatable area
Rewrite control program
executable areas
Rewritable area
EW0 Mode
Single-chip mode
User ROM
EW1 Mode
Single-chip mode
User ROM
RAM (The rewrite control program must User ROM or RAM
be transferred before being executed.)
However, the program can be executed
in the program ROM area when rewriting
the data flash area.
User ROM
However, blocks which contain the
rewrite control program are excluded.
Software command
Read status register command cannot be • Program and block erase commands
restrictions
executed.
cannot be executed to any block which
contains the rewrite control program.
• Read status register command
cannot be executed.
Mode after program or block Read array mode
Read array mode
erase
CPU state during
The CPU operates.
• The CPU operates while the data flash
programming and
area is being programmed or block
block erasure
erased.
• The CPU is put in a hold state while the
program ROM area is being programmed
or block erased. (I/O ports retain the state
before the command execution).
Flash memory
Read bits FST7, FMT5, and FMT4 in
Read bits FST7, FMT5, and FMT4 in
status detection
the FST register by a program.
the FST register by a program.
Conditions for entering
• Set bits FMR20 and FMR21 in the
• Set bits FMR20 and FMR21 in the FMR2
program-suspend
FMR2 register to 1 by a program.
register to 1 by a program (while rewriting
• Set bits FMR20 and FMR22 in the
the data flash area).
FMR2 register to 1 and the enabled
• Set bits FMR20 and FMR22 in the FMR2
maskable interrupt is generated.
register to 1 and the enabled maskable
interrupt is generated.
CPU clock
20 MHz
20 MHz
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User ROM
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.1
30. Flash Memory
Flash Memory Status Register (FST)
Address 01B2h
Bit
b7
Symbol FST7
After Reset
1
Bit
b0
b1
b2
b6
FST6
0
b5
FST5
0
b4
FST4
0
b3
—
0
b2
LBDATA
X
b1
BSYAEI
0
Symbol
Bit Name
RDYSTI Flash ready status interrupt request
flag (1)
BSYAEI Flash access error interrupt request
flag (2)
LBDATA LBDATA monitor flag
b3
b4
—
FST4
b5
FST5
b6
FST6
b7
FST7
b0
RDYSTI
0
Function
0: No flash ready status interrupt request
1: Flash ready status interrupt request
0: No flash access error interrupt request
1: Flash access error interrupt request
0: Locked
1: Not locked
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
0: No program error
Program error status flag (3)
1: Program error
(3)
0: No erase error
Erase error status flag
1: Erase error
Erase-suspend status flag
0: Other than erase-suspend
1: During erase-suspend
Ready/busy status flag
0: Busy
1: Ready
R/W
R/W
R/W
R
—
R
R
R
R
Notes:
1. The RDYSTI bit cannot be set to 1 (flash ready status interrupt request) by a program. In parallel I/O mode, this
bit is fixed to 0 (no flash ready status interrupt request).
2. The BSYAEI bit cannot be set to 1 (flash access error interrupt request) by a program. In parallel I/O mode, this
bit is fixed to 0 (no flash access error interrupt request).
3. This bit is also set to 1 (error) when a command error occurs.
RDYSTI Bit (Flash Ready Status Flag Interrupt Request Flag)
When the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled) and autoprogramming or auto-erasure completes, or erase-suspend mode is entered, the RDYSTI bit is set to 1 (flash
ready status interrupt request).
During interrupt handling, set the RDYSTI bit to 0 (no flash ready status interrupt request).
[Condition for setting to 0]
Set to 0 by an interrupt handling program.
[Condition for setting to 1]
When the flash memory status changes from busy to ready while the RDYSTIE bit in the FRMR0 register is set
to 1, the RDYSTI bit is set to 1.
The status is changed from busy to ready by the following operations: erasing/writing to the flash memory,
suspend acknowledgement, forcible termination, completion of the lock bit program, and completion of the
read lock bit status.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
BYSAEI Bit (Flash Access Error Interrupt Request Flag)
The BYSAEI bit is set to 1 (flash access error interrupt request) when the BSYAEIE bit in the FMR0 register is
set to 1 (flash access error interrupt enabled) and the block during auto-programming/auto-erasure is accessed.
This bit is also set to 1 if an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to
1 (erase/write error interrupt enabled).
During interrupt handling, set the BSYAEI bit to 0 (no flash access error interrupt request).
[Conditions for setting to 0]
(1) Set to 0 by an interrupt handling program.
(2) Execute the status clear instruction.
[Conditions for setting to 1]
(1) Read or write the area that is being erased/written when the BSYAEIE bit in the FRMR0 register is set to 1
and while the flash memory is busy.
Or, read the data flash area while erasing/writing to the program ROM area. (Note that the read value is
undefined in both cases. Writing has no effect.)
(2) If an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to 1 (erase/write
error interrupt enabled).
LBDATA Bit (LBDATA Monitor Flag)
This is a read-only bit indicating the lock bit status. To confirm the lock bit status, execute the read lock bit
status command and read the LBDATA bit after the FST7 bit is set to 1 (ready).
The condition for updating this bit is when the program, erase, read lock bit status commands are generated.
When the read lock bit status command is input, the FST7 bit is set to 0 (busy). At the time when the FST7 bit
is set to 1 (ready), the lock bit status is stored in the LBDATA bit. The data in the LBDATA bit is retained until
the next command is input.
FST4 Bit (Program Error Status Flag)
This is a read-only bit indicating the auto-programming status. The bit is set to 1 if a program error occurs;
otherwise, it is set to 0. For details, refer to the description in 30.4.17 Full Status Check.
FST5 Bit (Erase Error Status Flag)
This is a read-only bit indicating the status of auto-programming or the blank check command. The bit is set to
1 if an erase error or blank check error occurs; otherwise, it is set to 0. Refer to 30.4.17 Full Status Check for
details.
FST6 Bit (Erase Suspend Status Flag)
This is a read-only bit indicating the suspend status. The bit is set to 1 when an erase-suspend request is
acknowledged and a suspend status is entered; otherwise, it is set to 0.
FST7 Bit (Ready/Busy Status Flag)
This is a read-only bit indicating the operating status of the flash memory. The bit is set to 0 during program and
erase operations; otherwise, it is set to 1.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.2
30. Flash Memory
Flash Memory Control Register 0 (FMR0)
Address 01B4h
Bit
b7
b6
b5
b4
Symbol RDYSTIE BSYAEIE CMDERIE CMDRST
After Reset
0
0
0
0
Bit
b0
b1
Symbol
—
FMR01
b2
FMR02
b3
FMSTP
b4
CMDRST
b5
CMDERIE
b6
BSYAEIE
b7
RDYSTIE
b3
FMSTP
0
b2
FMR02
0
Bit Name
Reserved bit
CPU rewrite mode select bit (1)
b1
FMR01
0
b0
—
0
Function
Set to 0.
0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
0: EW0 mode
EW1 mode select bit (1)
1: EW1 mode
(2)
0: Flash memory operates
Flash memory stop bit
1: Flash memory stops
(Low-power consumption state, flash memory
initialization)
When the CMDRST bit is set to 1, the erase/write
Erase/write sequence reset bit (3)
sequence is reset and erasure/writing can be
forcibly stopped.
When read, the content is 0.
Erase/write error interrupt enable bit 0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
Flash access error interrupt enable bit 0: Flash access error interrupt disabled
1: Flash access error interrupt enabled
Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
1: Flash ready status interrupt enabled
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes:
1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and
writing 1.
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in
the FST register is set to 1 (ready).
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
FST register is set to 0 (busy).
FMR01 Bit (CPU Rewrite Mode Select Bit)
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software
commands.
FMR02 Bit (EW1 Mode Select Bit)
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
FMSTP Bit (Flash Memory Stop Bit)
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Write to the FMSTP bit by a program transferred to the RAM.
To reduce the power consumption further in high-speed on-chip oscillator mode, low-speed on-chip oscillator
mode (XIN clock stopped), and low-speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to
31.2.10 Stopping Flash Memory for details.
When entering stop mode or wait mode while CPU rewrite mode is disabled, the FMR0 register does not need
to be set because the power for the flash memory is automatically turned off and is turned back on when exiting
stop or wait mode.
CMDRST Bit (Erase/Write Sequence Reset Bit)
This bit is used to initialize the flash memory sequence and forcibly stop a program or erase command. The user
ROM area can be read while the flash memory sequence is being initialized.
For addresses and blocks which the program or erase command is forcibly stopped by the CMDRST bit,
execute a block erasure again and ensure it completes normally.
The time from when the command is forcibly stopped and until reading is enabled is some hundreds µs where
the suspend response time is 10 ms.
CMDERIE Bit (Erase/Write Interrupt Enable Bit)
This bit enables an flash command error interrupt to be generated if a program or block erase error occurs. If the
CMDERIE bit is set to 1 (erase/write error interrupt enabled) and erasure/writing is performed, an interrupt is
generated if an erase or program error occurs.
If a flash command error interrupt is generated, execute the clear status register command during interrupt
handling.
BSYAEIE Bit (Flash Access Error Interrupt Enable Bit)
This bit enables a flash access error interrupt to be generated if the flash memory during rewriting is accessed.
RDYSTIE Bit (Flash Ready Status Interrupt Enable Bit)
This bit enables a flash ready status error interrupt to be generated when the status of the flash memory
sequence changes from the busy to ready status.
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R8C/32A Group
30.4.3
Flash Memory Control Register 1 (FMR1)
Address 01B5h
Bit
b7
Symbol FMR17
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
30. Flash Memory
b6
FMR16
0
b5
FMR15
0
b4
FMR14
0
b3
FMR13
0
b2
FMR12
0
b1
FMR11
0
b0
FMR10
0
Symbol
Bit Name
Function
FMR10 Nothing is assigned. If necessary, set to 0. When read, the content is 0.
FMR11
FMR12
FMR13 Lock bit disable select bit (1)
0: Lock bit enabled
1: Lock bit disabled
FMR14 Data flash block A rewrite
0: Rewrite enabled (software command acceptable)
1: Rewrite disabled (software command not acceptable,
disable bit (2)
no error occurred)
0: Rewrite enabled (software command acceptable)
FMR15 Data flash block B rewrite
1: Rewrite disabled (software command not acceptable,
disable bit (2)
no error occurred)
0: Rewrite enabled (software command acceptable)
FMR16 Data flash block C rewrite
1: Rewrite disabled (software command not acceptable,
disable bit (2)
no error occurred)
0: Rewrite enabled (software command acceptable)
FMR17 Data flash block D rewrite
1: Rewrite disabled (software command not acceptable,
disable bit (2)
no error occurred)
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
Notes:
1. To set the FMR13 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0
and writing 1.
2. To set this bit to 0, first write 1 and then 0 immediately. Do not generate an interrupt between writing 1 and
writing 0.
FMR13 Bit (Lock Bit Disable Select Bit)
When the FMR13 bit is set to 1 (lock bit disabled), the lock bit is disabled. When the FMR13 bit is set to 0, the
lock bit is enabled. Refer to 30.4.10 Data Protect Function for the details of the lock bit.
The FMR13 bit enables the lock bit function only and the lock bit data does not change. However, when a block
erase command is executed while the FMR13 bit is set to 1, the lock bit data set to 0 (locked) changes to 1 (not
locked) after erasure completes.
[Conditions for setting to 0]
The FMR13 bit is set to 0 when one of the following conditions is met.
• Completion of the program command
• Completion of the erase command
• Generation of a command error
• If the FMR01 bit in the FMR0 register is set to 0 (CPU rewrite mode disabled).
• If the FMSTP bit in the FMR0 register is set to 1 (flash memory stops).
• If the CMDRST bit in the FMR0 register is set to 1 (erasure/writing stopped).
[Condition for setting to 1]
Set to 1 by a program.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
FMR14 Bit (Data Flash Block A Rewrite Disable Bit)
When the FMR 14 bit is set to 0, data flash block A accepts program and block erase commands.
FMR15 Bit (Data Flash Block B Rewrite Disable Bit)
When the FMR 15 bit is set to 0, data flash block B accepts program and block erase commands.
FMR16 Bit (Data Flash Block C Rewrite Disable Bit)
When the FMR 16 bit is set to 0, data flash block C accepts program and block erase commands.
FMR17 Bit (Data Flash Block D Rewrite Disable Bit)
When the FMR 17 bit is set to 0, data flash block D accepts program and block erase commands.
REJ09B0458-0010 Rev.0.10
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.4
Flash Memory Control Register 2 (FMR2)
Address 01B6h
Bit
b7
Symbol FMR27
After Reset
0
Bit
b0
b1
b2
b3
b4
b5
b6
b7
30. Flash Memory
b6
—
0
b5
—
0
b4
—
0
b3
—
0
b2
FMR22
0
b1
FMR21
0
Symbol
Bit Name
FMR20 Erase-suspend enable bit (1)
b0
FMR20
0
Function
0: Erase-suspend disabled
1: Erase-suspend enabled
FMR21 Erase-suspend request bit
0: Erase restart
1: Erase-suspend request
0: Erase-suspend request disabled by interrupt request
FMR22 Interrupt request suspend
1: Erase-suspend request enabled by interrupt request
request enable bit (1)
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
Reserved bits
Set to 0.
—
—
0: Low-consumption-current read mode disabled
FMR27 Low-consumption-current
1: Low-consumption-current read mode enabled
read mode enable bit (1)
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Note:
1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and
writing 1.
FMR20 Bit (Erase-Suspend Enable Bit)
When the FMR20 bit is set to 1 (enabled), the erase-suspend function is enabled.
FMR21 Bit (Erase-Suspend Request Bit)
When the FMR21 bit is set to 1, erase-suspend mode is entered. If the FMR22 bit is set to 1 (erase-suspend
request enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request) when an
interrupt request for the enabled interrupt is generated, and erase-suspend mode is entered. To restart autoerasure, set the FMR21 bit to 0 (erase restart).
[Condition for setting to 0]
Set to 0 by a program.
[Conditions for setting to 1]
• When the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request) at the time an interrupt is
generated.
• Set to 1 by a program.
FMR22 Bit (Interrupt Request Suspend-Request Enable Bit)
When the FMR 22 bit is set to 1 (erase-suspend request enabled by interrupt request), the FMR21 bit is
automatically set to 1 (erase-suspend request) at the time an interrupt request is generated during auto-erasure.
Set the FMR22 bit to 1 when using erase-suspend while rewriting the user ROM area in EW1 mode.
FMR27 Bit (Low-Power-Current Read Mode Enable Bit)
When the FMR 27 bit is set to 1 (low-consumption-current read mode enabled) in low-speed clock mode (XIN
clock stopped) or low-speed on-chip oscillator mode (XIN clock stopped), power consumption when reading
the flash memory can be reduced. Refer to 31.2.11 Low-Current-Consumption Read Mode for details.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.5
30. Flash Memory
EW0 Mode
When the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), the MCU enters CPU
rewrite mode and software commands can be accepted. At this time, the FMR02 bit in the FMR0 register is set
to 0 so that EW0 mode is selected.
Software commands are used to control program and erase operations. The FST register or the status register
can be used to confirm whether programming or erasure has completed.
To enter erase-suspend during auto-erasure, set the FMR20 bit to 1 (erase-suspend enabled) and the FMR21 bit
to 1 (erase-suspend request). Wait for td(SR-SUS) and ensure that the FST6 bit in the FST register is set to 1
(during erase-suspend) before accessing the flash memory. Auto-erasure can be restarted by setting the FMR21
bit in the FMR2 register to 0 (erase restart).
30.4.6
EW1 Mode
After the FMR01 bit in the FMR0 register is set to 1 (CPU rewrite mode enabled), EW1 mode is selected by
setting the FMR02 bit is set to 1.
The FST register can be used to confirm whether programming and erasure has completed. Do not execute the
read status register command in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR20 bit in the FMR2 register to 1 (suspend enabled). To enter erase-suspend while auto-erasing the user
ROM area, set the FMR22 bit in the FMR2 register to 1 (erase-suspend request enabled by interrupt request).
Also, the interrupt to enter program-suspend must be enabled beforehand.
When an interrupt request is generated, the FMR21 bit in the FMR2 register is automatically set to 1 (erasesuspend request) and auto-erasure suspends after td(SR-SUS). After interrupt handling completes, set the
FMR21 bit to 0 (erase restart) to restart auto-erasure.
30.4.7
Suspend Operation
Figure 30.2 shows the Suspend Operation Timing.
User ROM
Suspend
(readable)
Erase
Data ROM
User
program
Command
issue
User
program
FMR21 bit in
FMR2 register
Set
FMR21
bit to 1
Data
read
Flash ready
interrupt
handling
User
program
Suspend
(readable)
Program
Suspend
(readable)
Erase
Command
issue
User
program
Flash ready
Set
interrupt
FMR21
handling
bit to 0
User
program
Flash ready
interrupt
handling
User
program
td(SR-SUS)
FST7 bit in
FST register
1 is set automatically.
FST6 bit in
FST register
1 is set automatically.
1 is set automatically.
RDYSTI bit in
FST register
Set to 0 by a program.
Figure 30.2
Suspend Operation Timing
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Set to 0 by a program.
Set to 0 by a program.
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.8
30. Flash Memory
How to Set and Exit Each Mode
Figure 30.3 shows How to Set and Exit EW0 Mode and Figure 30.4 shows How to Set and Exit EW0 Mode
(When Rewriting Data Flash) and EW1 Mode.
EW0 Mode Execution Procedure
(When Rewriting User ROM)
Rewrite control program
After writing 0 to the FMR01 bit,
write 1 (CPU rewrite mode enabled) (1)
Transfer the rewrite mode program that uses
CPU rewrite mode to the RAM
Execute software commands
Write 0 (CPU rewrite mode disabled) to
the FMR01 bit
Jump to the rewrite control program transferred
to the RAM
(The subsequent process is executed by the
rewrite control program in the RAM)
Jump to the specified address in the flash memory
FMR01: Bit in FMR0 register
Note:
To set the FMR01 bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and writing 1.
Writing to the FMR01 bit must be performed in the RAM.
Figure 30.3
How to Set and Exit EW0 Mode
EW0 Mode Execution Procedure (When Rewriting Data Flash)
EW1 Mode Execution Procedure
Program in ROM
After writing 0 to the FMR01 bit,
write 1 (CPU rewrite mode enabled) (1)
After writing 0 to the FMR02 bit,
write 1 (EW1 mode) (2)
Execute software commands
Write 0 (CPU rewrite mode disabled) to
the FMR01 bit
FMR01, FMR02: Bits in FMR0 register
Notes:
1. To set the FMR01 bit to 1, first write 0 and then 1 immediately.
Do not generate an interrupt between writing 0 and writing 1.
2. Not required when rewriting the data flash in EW0 mode.
Figure 30.4
How to Set and Exit EW0 Mode (When Rewriting Data Flash) and EW1 Mode
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.4.9
30. Flash Memory
BGO (BackGround Operation) Function
When the program ROM area is specified while a program or block erase operation to the data flash, array data
can be read. This eliminates the need for writing software commands. Access time is the same as for normal
read operations.
Figure 30.5 shows the BGO Function.
Time
Data flash
Erase/program
Program ROM
Figure 30.5
Read
BGO Function
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Read
Read
Read
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.10 Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR13 bit in
the FMR1 register is set to 0 (lock bit enabled). The lock bit can be used to disable (lock) programming or
erasing each block. This prevents data from being written or erased inadvertently. A block status changes
according to the lock bit as follows:
• When the lock bit data is set to 0: locked (the block cannot be programmed or erased)
• When the lock bit data is set to 1: not locked (the block can be programmed and erased)
The lock bit data is set to 0 (locked) by executing the lock bit program command and to 1 (not locked) by
erasing the block. No commands can be used to set only the lock bit data to 1.
The lock bit data can be read using the read lock bit status command.
When the FMR13 bit is set to 1 (lock bit disabled), the lock bit function is disabled and all blocks are not locked
(each lock bit data remains unchanged). The lock bit function is enabled by setting the FMR13 bit to 0 (the lock
bit data is retained).
When the block erase command is executed while the FMR13 bit is set to 1, the target block is erased regardless
of the lock bit status. The lock bit of the erase target block is set to 1 after auto-erasure completes.
Refer to 30.4.11 Software Commands for the details of individual commands.
The FMR13 bit is set to 0 after auto-erasure completes. This bit is also set to 0 if one of the following conditions
is met. To erase or program a different locked block, set the FMR 13 bit to 1 again and execute the block erase
or program command.
• If the FST7 bit in the FST register is changed from 0 (busy) to 1 (ready).
• If an incorrect command is input.
• If the FMR01 bit in the FMR0 register is set to 0 (CPU mode disabled).
• If the FMSTP bit in the FM0 register is set to 1 (flash memory stops).
Figure 30.6 shows the FMR13 Bit Operation Timing.
Erase start
Operation
Erase completion
Erase
FST7 bit
(Ready/busy status flag)
1
0
FMR13 bit
(Lock bit disable select bit)
1
0
0 is set at the rising edge of the FST7 bit.
Set to 1 by a program.
Lock bit enabled
FST7: Bit in FST register
FMR13: Bit in FMR1 register
Figure 30.6
FMR13 Bit Operation Timing
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11 Software Commands
The software commands are described below. Read or write commands and data in 8-bit units.
Table 30.4
Software Commands
Command
Read array
Read status register
Clear status register
Program
Block erase
Lock bit program
Read lock bit status
Block blank check
Mode
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
Address
×
×
×
WA
×
BT
×
×
Data
FFh
70h
50h
40h
20h
77h
71h
25h
Mode
Second Bus Cycle
Address
Data
Read
×
SRD
Write
Write
Write
Write
Write
WA
BA
BT
BT
BA
WD
D0h
D0h
D0h
D0h
SRD: Status register data
WA: Write address
WD: Write data
BA: Any block address
BT: Starting block address
×:
Any address in the user ROM area
30.4.11.1 Read Array Command
The read array command is used to read the flash memory.
When FFh is written in the first bus cycle, the MCU enters read array mode. When the read address is input in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since read array mode remains until another command is written, the contents of multiple addresses can be read
continuously.
In addition, the MCU enters read array mode after a reset.
30.4.11.2 Read Status Register Command
The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle. When reading
the status register, read the same address as the address value in the first bus cycle.
In CPU rewrite mode, do not execute this command.
Read status register mode remains until the next read array command is written.
30.4.11.3 Clear Status Register Command
The clear status register command is used to set the status register to 0.
When 50h is written in the first bus cycle, bits FST4 and FST5 in the FST register and bits SR4 and SR5 in the
status register are set to 0. If the clear status register is input in read array mode, the MCU enters read array
mode after the status register is set to 0.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11.4 Program Command
The program command is used to write data to the flash memory in 1-byte units.
When 40h is written in the first bus cycle and data is written in the second bus cycle to the write address, autoprogramming (data program and verify operation) starts. Make sure the address value specified in the first bus
cycle is the same address as the write address specified in the second bus cycle.
The FST7 bit in the FST register can be used to confirm whether auto-programming has completed. The FST7
bit is set to 0 during auto-programming and is set to 1 when auto-programming completes.
After auto-programming has completed, the auto-program result can be confirmed by the FST4 bit in the FST
register (refer to 30.4.17 Full Status Check).
Do not write additions to the already programmed addresses.
The program command targeting each block in the program ROM can be disabled using the lock bit.
The following commands are not accepted under the following conditions:
• Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1
(rewrite disabled).
• Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled).
Figure 30.7 shows a Program Flowchart (Flash Ready Status Interrupt Disabled) and Figure 30.8 shows a
Program Flowchart (Flash Ready Status Interrupt Enabled).
In EW1 mode, do not execute this command to any address where a rewrite control program is allocated.
When RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready status
interrupt can be generated upon completion of auto-programming. The auto-program result can be confirmed
by reading the FST register during the interrupt routine.
Start
Write the command code 40h
Write data to the write address
FST7 = 1?
No
Yes
Full status check
Program completed
Figure 30.7
FST7: Bit in FST register
Program Flowchart (Flash Ready Status Interrupt Disabled)
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R8C/32A Group
30. Flash Memory
Start
Flash ready status
interrupt
RDYSTIE = 1
Status check
Write the command code 40h
I = 1 (interrupt enabled)
RDYSTI = 0
REIT
Write data to the write address
Program completed
Figure 30.8
RDYSTI: Bit in FST register
RDYSTIE: Bit in FMR0 register
Program Flowchart (Flash Ready Status Interrupt Enabled)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11.5 Block Erase Command
When 20h is written in the first bus cycle and then D0h is written in the second bus cycle to any block address,
auto-erasure (erase and erase verify operation) starts in the specified block.
The FST7 bit in the FST register can be used to confirm whether auto-erasure has completed. The FST7 bit is
set to 0 during auto-erasure and is set to 1 when auto-erasure completes.
After auto-erasure has completed, the auto-erase result can be confirmed by the FST5 bit in the FST register.
(Refer to 30.4.17 Full Status Check).
The block erase command targeting each block in the program ROM can be disabled using the lock bit.
The following commands are not accepted under the following conditions:
• Block erase commands targeting data flash block A when the FMR14 bit in the FMR1 register is set to 1
(rewrite disabled).
• Block erase commands targeting data flash block B when the FMR15 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block C when the FMR16 bit is set to 1 (rewrite disabled).
• Block erase commands targeting data flash block D when the FMR17 bit is set to 1 (rewrite disabled).
Figure 30.9 shows a Block Erase Flowchart (Flash Ready Status Interrupt Disabled), Figure 30.10 shows a
Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled), and Figure 30.11 shows
a Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled).
In EW1 mode, do not execute this command to any block where a rewrite control program is allocated.
While the RDYSTIE bit in the FMR0 register is set to 1 (flash ready status interrupt enabled), a flash ready
status interrupt can be generated upon completion of auto-erasure. While the RDYSTIE bit is set to 1 and the
FMR20 bit in the FMR2 register is set to 1 (erase-suspend enabled), a flash ready status interrupt is generated
when the FMR21 bit is set to 1 (erase-suspend request) and auto-erasure suspends. The auto-erase result can be
confirmed by reading the FST register during the interrupt routine.
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R8C/32A Group
30. Flash Memory
Start
Write the command code 20h
Write D0h to any block address
FST7 = 1?
No
Yes
Full status check
Block erase completed
Figure 30.9
FST7: Bit in FST register
Block Erase Flowchart (Flash Ready Status Interrupt Disabled)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
Start
Maskable interrupt (1)
FMR20 = 1
FMR21 = 1 (2)
Write the command code 20h
FST6 = 1?
No
Yes
I = 1 (interrupt enabled)
Access the flash memory
Write D0h to any block address
FST7 = 1?
FMR21 = 0
No
REIT
Yes
Full status check
Block erase completed
I: Flag in CPU register
FST6, FST7: Bits in FST register
FMR20, FMR21: Bits in FMR2 register
Notes:
1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase target area.
2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1.
The interrupt to enter suspend must be enabled beforehand.
Figure 30.10
Block Erase Flowchart (Flash Ready Status Interrupt Disabled and Suspend Enabled)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
Start
Maskable interrupt (1)
RDYSTIE = 1
FMR21 = 1 (2)
FMR20 = 1
REIT
Write the command code 20h
I = 1 (interrupt enabled)
Write D0h to any block address
Block erase completed
Flash ready status
interrupt (1, 3)
FST6 = 1?
No
Yes
Access the flash memory
Full status check
FMR21 = 0
RDYSTI = 0
REIT
I: Flag in CPU register
RDYSTI, FST6: Bits in FST register
RDYSTIE: Bit in FMR0 register
FMR20, FMR21: Bits in FMR2 register
Notes:
1. The interrupt vector table and interrupt routine for interrupts to be used must be allocated to an area other the erase target area.
2. td(SR-SUS) is required until suspend is acknowledged after the FMR21 bit is set to 1.
The interrupt to enter suspend must be enabled beforehand.
3. When auto-erasure suspends, a flash ready status interrupt is generated.
Figure 30.11
Block Erase Flowchart (Flash Ready Status Interrupt Enabled and Suspend Enabled)
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11.6 Lock Bit Program Command
This command is used to set the lock bit of any block in the program ROM area to 0 (locked).
When 77h is written in the first bus cycle and D0h is written in the second bus cycle to the starting block
address, 0 is written to the lock bit of the specified block. Make sure the address value in the first bus cycle is
the same address as the starting block address specified in the second bus cycle.
Figure 30.12 shows a Lock Bit Program Flowchart. The lock bit status (lock bit data) can be read using the read
lock bit status command.
The FST7 bit in the FST register can be used to confirm whether writing to the lock bit has completed.
Refer to 30.4.10 Data Protect Function for the lock bit function and how to set the lock bit to 1 (not locked).
Start
Write the command code 77h
Write D0h to the starting
block address
FST7 = 1?
No
Yes
Full status check
Completed
Figure 30.12
Lock Bit Program Flowchart
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FST7: Bit in FST register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11.7 Read Lock Bit Status Command
This command is used to read the lock bit status of any address in the program ROM area.
When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the
lock bit status of the specified block is stored in the LBDATA bit in the FST register. After the FST7 bit in the
FST register has been set to 1 (ready), read the LBDATA bit.
Figure 30.13 shows a Read Lock Bit Status Flowchart.
Start
Write the command code 71h
Write D0h to the starting
block address
No
FST7 = 1?
Yes
No
LBDATA = 1?
Yes
Block not locked
Figure 30.13
Block locked
Read Lock Bit Status Flowchart
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LBDATA, FST7: Bits in FST register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.11.8 Block Blank Check Command
This command is used to confirm that all addresses in any block are blank data FFh.
When 25h is written in the first bus cycle and D0h is written in the second bus cycle to any block address, blank
checking starts in the specified block. The FST7 bit in the FST register can be used to confirm whether blank
checking has completed. The FST7 bit is set to 0 during the blank-check period and set to 1 when blank
checking completes.
After blank checking has completed, the blank-check result can be confirmed by the FST5 bit in the FST
register. (Refer to 30.4.17 Full Status Check.).
Figure 30.14 shows a Block Blank Check Flowchart.
Start
Write the command code 25h
Write D0h to the starting
block address
FST7 = 1?
No
Yes
No
FST5 = 0?
Yes
Blank
Figure 30.14
Not blank
Block Blank Check Flowchart
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FST5, FST7: Bits in FST register
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.12 Status Register
The status register indicates the operating status of the flash memory and whether erasure or programming has
completed normally or terminated in error. The status of the status register can be read by the FST register.
30.4.13 Sequence Status
The clear sequence status bit indicates the operating status of the flash memory. This bit is set to 0 (busy) during
auto-programming and auto-erasure. It is set to 1 (ready) when these operations complete.
30.4.14 Erase Status
Refer to 30.4.17 Full Status Check.
30.4.15 Program Status
Refer to 30.4.17 Full Status Check.
30.4.16 Suspend Status
The suspend status bit indicates the suspend status of the flash memory commands. This bit is set to 1 (during
erase-suspend) while auto-erasure suspends and set to 0 (other than erase-suspend) when auto-erasure restarts.
Table 30.5 lists the Status Register.
Table 30.5
Status Register
Status Register
Bit
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4)
FST Register
Bit
−
−
−
−
FST4
Reserved
Reserved
Reserved
Reserved
Program status
SR5 (D5)
FST5
SR6 (D6)
FST6
Erase status/
blank check
Suspend status
SR7 (D7)
FST7
Sequencer status
Status Name
Content
0
−
−
−
−
Completed
normally
Completed
normally
Other than
erase-suspend
Busy
1
−
−
−
−
Terminated
in error
Terminated
in error
During
erase-suspend
Ready
Value
After Reset
−
−
−
−
0
0
0
1
D0 to D7: Indicate the data bus which is read when the read status register command is executed.
Bits FST4 (SR4) and FST5 (SR5) are set to 0 by executing the clear status command.
When the FST4 bit (SR4) or FST5 bit (SR5) is set to 1, the program and block erase commands cannot be
accepted.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
30.4.17 Full Status Check
If an error occurs, bits FST4 and FST5 in the FST register are set to 1, indicating the occurrence of an error. The
execution result can be confirmed by checking these status bits (full status check).
Table 30.6 lists the Errors and FST Register Status. Figure 30.15 shows the Full Status Check and Handling
Procedure for Individual Errors.
Table 30.6
Errors and FST Register Status
FST Register
(Status Register) Status
Error
FST5 (SR5) FST4 (SR4)
1
1
Command
sequence error
1
0
0
1
Error Occurrence Condition
• When a command is not written correctly.
• When data other than valid data (i.e., D0h or FFh) is
written in the second bus cycle of the block erase
command (1).
Erase error
When the block erase command is executed, but autoerasure does not complete correctly.
Blank check error When the blank check command is executed and data
other than blank data FFh is read.
Program error
When the program command is executed, but autoprogramming does not complete correctly.
Note:
1. When FFh is written in the second bus cycle of these commands, the MCU enters read array mode.
At the same time, the command code written in the first bus cycle is invalid.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
Command sequence error
Execute the clear status register command
(Set the status flags to 0)
Check if the command is properly input
Full status check
FST4 = 1
and
FST5 = 1?
Re-execute the command
Yes
Command sequence error
No
FST5 = 1?
Erase error/
blank check error
Execute the clear status register command
(Set the status flags to 0)
Yes
Erase error/
blank check error
Is the lock bit disabled?
or
Is the command executed on
the data flash area?
No
Set FMR13 bit to 1
No
Yes
Erase command
Re-execution times ≤ 3 times?
No
The erasure target block
cannot be used
Yes
FST4 = 1?
Yes
Program error
Re-execute the block erase command
No
Program error
Execute the clear status register command
(Set the status flags to 0)
Full status check completed
Is the lock bit disabled?
or
Is the command executed on
the data flash area?
No
Set FMR13 bit to 1
Yes
Specify an address other than the write
address where the error occurs (1)
as the program address
Note:
1. To rewrite to the address where the program error occurs, ensure that
the full status check completes normally and write to the address
after the block erase command is executed.
Figure 30.15
Re-execute the program command
FST4, FST5: Bits in FST register
FMR13: Bits in FMR1 register
Full Status Check and Handling Procedure for Individual Errors
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30.5
30. Flash Memory
Standard Serial I/O Mode
In standard serial I/O mode, a serial programmer which supports the MCU can be used to rewrite the user ROM
area while the MCU is mounted on-board.
There are three types of standard serial I/O modes:
• Standard serial I/O mode 1 .................Clock synchronous serial I/O used to connect to a serial programmer
• Standard serial I/O mode 2 .................Clock asynchronous serial I/O used to connect to a serial programmer
• Standard serial I/O mode 3 .................Special clock asynchronous serial I/O used to connect to a serial
programmer
Standard serial I/O mode 2 and standard serial I/O mode 3 can be used for the MCU.
Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator for
examples of connecting to a serial programmer. Contact the serial programmer manufacturer for more information.
Refer to the user’s manual included with your serial programmer for instructions.
Table 30.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2) and Figure 30.16 shows Pin
Handling in Standard Serial I/O Mode 2. Table 30.8 lists the Pin Functions (Flash Memory Standard Serial I/O
Mode 3) and Figure 30.17 shows Pin Handling in Standard Serial I/O Mode 3.
After handling the pins shown in Table 30.8 and rewriting the flash memory using the programmer, apply a “H”
level signal to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
30.5.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match.
Refer to 12. ID Code Areas for details of the ID code check.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
30. Flash Memory
Table 30.7
Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin
VCC, VSS
Name
Power supply input
RESET
P4_6/XIN/(XCIN)
P4_7/XOUT/(XCOUT)
P1_0 to P1_3,
P1_6, P1_7
P3_3 to P3_5, P3_7
P4_2/VREF, P4_5
MODE
P1_4
P1_5
Reset input
I/O
Description
Apply the guaranteed programming and erasure
voltage to the VCC pin and 0 V to the VSS pin.
Reset input pin
I
P4_6 input/clock input
I Connect a ceramic resonator or crystal oscillator
P4_7 input/clock output I/O between pins XIN(XCIN) and XOUT(XCOUT).
Input port P1
I Input a “H” or “L” level signal or leave open.
Input port P3
Input port P4
MODE
TXD output
RXD input
I
I
I/O
O
I
Input a “H” or “L” level signal or leave open.
Input a “H” or “L” level signal or leave open.
Input a “L” level signal.
Serial data output pin
Serial data input pin
MCU
Data output
VCC
TXD
AVCC
Data input
RXD
MODE
User reset signal
RESET
VSS
XIN/
(XCIN )
AVSS
XOUT/
(XCOUT)
Connect an oscillator (2)
Notes:
1. In this example, modes are switched between single-chip mode and standard serial I/O mode
by controlling the MODE input with a switch.
2. Always connect an oscillator. Set the main clock frequency to 1 MHz to 20 MHz.
Refer to Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806).
Figure 30.16
Pin Handling in Standard Serial I/O Mode 2
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 30.8
30. Flash Memory
Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin
VCC, VSS
Name
Power supply input
I/O
RESET
P4_6/XIN/(XCIN)
Reset input
I
P4_6 input/clock input
I
P1_0 to P1_7
P3_3 to P3_5, P3_7
P4_2/VREF, P4_5
MODE
Input port P1
Input port P3
Input port P4
MODE
Description
Apply the guaranteed programming and erasure
voltage to the VCC pin and 0 V to the VSS pin.
Reset input pin
If an external oscillator is connected, connect a
ceramic resonator or crystal oscillator between pins
XIN(XCIN) and XOUT(XCOUT).
P4_7/XOUT/(XCOUT) P4_7 input/clock output I/O To use as an input port, input a “H” or “L” level
signal or leave the pin open.
I
I
I
I/O
Input a “H” or “L” level signal or leave open.
Input a “H” or “L” level signal or leave open.
Input a “H” or “L” level signal or leave open.
Serial data I/O pin. Connect the pin to a
programmer.
MCU
MODE I/O
MODE
VCC
AVCC
Reset input
RESET
User reset signal
VSS
AVSS
Notes:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillation circuit.
Figure 30.17
Pin Handling in Standard Serial I/O Mode 3
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R8C/32A Group
30.6
30. Flash Memory
Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory.
Use a parallel programmer which supports the MCU. Contact the parallel programmer manufacturer for more
information. Refer to the user’s manual included with your parallel programmer for instructions.
In parallel I/O mode, the user ROM areas shown in Figure 30.1 can be rewritten.
30.6.1
ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten. (Refer to the 30.3.2
ROM Code Protect Function.)
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R8C/32A Group
30.7
30. Flash Memory
Notes on Flash Memory
30.7.1
CPU Rewrite Mode
30.7.1.1
Prohibited Instructions
The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode
because they reference data in the flash memory: UND, INTO, and BRK.
30.7.1.2
Non-Maskable Interrupts
Tables 30.9 and 30.10 show CPU Rewrite Mode Interrupts (1) and (2), respectively.
Table 30.9
Mode
EW0
Erase/
Write
Target
Data
flash
CPU Rewrite Mode Interrupts (1)
Status
Maskable Interrupt
• Address Match
• Address Break
(Note 1)
During auto-erasure
(suspend enabled)
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request),
the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request
disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The flash
memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit
to 0 (erase restart).
During auto-erasure
(suspend disabled
or FMR22 = 0)
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
During
auto-programming
Program During auto-erasure
ROM
(suspend enabled)
Usable by allocating a vector in RAM.
Not usable during auto-erasure or
auto-programming.
During auto-erasure
(suspend disabled)
During
auto-programming
EW1
Data
flash
During auto-erasure
(suspend enabled)
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1 during
interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21 bit
to 0.
During auto-erasure
(suspend disabled
or FMR22 = 0)
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
During
auto-programming
Program During auto-erasure
ROM
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Autoerasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes.
While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read.
Auto-erasure and auto-programming have priority and interrupt requests are put on
standby. Interrupt handling is executed after auto-erase and auto-program complete.
During
auto-programming
FMR21, FMR22: Bits in FMR2 register
Note:
1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0.
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R8C/32A Group
Table 30.10
Mode
EW0
Erase/
Write
Target
30. Flash Memory
CPU Rewrite Mode Interrupts (2)
Status
Data flash During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
•
•
•
•
•
Watchdog Timer
Oscillation Stop Detection
Voltage Monitor 2
Voltage Monitor 1
NMI
(Note 1)
•
•
•
•
Undefined Instruction
INTO Instruction
BRK Instruction
Single Step
(Note 1)
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request),
the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request
disabled by interrupt request), set the FMR 21 bit to 1 during interrupt handling. The
flash memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21
bit is set to 0 (erase restart).
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
During
auto-programming
Program
ROM
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled)
During
auto-programming
EW1
Data flash During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
Not usable during auto-erasure or
When an interrupt request is acknowledged,
auto-programming.
auto-erasure or auto-programming is forcibly
stopped immediately and the flash memory is
reset. Interrupt handling starts when the flash
memory restarts after the fixed period.
Since the block during auto-erasure or the
address during auto-programming is forcibly
stopped, the normal value may not be read. After
the flash memory restarts, execute auto-erasure
again and ensure it completes normally.
The watchdog timer does not stop during the
command operation, so interrupt requests may
be generated. Initialize the watchdog timer
regularly using the erase-suspend function.
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0, set the FMR 21 bit to 1
during interrupt handling. The flash memory suspends auto-programming after td(SRSUS).
While auto-erasure is being suspended, any block other than the block during autoerasure execution can be read. Auto-erasure can be restarted by setting the FMR21
bit is set to 0.
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
During
auto-programming
Program
ROM
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
Not usable during auto-erasure or
When an interrupt request is acknowledged,
auto-programming.
auto-erasure or auto-programming is forcibly
stopped immediately and the flash memory is
reset. Interrupt handling starts when the flash
memory restarts after the fixed period.
Since the block during auto-erasure or the
address during auto-programming is forcibly
stopped, the normal value may not be read. After
the flash memory restarts, execute auto-erasure
again and ensure it completes normally.
The watchdog timer does not stop during the
command operation, so interrupt requests may
be generated. Initialize the watchdog timer
regularly using the erase-suspend function.
FMR21, FMR22: Bits in FMR2 register
Note:
1. Do not use a non-maskable interrupt while block 0 is being auto-erased because the fixed vector is allocated in block 0.
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R8C/32A Group
30.7.1.3
30. Flash Memory
How to Access
To set one of the following bits to 1, first write 0 and then 1 immediately. Do not generate an interrupt between
writing 0 and writing 1.
• The FMR01 bit or FMR02 bit in the FMR0 register
• The FMR13 bit in the FMR1 register
• The FMR20 bit, FMR22 bit, or FMR 27 bit in the FMR2 register
To set one of the following bits to 0, first write 1 and then 0 immediately. Do not generate an interrupt between
writing 1 and writing 0.
• The FMR14 bit, FMR15 bit, FMR16 bit, or FMR17 bit in the FMR1 register
30.7.1.4
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
30.7.1.5
Programming
Do not write additions to the already programmed address.
30.7.1.6
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
If the FST7 in the FST register is set to 0 (busy (during programming or erasure execution), do not enter to stop
mode or wait mode.
30.7.1.7
Programming and Erasure Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
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R8C/32A Group
31. Reducing Power Consumption
31. Reducing Power Consumption
31.1
Overview
This chapter describes key points and processing methods for reducing power consumption.
31.2
Key Points and Processing Methods for Reducing Power Consumption
Key points for reducing power consumption are shown below. They should be referred to when designing a system
or creating a program.
31.2.1
Voltage Detection Circuit
If voltage monitor 1 and comparator A1 are not used, set the VCA26 bit in the VCA2 register to 0 (voltage
detection 1 circuit disabled). If voltage monitor 2 and comparator A2 are not used, set the VCA27 bit in the
VCA2 register to 0 (voltage detection 2 circuit disabled).
If the power-on reset and voltage monitor 0 reset are not used, set the VCA25 bit in the VCA2 register to 0
(voltage detection 0 circuit disabled).
31.2.2
Ports
Even after the MCU enters wait mode or stop mode, the states of the I/O ports are retained. Current flows into
the output ports in the active state, and shoot-through current flows into the input ports in the high-impedance
state. Unnecessary ports should be set to input and fixed to a stable electric potential before the MCU enters
wait mode or stop mode.
31.2.3
Clocks
Power consumption generally depends on the number of the operating clocks and their frequencies. The fewer
the number of operating clocks or the lower their frequencies, the more power consumption decreases.
Unnecessary clocks should be stopped accordingly.
Stopping low-speed on-chip oscillator oscillation: CM14 bit in CM1 register
Stopping high-speed on-chip oscillator oscillation: FRA00 bit in FRA0 register
31.2.4
Wait Mode, Stop Mode
Power consumption can be reduced in wait mode and stop mode. Refer to 9.7 Power Control for details.
31.2.5
Stopping Peripheral Function Clocks
If the peripheral function f1, f2, f4, f8, and f32 clocks are not necessary in wait mode, set the CM02 bit in the
CM0 register to 1 (peripheral function clock stops in wait mode). This will stop the f1, f2, f4, f8, and f32 clocks
in wait mode.
31.2.6
Timers
If timer RA is not used, set the TCKCUT bit in the TRAMR register to 1 (count source cutoff).
If timer RB is not used, set the TCKCUT bit in the TRBMR register to 1 (count source cutoff).
If timer RC is not used, set the MSTTRC bit in the MSTCR register to 1 (standby).
31.2.7
A/D Converter
When the A/D converter is not used, power consumption can be reduced by setting the ADSTBY bit in the
ADCON1 register to 0 (A/D operation stops (standby)) to shut off any analog circuit current flow.
31.2.8
Clock Synchronous Serial Interface
When the SSU or the I2C bus is not used, set the MSTIIC bit in the MSTCR register to 1 (standby).
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R8C/32A Group
31.2.9
31. Reducing Power Consumption
Reducing Internal Power Consumption
When the MCU enters wait mode using low-speed clock mode or low-speed on-chip oscillator mode, internal
power consumption can be reduced by using the VCA20 bit in the VCA2 register. Figure 31.1 shows the
Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit. To enable reduced internal
power consumption by the VCA20 bit, follow Figure 31.1 Handling Procedure for Reducing Internal Power
Consumption Using VCA20 Bit.
Exit wait mode by interrupt
Procedure for enabling reduced internal
power consumption using VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (5)
VCA20 ← 0
(internal power low consumption disabled) (2)
(This is automatically set when exiting wait mode)
Step (2)
Stop XIN clock and
high-speed on-chip oscillator clock
Step (6)
Start XIN clock
or high-speed on-chip oscillator clock
Step (3)
VCA20 ← 1
(internal power low consumption enabled) (2, 3)
Step (7)
(Wait until XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Step (4)
Enter wait mode (4)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (5)
VCA20 ← 0
(internal power low consumption disabled) (2)
Start XIN clock or
high-speed on-chip oscillator clock
Step (1)
Step (6)
(Wait until XIN clock or high-speed on-chip
oscillator clock oscillation stabilizes)
Step (2)
Step (7)
Stop XIN clock and
high-speed on-chip oscillator clock
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (3)
Step (8)
VCA20 ← 1
(internal power low consumption enabled) (2, 3)
If it is necessary to start
the high-speed clock or
high-speed on-chip oscillator
during the interrupt routine,
execute steps (6) to (7)
in the routine.
Interrupt handling
Enter low-speed clock mode or
low-speed on-chip oscillator mode
If the high-speed clock or
high-speed on-chip oscillator
starts during the interrupt
routine, execute steps (1) to
(3) at the end of the routine.
Interrupt handling completed
Notes:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When the MCU enters wait mode, follow 9.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 31.1
Handling Procedure for Reducing Internal Power Consumption Using VCA20 Bit
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R8C/32A Group
31. Reducing Power Consumption
31.2.10 Stopping Flash Memory
In low-speed on-chip oscillator mode and low-speed clock mode, power consumption can be further reduced by
stopping the flash memory using the FMSTP bit in the FMR0 register.
Access to the flash memory is disabled by setting the FMSTP bit to 1 (flash memory stops). The FMSTP bit
must be written to by a program transferred to RAM.
When the MCU enters stop mode or wait mode while CPU rewrite mode is disabled, the power for the flash
memory is automatically turned off. It is turned back on again after the MCU exit stop mode or wait mode. This
eliminates the need to set the FMR0 register.
Figure 31.2 shows the Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit.
FMSTP bit setting program
Transfer the FMSTP bit setting program to
the RAM
After writing 0 to the FMR01 bit,
write 1 (CPU rewrite mode enabled)
Write 1 to the FMSTP bit (flash memory stops.
low power consumption state) (1)
Jump to the FMSTP bit setting program
(The subsequent processing is executed
by the program in the RAM)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Stop the high-speed on-chip oscillator
Process in low-speed clock mode or
low-speed on-chip oscillator mode
Switch the clock source for the CPU clock
(2)
Write 0 to the FMSTP bit
(flash memory operates)
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Notes:
1. After setting the FMR01 bit to 1 (CPU rewrite mode enabled),
set the FMSTP bit to 1 (flash memory stops).
2. Before switching the CPU clock source, make sure the designated
clock is stable.
3. Insert a 60- µs wait time by a program.
Do not access the flash memory during this wait time.
Wait until the flash memory circuit stabilizes
(60 µs) (3)
Jump to the specified address in the flash memory
FMR01, FMSTP: Bits in FMR0 register
Figure 31.2
Handling Procedure Example for Reducing Power Consumption Using FMSTP Bit
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R8C/32A Group
31. Reducing Power Consumption
31.2.11 Low-Current-Consumption Read Mode
In low-speed clock mode and low-speed on-chip oscillator mode, the current consumption when reading the
flash memory can be reduced by setting the FMR27 bit in the FMR2 register to 1 (enabled).
Figure 31.3 shows the Handling Procedure Example of Low-Current-Consumption Read Mode.
Handling procedure for enabling
low-current-consumption read mode
by FMR27 bit
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (2)
Stop the high-speed on-chip oscillator clock
Step (3)
FMR27 ← 1
(low-current-consumption read mode enabled) (1)
Step (4)
Enter low-current-consumption read mode (2)
Step (5)
FMR27 ← 0
(low-current-consumption read mode disabled)
Step (6)
Start the high-speed on-chip oscillator clock
Step (7)
(Wait until the high-speed on-chip oscillator clock
oscillation stabilizes)
Step (8)
Enter high-speed on-chip oscillator mode
Notes:
1. To set the FMR27 bit to 1, first write 0 and then write 1 immediately.
After writing 0, do not generate an interrupt before writing 1.
2. In low-current-consumption read mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled).
FMR27: Bit in FMR2 register
Figure 31.3
Handling Procedure Example of Low-Current-Consumption Read Mode
31.2.12 Others
Set the MSTTRD bit in the MSTCR register to 1.
The power consumption of the peripheral functions can be reduced.
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Specifications in this manual are tentative and subject to change.
R8C/32A Group
32. Electrical Characteristics
32. Electrical Characteristics
Table 32.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
VI
VO
Input voltage
Output voltage
P1_0 to P1_7, P3_3 to P3_5, P3_7,
P4_5 to P4_7, MODE, RESET
Rated Value
Unit
−0.3 to 6.5
−0.3 to VCC + 0.3
V
V
XIN, XOUT
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XIN, XOUT
XIN-XOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
XCIN
XCIN-XCOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XCIN
XCIN-XCOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
−0.3 to VCC + 0.3
V
P1_0 to P1_7, P3_3 to P3_5, P3_7,
P4_5 to P4_7
XOUT
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XOUT
XIN-XOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
XCOUT
XCIN-XCOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XCOUT
XCIN-XCOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
TBD
−20 to 85 (N version) /
−40 to 85 (D version)
−65 to 150
mW
Topr = 25°C
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Note:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit.
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°C
°C
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 32.2
32. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC Supply voltage
1.8
−
5.5
V
VSS/AVSS Supply voltage
−
0.45 VCC
0.55 VCC
0.65 VCC
0.6 VCC
0.7 VCC
0.8 VCC
0.85 VCC
0
−
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
0.85 VCC
VCC
V
VCC
V
0.2 VCC
V
0.2 VCC
V
0.2 VCC
V
0.4 VCC
V
0.3 VCC
V
0.2 VCC
V
0.55 VCC
V
0.45 VCC
V
−
−
−
−
−
−
−
−
−
−
−
−
−
VIH
Input “H” voltage Input level
switching
function
(I/O port)
CMOS Input level selection 4.0 V ≤ VCC ≤ 5.5 V
input
: 0.35 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.5 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.7 VCC
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
VIL
Input “L” voltage Input level
switching
function
(I/O port)
0.85 VCC
CMOS Input level selection 4.0 V ≤ VCC ≤ 5.5 V
input
: 0.35 VCC
2.7 V ≤ VCC < 4.0 V
0
1.8 V ≤ VCC < 2.7 V
0
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.5 VCC
2.7 V ≤ VCC < 4.0 V
0
1.8 V ≤ VCC < 2.7 V
0
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.7 VCC
2.7 V ≤ VCC < 4.0 V
0
1.8 V ≤ VCC < 2.7 V
0
0
0
0
−
−
−
−
−
−
−
V
V
V
V
V
V
V
0.35 VCC
V
TBD
mA
IOH(sum)
Peak sum output Sum of all pins IOH(peak)
IOH(sum)
Average sum
Sum of all pins IOH(avg)
−
−
TBD
mA
IOH(peak)
Peak output “H”
current
Drive capacity Low
Average output
“H” current
Drive capacity Low
Peak sum output Sum of all pins IOL(peak)
−10
−40
−5
−20
TBD
mA
IOL(sum)
−
−
−
−
−
mA
IOH(avg)
−
−
−
−
−
IOL(sum)
Average sum
Sum of all pins IOL(avg)
−
−
TBD
mA
IOL(peak)
Peak output “L”
current
Drive capacity Low
−
−
−
−
0
0
0
0
−
2.7
1.8
−
−
−
−
−
−
−
−
32.768
−
−
10
mA
3.0 V ≤ VCC ≤ 5.5 V
0
2.7 V ≤ VCC < 3.0 V
0
2.2 V ≤ VCC < 2.7 V
0
fOCO-S operating voltage
fOCO-S = 125kHz
1.8
System clock frequency
3.0 V ≤ VCC ≤ 5.5 V
0
2.7 V ≤ VCC < 3.0 V
0
2.2 V ≤ VCC < 2.7 V
0
Drive capacity High
Drive capacity High
Drive capacity High
IOL(avg)
Average output
“L” current
f(XIN)
XIN clock input oscillation frequency
Drive capacity Low
Drive capacity High
3.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 3.0 V
2.2 V ≤ VCC < 2.7 V
1.8 V ≤ VCC < 2.2 V
f(XCIN)
XCIN clock input oscillation frequency
−
fOCO40M
operating
fOCO-F
−
−
f(BCLK)
1.8 V ≤ VCC ≤ 5.5 V
When used as the count source for timer RC fOCO40M = 40MHz
When used as the count source for fOCO-F fOCO40M = 40MHz
fOCO-F frequency
CPU clock frequency
1.8 V ≤ VCC < 2.2 V
0
3.0 V ≤ VCC ≤ 5.5 V
0
2.7 V ≤ VCC < 3.0 V
0
2.2 V ≤ VCC < 2.7 V
0
1.8 V ≤ VCC < 2.2 V
0
Apr 01, 2008
mA
mA
40
mA
5
mA
20
mA
20
MHz
10
MHz
5
MHz
2
MHz
50
kHz
5.5
V
5.5
V
−
−
−
20
MHz
−
−
−
−
−
−
−
−
−
5.5
V
20
MHz
Notes:
1. VCC = 1.8 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
REJ09B0458-0010 Rev.0.10
Page 519 of 572
mA
10
MHz
5
MHz
10
MHz
5
MHz
2
MHz
20
MHz
10
MHz
5
MHz
2
MHz
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
32. Electrical Characteristics
P1
P3
P4
Figure 32.1
30pF
Ports P1, P3, P4 Timing Measurement Circuit
REJ09B0458-0010 Rev.0.10
Page 520 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 32.3
32. Electrical Characteristics
A/D Converter Characteristics (1)
Symbol
−
INL
Parameter
Conditions
Resolution
Vref = AVCC
Integral non-linearity error
10-bit mode
8-bit mode
−
Absolute accuracy
10-bit mode
8-bit mode
−
DNL
−
−
RLADDER
tCONV
Vref = AVCC = 5.0V
AN8 to AN11 input
Vref = AVCC = 3.3V
AN8 to AN11 input
Vref = AVCC = 3.0V
AN8 to AN11 input
Vref = AVCC = 2.2V
AN8 to AN11 input
Vref = AVCC = 5.0V
AN8 to AN11 input
Vref = AVCC = 3.3V
AN8 to AN11 input
Vref = AVCC = 3.0V
AN8 to AN11 input
Vref = AVCC = 2.2V
AN8 to AN11 input
Vref = AVCC = 5.0V
AN8 to AN11 input
Vref = AVCC = 3.3V
AN8 to AN11 input
Vref = AVCC = 3.0V
AN8 to AN11 input
Vref = AVCC = 2.2V
AN8 to AN11 input
Vref = AVCC = 5.0V
AN8 to AN11 input
Vref = AVCC = 3.3V
AN8 to AN11 input
Vref = AVCC = 3.0V
AN8 to AN11 input
Vref = AVCC = 2.2V
AN8 to AN11 input
Tolerance level impedance
Differential non-linearity error
Offset error
Gain error
Ladder resistance
Vref = AVCC
Conversion time
10-bit mode
Vref = AVCC = 5.0V,
φAD = 20 MHz
8-bit mode
Vref = AVCC = 5.0V,
φAD = 20 MHz
Standard
Typ.
Max.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
10
2.0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3
−
−
−
−
−
10
Bit
±3
LSB
±5
LSB
±5
LSB
±5
LSB
±2
LSB
±2
LSB
±2
LSB
±2
LSB
±3
LSB
±5
LSB
±5
LSB
±5
LSB
±2
LSB
±2
LSB
±2
LSB
±2
LSB
2.0
−
−
µs
−
AVCC
0
−
−
−
Vref
µs
V
V
1.24
1.34
1.44
V
tSAMP
Sampling time
0.60
Vref
Reference voltage
2.2
VIA
Analog input voltage (3)
OCVREF On-chip reference voltage
Unit
Min.
−
±1
±3
±3
40
−
kΩ
LSB
LSB
LSB
kΩ
µs
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise
specified.
2. Set φAD frequency as follows:
When AVCC = 4.0 to 5.5 V, 2 MHz ≤ φAD ≤ 20 MHz
When AVCC = 3.2 to 4.0 V, 2 MHz ≤ φAD ≤ 16 MHz
When AVCC = 3.0 to 3.2 V, 2 MHz ≤ φAD ≤ 10 MHz
When AVCC = 2.2 to 3.0 V, 2 MHz ≤ φAD ≤ 5 MHz
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
REJ09B0458-0010 Rev.0.10
Page 521 of 572
Apr 01, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 32.4
32. Electrical Characteristics
Comparator A Electrical Characteristics
Symbol
Parameter
LVREF
External reference voltage input range
LVCMP1,
LVCMP2
External comparison voltage input range
−
−
Offset
−
Comparator operating current
Condition
Comparator output delay time (2)
VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
1.4
−0.3
−
−
VCC
V
VCC + 0.3
V
−
−
TBD
TBD
mV
TBD
TBD
µs
−
TBD
TBD
µA
Note:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is not selected.
Table 32.5
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
−
td
Offset
Comparator output delay time (2)
VI = Vref ± 10 mV
ICMP
Comparator operating current
VCC = 5.0 V
Standard
Typ.
Max.
0
−0.3
−
−
−
−
TBD
TBD
VCC − 1.4
TBD
µs
−
TBD
TBD
µA
Apr 01, 2008
V
VCC + 0.3
V
TBD
mV
Note:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is not selected.
REJ09B0458-0010 Rev.0.10
Page 522 of 572
Unit
Min.
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/32A Group
Table 32.6
32. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
−
Program/erase endurance (2)
−
−
td(SR-SUS)
Byte program time
−
Conditions
Standard
Min.
Typ.
Max.
Unit
1,000 (3)
−
−
times
−
−
−
80
TBD
0.3
TBD
−
5+CPU clock
× 3 cycles
µs
s
ms
Interval from erase start/restart until
following suspend request (8)
0
−
−
µs
−
Time from suspend until erase restart
−
−
30+CPU clock
× 1 cycle
µs
−
−
−
−
Program, erase voltage
2.7
V
1.8
−
−
−
−
5.5
Read voltage
5.5
V
°C
year
Block erase time
Time delay from suspend request until
suspend
Program, erase temperature
0
Ambient temperature = 55°C
Data hold time (7)
20
60
−
Notes:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation.