RENESAS R28

To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas
Electronics products or the technology described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
User’s Manual
16
R8C/28 Group,
R8C/29 Group
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
Rev.2.10 2008.09
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1.
Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/28 Group, R8C/29 Group. Make sure to refer to the latest versions of these
documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Document Type
Datasheet
Description
Document Title
Document No.
Hardware overview and electrical characteristics R8C/28, R8C/29
REJ03B0169
Group Datasheet
This hardware
R8C/28 Group,
Hardware manual Hardware specifications (pin assignments,
manual
R8C/29 Group
memory maps, peripheral function
Hardware Manual
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set
R8C/Tiny Series
REJ09B0001
Software Manual
Available from Renesas
Application note Information on using peripheral functions and
Technology Web site.
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1)
Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2)
Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7
b6
b5
b4
b3
*1
b2
b1
b0
Symbol
XXX
0
Bit Symbol
XXX0
Address
XXX
Bit Name
XXX bits
XXX1
After Reset
00h
Function
RW
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
RW
RW
(b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(b3)
Reserved bits
Set to 0.
RW
XXX bits
Function varies according to the operating
mode.
RW
XXX4
*3
XXX5
WO
XXX6
RW
XXX7
XXX bit
*2
b1 b0
0: XXX
1: XXX
*4
RO
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SIM
UART
VCO
Full Form
Asynchronous Communication Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment Bus
Input / Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connect
Phase Locked Loop
Pulse Width Modulation
Subscriber Identity Module
Universal Asynchronous Receiver / Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1.
Overview ......................................................................................................................................... 1
1.1
1.2
1.3
1.4
1.5
1.6
2.
Applications ...............................................................................................................................................
Performance Overview ..............................................................................................................................
Block Diagram ..........................................................................................................................................
Product Information ..................................................................................................................................
Pin Assignments ........................................................................................................................................
Pin Functions .............................................................................................................................................
1
2
4
5
7
8
Central Processing Unit (CPU) ..................................................................................................... 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.10
3.
Data Registers (R0, R1, R2, and R3) ......................................................................................................
Address Registers (A0 and A1) ...............................................................................................................
Frame Base Register (FB) .......................................................................................................................
Interrupt Table Register (INTB) ..............................................................................................................
Program Counter (PC) .............................................................................................................................
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..................................................................
Static Base Register (SB) ........................................................................................................................
Flag Register (FLG) ................................................................................................................................
Carry Flag (C) .....................................................................................................................................
Debug Flag (D) ...................................................................................................................................
Zero Flag (Z) .......................................................................................................................................
Sign Flag (S) .......................................................................................................................................
Register Bank Select Flag (B) ............................................................................................................
Overflow Flag (O) ..............................................................................................................................
Interrupt Enable Flag (I) .....................................................................................................................
Stack Pointer Select Flag (U) ..............................................................................................................
Processor Interrupt Priority Level (IPL) .............................................................................................
Reserved Bit ........................................................................................................................................
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
Memory ......................................................................................................................................... 13
3.1
3.2
R8C/28 Group ......................................................................................................................................... 13
R8C/29 Group ......................................................................................................................................... 14
4.
Special Function Registers (SFRs) ............................................................................................... 15
5.
Resets ........................................................................................................................................... 22
5.1
5.1.1
5.1.2
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Hardware Reset .......................................................................................................................................
When Power Supply is Stable .............................................................................................................
Power On ............................................................................................................................................
Power-On Reset Function .......................................................................................................................
Voltage Monitor 0 Reset (N, D Version) ................................................................................................
Voltage Monitor 1 Reset (N, D Version) ................................................................................................
Voltage Monitor 1 Reset (J, K Version) ..................................................................................................
Voltage Monitor 2 Reset .........................................................................................................................
Watchdog Timer Reset ............................................................................................................................
Software Reset .........................................................................................................................................
A-1
26
26
26
28
30
30
30
31
31
31
6.
Voltage Detection Circuit .............................................................................................................. 32
6.1
6.1.1
6.1.2
6.1.3
6.2
6.3
6.4
6.5
7.
VCC Input Voltage ..................................................................................................................................
Monitoring Vdet0 ...............................................................................................................................
Monitoring Vdet1 ...............................................................................................................................
Monitoring Vdet2 ...............................................................................................................................
Voltage Monitor 0 Reset (For N, D Version only) ..................................................................................
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset (N, D Version) ............................................
Voltage Monitor 1 Reset (J, K Version) ..................................................................................................
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset .....................................................................
43
43
43
43
44
45
47
48
Programmable I/O Ports ............................................................................................................... 50
7.1
7.2
7.3
7.4
7.5
8.
Functions of Programmable I/O Ports .....................................................................................................
Effect on Peripheral Functions ................................................................................................................
Pins Other than Programmable I/O Ports ................................................................................................
Port Settings ............................................................................................................................................
Unassigned Pin Handling ........................................................................................................................
50
51
51
61
69
Processor Mode ............................................................................................................................ 70
8.1
Processor Modes ...................................................................................................................................... 70
9.
Bus ................................................................................................................................................ 71
10.
Clock Generation Circuit ............................................................................................................... 72
10.1
10.2
10.2.1
10.2.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
10.5
10.5.1
10.5.2
10.5.3
10.6
10.6.1
10.7
10.7.1
10.7.2
10.7.3
10.7.4
XIN Clock ............................................................................................................................................... 82
On-Chip Oscillator Clocks ...................................................................................................................... 83
Low-Speed On-Chip Oscillator Clock ................................................................................................ 83
High-Speed On-Chip Oscillator Clock ............................................................................................... 83
XCIN Clock (For N, D Version Only) .................................................................................................... 84
CPU Clock and Peripheral Function Clock ............................................................................................. 85
System Clock ...................................................................................................................................... 85
CPU Clock .......................................................................................................................................... 85
Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. 85
fOCO ................................................................................................................................................... 85
fOCO40M ........................................................................................................................................... 85
fOCO-F ............................................................................................................................................... 85
fOCO-S ............................................................................................................................................... 85
fC4 and fC32 ....................................................................................................................................... 86
fOCO128 ............................................................................................................................................. 86
Power Control .......................................................................................................................................... 87
Standard Operating Mode ................................................................................................................... 87
Wait Mode .......................................................................................................................................... 89
Stop Mode ........................................................................................................................................... 93
Oscillation Stop Detection Function ....................................................................................................... 97
How to Use Oscillation Stop Detection Function ............................................................................... 97
Notes on Clock Generation Circuit ....................................................................................................... 101
Stop Mode ......................................................................................................................................... 101
Wait Mode ........................................................................................................................................ 101
Oscillation Stop Detection Function ................................................................................................. 101
Oscillation Circuit Constants ............................................................................................................ 101
A-2
11.
Protection .................................................................................................................................... 102
12.
Interrupts ..................................................................................................................................... 103
12.1
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
12.2
12.2.1
12.2.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
12.6.3
12.6.4
12.6.5
13.
13.1
13.2
14.
Interrupt Overview ................................................................................................................................ 103
Types of Interrupts ............................................................................................................................ 103
Software Interrupts ........................................................................................................................... 104
Special Interrupts .............................................................................................................................. 105
Peripheral Function Interrupt ............................................................................................................ 105
Interrupts and Interrupt Vectors ........................................................................................................ 106
Interrupt Control ............................................................................................................................... 108
INT Interrupt ......................................................................................................................................... 117
INTi Interrupt (i = 0, 1, 3) ................................................................................................................. 117
INTi Input Filter (i = 0, 1, 3) ............................................................................................................. 119
Key Input Interrupt ................................................................................................................................ 120
Address Match Interrupt ........................................................................................................................ 122
Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface
Interrupt (Interrupts with Multiple Interrupt Request Sources) ............................................................ 124
Notes on Interrupts ................................................................................................................................ 126
Reading Address 00000h .................................................................................................................. 126
SP Setting .......................................................................................................................................... 126
External Interrupt and Key Input Interrupt ....................................................................................... 126
Changing Interrupt Sources .............................................................................................................. 127
Changing Interrupt Control Register Contents ................................................................................. 128
Watchdog Timer .......................................................................................................................... 129
Count Source Protection Mode Disabled .............................................................................................. 132
Count Source Protection Mode Enabled ............................................................................................... 133
Timers ......................................................................................................................................... 134
14.1
Timer RA ...............................................................................................................................................
14.1.1 Timer Mode ......................................................................................................................................
14.1.2 Pulse Output Mode ...........................................................................................................................
14.1.3 Event Counter Mode .........................................................................................................................
14.1.4 Pulse Width Measurement Mode ......................................................................................................
14.1.5 Pulse Period Measurement Mode .....................................................................................................
14.1.6 Notes on TImer RA ...........................................................................................................................
14.2
Timer RB ...............................................................................................................................................
14.2.1 Timer Mode ......................................................................................................................................
14.2.2 Programmable Waveform Generation Mode ....................................................................................
14.2.3 Programmable One-shot Generation Mode ......................................................................................
14.2.4 Programmable Wait One-Shot Generation Mode .............................................................................
14.2.5 Notes on Timer RB ...........................................................................................................................
14.3
Timer RC ...............................................................................................................................................
14.3.1 Overview ...........................................................................................................................................
14.3.2 Registers Associated with Timer RC ................................................................................................
14.3.3 Common Items for Multiple Modes .................................................................................................
14.3.4 Timer Mode (Input Capture Function) .............................................................................................
14.3.5 Timer Mode (Output Compare Function) .........................................................................................
14.3.6 PWM Mode .......................................................................................................................................
A-3
136
139
141
143
145
148
151
152
156
159
162
166
169
173
173
175
185
191
196
202
14.3.7 PWM2 Mode .....................................................................................................................................
14.3.8 Timer RC Interrupt ...........................................................................................................................
14.3.9 Notes on Timer RC ...........................................................................................................................
14.4
Timer RE ...............................................................................................................................................
14.4.1 Real-Time Clock Mode (For N, D Version Only) ............................................................................
14.4.2 Output Compare Mode .....................................................................................................................
14.4.3 Notes on Timer RE ...........................................................................................................................
15.
Serial Interface ............................................................................................................................ 231
15.1
Clock Synchronous Serial I/O Mode .....................................................................................................
15.1.1 Polarity Select Function ....................................................................................................................
15.1.2 LSB First/MSB First Select Function ...............................................................................................
15.1.3 Continuous Receive Mode ................................................................................................................
15.2
Clock Asynchronous Serial I/O (UART) Mode ....................................................................................
15.2.1 Bit Rate .............................................................................................................................................
15.3
Notes on Serial Interface .......................................................................................................................
16.
238
241
241
242
243
247
248
Clock Synchronous Serial Interface ............................................................................................ 249
16.1
Mode Selection ......................................................................................................................................
16.2
Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................
16.2.1 Transfer Clock ..................................................................................................................................
16.2.2 SS Shift Register (SSTRSR) .............................................................................................................
16.2.3 Interrupt Requests .............................................................................................................................
16.2.4 Communication Modes and Pin Functions .......................................................................................
16.2.5 Clock Synchronous Communication Mode ......................................................................................
16.2.6 Operation in 4-Wire Bus Communication Mode ..............................................................................
16.2.7 SCS Pin Control and Arbitration ......................................................................................................
16.2.8 Notes on Clock Synchronous Serial I/O with Chip Select ...............................................................
16.3
I2C bus Interface ....................................................................................................................................
16.3.1 Transfer Clock ..................................................................................................................................
16.3.2 Interrupt Requests .............................................................................................................................
16.3.3 I2C bus Interface Mode .....................................................................................................................
16.3.4 Clock Synchronous Serial Mode ......................................................................................................
16.3.5 Noise Canceller .................................................................................................................................
16.3.6 Bit Synchronization Circuit ..............................................................................................................
16.3.7 Examples of Register Setting ............................................................................................................
16.3.8 Notes on I2C bus Interface ................................................................................................................
17.
207
213
214
215
216
224
228
249
250
260
262
263
264
265
272
278
279
280
290
291
292
303
306
307
308
312
Hardware LIN .............................................................................................................................. 313
17.1
17.2
17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.5
17.6
Features .................................................................................................................................................
Input/Output Pins ..................................................................................................................................
Register Configuration ..........................................................................................................................
Functional Description ..........................................................................................................................
Master Mode .....................................................................................................................................
Slave Mode .......................................................................................................................................
Bus Collision Detection Function .....................................................................................................
Hardware LIN End Processing .........................................................................................................
Interrupt Requests ..................................................................................................................................
Notes on Hardware LIN ........................................................................................................................
A-4
313
314
315
317
317
320
324
325
326
327
18.
A/D Converter ............................................................................................................................. 328
18.1
18.2
18.3
18.4
18.5
18.6
18.7
19.
One-Shot Mode .....................................................................................................................................
Repeat Mode ..........................................................................................................................................
Sample and Hold ...................................................................................................................................
A/D Conversion Cycles .........................................................................................................................
Internal Equivalent Circuit of Analog Input ..........................................................................................
Output Impedance of Sensor under A/D Conversion ............................................................................
Notes on A/D Converter ........................................................................................................................
Flash Memory ............................................................................................................................. 340
19.1
19.2
19.3
19.3.1
19.3.2
19.4
19.4.1
19.4.2
19.4.3
19.4.4
19.4.5
19.5
19.5.1
19.6
19.6.1
19.7
19.7.1
20.
20.1
20.2
21.
332
334
336
336
337
338
339
Overview ...............................................................................................................................................
Memory Map .........................................................................................................................................
Functions to Prevent Rewriting of Flash Memory ................................................................................
ID Code Check Function ..................................................................................................................
ROM Code Protect Function ............................................................................................................
CPU Rewrite Mode ...............................................................................................................................
EW0 Mode ........................................................................................................................................
EW1 Mode ........................................................................................................................................
Software Commands .........................................................................................................................
Status Registers .................................................................................................................................
Full Status Check ..............................................................................................................................
Standard Serial I/O Mode ......................................................................................................................
ID Code Check Function ..................................................................................................................
Parallel I/O Mode ..................................................................................................................................
ROM Code Protect Function ............................................................................................................
Notes on Flash Memory ........................................................................................................................
CPU Rewrite Mode ...........................................................................................................................
340
341
343
343
344
345
346
346
355
360
361
363
363
366
366
367
367
Electrical Characteristics ............................................................................................................ 370
N, D Version .......................................................................................................................................... 370
J, K Version ........................................................................................................................................... 395
Usage Notes ............................................................................................................................... 415
21.1
Notes on Clock Generation Circuit ....................................................................................................... 415
21.1.1 Stop Mode ......................................................................................................................................... 415
21.1.2 Wait Mode ........................................................................................................................................ 415
21.1.3 Oscillation Stop Detection Function ................................................................................................. 415
21.1.4 Oscillation Circuit Constants ............................................................................................................ 415
21.2
Notes on Interrupts ................................................................................................................................ 416
21.2.1 Reading Address 00000h .................................................................................................................. 416
21.2.2 SP Setting .......................................................................................................................................... 416
21.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 416
21.2.4 Changing Interrupt Sources .............................................................................................................. 417
21.2.5 Changing Interrupt Control Register Contents ................................................................................. 418
21.3
Notes on Timers .................................................................................................................................... 419
21.3.1 Notes on TImer RA ........................................................................................................................... 419
21.3.2 Notes on Timer RB ........................................................................................................................... 420
21.3.3 Notes on Timer RC ........................................................................................................................... 424
21.3.4 Notes on Timer RE ........................................................................................................................... 425
A-5
21.4
21.5
21.5.1
21.5.2
21.6
21.7
21.8
21.8.1
21.9
21.9.1
Notes on Serial Interface ....................................................................................................................... 428
Notes on Clock Synchronous Serial Interface ....................................................................................... 429
Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 429
Notes on I2C bus Interface ................................................................................................................ 429
Notes on Hardware LIN ........................................................................................................................ 430
Notes on A/D Converter ........................................................................................................................ 431
Notes on Flash Memory ........................................................................................................................ 432
CPU Rewrite Mode ........................................................................................................................... 432
Notes on Noise ...................................................................................................................................... 435
Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 435
21.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 435
22.
Notes on On-Chip Debugger ...................................................................................................... 436
Appendix 1. Package Dimensions ........................................................................................................ 437
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 438
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 439
Index ..................................................................................................................................................... 440
A-6
SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
Register
Symbol
Page
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
70
70
74
75
Protect Register
PRCR
102
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
76
131
131
130
123
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
Count Source Protection Mode Register
AIER
RMAD1
CSPR
123
123
131
High-Speed On-Chip Oscillator Control
Register 0
High-Speed On-Chip Oscillator Control
Register 1
High-Speed On-Chip Oscillator Control
Register 2
FRA0
77
FRA1
77
FRA2
78
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control
Register 4
CPSRF
FRA4
79
78
High-Speed On-Chip Oscillator Control
Register 6
High-Speed On-Chip Oscillator Control
Register 7
FRA6
78
FRA7
78
Voltage Detection Register 1
Voltage Detection Register 2
VCA1
VCA2
37
37, 38, 79,
80
Voltage Monitor 1 Circuit Control Register
Voltage Monitor 2 Circuit Control Register
Voltage Monitor 0 Circuit Control Register
VW1C
VW2C
VW0C
40, 41
42
39
003Bh
003Ch
003Dh
003Eh
003Fh
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B-1
Register
Symbol
Page
Timer RC Interrupt Control Register
TRCIC
109
Timer RE Interrupt Control Register
TREIC
108
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU/IIC bus Interrupt Control Register
KUPIC
ADIC
SSUIC/IICIC
108
108
109
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
108
108
108
108
Timer RA Interrupt Control Register
TRAIC
108
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
108
110
110
INT0 Interrupt Control Register
INT0IC
110
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
Page
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
234
234
233
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
235
236
233
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
234
234
233
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
235
236
233
SS Control Register H / IIC bus Control Register 1
SS Control Register L / IIC bus Control Register 2
SS Mode Register / IIC bus Mode Register
SS Enable Register / IIC bus Interrupt Enable
Register
SS Status Register / IIC bus Status Register
SS Mode Register 2 / Slave Address Register
SS Transmit Data Register / IIC bus Transmit
Data Register
SS Receive Data Register / IIC bus Receive
Data Register
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
252, 283
253, 284
254, 285
255, 286
SSSR / ICSR
SSMR2 / SAR
SSTDR / ICDRT
256, 287
257, 288
258, 288
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
SSRDR / ICDRR 258, 288
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B-2
A/D Register
Register
Symbol
AD
Page
331
A/D Control Register 2
ADCON2
331
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
330
331
Port P1 Register
P1
57
Port P1 Direction Register
PD1
57
Port P3 Register
P3
57
Port P3 Direction Register
Port P4 Register
PD3
P4
57
57
Port P4 Direction Register
PD4
57
Pin Select Register 1
Pin Select Register 2
Pin Select Register 3
Port Mode Register
PINSR1
PINSR2
PINSR3
PMR
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
Port P1 Drive Capacity Control Register
INTEN
INTF
KIEN
PUR0
PUR1
P1DRR
58, 237
58
58
59, 237, 259,
289
117
118
121
60
60
60
Address
Register
0100h Timer RA Control Register
0101h Timer RA I/O Control Register
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
Symbol
TRACR
TRAIOC
Page
137
137, 139, 142,
144, 146, 149
138
138
138
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
TRAMR
TRAPRE
TRA
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
TRBMR
TRBPRE
TRBSC
TRBPR
315
316
153
153
154, 156, 160,
163, 167
154
155
155
155
0118h
Timer RE Second Data Register / Counter
Data Register
Timer RE Minute Data Register / Compare
Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
218, 225
TREMIN
218, 225
TREHR
TREWK
TRECR1
TRECR2
TRECSR
219
219
220, 226
221, 226
222, 227
Timer RC Mode Register
Timer RC Control Register 1
TRCMR
TRCCR1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
176
177, 200, 204,
209
178
179
184, 193, 198
184, 194, 199
180
Timer RC General Register A
TRCGRA
180
Timer RC General Register B
TRCGRB
180
Timer RC General Register C
TRCGRC
180
Timer RC General Register D
TRCGRD
180
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
Address
Register
0130h Timer RC Control Register 2
0131h Timer RC Digital Filter Function Select
Register
0132h Timer RC Output Master Enable Register
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B-3
Symbol
TRCCR2
TRCDF
TRCOER
Page
181
182
183
Address
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
Register
Symbol
Page
Address
Register
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4
01B4h
01B5h Flash Memory Control Register 1
01B6h
01B7h Flash Memory Control Register 0
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
FFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these
regions.
B-4
Option Function Select Register
Symbol
Page
FMR4
351
FMR1
350
FMR0
349
OFS
25, 130, 344
R8C/28 Group, R8C/29 Group
SINGLE-CHIP 16-BIT CMOS MCU
1.
REJ09B0279-0210
Rev.2.10
Sep 26, 2008
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and
are packaged in a 20-pin molded-plastic LSSOP. It implements sophisticated instructions for a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/29 Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/28 Group and R8C/29 Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 1 of 441
R8C/28 Group, R8C/29 Group
1.2
1. Overview
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/28 Group and Table 1.2 outlines the Functions and
Specifications for R8C/29 Group.
Table 1.1
CPU
Peripheral
Functions
Functions and Specifications for R8C/28 Group
Item
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
Address space
Memory capacity
Ports
LED drive ports
Timers
Serial interfaces
Clock synchronous serial
interface
LIN module
A/D converter
Watchdog timer
Interrupts
Clock generation circuits
Electrical
Characteristics
Oscillation stop detection
function
Voltage detection circuit
Power-on reset circuit
Supply voltage
Current consumption
(N, D version)
Flash Memory
Programming and erasure
voltage
Programming and erasure
endurance
Operating Ambient Temperature
Package
Specification
89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Single-chip
1 Mbyte
Refer to Table 1.3 Product Information for R8C/28 Group
I/O ports: 13 pins, Input port: 3 pins
I/O ports: 8 pins (N, D version)
Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
(For J, K version, compare match function only.)
1 channel (UART0): Clock synchronous serial I/O, UART
1 channel (UART1): UART
1 channel
I2C bus Interface(1)
Clock synchronous serial I/O with chip select
Hardware LIN: 1 channel (timer RA, UART0)
10-bit A/D converter: 1 circuit, 4 channels
15 bits × 1 channel (with prescaler)
Reset start selectable
Internal: 15 sources (N, D version), Internal: 14 sources (J, K version)
External: 4 sources, Software: 4 sources, Priority levels: 7 levels
3 circuits
• XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
XIN clock oscillation stop detection function
On-chip
On-chip
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
VCC = 2.7 to 5.5 V
100 times
-20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
20-pin molded-plastic LSSOP
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 2 of 441
R8C/28 Group, R8C/29 Group
Table 1.2
CPU
Peripheral
Functions
1. Overview
Functions and Specifications for R8C/29 Group
Item
Number of fundamental
instructions
Minimum instruction
execution time
Operating mode
Address space
Memory capacity
Ports
LED drive ports
Timers
Serial interfaces
Clock synchronous serial
interface
LIN module
A/D converter
Watchdog timer
Interrupts
Clock generation circuits
Oscillation stop detection
function
Voltage detection circuit
Power-on reset circuit
Supply voltage
Specification
89 instructions
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Single-chip
1 Mbyte
Refer to Table 1.4 Product Information for R8C/29 Group
I/O ports: 13 pins, Input port: 3 pins
I/O ports: 8 pins (N, D version)
Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
(For J, K version, compare match function only.)
1 channel (UART0): Clock synchronous serial I/O, UART
1 channel (UART1): UART
1 channel
I2C bus Interface(1)
Clock synchronous serial I/O with chip select
Hardware LIN: 1 channel (timer RA, UART0)
10-bit A/D converter: 1 circuit, 4 channels
15 bits × 1 channel (with prescaler)
Reset start selectable
Internal: 15 sources (N, D version), Internal: 14 sources (J, K version)
External: 4 sources, Software: 4 sources, Priority levels: 7 levels
3 circuits
• XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
XIN clock oscillation stop detection function
On-chip
On-chip
Electrical
VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
Characteristics
VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Current consumption
Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
(N, D version)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory
Programming and erasure VCC = 2.7 to 5.5 V
voltage
Programming and erasure 10,000 times (data flash)
endurance
1,000 times (program ROM)
Operating Ambient Temperature
-20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
Package
20-pin molded-plastic LSSOP
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 3 of 441
R8C/28 Group, R8C/29 Group
1.3
1. Overview
Block Diagram
Figure 1.1 shows a Block Diagram.
I/O ports
8
4
Port P1
Port P3
1
3
Port P4
Peripheral functions
System clock generation
circuit
A/D converter
(10 bits × 4 channels)
Timers
Timer RA (8 bits)
Timer RB (8 bits)
Timer RC
(16 bits × 1 channel)
Timer RE (8 bits)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT(3)
UART or
clock synchronous serial I/O
(8 bits × 1 channel)
LIN module
(1 channel)
UART
(8 bits × 1 channel)
I2C bus interface or clock synchronous
serial I/O with chip select
(8 bits × 1 channel)
Watchdog timer
(15 bits)
Memory
R8C CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ISP
INTB
A0
A1
FB
ROM(1)
USP
RAM(2)
PC
FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. XCIN, XCOUT can be used only for N or D version.
Figure 1.1
Block Diagram
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 4 of 441
R8C/28 Group, R8C/29 Group
1.4
1. Overview
Product Information
Table 1.3 lists the Product Information for R8C/28 Group and Table 1.4 lists the Product Information for R8C/29
Group.
Table 1.3
Product Information for R8C/28 Group
Type No.
R5F21282SNSP
R5F21284SNSP
R5F21282SDSP
R5F21284SDSP
R5F21284JSP
R5F21286JSP
R5F21284KSP
R5F21286KSP
R5F21282SNXXXSP
R5F21284SNXXXSP
R5F21282SDXXXSP
R5F21284SDXXXSP
R5F21284JXXXSP
R5F21286JXXXSP
R5F21284KXXXSP
R5F21286KXXXSP
ROM
Capacity
8 Kbytes
16 Kbytes
8 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
16 Kbytes
32 Kbytes
8 Kbytes
16 Kbytes
8 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
16 Kbytes
32 Kbytes
RAM
Capacity
512 bytes
1 Kbyte
512 bytes
1 Kbyte
1 Kbyte
1.5 Kbyte
1 Kbyte
1.5 Kbyte
512 bytes
1 Kbyte
512 bytes
1 Kbyte
1 Kbyte
1.5 Kbyte
1 Kbyte
1.5 Kbyte
Current of Sep. 2008
Package Type
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Remarks
N version
D version
J version
K version
N version
D version
Factory
programming
product(1)
J version
K version
NOTE:
1. The user ROM is programmed before shipment.
Type No.
R 5 F 21 28 4 S N XXX SP
Package type:
SP: PLSP0020JB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N version)
D: Operating ambient temperature -40 to 85°C (D version)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K version)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
6: 32 KB
R8C/28 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Type Number, Memory Size, and Package of R8C/28 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 5 of 441
R8C/28 Group, R8C/29 Group
Table 1.4
1. Overview
Product Information for R8C/29 Group
Type No.
R5F21292SNSP
R5F21294SNSP
R5F21292SDSP
R5F21294SDSP
R5F21294JSP
R5F21296JSP
R5F21294KSP
R5F21296KSP
R5F21292SNXXXSP
R5F21294SNXXXSP
R5F21292SDXXXSP
R5F21294SDXXXSP
R5F21294JXXXSP
R5F21296JXXXSP
R5F21294KXXXSP
R5F21296KXXXSP
ROM Capacity
Program
Data flash
ROM
8 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
8 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
32 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
32 Kbytes 1 Kbyte × 2
8 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
8 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
32 Kbytes 1 Kbyte × 2
16 Kbytes 1 Kbyte × 2
32 Kbytes 1 Kbyte × 2
Current of Sep. 2008
RAM
Capacity
Package Type
512 bytes
1 Kbyte
512 bytes
1 Kbyte
1 Kbyte
1.5 Kbyte
1 Kbyte
1.5 Kbyte
512 bytes
1 Kbyte
512 bytes
1 Kbyte
1 Kbyte
1.5 Kbyte
1 Kbyte
1.5 Kbyte
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
PLSP0020JB-A
Remarks
N version
D version
J version
K version
N version
D version
Factory
programming
product(1)
J version
K version
NOTE:
1. The user ROM is programmed before shipment.
Type No.
R 5 F 21 29 4 S N XXX SP
Package type:
SP: PLSP0020JB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N version)
D: Operating ambient temperature -40 to 85°C (D version)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K version)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
6: 32 KB
R8C/29 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Type Number, Memory Size, and Package of R8C/29 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 6 of 441
R8C/28 Group, R8C/29 Group
1.5
1. Overview
Pin Assignments
Figure 1.4 shows Pin Assignments (Top View).
20
P3_4/SDA/SCS/TRCIOC
P3_7/TRAO/SSO/RXD1/(TXD1)(2)
2
19
P3_3/INT3/SSI/TRCCLK
RESET
3
18
P1_0/KI0/AN8
(1, 3)
4
17
P1_1/KI1/AN9/TRCIOA/TRCTRG
VSS/AVSS
5
16
VREF/P4_2
(3)
6
15
P1_2/KI2/AN10/TRCIOB
VCC/AVCC
7
14
P1_3/KI3/AN11/TRBO
MODE
8
13
P1_4/TXD0
P4_5/INT0/(RXD1)(2)
9
12
P1_5/RXD0/(TRAIO)/(INT1)(2)
10
11
P1_6/CLK0/(SSI)(2)
XOUT/XCOUT/P4_7
XIN/XCIN/P4_6
P1_7/TRAIO/INT1
R8C/28 Group
R8C/29 Group
1
PLSP0020JB-A
(20P2F-A)
(top view)
P3_5/SCL/SSCK/TRCIOD
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. XCIN, XCOUT can be used only for N or D version.
4. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
Pin Assignments (Top View)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 7 of 441
R8C/28 Group, R8C/29 Group
1.6
1. Overview
Pin Functions
Table 1.5 lists Pin Functions.
Table 1.5
Pin Functions
Type
Symbol
I/O Type
Description
Power supply input
VCC, VSS
I
Apply 2.2 to 5.5 V (J, K version are 2.7 to 5.5 V) to the VCC
pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
I
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins. To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XCIN clock input
(N, D version)
XCIN
I
XCIN clock output
(N, D version)
XCOUT
O
INT interrupt input
INT0, INT1, INT3
I
INT interrupt input pins
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAO
O
Timer RA output pin
TRAIO
I/O
Timer RA I/O pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
Serial interface
I2C bus interface
Clock synchronous
serial I/O with chip
select
Reference voltage
input
I
External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Sharing output-compare output / input-capture input / PWM /
PWM2 output pins
CLK0
I/O
Clock I/O pin
RXD0, RXD1
I
Receive data input pin
TXD0, TXD1
O
Transmit data output pin
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
VREF
I
Reference voltage input pin to A/D converter
I
Analog input pins to A/D converter
A/D converter
AN8 to AN11
I/O port
P1_0 to P1_7,
P3_3 to P3_5, P3_7,
P4_5
Input port
P4_2, P4_6, P4_7
I: Input
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins. To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
O: Output
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
I/O
I
I/O: Input and output
Page 8 of 441
Data I/O pin
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P1_0 to P1_7 also function as LED drive ports (N, D version).
Input-only ports
R8C/28 Group, R8C/29 Group
Table 1.6
Pin Name Information by Pin Number
Pin
Control Pin
Number
Port
1
P3_5
2
P3_7
3
4
5
6
7
8
1. Overview
RESET
XOUT/
XCOUT(2)
VSS/AVSS
XIN/XCIN(2)
VCC/AVCC
MODE
9
Interrupt
I/O Pin Functions for of Peripheral Modules
Clock
Synchronous
I2C bus
Timer
Serial Interface
Serial I/O with Interface
Chip Select
TRCIOD
SSCK
SCL
TRAO
RXD1/(TXD1)(1)
A/D
Converter
SSO
P4_7
P4_6
(RXD1)(1)
P4_5
INT0
10
P1_7
INT1
TRAIO
11
P1_6
(INT1)(1)
(TRAIO)(1)
CLK0
(SSI)(1)
12
P1_5
13
P1_4
14
P1_3
KI3
TRBO
AN11
15
16
17
VRFF
RXD0
TXD0
P1_2
KI2
TRCIOB
AN10
P4_2
P1_1
KI1
TRCIOA/
TRCTRG
AN9
KI0
18
P1_0
19
P3_3
20
P3_4
INT3
AN8
TRCCLK
SSI
TRCIOC
SCS
NOTES:
1. This can be assigned to the pin in parentheses by a program.
2. XCIN, XCOUT can be used only for N or D version.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 9 of 441
SDA
R8C/28 Group, R8C/29 Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
A0
A1
FB
b19
b15
Address registers(1)
Frame base register(1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 10 of 441
R8C/28 Group, R8C/29 Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 11 of 441
R8C/28 Group, R8C/29 Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 12 of 441
R8C/28 Group, R8C/29 Group
3.
3. Memory
Memory
3.1
R8C/28 Group
Figure 3.1 is a Memory Map of R8C/28 Group. The R8C/28 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte internal
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
8 Kbytes
0E000h
512 bytes
005FFh
R5F21284SNSP, R5F21284SDSP,
R5F21284JSP, R5F21284KSP,
R5F21284SNXXXSP, R5F21284SDXXXSP,
R5F21284JXXXSP, R5F21284KXXXSP
16 Kbytes
0C000h
1 Kbyte
007FFh
R5F21286JSP, R5F21286KSP,
R5F21286JXXXSP, R5F21286KXXXSP
32 Kbytes
08000h
1.5 Kbytes
009FFh
R5F21282SNSP, R5F21282SDSP,
R5F21282SNXXXSP, R5F21282SDXXXSP
Figure 3.1
Memory Map of R8C/28 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 13 of 441
R8C/28 Group, R8C/29 Group
3.2
3. Memory
R8C/29 Group
Figure 3.2 is a Memory Map of R8C/29 Group. The R8C/29 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte
internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0XXXXh
02400h
Internal ROM
(data flash)(1)
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
02BFFh
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Size
Address 0XXXXh
R5F21292SNSP, R5F21292SDSP,
R5F21292SNXXXSP, R5F21292SDXXXSP
8 Kbytes
0E000h
512 bytes
005FFh
R5F21294SNSP, R5F21294SDSP,
R5F21294JSP, R5F21294KSP,
R5F21294SNXXXSP, R5F21294SDXXXSP,
R5F21294JXXXSP, R5F21294KXXXSP
16 Kbytes
0C000h
1 Kbyte
007FFh
R5F21296JSP, R5F21296KSP,
R5F21296JXXXSP, R5F21296KXXXSP
32 Kbytes
08000h
1.5 Kbytes
009FFh
Figure 3.2
Memory Map of R8C/29 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 14 of 441
R8C/28 Group, R8C/29 Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
SFR Information (1)(1)
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
PM1
CM0
CM1
00h
00h
01101000b
00100000b
Protect Register
PRCR
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
00000100b
XXh
XXh
00X11111b
00h
00h
00h
00h
00h
00h
00h
Count Source Protection Mode Register
CSPR
00h
10000000b(2)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
FRA0
FRA1
FRA2
00h
When shipping
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4(3)
CPSRF
FRA4
00h
When shipping
High-Speed On-Chip Oscillator Control Register 6(3)
High-Speed On-Chip Oscillator Control Register 7(3)
FRA6
FRA7
When shipping
When shipping
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The CSPROINI bit in the OFS register is set to 0.
3. In J, K version these regions are reserved. Do not access locations in these regions.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 15 of 441
R8C/28 Group, R8C/29 Group
Table 4.2
Address
0030h
0031h
0032h
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register
Symbol
After reset
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
0033h
0034h
0035h
0036h
Voltage Monitor 1 Circuit Control Register(5)
VW1C
0037h
0038h
Voltage Monitor 2 Circuit Control Register(5)
Voltage Monitor 0 Circuit Control Register(6)
VW2C
VW0C
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RE Interrupt Control Register
TREIC
XXXXX000b
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU/IIC bus Interrupt Control Register(9)
KUPIC
ADIC
SSUIC/IICIC
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
S0TIC
S0RIC
S1TIC
S1RIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
Timer RA Interrupt Control Register
TRAIC
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
• N, D version 00h(3)
00100000b(4)
• J, K version 00h(7)
01000000b(8)
• N, D version 00001000b
• J, K version 0000X000b(7)
0100X001b(8)
00h
0000X000b(3)
0100X001b(4)
0039h
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
006Fh
0070h
007Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.
6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
(J, K version) These regions are reserved. Do not access locations in these regions.
7. The LVD1ON bit in the OFS register is set to 1 and hardware reset.
8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.
9. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 16 of 441
R8C/28 Group, R8C/29 Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register
Symbol
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
SS Control Register H / IIC bus Control Register 1(2)
SS Control Register L / IIC bus Control Register 2(2)
SS Mode Register / IIC bus Mode Register(2)
SS Enable Register / IIC bus Interrupt Enable Register(2)
SS Status Register / IIC bus Status Register(2)
SS Mode Register 2 / Slave Address Register(2)
SS Transmit Data Register / IIC bus Transmit Data Register(2)
SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
SSTDR / ICDRT
SSRDR / ICDRR
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 17 of 441
After reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FFh
FFh
R8C/28 Group, R8C/29 Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register
Symbol
After reset
A/D Register
AD
XXh
XXh
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00h
00h
Port P1 Register
P1
00h
Port P1 Direction Register
PD1
00h
Port P3 Register
P3
00h
Port P3 Direction Register
Port P4 Register
PD3
P4
00h
00h
Port P4 Direction Register
PD4
00h
Pin Select Register 1
Pin Select Register 2
Pin Select Register 3
Port Mode Register
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
Port P1 Drive Capacity Control Register(2)
PINSR1
PINSR2
PINSR3
PMR
INTEN
INTF
KIEN
PUR0
PUR1
P1DRR
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. In J, K version these regions are reserved. Do not access locations in these regions.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 18 of 441
R8C/28 Group, R8C/29 Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
4. Special Function Registers (SFRs)
SFR Information (5)(1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
00h
00h
00h
FFh
FFh
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register(2)
Timer RE Day of Week Data Register(2)
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
TRCCR2
TRCDF
TRCOER
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011111b
00h
01111111b
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. In J, K version these regions are reserved. Do not access locations in these regions.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 19 of 441
After reset
R8C/28 Group, R8C/29 Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6)(1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 20 of 441
Symbol
After reset
R8C/28 Group, R8C/29 Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh
4. Special Function Registers (SFRs)
SFR Information (7)(1)
Register
Symbol
After reset
Flash Memory Control Register 4
FMR4
01000000b
Flash Memory Control Register 1
FMR1
1000000Xb
Flash Memory Control Register 0
FMR0
00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 21 of 441
R8C/28 Group, R8C/29 Group
5.
5. Resets
Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset (for N, D version only),
voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit (N, D Version), and
Figure 5.2 shows the Block Diagram of Reset Circuit (J, K Version).
Table 5.1
Reset Names and Sources
Reset Name
Source
Hardware reset
Power-on reset
Input voltage of RESET pin is held “L”
VCC rises
VCC falls (monitor voltage: Vdet0)
Voltage monitor 0 reset(1)
Voltage monitor 1 reset
Voltage monitor 2 reset
Watchdog timer reset
Software reset
VCC falls (monitor voltage: Vdet1)
VCC falls (monitor voltage: Vdet2)
Underflow of watchdog timer
Write 1 to PM03 bit in PM0 register
NOTE:
1. For N, D version only.
Hardware reset
RESET
SFRs
Bits VCA25,
VW0C0, and
VW0C6
Power-on reset
circuit
VCC
Power-on reset
Voltage monitor 0 reset
Voltage
detection
circuit
Voltage monitor 1 reset
Voltage monitor 2
reset
Watchdog
timer
CPU
SFRs
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Watchdog timer
reset
Pin, CPU, and
SFR bits other than
those listed above
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Figure 5.1
Block Diagram of Reset Circuit (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 22 of 441
R8C/28 Group, R8C/29 Group
5. Resets
Hardware reset
RESET
SFRs
Bits VCA25,
VW0C0, and
VW0C6
Power-on reset
circuit
VCC
Power-on reset
Voltage monitor 0 reset
Voltage
detection
circuit
Voltage monitor 1 reset
Voltage monitor 2
reset
Watchdog
timer
CPU
SFRs
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Watchdog timer
reset
Pin, CPU, and
SFR bits other than
those listed above
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Figure 5.2
Block Diagram of Reset Circuit (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 23 of 441
R8C/28 Group, R8C/29 Group
5. Resets
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.3 shows the CPU Register Status after
Reset, Figure 5.4 shows the Reset Sequence, and Figure 5.5 shows the OFS Register.
Table 5.2
Pin Functions while RESET Pin Level is “L”
Pin Name
P1
P3_3 to P3_5, P3_7
P4_2, P4_5 to P4_7
Pin Functions
Input port
Input port
Input port
b15
b0
0000h
Data register(R0)
0000h
Data register(R1)
0000h
Data register(R2)
0000h
0000h
0000h
0000h
Data register(R3)
b19
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
Interrupt table register(INTB)
Program counter(PC)
b0
0000h
User stack pointer(USP)
0000h
Interrupt stack pointer(ISP)
0000h
Static base register(SB)
b15
b0
Flag register(FLG)
0000h
b15
b8
IPL
Figure 5.3
b0
b7
U I O B S Z D C
CPU Register Status after Reset
fOCO-S
RESET pin
10 cycles or more are needed(1)
fOCO-S clock × 32 cycles(2)
Internal reset
signal
Start time of flash memory
(CPU clock × 14 cycles)
CPU clock × 28 cycles
CPU clock
0FFFCh
0FFFEh
Address
(internal address
signal)
0FFFDh
Content of reset vector
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Figure 5.4
Reset Sequence
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 24 of 441
R8C/28 Group, R8C/29 Group
5. Resets
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
LVD1ON
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2, 4)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
Voltage detection 1
circuit start bit(5, 6)
0 : Voltage monitor 1 reset enabled after hardw are
reset
1 : Voltage monitor 1 reset disabled after hardw are
reset
RW
Count source protect
CSPROINI mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
RW
RW
RW
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
4. For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are
reset).
5. The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the
LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).
6. For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are
reset).
Figure 5.5
OFS Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 25 of 441
R8C/28 Group, R8C/29 Group
5.1
5. Resets
Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.6 shows an Example of Hardware Reset Circuit and Operation and Figure 5.7 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1
When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs or more.
(3) Apply “H” to the RESET pin.
5.1.2
Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 20. Electrical
Characteristics).
(4) Wait for 10 µs or more.
(5) Apply “H” to the RESET pin.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 26 of 441
R8C/28 Group, R8C/29 Group
5. Resets
VCC
VCC
2.2 V
(2.7 V for
J, K version)
0V
RESET
RESET
0.2 VCC or below
0V
td(P-R) + 10 µs or more
NOTE:
1. Refer to 20. Electrical Characteristics.
Figure 5.6
Example of Hardware Reset Circuit and Operation
Supply voltage
detection circuit
RESET
5V
VCC
VCC
2.2 V
(2.7 V for
J, K version)
0V
5V
RESET
0V
td(P-R) + 10 µs or more
Example when
VCC = 5 V
NOTE:
1. Refer to 20. Electrical Characteristics.
Figure 5.7
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 27 of 441
R8C/28 Group, R8C/29 Group
5.2
5. Resets
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 (Vdet1 for J, K version) level or above, the low-speed
on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal
reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figures 5.8 and 5.9 show the Example of Power-On Reset Circuit and Operation.
VCC
4.7 kΩ
(reference)
RESET
Vdet0(3)
Vdet0(3)
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 20. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.8
Example of Power-On Reset Circuit and Operation (N, D version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 28 of 441
R8C/28 Group, R8C/29 Group
5. Resets
VCC
4.7 kΩ
(reference)
RESET
Vdet1(3)
Vdet1(3)
trth
trth
2.0 V
External
power VCC
td(Vdet1-A)
Vpor2
Vpor1
tw(por1)
Sampling time(1, 2)
Internal reset
signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 20. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS
register to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the
VCA2 register to 1.
Figure 5.9
Example of Power-On Reset Circuit and Operation (J, K version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 29 of 441
R8C/28 Group, R8C/29 Group
5.3
5. Resets
Voltage Monitor 0 Reset (N, D Version)
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset. Setting the LVD0ON
bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.5 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4
Voltage Monitor 1 Reset (N, D Version)
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5
Voltage Monitor 1 Reset (J, K Version)
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet1 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.4). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD1ON bit in the OFS register can be used to enable or disable voltage monitor 1 reset. Setting the LVD1ON
bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register
to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register
to 1.
The LVD1ON bit cannot be changed by a program. To set the LVD1ON bit, write 0 (voltage monitor 1 reset
enabled after hardware reset) or 1 (voltage monitor 1 reset disabled after hardware reset) to bit 6 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.5 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 30 of 441
R8C/28 Group, R8C/29 Group
5.6
5. Resets
Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.7
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.
Refer to 13. Watchdog Timer for details of the watchdog timer.
5.8
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 31 of 441
R8C/28 Group, R8C/29 Group
6.
6. Voltage Detection Circuit
Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC
input voltage by a program. Alternately, voltage monitor 0 reset (for N, D version only), voltage monitor 1 interrupt
(for N, D version only), voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be
used.
Tables 6.1 and 6.2 list the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.6 show the Block Diagrams.
Figures 6.7 to 6.12 show the associated registers.
Table 6.1
VCC Monitor
Specifications of Voltage Detection Circuit (N, D Version)
Item
Voltage to monitor
Detection target
Monitor
Process
Reset
When Voltage
is Detected
Interrupt
Digital Filter
Switch
enabled/disabled
Sampling time
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Voltage Detection 0
Vdet0
Whether passing
through Vdet0 by rising
or falling
None
Voltage Detection 1
Voltage Detection 2
Vdet1
Vdet2
Passing through Vdet1 by Passing through Vdet2 by
rising or falling
rising or falling
VW1C3 bit in VW1C
register
Whether VCC is higher or
lower than Vdet1
Voltage monitor 0 reset Voltage monitor 1 reset
Reset at Vdet0 > VCC; Reset at Vdet1 > VCC;
restart CPU operation at restart CPU operation
VCC > Vdet0
after a specified time
None
Voltage monitor 1 interrupt
Interrupt request at Vdet1
> VCC and VCC > Vdet1
when digital filter is
enabled;
interrupt request at Vdet1
> VCC or VCC > Vdet1
when digital filter is
disabled
Available
Available
VCA13 bit in VCA1
register
Whether VCC is higher or
lower than Vdet2
Voltage monitor 2 reset
Reset at Vdet2 > VCC;
restart CPU operation
after a specified time
Voltage monitor 2 interrupt
Interrupt request at Vdet2
> VCC and VCC > Vdet2
when digital filter is
enabled;
interrupt request at Vdet2
> VCC or VCC > Vdet2
when digital filter is
disabled
Available
(Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S)
×4
×4
n: 1, 2, 4, and 8
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
×4
n: 1, 2, 4, and 8
Page 32 of 441
R8C/28 Group, R8C/29 Group
Table 6.2
VCC Monitor
Specifications of Voltage Detection Circuit (J, K Version)
Item
Voltage to monitor
Detection target
Monitor
Process
Reset
When Voltage
is Detected
Voltage Detection 1
Vdet1
Whether passing through Vdet1
by rising or falling
None
Voltage monitor 1 reset
Reset at Vdet1 > VCC;
restart CPU operation at VCC >
Vdet1
None
Interrupt
Digital Filter
6. Voltage Detection Circuit
Switch
enabled/disabled
Sampling time
Voltage Detection 2
Vdet2
Passing through Vdet2 by rising or falling
VCA13 bit in VCA1 register
Whether VCC is higher or lower than Vdet2
Voltage monitor 2 reset
Reset at Vdet2 > VCC; restart CPU operation
after a specified time
Available
Voltage monitor 2 interrupt
Interrupt request at Vdet2 > VCC and VCC >
Vdet2 when digital filter is enabled;
interrupt request at Vdet2 > VCC or VCC >
Vdet2 when digital filter is disabled
Available
(Divide-by-n of fOCO-S) × 4
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S) × 4
n: 1, 2, 4, and 8
VCA27
VCC
Noise
filter
+
Internal
reference
voltage
-
Voltage detection 2
signal
≥ Vdet2
VCA1 register
b3
VCA13 bit
VCA26
Noise
filter
+
-
≥ Vdet1
Voltage detection 1
signal
VW1C register
b3
VCA25
Voltage detection 0
signal
+
-
Figure 6.1
≥ Vdet0
Block Diagram of Voltage Detection Circuit (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
VW1C3 bit
Page 33 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
VCA27
VCC
Internal
reference
voltage
-
Voltage detection 2
signal
Noise
filter
+
≥ Vdet2
VCA1 register
b3
VCA26
VCA13 bit
-
Figure 6.2
Voltage detection 1
signal
Noise
filter
+
≥ Vdet1
Block Diagram of Voltage Detection Circuit (J, K Version)
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
Voltage detection 0 circuit
= 10b
fOCO-S
1/2
1/2
1/2
= 11b
VCA25
VW0C1
VCC
Internal
reference
voltage
+
Digital
filter
Voltage
detection 0
signal
-
Voltage detection 0
signal is held “H” when
VCA25 bit is set to 0
(disabled)
Voltage monitor 0
reset signal
VW0C1
VW0C0
VW0C7
VW0C6
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register
VCA25: Bit in VCA2 register
Figure 6.3
Block Diagram of Voltage Monitor 0 Reset Generation Circuit (For N, D Version Only)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 34 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0
= 00b
= 01b
Voltage detection 1 circuit
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
= 10b
fOCO-S
1/2
1/2
1/2
= 11b
VCA26
VW1C1
VW1C3
VCC
+
Noise filter
Internal
reference
voltage
(Filter width: 200 ns)
Digital
filter
Voltage
detection
1 signal
Watchdog
timer interrupt
signal
VW1C2
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Voltage monitor 1
interrupt signal
Non-maskable
interrupt signal
VW1C1
Oscillation stop
detection
interrupt signal
VW1C7
VW1C0
VW1C6
Voltage monitor 1
reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
Figure 6.4
Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit (N, D Version)
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0
= 00b
= 01b
Voltage detection 1 circuit
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
= 10b
fOCO-S
1/2
1/2
1/2
= 11b
VCA26
VW1C1
VW1C3
VCC
+
Noise filter
Internal
reference
voltage
(Filter width: 200 ns)
Digital
filter
Voltage
detection
1 signal
VW1C2
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
VW1C1
VW1C7
VW1C0
VW1C6
Voltage monitor 1
reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
Figure 6.5
Block Diagram of Voltage Monitor 1 Interrupt Generation Circuit (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 35 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage monitor 2 interrupt/reset generation circuit
VW2F1 to VW2F0
= 00b
= 01b
Voltage detection 2 circuit
= 10b
fOCO-S
1/2
1/2
1/2
VW2C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
= 11b
VCA27
VW2C1
VCA13
VCC
+
Noise filter
Internal
reference
voltage
(Filter width: 200 ns)
Digital
filter
Voltage
detection
2 signal
Watchdog
timer interrupt
signal
VW2C2
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Voltage monitor 2
interrupt signal
Non-maskable
interrupt signal
VW2C1
Oscillation stop
detection
interrupt signal
Watchdog timer block
VW2C3
VW2C7
Watchdog timer
underflow signal
This bit is set to 0 (not detected) by writing 0
by a program.
VW2C0
VW2C6
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
Figure 6.6
Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 36 of 441
Voltage monitor 2
reset signal
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
After Reset(2)
00001000b
Function
Symbol
Address
0031h
VCA1
Bit Symbol
Bit Name
—
Reserved bits
(b2-b0)
VCA13
—
(b7-b4)
Set to 0.
Voltage detection 2 signal monitor
flag(1)
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled
Reserved bits
Set to 0.
RW
RW
RO
RW
NOTES:
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
Voltage Detection Register 2(1) (N, D Version)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
VCA2
Bit Symbol
VCA20
—
(b4-b1)
Address
0032h
Bit Name
Internal pow er low
consumption enable bit(6)
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
: 00100000b
Function
0 : Disables low consumption
1 : Enables low consumption
RW
RW
Reserved bits
Set to 0.
VCA25
Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled
RW
VCA26
Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 6.7
Registers VCA1 and VCA2 (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 37 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Detection Register 2(1) (J, K Version)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
VCA2
Bit Symbol
VCA20
—
(b5-b1)
Address
0032h
Bit Name
Internal pow er low
consumption enable bit(5)
After Reset(4)
The LVD1ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 1 reset
or LVD1ON bit in the OFS register is
set to 0, and hardw are reset
: 0100000b
Function
0 : Disables low consumption
1 : Enables low consumption
RW
RW
Reserved bits
Set to 0.
VCA26
Voltage detection 1 enable
bit(2)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(3)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 1 reset, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. Softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register.
5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 6.8
VCA2 Register (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 38 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW0C
Bit Symbol
VW0C0
VW0C1
VW0C2
—
(b3)
0038h
Bit Name
Voltage monitor 0 reset
enable bit(3)
Function
0 : Disable
1 : Enable
Set to 0.
Reserved bit
When read, the content is undefined.
Sampling clock select bits
b5 b4
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
RW
RW
Reserved bit
VW0F1
VW0C7
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 0000X000b
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset
: 0100X001b
Voltage monitor 0 digital filter 0 : Digital filter enabled mode
(digital filter circuit enabled)
disable mode select bit
1 : Digital filter disabled mode
(digital filter circuit disabled)
VW0F0
VW0C6
After Reset(2)
Address
RW
RW
1
2
4
8
RO
RW
RW
Voltage monitor 0 circuit
mode select bit
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1.
RW
Voltage monitor 0 reset
generation condition select
bit(4)
When the VW0C1 bit is set to 1 (digital filter
disabled mode), set to 1.
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register.
2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Figure 6.9
VW0C Register (For N, D Version Only)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 39 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register(1) (N, D Version)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW1C
Bit Symbol
VW1C0
VW1C1
VW1C2
VW1C3
Address
0036h
Bit Name
Voltage monitor 1 interrupt/reset
enable bit(6)
After Reset(8)
00001000b
Function
RW
0 : Disable
1 : Enable
RW
Voltage monitor 1 digital filter
disable mode select bit(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
Voltage change detection
flag(3, 4, 8)
0 : Not detected
1 : Vdet1 crossing detected
RW
Voltage detection 1 signal monitor
flag(3, 8)
0 : VCC < Vdet1
1 : VCC ≥ Vdet1 or voltage detection 1
circuit disabled
RO
Sampling clock select bits
b5 b4
VW1F0
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
VW1F1
1
2
4
8
RW
RW
VW1C6
Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode
RW
VW1C7
Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).
6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or
voltage monitor 2 reset.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Figure 6.10
VW1C Register (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 40 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register(1) (J, K Version)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW1C
Bit Symbol
VW1C0
VW1C1
Address
0036h
Bit Name
Voltage monitor 1 reset
enable bit(4)
After Reset(6)
The LVD1ON bit in the OFS register is
set to 1 and hardw are reset
: 0000X000b
Pow er-on reset, voltage monitor 1 reset
or LVD1ON bit in the OFS register is set
to 0, and hardw are reset
: 0100X001b
Function
0 : Disable
1 : Enable
RW
Voltage monitor 1 digital filter 0 : Digital filter enabled mode
(digital filter circuit enabled)
disable mode select bit(2)
1 : Digital filter disabled mode
(digital filter circuit disabled)
—
(b2)
Reserved bit
Set to 0.
—
(b3)
Reserved bit
When read, the content is undefined.
Sampling clock select bits
b5 b4
VW1F0
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
VW1F1
RW
RW
RW
1
2
4
8
VW1C6
Voltage monitor 1 circuit
mode select bit(3)
When the VW1C0 bit is 1(voltage monitor 1 reset
enabled), set to 1.
VW1C7
Voltage monitor 1 reset
generation condition select
bit(5, 7)
When the VW1C1 bit is 1(digital filter disabled
mode), set to 1.
RO
RW
RW
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
3. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 reset enabled).
4. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
5. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
6. Softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register.
7. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Figure 6.11
VW1C Register (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 41 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW2C
Bit Symbol
VW2C0
VW2C1
VW2C2
VW2C3
Address
0037h
Bit Name
Voltage monitor 2 interrupt/reset 0 : Disable
1 : Enable
enable bit(6)
RW
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
Voltage change detection
flag(3,4,8)
0 : Not detected
1 : VCC has crossed Vdet2
RW
WDT detection flag(4,8)
0 : Not detected
1 : Detected
RW
Sampling clock select bits
b5 b4
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
VW2F1
VW2C7
RW
Voltage monitor 2 digital filter
disable mode select bit(2)
VW2F0
VW2C6
After Reset(8)
00h
Function
Voltage monitor 2 circuit mode
select bit(5)
1
2
4
8
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode
Voltage monitor 2 interrupt/reset 0 : When VCC reaches Vdet2 or above
generation condition select
1 : When VCC reaches Vdet2 or below
bit(7,9)
RW
RW
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register.
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset
(for N, D version only), or voltage monitor 2 reset.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or
below ). (Do not set to 0.)
Figure 6.12
VW2C Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 42 of 441
R8C/28 Group, R8C/29 Group
6.1
6. Voltage Detection Circuit
VCC Input Voltage
6.1.1
Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2
Monitoring Vdet1
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed
(refer to 20. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.
6.1.3
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed
(refer to 20. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 43 of 441
R8C/28 Group, R8C/29 Group
6.2
6. Voltage Detection Circuit
Voltage Monitor 0 Reset (For N, D Version only)
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.13 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C register to 1 (digital filter disabled).
Table 6.3
Step
1
2
3
4(1)
5(1)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor Reset
When Using Digital Filter
When Not Using Digital Filter
Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to
by the VW0F0 to VW0F1 bits in the VW0C 1
register
Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to
0 (digital filter enabled)
1 (digital filter disabled)
Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
Set the VW0C2 bit in the VW0C register to 0
Set the CM14 bit in the CM1 register to 0 −
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of
− (No wait time required)
the digital filter
Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
NOTE:
1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet0
Sampling clock of
digital filter × 4 cycles
When the VW0C1 bit is set
to 0 (digital filter enabled)
1
× 32
fOCO-S
Internal reset signal
1
× 32
fOCO-S
When the VW0C1 bit is set
to 1 (digital filter disabled)
and the VW0C7 bit is set
to 1
Internal reset signal
VW0C1 and VW0C7: Bits in VW0C register
The above applies under the following conditions.
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.13
Example of Voltage Monitor 0 Reset Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 44 of 441
R8C/28 Group, R8C/29 Group
6.3
6. Voltage Detection Circuit
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset (N, D Version)
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.14
shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation (N, D Version). To use
the voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C
register to 1 (digital filter disabled).
Table 6.4
Step
1
2
3
4(2)
5(2)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
When Using Digital Filter
When Not Using Digital Filter
Voltage Monitor 1
Voltage Monitor 1
Voltage Monitor 1
Voltage Monitor 1
Interrupt
Reset
Interrupt
Reset
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
request by the VW1C7 bit in the VW1C
by the VW1F0 to VW1F1 bits in the VW1C
register
register(1)
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1
(digital filter enabled)
(digital filter disabled)
Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in
the VW1C register to the VW1C register to the VW1C register to the VW1C register to
0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1
reset mode)
interrupt mode)
reset mode)
interrupt mode)
Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 45 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
VCC
Vdet1
2.2 V(1)
1
VW1C3 bit
0
4 cycles of sampling clock of digital filter
4 cycles of sampling clock of digital filter
1
VW1C2 bit
0
Set to 0 by a program
When the VW1C1 bit is set
to 0 (digital filter enabled)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
Set to 0 by a program
1
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 0
(Vdet1 or above)
VW1C2 bit
0
Set to 0 by interrupt
request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by a program
1
VW1C2 bit
0
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 1
(Vdet1 or below)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by interrupt
request acknowledgement
Internal reset signal
(VW1C6 = 1)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.14
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation (N, D
Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 46 of 441
R8C/28 Group, R8C/29 Group
6.4
6. Voltage Detection Circuit
Voltage Monitor 1 Reset (J, K Version)
Table 6.5 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Reset. Figure 6.15 shows an
Example of Voltage Monitor 1 Reset Operation (J, K Version). To use the voltage monitor 1 reset to exit stop mode,
set the VW1C1 bit in the VW1C register to 1 (digital filter disabled).
Table 6.5
Step
1
2
3
4(1)
5(1)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor 1 Reset
When Using Digital Filter
When Not Using Digital Filter
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW1C7 bit in the VW1C register to 1
by the VW1F0 to VW1F1 bits in the VW1C
register
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1
(digital filter enabled)
(digital filter disabled)
Set the VW1C6 bit in the VW1C register to 1 (voltage monitor 1 reset mode)
Set the VW1C2 bit in the VW1C register to 0
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 reset enabled)
NOTE:
1. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet1
Sampling clock of
digital filter × 4 cycles
When the VW1C1 bit is set
to 0 (digital filter enabled)
1
× 32
fOCO-S
Internal reset signal
1
× 32
fOCO-S
When the VW1C1 bit is set
to 1 (digital filter disabled)
and the VW1C7 bit is set
to 1
Internal reset signal
VW1C1 and VW1C7: Bits in VW1C register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 reset enabled)
• VW1C6 bit in VW1C register = 1 (voltage monitor 1 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.15
Example of Voltage Monitor 1 Reset Operation (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 47 of 441
R8C/28 Group, R8C/29 Group
6.5
6. Voltage Detection Circuit
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.6 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.16
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Table 6.6
Step
1
2
3
4
5(2)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
When Using Digital Filter
When Not Using Digital Filter
Voltage Monitor 2
Voltage Monitor 2
Voltage Monitor 2
Voltage Monitor 2
Interrupt
Reset
Interrupt
Reset
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
request by the VW2C7 bit in the VW2C
by the VW2F0 to VW2F1 bits in the VW2C
register
register(1)
Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1
(digital filter enabled)
(digital filter disabled)
Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in
the VW2C register to the VW2C register to the VW2C register to the VW2C register to
0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2
reset mode)
interrupt mode)
reset mode)
interrupt mode)
Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
Set the CM14 bit in the CM1 register to 0
−
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 48 of 441
R8C/28 Group, R8C/29 Group
6. Voltage Detection Circuit
VCC
Vdet2
2.2 V(1)
1
VCA13 bit
0
4 cycles of sampling clock of digital filter
4 cycles of sampling clock of digital filter
1
VW2C2 bit
0
Set to 0 by a program
When the VW2C1 bit is set
to 0 (digital filter enabled)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
Set to 0 by a program
1
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 0
(Vdet2 or above)
VW2C2 bit
0
Set to 0 by interrupt
request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by a program
1
VW2C2 bit
0
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 1
(Vdet2 or below)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by interrupt
request acknowledgement
Internal reset signal
(VW2C6 = 1)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.16
Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 49 of 441
R8C/28 Group, R8C/29 Group
7.
7. Programmable I/O Ports
Programmable I/O Ports
There are 13 programmable Input/Output ports (I/O ports) P1, P3_3 to P3_5, P3_7, and P4_5. Also, P4_6 and P4_7
can be used as input-only ports if the XIN clock oscillation circuit and XCIN clock oscillation circuit(1) is not used, and
the P4_2 can be used as an input-only port if the A/D converter is not used.
Table 7.1 lists an Overview of Programmable I/O Ports.
NOTE:
1. The XCIN clock oscillation circuit cannot be used for J, K version.
Table 7.1
Overview of Programmable I/O Ports
Ports
P1
I/O
I/O
Type of Output
CMOS3 State
I/O Setting
Set per bit
Set every 4 bits(1)
P3_3 to P3_5, P3_7
I/O
CMOS3 State
Set per bit
Set every 1 bit, 3 bits(1)
P4_5
I/O
CMOS3 State
Set per bit
Set every bit(1)
(No output function)
None
None
P4_2(2)
P4_6, P4_7(3)
I
Internal Pull-Up Resister
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers
PUR0 and PUR1.
2. When the A/D converter is not used, this port can be used as the input-only port.
3. When the XIN clock oscillation circuit and XCIN clock oscillation circuit (for N, D version only) is not
used, these ports can be used as the input-only ports.
7.1
Functions of Programmable I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 1, 3, 4) register controls I/O of the ports P1, P3_3 to P3_5, P3_7, and P4_5.
The Pi register consists of a port latch to hold output data and a circuit to read pin states.
Figures 7.1 to 7.4 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.6 shows the PDi (i = 1, 3, 4) Register. Figure 7.7 shows the Pi (i = 1, 3, 4)
Register, Figure 7.8 shows Registers PINSR1, PINSR2, and PINSR3, Figure 7.9 shows the PMR Register, Figure
7.10 shows Registers PUR0 and PUR1, and Figure 7.11 shows the P1DRR Register.
Table 7.2
Functions of Programmable I/O Ports
Operation When
Value of PDi_j Bit in PDi Register(1)
Accessing
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Pi Register
Reading
Read pin input level
Read the port latch
Write to the port latch. The value written to
Writing
Write to the port latch
the port latch is output from the pin.
i = 1, 3, 4, j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD3_0 to PD3_2, PD3_6, PD4_0 to PD4_4, PD4_6, and PD4_7.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 50 of 441
R8C/28 Group, R8C/29 Group
7.2
7. Programmable I/O Ports
Effect on Peripheral Functions
Programmable I/O ports function as I/O ports for peripheral functions (refer to Table 1.6 Pin Name Information
by Pin Number).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, j = 0 to
7). Refer to the description of each function for information on how to set peripheral functions.
Table 7.3
Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 1, 3, 4, j = 0 to 7)
I/O of Peripheral Functions
PDi_j Bit Settings for Shared Pin Functions
Input
Set this bit to 0 (input mode).
Output
This bit can be set to either 0 or 1 (output regardless of the port setting)
7.3
Pins Other than Programmable I/O Ports
Figure 7.5 shows the Configuration of I/O Pins.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 51 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Drive capacity select
(For N, D version only)
P1_0 to P1_3
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
Analog input
Drive capacity select
(For N, D version only)
Drive capacity select
(For N, D version only)
P1_4
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Drive capacity select
(For N, D version only)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.1
Configuration of Programmable I/O Ports (1)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 52 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Drive capacity select
(For N, D version only)
P1_5 and P1_7
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Port latch
Data bus
(Note 1)
Digital
filter
Input to external interrupt
Input to individual peripheral function
Drive capacity select
(For N, D version only)
Drive capacity select
(For N, D version only)
P1_6
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Port latch
Data bus
(Note 1)
Input to individual peripheral function
Drive capacity select
(For N, D version only)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.2
Configuration of Programmable I/O Ports (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 53 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
P3_3
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Port latch
Data bus
(Note 1)
Input to individual peripheral function
Input to external interrupt
P3_4, P3_5, and P3_7
Digital
filter
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.3
Configuration of Programmable I/O Ports (3)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 54 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
(Note 1)
P4_2/VREF
Data bus
(Note 1)
P4_5
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
Digital
filter
Input to external interrupt
(N, D Version)
P4_6/XIN
(Note 1)
Data bus
CM01
CM13
XIN
oscillation
circuit
0
1
(Note 1)
XCIN
oscillation
circuit
CM04
CM05
CM11
CM12
RfXIN
RfXCIN
P4_7/XOUT
0
1
(Note 2)
(Note 1)
CM01
Data bus
(Note 1)
(J, K Version)
P4_6/XIN
(Note 1)
Data bus
CM13
(Note 1)
XIN
oscillation
circuit
CM05
CM11
RfXIN
P4_7/XOUT
(Note 2)
(Note 1)
Data bus
(Note 1)
NOTES:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. This pin is pulled up in one of the following conditions:
• CM01 = CM05 = CM13 = 1
• CM01 = CM04 = 1
• CM01 = CM10 = CM13 = 1
• CM01 = CM10 = CM04 = 1
CM01, CM04, CM05: Bits in CM0 register
CM10, CM13: Bits in CM1 register
Figure 7.4
Configuration of Programmable I/O Ports (4)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 55 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
MODE
MODE signal input
(Note 1)
RESET
RESET signal input
(Note 1)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.5
Configuration of I/O Pins
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 56 of 441
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Port Pi Direction Register (i = 1, 3, 4)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD1
PD3
PD4
Bit Symbol
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Address
00E3h
00E7h
00EAh
Bit Name
Port Pi_0 direction bit
Port Pi_1 direction bit
Port Pi_2 direction bit
Port Pi_3 direction bit
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit
Port Pi_7 direction bit
After Reset
00h
00h
00h
Function
0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. Bits PD3_0 to PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU.
If it is necessary to set bits PD3_0 to PD3_2 and PD3_6, set to 0 (input mode). When read, the content is 0.
2. Bits PD4_0 to PD4_4, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_4, PD4_6, and PD4_7, set to 0 (input mode). When read, the content is 0.
Figure 7.6
PDi (i = 1, 3, 4) Register
Port Pi Register (i = 1, 3, 4)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P1
P3
P4
Bit Symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Address
00E1h
00E5h
00E8h
Bit Name
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit
Port Pi_7 bit
After Reset
00h
00h
00h
Function
The pin level of any I/O port w hich is set
to input mode can be read by reading the
corresponding bit in this register. The pin
level of any I/O port w hich is set to output
mode can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
NOTES:
1. Bits P3_0 to P3_2 and P3_6 in the P3 register are unavailable on this MCU.
If it is necessary to set bits P3_0 to P3_2 and P3_6, set to 0 (“L” level). When read, the content is 0.
2. Bits P4_0, P4_1, P4_3, and P4_4, in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0, P4_1, P4_3, and P4_4, set to 0 (“L” level). When read, the content is 0.
Figure 7.7
Pi (i = 1, 3, 4) Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 57 of 441
RW
RW
RW
RW
RW
RW
RW
RW
RW
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Pin Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 1
Symbol
PINSR1
Bit Symbol
Address
00F5h
Bit Name
TXD1/RXD1 pin select bit(1)
After Reset
00h
Function
RW
b1 b0
0 0 : P3_7(TXD1/RXD1)
0 1 : P3_7(TXD1), P4_5(RXD1)
1 0 : Do not set.
1 1 : Do not set.
UART1SEL0
UART1SEL1
—
(b2)
Reserved bit
Set to 1. When read, the content is 0.
—
(b7-b3)
Reserved bits
Set to 0. When read, the content is 0.
RW
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN in the PMR register. Refer to Figure 7.9 PMR
Register .
Pin Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 0 0 0 0
Symbol
PINSR2
Bit Symbol
—
(b5-b0)
TRBOSEL
—
(b7)
Address
00F6h
Bit Name
Reserved bits
After Reset
00h
Function
Set to 0. When read, the content is 0.
TRBO pin select bit(1)
0 : Disabled
1 : Enabled
Reserved bit
Set to 0. When read, the content is 0.
RW
RW
RW
RW
NOTE:
1. Set the TRBOSEL bit to 1 (enabled) before using timer RB.
Pin Select Register 3
b7 b6 b5 b4 b3 b2 b1 b0
1
1 1 1
Symbol
PINSR3
Bit Symbol
—
(b2-b0)
TRCIOCSEL
TRCIODSEL
—
(b5)
—
(b7-b6)
Address
00F7h
Bit Name
Reserved bits
After Reset
00h
Function
Set to 1. When read, the content is 0.
TRCIOC pin select bit(1)
0 : Disabled
1 : Enabled
RW
TRCIOD pin select bit(1)
0 : Disabled
1 : Enabled
RW
Reserved bit
Set to 1. When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Set these bits to 1 (enabled) before using timer RC.
Figure 7.8
Registers PINSR1, PINSR2, and PINSR3
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 58 of 441
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
00F8h
PMR
Bit Symbol
Bit Name
—
Reserved bit
(b0)
—
(b2-b1)
SSISEL
U1PINSEL
TXD1SEL
TXD1EN
IICSEL
After Reset
00h
Function
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
SSI pin select bit
0 : P3_3
1 : P1_6
TXD1 pin sw itch bit(1)
Set to 1 to use UART1.
Port/TXD1 pin sw itch bit(1)
0 : Programmable I/O port
1 : TXD1
RW
TXD1/RXD1 select bit(1)
0 : RXD1
1 : TXD1
RW
SSU / I2C bus pin sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN, and bits UART1SEL1 and UART1SEL0 in the
PINSR1 register.
PINSR1 Register
UART1SEL1,
UART1SEL0 bit
00b
01b
Pin Function
PMR Register
TXD1SEL bit
TXD1EN bit
P3_7(TXD1)
P3_7(RXD1)
P3_7(TXD1)
1
P4_5(RXD1)
×
×: 0 or 1
Figure 7.9
PMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
×
Page 59 of 441
1
0
×
R8C/28 Group, R8C/29 Group
7. Programmable I/O Ports
Pull-Up Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
Address
00FCh
PUR0
Bit Symbol
Bit Name
—
Reserved bits
(b1-b0)
PU02
PU03
—
(b5-b4)
PU06
PU07
(1)
After Reset
00h
Function
Set to 0. When read, the content is 0.
P1_0 to P1_3 pull-up
P1_4 to P1_7 pull-up(1)
Reserved bits
0 : Not pulled up
1 : Pulled up
P3_3 pull-up(1)
P3_4, P3_5, P3_7 pull-up(1)
0 : Not pulled up
1 : Pulled up
Set to 0. When read, the content is 0.
RW
RW
RW
RW
RW
RW
RW
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0
Symbol
Address
00FDh
PUR1
Bit Symbol
Bit Name
—
Reserved bit
(b0)
After Reset
00h
Function
Set to 0. When read, the content is 0.
P4_5 pull-up(1)
0 : Not pulled up
1 : Pulled up
—
(b5-b2)
Reserved bits
Set to 0. When read, the content is 0.
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
PU11
RW
RW
RW
RW
—
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Figure 7.10
Registers PUR0 and PUR1
Port P1 Drive Capacity Control Register (For N, D Version Only)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P1DRR
Bit Symbol
P1DRR0
P1DRR1
P1DRR2
P1DRR3
P1DRR4
P1DRR5
P1DRR6
P1DRR7
Address
00FEh
Bit Name
P1_0 drive capacity
P1_1 drive capacity
P1_2 drive capacity
P1_3 drive capacity
P1_4 drive capacity
P1_5 drive capacity
P1_6 drive capacity
P1_7 drive capacity
NOTE:
1. Both “H” and “L” output are set to high drive capacity.
Figure 7.11
P1DRR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 60 of 441
After Reset
00h
Function
Set P1 output transistor drive capacity
0 : Low
1 : High(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
R8C/28 Group, R8C/29 Group
7.4
7. Programmable I/O Ports
Port Settings
Tables 7.4 to 7.25 list the port settings.
Table 7.4
Port P1_0/KI0/AN8
Register
PD1
KIEN
Bit
PD1_0
KI0EN
ADCON0
0
0
X
X
X
X
Input port(1)
Setting
Value
1
0
X
X
X
X
Output port
0
1
X
X
X
X
KI0 input(1)
0
0
1
0
0
1
A/D converter input (AN8)
CH2
CH1
CH0
Function
ADGSEL0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.5
Register
Bit
Setting
Value
Port P1_1/KI1/AN9/TRCIOA/TRCTRG
PD1
KIEN
Timer RC Setting
ADCON0
−
PD1_1 KI1EN
CH2
CH1
CH0 ADGSEL0
Function
0
0
Other than TRCIOA usage conditions
X
X
X
X
Input port(1)
1
0
Other than TRCIOA usage conditions
X
X
X
X
Output port
0
0
Other than TRCIOA usage conditions
1
0
1
1
A/D converter input (AN9)
0
1
Other than TRCIOA usage conditions
X
X
X
X
KI1 input(1)
X
0
Refer to Table 7.6 TRCIOA Pin
Setting
X
X
X
X
TRCIOA output
0
0
Refer to Table 7.6 TRCIOA Pin
Setting
X
X
X
X
TRCIOA input(1)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.6
TRCIOA Pin Setting
Register
TRCOER
TRCMR
Bit
EA
PWM2
0
1
0
Setting
Value
1
1
TRCIOR0
IOA2
IOA1
0
0
1
0
TRCCR2
IOA0
TCEG1
TCEG0
0
1
X
X
1
X
X
X
1
X
X
X
X
X
X
X
X
X
0
1
1
X
Other than above
Function
Timer waveform output
(output compare function)
Timer mode (input capture function)
PWM2 mode TRCTRG input
Other than TRCIOA usage conditions
X: 0 or 1
Table 7.7
Register
Bit
Setting
Value
Port P1_2/KI2/AN10/TRCIOB
PD1
KIEN
Timer RC Setting
−
PD1_2 KI2EN
ADCON0
CH2
CH1
CH0 ADGSEL0
Function
0
0
Other than TRCIOB usage conditions
X
X
X
X
Input port(1)
1
0
Other than TRCIOB usage conditions
X
X
X
X
Output port
0
0
Other than TRCIOB usage conditions
1
1
0
1
A/D converter input (AN10)
0
1
Other than TRCIOB usage conditions
X
X
X
X
KI2 input(1)
X
0
Refer to Table 7.8 TRCIOB Pin
Setting
X
X
X
X
TRCIOB output
0
0
Refer to Table 7.8 TRCIOB Pin
Setting
X
X
X
X
TRCIOB input(1)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 61 of 441
R8C/28 Group, R8C/29 Group
Table 7.8
7. Programmable I/O Ports
TRCIOB Pin Setting
Register
TRCOER
Bit
EB
Setting
Value
TRCMR
TRCIOR0
PWMB
0
0
X
X
X
X
PWM2 mode waveform output
0
1
1
X
X
X
PWM mode waveform output
0
1
0
0
0
1
0
1
X
Timer waveform output (output compare
function)
1
0
1
X
X
Timer mode (input capture function)
0
1
IOB2
IOB1
Function
PWM2
IOB0
Other than above
Other than TRCIOB usage conditions
X: 0 or 1
Table 7.9
Port P1_3/KI3/AN11/TRBO
Register
PD1
KIEN
Timer RB Setting
Bit
PD1_3
KI3EN
−
CH2
CH1
CH0
ADGSEL0
0
0
Other than TRBO usage conditions
X
X
X
X
Input port(1)
Setting
Value
ADCON0
Function
1
0
Other than TRBO usage conditions
X
X
X
X
Output port
0
0
Other than TRBO usage conditions
1
1
1
1
A/D converter input (AN11)
0
1
Other than TRBO usage conditions
X
X
X
X
KI3 input
0
Refer to Table 7.10 TRBO Pin
Setting
X
X
X
X
TRBO output
X
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.10
TRBO Pin Setting
Register
PINSR2
TRBIOC
Bit
TRBOSEL
TOCNT(1)
Setting
Value
TRBMR
TMOD1
Function
TMOD0
1
0
0
1
Programmable waveform generation mode
1
0
1
0
Programmable one-shot generation mode
1
0
1
1
Programmable wait one-shot generation mode
1
1
0
1
P1_3 output port
Other than above
Other than TRBO usage conditions
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
Table 7.11
Port P1_4/TXD0
Register
PD1
Bit
PD1_4
SMD2
SMD1
SMD0
0
0
0
0
Input port(1)
1
0
0
0
Output port
Setting
Value
X
U0MR
0
0
1
1
0
0
1
0
1
1
1
0
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 62 of 441
Function
TXD0 output(2)
R8C/28 Group, R8C/29 Group
Table 7.12
7. Programmable I/O Ports
Port P1_5/RXD0/(TRAIO)/(INT1)
Register
PD1
Bit
PD1_5
TIOSEL
TRAIOC
TOPCR(3)
TMOD2
TMOD1
TMOD0
INT1EN
0
X
X
X
X
X
0
1
1
0
0
1
0
1
Setting
Value
0
X
TRAMR
INTEN
1
0
0
0
0
0
0
X
X
X
X
X
1
0
0
0
0
X
0
X
X
X
X
X
1
0
1
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
1
0
Other than 001b
0
Output port
RXD0 input(1)
TRAIO input(1)
0
Other than 000b, 001b
0
Input port(1)
0
Other than 000b, 001b
1
Function
INT1(2)
1
TRAIO input/INT1(1, 2)
X
TRAIO pulse output
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set bit 0 (reserved bit) in the PMR register to 0.
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
Table 7.13
Register
Bit
Setting
Value
Port P1_6/CLK0/(SSI)
PD1
U0MR
PD1_6 CKDIR
0
X
Clock Synchronous Serial I/O with Chip
Select (Refer to Table 16.4
Association between
Communication Modes and I/O Pins.)
PMR
Function(3)
SMD2
SMD1
SMD0
IICSEL
SSI output control
SSI input control
X
X
X
X
0
0
Input port(1)
1
X
X
0
0
Output port
X
0
0
Other than 001b
0
1
X
0
0
CLK0 output
0
1
X
X
X
X
0
0
CLK0 input(1)
X
X
X
X
X
0
1
0
SSI output(2)
X
X
X
X
X
0
0
1
SSI input(1, 2)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the SSISEL bit in the PMR register to 1 (P1_6).
3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register,
this pin is set to N-channel open drain output.
Table 7.14
Port P1_7/TRAIO/INT1
Register
PD1
Bit
PD1_7
TIOSEL
TRAIOC
TOPCR(3)
TMOD2
TMOD1
TMOD0
INT1EN
1
X
X
X
X
X
0
0
1
0
0
1
0
0
0
0
0
0
0
1
X
X
X
X
X
0
0
0
0
0
X
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
1
Setting
Value
0
X
TRAMR
INTEN
Other than 000b, 001b
Other than 000b, 001b
0
0
1
0
Page 63 of 441
Input port(1)
Output port
TRAIO input(1)
INT1(2)
1
TRAIO input/INT1(1, 2)
X
TRAIO pulse output
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set bit 0 (reserved bit) in the PMR register to 0.
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Function
R8C/28 Group, R8C/29 Group
Table 7.15
7. Programmable I/O Ports
Port P3_3/INT3/SSI/TRCCLK
Clock Synchronous Serial I/O with Chip
Select (Refer to Table 16.4
Association between
Communication Modes and I/O Pins.)
TRCCR1
INTEN
Register
PD3
PMR
Bit
PD3_3
IICSEL
SSI output control
SSI input control
0
X
0
0
Other than 101b
0
Input port(1)
1
X
0
0
Other than 101b
0
Output port
0
X
0
0
1
INT3 input(1)
0
X
0
0
0
TRCCLK input(1)
X
0
1
0
Other than 101b
0
SSI output(2)
X
0
0
1
Other than 101b
0
SSI input(2)
Setting
Value
TCK2
TCK1
TCK0
Other than 101b
1
0
1
Function(3)
INT3EN
X: 0 or 1
NOTES:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. Set the SSISEL bit in the PMR register to 0 (P3_3).
3. When the SOOS bit is set to 1 (N-channel open drain output) and BIDE bit is set to 0 (standard mode) in the SSMR2 register,
this pin is set to N-channel open drain output.
Table 7.16
Port P3_4/SDA/SCS/TRCIOC
Register
PD3
PMR
ICCR1
Bit
PD3_4
IICSEL
ICE
0
X
0
0
Other than TRCIOC usage conditions
1
0
0
0
Other than TRCIOC usage conditions
0
X
0
0
Other than TRCIOC usage conditions
1
0
0
0
Other than TRCIOC usage conditions
0
1
Setting
Value
SSMR2
CSS1
Timer RC setting
Function(2)
−
CSS0
Input port(1)
Output port
X
X
0
0
0
Refer to Table 7.17 TRCIOC Pin Setting TRCIOC output
0
X
0
0
0
Refer to Table 7.17 TRCIOC Pin Setting TRCIOC input(1)
X
0
X
1
0
Other than TRCIOC usage conditions
SCS output
X
0
X
1
1
Other than TRCIOC usage conditions
SCS input(1)
X
1
1
X
X
Other than TRCIOC usage conditions
SDA input/output
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open drain output).
Table 7.17
TRCIOC Pin Setting
Register
PINSR3
TRCOER
Bit
TRCIOCSEL
EC
PWM2
PWMC
IOC2
IOC1
IOC0
1
0
1
1
X
X
X
PWM mode waveform output
0
0
1
0
1
X
Timer waveform output (output compare
function)
1
X
X
Timer mode (input capture function)
1
Setting
Value
1
0
1
0
1
1
TRCMR
TRCIOR1
1
0
1
0
Other than above
X: 0 or 1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 64 of 441
Function
Other than TRCIOC usage conditions
R8C/28 Group, R8C/29 Group
Table 7.18
Register
Port P3_5/SCL/SSCK/TRCIOD
PD3
Bit
7. Programmable I/O Ports
PMR
ICCR1
Clock Synchronous Serial I/O with Chip
Select (Refer to Table 16.4
Association between Communication
Modes and I/O Pins.)
Function(2)
ICE
SSCK output
control
SSCK input
control
−
0
X
0
0
Other than TRCIOD
usage conditions
1
0
0
0
Other than TRCIOD
usage conditions
0
X
0
0
Other than TRCIOD
usage conditions
1
0
0
0
Other than TRCIOD
usage conditions
X
X
0
0
0
Refer to Table 7.19
TRCIOD Pin Setting
TRCIOD output
0
X
0
0
0
Refer to Table 7.19
TRCIOD Pin Setting
TRCIOD input(1)
X
0
X
1
0
Other than TRCIOD
usage conditions
SSCK output(2)
X
0
X
0
1
Other than TRCIOD
usage conditions
SSCK input(1)
X
1
1
X
X
Other than TRCIOD
usage conditions
SCL input/output
PD3_5 IICSEL
0
1
Setting
Value
Timer RC setting
Input port(1)
Output port
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the SCKOS bit in the SSMR2 register to 1 (N-channel open drain output).
Table 7.19
TRCIOD Pin Setting
Register
PINSR3
TRCOER
Bit
TRCIODSEL
EC
PWM2
PWMD
IOD2
IOD1
IOD0
1
0
1
1
X
X
X
PWM mode waveform output
0
0
1
0
1
X
Timer waveform output (output
compare function)
1
X
X
Timer mode (input capture function)
1
Setting
Value
1
0
1
0
1
1
TRCMR
TRCIOR1
1
0
1
0
Other than above
X: 0 or 1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 65 of 441
Function
Other than TRCIOD usage conditions
R8C/28 Group, R8C/29 Group
Table 7.20
Port P3_7/TRAO/SSO/RXD1/(TXD1)
Register
PD3
PMR
Bit
PD3_7
IICSEL
Setting
Value
7. Programmable I/O Ports
Clock Synchronous Serial I/O with Chip
Select (Refer to Table 16.4
TRAMR
Association between
Communication Modes and I/O Pins.)
SSO output control
SSO input control
UART1 setting
Function(3)
−
TOENA
0
X
0
0
0
Other than TXD1, RXD1
Input port(1)
usage conditions
1
X
0
0
0
Other than TXD1, RXD1
Output port
usage conditions
X
X
0
0
X
Refer to Table 7.21Port
P3_7 UART1 Setting
Condition
TXD1 output(4)
0
X
0
0
0
Refer to Table 7.21Port
P3_7 UART1 Setting
Condition
RXD1 input(1)
X
X
0
0
1
Other than TXD1, RXD1
TRAO output
usage conditions
X
0
1
0
X
Other than TXD1, RXD1
SSO output(2)
usage conditions
X
0
0
1
X
Other than TXD1, RXD1
SSO input(2)
usage conditions
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. Set the SSISEL bit in the PMR register to 0 (P3_3).
3. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open drain output).
4. N-channel open drain output by setting the NCH bit in the U1C0 register to 1.
Table 7.21
Port P3_7 UART1 Setting Condition(1)
Register
Bit
PINSR1
UART1SEL1
PMR
UART1SEL0
TXD1SEL
0
Setting
Value
U1MR
TXD1EN
X
1
0
1
0
1
X
X
0
Other than above
X: 0 or 1
NOTE:
1. Set the U1PINSEL bit in the PMR register to 1 (enabled).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 66 of 441
SMD2
SMD1
SMD0
0
0
1
1
0
0
1
0
1
1
1
0
0
0
1
1
0
0
1
0
1
1
1
0
X
X
X
Function
TXD1 output
RXD1 input
Other than TXD1, RXD1
usage conditions
R8C/28 Group, R8C/29 Group
Table 7.22
7. Programmable I/O Ports
Port P4_2/VREF
Register
ADCON1
Bit
VCUT
Setting
Value
0
Input port
1
Input port/VREF input
Table 7.23
Function
Port P4_5/INT0/(RXD1)
Register
PD4
INTEN
Bit
PD4_5
INT0EN
PINSR1
0
0
Other than 01b
Input port(1)
Setting
Value
1
0
Other than 01b
Output port
0
1
0
0
UART1SEL1
Function
UART1SEL0
Other than 01b
0
INT0 input(1)
RXD1(1, 2)
1
NOTES:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Set the U1PINSEL bit in the PMR register to 1.
Table 7.24
Port P4_6/XIN/XCIN
Register
Bit
CM0
CM1
Circuit specifications
CM01
CM04
CM05
CM13
CM12
CM11
CM10
X
0
1
0
X
X
0
OFF
−
0
ON
ON
XIN clock oscillation (on-chip
feedback resistor enabled)
1
ON
OFF
XIN clock oscillation (on-chip
feedback resistor disabled)
OFF
ON
External clock input
0
0
0
X
1
X
0
0
OFF
ON
1
OFF
OFF
XIN clock oscillation stop (onchip feedback resistor disabled)
OFF
OFF
XIN clock oscillation stop (stop
mode)
0
ON
ON
XCIN clock oscillation (on-chip
feedback resistor enabled)(1)
1
ON
OFF
XCIN clock oscillation (on-chip
feedback resistor disabled)(1)
OFF
ON
External XCIN clock input(1)
OFF
ON
XCIN clock oscillation stop (onchip feedback resistor
enabled)(1)
OFF
OFF
XCIN clock oscillation stop (onchip feedback resistor
disabled)(1)
OFF
OFF
XCIN clock oscillation stop
(stop mode)(1)
1
1
1
0
0
1
X
X
0
X
0
1
1
X: 0 or 1
NOTE:
1. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 67 of 441
Input port
XIN clock oscillation stop (onchip feedback resistor enabled)
1
Setting
Value
Function
Oscillation Feedback
buffer
resistor
1
R8C/28 Group, R8C/29 Group
Table 7.25
Port P4_7/XOUT/XCOUT
Register
Bit
7. Programmable I/O Ports
CM0
CM1
Circuit specifications
CM01
CM04
CM05
CM13
CM12
CM11
CM10
X
0
1
0
X
X
0
OFF
−
0
ON
ON
XIN clock oscillation (on-chip
feedback resistor enabled)
1
ON
OFF
XIN clock oscillation (on-chip
feedback resistor disabled)
OFF
ON
External clock input
0
0
X
1
X
0
0
0
OFF
ON
1
OFF
OFF
XIN clock oscillation stop (onchip feedback resistor disabled)
OFF
OFF
XOUT pulled up(2)
0
ON
ON
XCIN clock oscillation (on-chip
feedback resistor enabled)(1, 2)
1
ON
OFF
XCIN clock oscillation (on-chip
feedback resistor disabled)(1, 2)
OFF
ON
External XCIN clock input(2)
OFF
ON
XCIN clock oscillation stop (onchip feedback resistor
enabled)(2)
OFF
OFF
XCIN clock oscillation stop (onchip feedback resistor
disabled)(2)
OFF
OFF
XCOUT pulled up(2)
1
1
1
0
1
X
X
Input port
XIN clock oscillation stop (onchip feedback resistor enabled)
1
Setting
Value
Function
Oscillation Feedback
buffer
resistor
0
X
0
0
1
1
1
X: 0 or 1
NOTES:
1. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as
the CMOS level signal directly.
2. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 68 of 441
R8C/28 Group, R8C/29 Group
7.5
7. Programmable I/O Ports
Unassigned Pin Handling
Table 7.26 lists the Unassigned Pin Handling.
Table 7.26
Unassigned Pin Handling
Pin Name
Ports P1, P3_3 to P3_5, P3_7,
P4_5
Connection
• After setting to input mode, connect each pin to VSS via a resistor
(pull-down) or connect each pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1, 2)
Ports P4_6, P4_7
Port P4_2/VREF
Connect to VCC via a pull-up resistor(2)
Connect to VCC
RESET (3)
Connect to VCC via a pull-up resistor(2)
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
MCU
Port P1, (Input mode )
:
P3_3 to P3_5, P3_7,
:
P4_5,
(Input mode)
(Output mode)
Port P4_6, P4_7
RESET(1)
Port P4_2/VREF
NOTE:
1. When the power-on reset function is in use.
Figure 7.12
Unassigned Pin Handling
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 69 of 441
:
:
Open
R8C/28 Group, R8C/29 Group
8.
8. Processor Mode
Processor Mode
8.1
Processor Modes
Single-chip mode can be selected as the processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Table 8.1
Features of Processor Mode
Processor Mode
Single-chip mode
Accessible Areas
Pins Assignable as I/O Port Pins
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
Address
PM0
0004h
Bit Symbol
Bit Name
—
Reserved bits
(b2-b0)
PM03
—
(b7-b4)
Softw are reset bit
After Reset
00h
Function
Set to 0.
RW
RW
The MCU is reset w hen this bit is set to 1.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
—
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 8.1
PM0 Register
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
PM1
0005h
Bit Symbol
Bit Name
—
Reserved bits
(b1-b0)
PM12
—
(b6-b3)
—
(b7)
WDT interrupt/reset sw itch bit
After Reset
00h
Function
Set to 0.
0 : Watchdog timer interrupt
1 : Watchdog timer reset(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bit
Set to 0.
NOTES:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
2. The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Figure 8.2
PM1 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 70 of 441
RW
RW
RW
—
RW
R8C/28 Group, R8C/29 Group
9.
9. Bus
Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/28 Group and Table 9.2 lists Bus Cycles by Access Space of the
R8C/29 Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations.
Table 9.1
Bus Cycles by Access Space of the R8C/28 Group
Access Area
SFR
ROM/RAM
Table 9.2
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Bus Cycles by Access Space of the R8C/29 Group
Access Area
SFR/Data flash
Program ROM/RAM
Table 9.3
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Access Units and Bus Operations
SFR, data flash
Area
Even address
Byte access
CPU clock
CPU clock
Even
Address
Data
Odd address
Byte access
CPU clock
Odd
Data
Even
Data
Even+1
Data
CPU clock
Data
Data
Odd
Data
Data
CPU clock
Data
Address
Data
Address
CPU clock
Address
Even
CPU clock
Data
Odd address
Word access
Address
Data
Address
Even address
Word access
ROM (program ROM), RAM
Address
Data
Even
Data
Even+1
Data
CPU clock
Odd
Odd+1
Data
Data
Address
Data
Odd+1
Odd
Data
Data
However, only following SFRs are connected with the 16-bit bus:
Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Therefore, when accessing in word (16-bit) unit, 16-bit data is accessed at a time. The bus operation is the same as
“Area: SFR, data flash, even address byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is
accessed at a time.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 71 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
10. Clock Generation Circuit
The clock generation circuit has:
• XIN clock oscillation circuit
• XCIN clock oscillation circuit (For N, D version only)
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
However, use one of the XIN clock oscillation circuit or the XCIN clock oscillation circuit because they share the
XIN/XCIN pin and the XOUT/XCOUT pin. (For J, K version, the XCIN clock oscillation circuit cannot be used.)
Table 10.1 lists the Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures
10.2 to 10.9 show clock associated registers. Figure 10.10 shows a Procedure for Enabling Reduced Internal Power
Consumption Using VCA20 bit.
Table 10.1
Specifications of Clock Generation Circuit
Clock frequency 0 to 20 MHz
32.768 kHz
On-Chip Oscillator
High-Speed On-Chip
Low-Speed On-Chip
Oscillator
Oscillator
• CPU clock source
• CPU clock source
• Peripheral function
• Peripheral function
clock source
clock source
• CPU and peripheral
• CPU and peripheral
function clock
function clock
sources when XIN
sources when XIN
clock stops oscillating clock stops oscillating
Approx. 125 kHz
Approx. 40 MHz(5)
Connectable
oscillator
Oscillator
connect pins
Oscillation stop,
restart function
Oscillator status
after reset
Others
• Ceramic resonator
• Crystal oscillator
• Crystal oscillator
−
−
XIN, XOUT(1)
XCIN, XCOUT(1)
−(1)
−(1)
Usable
Usable
Usable
Usable
Stop
Stop
Stop
Oscillate
Item
Applications
XIN Clock Oscillation
Circuit
• CPU clock source
• Peripheral function
clock source
XCIN Clock Oscillation
Circuit
(For N, D Version Only)
• CPU clock source
• Peripheral function
clock source
• Externally generated −
• Externally generated
clock can be input(2, 3) clock can be input(4)
• On-chip feedback
• On-chip feedback
resistor RfXIN
resistor RfXCIN
(connected/ not
(connected/ not
connected, selectable) connected,
selectable)
−
NOTES:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit and XCIN clock oscillation circuit is not used.
2. Set the CM01 bit in the CM0 register to 0 (XIN clock), the CM05 bit in the CM0 register to 1 (XIN clock stopped),
and the CM13 bit in the CM1 register to 1 (XIN-XOUT pin) when an external clock is input.
3. When 32.768 kHz is used as an external clock, set the CM01 bit in the CM0 register to 1 (XCIN clock). In other
cases, set the CM01 bit in the CM0 register to 0 (XIN clock).
4. Set the CM01 bit in the CM0 register to 1 (XCIN clock) and the CM04 bit in the CM0 register to 1 (XCIN clock
oscillator) when an external clock is input.
5. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 72 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Clock prescaler
fC4
fC
1/4
fC32
1/8
FRA1 register
Frequency adjustable
High-speed
on-chip
oscillator
FRA00
fOCO40M
FRA2 register
Divider
fOCO-F
On-chip oscillator
clock
FRA01 = 1
FRA01 = 0
Stop signal
Low-speed
on-chip
oscillator
CM14
SSU /
I2C bus
INT0
Timer RA
A/D
Timer RB Timer RC Timer RE converter UART0
fOCO
Power-on
reset circuit
fOCO-S
Voltage
detection
circuit
XOUT/XCOUT(1)
XIN/XCIN(1)
fOCO128
Watchdog
timer
Divider
CM01 = 0
f1
b
CM13
f2
c
CM05
Oscillation
stop
detection
f4
d
f8
e
g
OCD2 = 1
f32
CM01 = 0
a
CM04
CM01
XIN
clock
CPU clock
Divider
OCD2 = 0
CM01 = 1
XCIN
clock
System clock
CM02
CM10 = 1 (stop mode)
S Q
R
RESET
Power-on reset
Software reset
Interrupt request
WAIT instruction
1/2
a
g
e
d
c
b
S Q
1/2
1/2
1/2
1/2
R
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to CM16 = 10b
CM01, CM02, CM04, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01: Bits in FRA0 register
h
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
Forcible discharge when OCD0 = 0
XIN clock
Pulse generation
circuit for clock
edge detection and
charge, discharge
control circuit
Charge,
discharge
circuit
Oscillation stop detection
interrupt generation
circuit detection
OCD1
Watchdog timer
interrupt
Voltage monitor 1
interrupt
Voltage monitor 2
interrupt
OCD2 bit switch signal
CM14 bit switch signal
NOTE:
1. For J, K version, the XCIN clock oscillation circuit cannot be used.
Figure 10.1
Clock Generation Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 73 of 441
Oscillation stop detection,
Watchdog timer,
Voltage monitor 1 interrupt,
Voltage monitor 2 interrupt
UART1
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
Address
0006h
CM0
Bit Symbol
Bit Name
—
Reserved bit
(b0)
(12)
After Reset
01101000b
Function
Set to 0.
RW
RW
XIN-XCIN sw itch bit
0 : XIN clock
1 : XCIN clock
RW
WAIT peripheral function clock
stop bit
0 : Peripheral function clock does not stop
in w ait mode
1 : Peripheral function clock stops in w ait
mode
RW
CM03
XCIN-XCOUT drive capacity
select bit(2)
0 : Low
1 : High
RW
CM04
XCIN clock (XCIN-XCOUT)
oscillate bit(3, 4, 5, 12)
0 : XCIN clock stops
1 : XCIN clock oscillates (6, 7)
CM01
CM02
CM05
XIN clock (XIN-XOUT)
stop bit(3, 8)
0 : XIN clock oscillates
1 : XIN clock stops (10)
CM06
System clock division select bit
0(11)
0 : CM16, CM17 enabled
1 : Divide-by-8 mode
Reserved bit
Set to 0.
—
(b7)
RW
(9)
RW
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. The MCU enters stop mode, the CM03 bit is set to 1 (high). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
3. P4_6 and P4_7 can be used as input ports w hen the CM04 bit is set to 0 (XCIN clock stops), the CM05 bit is set to 1
(XIN clock stops) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7).
4. The CM04 bit can be set to 1 by a program but cannot be set to 0.
5. When the CM10 bit is set to 1 (stop mode) and the CM04 bit is set to 1 (XCIN clock oscillates), the XCOUT (P4_7) pin
goes “H”.
When the CM04 bit is set to 0 (XCIN clock stops), P4_7 (XCOUT) enters input mode.
6. To use the XCIN clock, set the CM04 bit to 1. Also, set ports P4_6 and P4_7 as input ports w ithout pull-up.
7. Set the CM01 bit to 1 (XCIN clock).
8. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is
selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
follow ing order:
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
9. Set the CM01 bit to 0 (XIN clock).
10. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.
11. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
12. For J, K version, the XCIN clock oscillation circuit cannot be used. Do not set to 1.
Figure 10.2
CM0 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 74 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Bit Symbol
CM10
Address
0007h
Bit Name
All clock stop control bit(4, 7, 8)
After Reset
00100000b
Function
0 : Clock operates
1 : Stops all clocks (stop mode)
RW
RW
CM11
XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled
select bit
1 : On-chip feedback resistor disabled
RW
CM12
XCIN-XCOUT on-chip feedback
resistor select bit(10)
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled
RW
Port XIN-XOUT sw itch bit
0 : Input ports P4_6, P4_7
1 : XIN-XOUT pin
RW
Low -speed on-chip oscillation stop
bit(5, 6, 8)
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator off
RW
0 : Low
1 : High
RW
(7, 9)
CM13
CM14
(2)
CM15
XIN-XOUT drive capacity select bit
(3)
System clock division select bits 1
CM16
CM17
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2. When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
3. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
4. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
5. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). It remains unchanged even if 1 is w ritten to it.
6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
7. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
8. In count source protect mode (refer to 13.2 Count Source Protection Mode Enabled), the value remains
unchanged even if bits CM10 and CM14 are set.
9. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
10. For J, K version, the XCIN clock oscillation circuit cannot be used. Set to 0.
Figure 10.3
CM1 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 75 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
OCD
Bit Symbol
OCD0
OCD1
Address
After Reset
000Ch
00000100b
Bit Name
Function
Oscillation stop detection enable 0 : Oscillation stop detection function
disabled(2)
bit(7)
1 : Oscillation stop detection function
enabled
Oscillation stop detection
interrupt enable bit
(4)
OCD2
OCD3
—
(b7-b4)
0 : Disabled(2)
1 : Enabled
RW
RW
RW
(7)
System clock select bit
0 : Selects XIN clock
1 : Selects on-chip oscillator clock(3)
RW
Clock monitor bit(5, 6)
0 : XIN clock oscillates
1 : XIN clock stops
RO
Reserved bits
Set to 0.
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains
unchanged even w hen set to 0 (XIN clock selected).
5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).
6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
7. Refer to Figure 10.18 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN
Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Figure 10.4
OCD Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 76 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
FRA0
Bit Symbol
FRA00
FRA01
—
(b7-b2)
Address
0023h
Bit Name
High-speed on-chip oscillator
enable bit
After Reset
00h
Function
0 : High-speed on-chip oscillator off
1 : High-speed on-chip oscillator on
RW
RW
(3)
High-speed on-chip oscillator
select bit(2)
0 : Selects low -speed on-chip oscillator
1 : Selects high-speed on-chip oscillator
Reserved bits
Set to 0.
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register.
2. Change the FRA01 bit under the follow ing conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register:
All divide ratio mode settings are supported w hen VCC = 3.0 to 5.5 V
000b to 111b (other than K version)
Divide ratio of 4 or more w hen VCC = 2.7 to 5.5 V or K version
010b to 111b
Divide ratio of 8 or more w hen VCC = 2.2 to 5.5 V (for N, D version only) 110b to 111b
3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time.
Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
High-Speed On-Chip Oscillator Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA1
Address
0024h
After Reset
When Shipping
Function
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping)
Setting the FRA1 register to a low er value results in a higher frequency.
Setting the FRA1 register to a higher value results in a low er frequency.(2)
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register.
2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
Figure 10.5
Registers FRA0 and FRA1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 77 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
FRA2
Bit Symbol
FRA20
Address
0025h
Bit Name
High-speed on-chip oscillator
frequency sw itching bits
After Reset
00h
Function
Selects the dividing ratio for the highspeed on-chip oscillator clock.
b2 b1 b0
RW
RW
(2)
0 0 0: Divide-by-2 mode
0 0 1: Divide-by-3 mode(2)
0 1 0: Divide-by-4 mode
0 1 1: Divide-by-5 mode
1 0 0: Divide-by-6 mode
1 0 1: Divide-by-7 mode
1 1 0: Divide-by-8 mode
1 1 1: Divide-by-9 mode
FRA21
FRA22
—
(b7-b3)
Reserved bits
Set to 0.
RW
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.
2. Do not set in K version.
High-Speed On-Chip Oscillator Control Register 4 (for N, D version only)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA4
Address
0029h
After Reset
When Shipping
Function
Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that
of the FRA1 register after a reset.) Optimal frequency correction to match the voltage
conditions can be achieved by transferring this value to the FRA1 register.
RW
RO
High-Speed On-Chip Oscillator Control Register 6 (for N, D version only)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA6
Address
002Bh
After Reset
When Shipping
Function
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the FRA1
register.
RW
RO
High-Speed On-Chip Oscillator Control Register 7 (For N, D Version Only)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA7
Address
002Ch
After Reset
When Shipping
Function
36.864 MHz frequency correction data is stored.
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz
by transferring this value to the FRA1 register.
Figure 10.6
Registers FRA2, FRA4, FRA6, and FRA7
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 78 of 441
RW
RO
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Clock Prescaler Reset Flag (For N, D Version Only)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Symbol
Address
0028h
CPSRF
Bit Symbol
Bit Name
—
Reserved bits
(b6-b0)
After Reset
00h
Function
Set to 0.
(1)
CPSR
Clock prescaler reset flag
Setting this bit to 1 initializes the clock
prescaler. (When read, the content is 0)
RW
RW
RW
NOTE:
1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
Figure 10.7
CPSRF Register
Voltage Detection Register 2(1) (N, D Version)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
VCA2
Bit Symbol
VCA20
—
(b4-b1)
Address
0032h
Bit Name
Internal pow er low
consumption enable bit(6)
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
: 00100000b
Function
0 : Disables low consumption
1 : Enables low consumption
RW
RW
Reserved bits
Set to 0.
VCA25
Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled
RW
VCA26
Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 10.8
VCA2 Register (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 79 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Voltage Detection Register 2(1) (J, K Version)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
VCA2
Bit Symbol
VCA20
—
(b5-b1)
Address
0032h
Bit Name
Internal pow er low
consumption enable bit(5)
After Reset(4)
The LVD1ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 1 reset
or LVD1ON bit in the OFS register is
set to 0, and hardw are reset
: 0100000b
Function
0 : Disables low consumption
1 : Enables low consumption
RW
RW
Reserved bits
Set to 0.
VCA26
Voltage detection 1 enable
bit(2)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(3)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 1 reset, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. Softw are reset, w atchdog timer reset, or voltage monitor 2 reset do not affect this register.
5. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 10.9
VCA2 Register (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 80 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Exit wait mode by
interrupt
(Note 1)
Handling procedure of internal power
low consumption enabled by VCA20 bit
In interrupt handling routine
Step (1)
Enter low-speed clock mode or low-speed onchip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (4)
Enter wait mode(4)
Step (8)
Enter mode other than low-speed clock mode
or low-speed on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
handling routine, execute
steps (5) to (7) in the
interrupt routine.
Interrupt handling
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt handling routine,
execute steps (1) to (3) at
the last of the interrupt
routine.
Interrupt handling completed
NOTES:
1. Execute this handling to all interrupt handlings generated around the WAIT instruction. If it is not necessary to start the high-speed
clock or the high-speed on-chip oscillator in the interrupt handling, it does not need to be started.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 10.10
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 81 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
The clocks generated by the clock generation circuits are described below.
10.1
XIN Clock
This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN
pin.
Figure 10.11 shows Examples of XIN Clock Connection Circuit.
In reset and after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after
setting the CM01 bit in the CM0 register to 1 (XIN clock) and the CM13 bit in the CM1 register to 1 (XIN- XOUT
pin).
To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after
the XIN clock is oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the
OCD2 bit is set to 1 (select on-chip oscillator clock).
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If
necessary, use an external circuit to stop the clock.
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM11
bit in the CM1 register.
In stop mode, all clocks including the XIN clock stop. Refer to 10.5 Power Control for details.
MCU
(on-chip feedback resistor)
MCU
(on-chip feedback resistor)
XIN
XIN
XOUT
XOUT
Open
Rf(1)
Rd(1)
Externally derived clock
CIN
COUT
VCC
VSS
Ceramic resonator external circuit
External clock input circuit
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the manufacturer of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after
oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN
and XOUT following the instructions.
To use MCU of N, D version with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the
CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
Figure 10.11
Examples of XIN Clock Connection Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 82 of 441
R8C/28 Group, R8C/29 Group
10.2
10. Clock Generation Circuit
On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1
Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
10.2.2
High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-F, and fOCO40M.
To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:
• All divide ratio mode settings are supported when VCC = 3.0 to 5.5 V
000b to 111b
(other than K version)
• Divide ratio of 4 or more when VCC = 2.7 to 5.5 V or K version
010b to 111b
• Divide ratio of 8 or more when VCC = 2.2 to 5.5 V (for N, D version only) 110b to 111b
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by registers FRA1 and FRA2.
The frequency correction data (the value is the same as that of the FRA1 register after a reset) corresponding to
the supply voltage ranges VCC = 2.7 to 5.5 V is stored in FRA4 register. Furthermore, the frequency correction
data corresponding to the supply voltage ranges VCC = 2.2 to 5.5 V is stored in FRA6 register (for N, D version
only). To use separate correction values to match these voltage ranges, transfer them from FRA4 or FRA6
register to the FRA1 register.
The frequency correction data of 36.864 MHz is stored in the FRA7 register (for N, D version only). To set the
frequency of the high-speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7
register to the FRA1 register before use. This enables the setting errors of bit rates such as 9600 bps and 38400
bps to be 0% when the serial interface is used in UART mode (refer to Table 15.7 Bit Rate Setting Example in
UART Mode (Internal Clock Selected)).
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make
adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the
high-speed on-chip oscillator clock will be 40 MHz or less.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 83 of 441
R8C/28 Group, R8C/29 Group
10.3
10. Clock Generation Circuit
XCIN Clock (For N, D Version Only)
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, peripheral function clock. The XCIN clock oscillation circuit is configured by connecting a resonator
between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor,
which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in
the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 10.12 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock stops.
The XCIN clock starts oscillating when the CM01 bit in the CM0 register is set to 1 (XCIN clock) and the CM04
bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (selects XIN clock)
after the XCIN clock is oscillating stably.
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 10.5 Power Control for details.
MCU
(on-chip feedback resistor)
XCIN
MCU
(on-chip feedback resistor)
XCIN
XCOUT
XCOUT
Open
Rf(1)
Rd(1)
CIN
COUT
Externally derived clock
VCC
VSS
External crystal oscillator circuit
External clock input circuit
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Figure 10.12
Examples of XCIN Clock Connection Circuits
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 84 of 441
R8C/28 Group, R8C/29 Group
10.4
10. Clock Generation Circuit
CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 10.1 Clock Generation Circuit.
10.4.1
System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock and
XCIN clock or the on-chip oscillator clock can be selected. (For J, K version, the XCIN clock cannot be
selected.)
10.4.2
CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
The system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
(For J, K version, the XCIN clock cannot be selected.)
10.4.3
Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers
RA, RB, RC, and RE, the serial interface and the A/D converter.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.4.4
fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
10.4.5
fOCO40M
fOCO40M is used as the count source for timer RC. fOCO40M is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.4.6
fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does not stop.
10.4.7
fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed onchip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer,
fOCO-S does not stop.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 85 of 441
R8C/28 Group, R8C/29 Group
10.4.8
fC4 and fC32
The clock fC4 is used for timer RE and the clock fC32 is used for timer RA.
Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
(For J, K version, fC4 and fC32 cannot be used.)
10.4.9
fOCO128
fOCO128 is generated by fOCO divided by 128.
The clock fOCO128 is used for capture signal of timer RC’s TRCGRA register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 86 of 441
10. Clock Generation Circuit
R8C/28 Group, R8C/29 Group
10.5
10. Clock Generation Circuit
Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
10.5.1
Standard Operating Mode
Standard operating mode is further separated into four modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation is stabilized before exiting.
Table 10.2
Settings and Modes of Clock Associated Bits
OCD
Register
Modes
OCD2
High-speed
clock mode
Low-speed
clock
mode(1)
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
CM1 Register
CM17,
CM16
00b
01b
10b
−
11b
00b
01b
10b
−
11b
00b
01b
10b
−
11b
00b
01b
10b
−
11b
−: can be 0 or 1, no change in outcome
NOTE:
1. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 87 of 441
CM0 Register
CM14
CM13
CM06
CM05
CM04
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
FRA0 Register
CM01 FRA01 FRA00
0
0
0
0
0
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−
R8C/28 Group, R8C/29 Group
10.5.1.1
10. Clock Generation Circuit
High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (highspeed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the
watchdog timer and voltage detection circuit.
10.5.1.2
Low-Speed Clock Mode (For N, D Version Only)
The XCIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide
by-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high
speed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RC.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.5.1.3
High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as
timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the
watchdog timer and voltage detection circuit.
10.5.1.4
Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as
timer RC. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the
watchdog timer and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 88 of 441
R8C/28 Group, R8C/29 Group
10.5.2
10. Clock Generation Circuit
Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, and on-chip oscillator
clock do not stop and the peripheral functions using these clocks continue operating.
10.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop
in wait mode. This reduces power consumption.
10.5.2.2
Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.5.2.3
Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 89 of 441
R8C/28 Group, R8C/29 Group
10.5.2.4
10. Clock Generation Circuit
Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function interrupt.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 10.3
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt
Serial interface interrupt
CM02 = 0
Usable when operating with
internal or external clock
Clock synchronous serial I/O Usable in all modes
with chip select interrupt /
I2C bus interface interrupt
Key input interrupt
Usable
A/D conversion interrupt
Usable in one-shot mode
Timer RA interrupt
Usable in all modes
Timer RB interrupt
Timer RE interrupt
Usable in all modes
Usable in all modes
INT interrupt
Usable
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Oscillation stop detection
interrupt
Usable
Usable
Usable
NOTE:
1. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 90 of 441
CM02 = 1
Usable when operating with external
clock
(Do not use)
Usable
(Do not use)
Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32(1)
as count source.
(Do not use)
Usable when operating in real time
clock mode(1)
Usable (INT0, INT1, INT3 can be used
if there is no filter.)
Usable
Usable
(Do not use)
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,
as described in Figure 10.13.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
FMR0 Register
FMSTP Bit
Time until Flash Memory
is Activated (T1)
Time until CPU Clock
is Supplied (T2)
0
(flash memory operates)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of CPU clock
× 6 cycles
1
(flash memory stops)
Period of system clock
× 12 cycles
Same as above
Wait mode
Time for Interrupt
Sequence (T3)
Period of CPU clock Following total
time is the time
× 20 cycles
from wait mode
until an interrupt
routine is
Same as above
executed.
T1
T2
T3
Flash memory
activation sequence
CPU clock restart sequence
Interrupt sequence
Interrupt request generated
Figure 10.13
Time from Wait Mode to Interrupt Routine Execution
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Remarks
Page 91 of 441
R8C/28 Group, R8C/29 Group
10.5.2.5
10. Clock Generation Circuit
Reducing Internal Power Consumption
Internal power consumption can be reduced by using low-speed clock mode (for N, D version only) or lowspeed on-chip oscillator mode. Figure 10.14 shows the Procedure for Enabling Reduced Internal Power
Consumption Using VCA20 bit.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Exit wait mode by
interrupt
(Note 1)
Handling procedure of internal power
low consumption enabled by VCA20 bit
In interrupt handling routine
Step (1)
Enter low-speed clock mode or low-speed onchip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (4)
Enter wait mode(4)
Step (8)
Enter mode other than low-speed clock mode
or low-speed on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
handling routine, execute
steps (5) to (7) in the
interrupt routine.
Interrupt handling
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt handling routine,
execute steps (1) to (3) at
the last of the interrupt
routine.
Interrupt handling completed
NOTES:
1. Execute this handling to all interrupt handlings generated around the WAIT instruction. If it is not necessary to start the high-speed
clock or the high-speed on-chip oscillator in the interrupt handling, it does not need to be started.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 10.14
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 92 of 441
R8C/28 Group, R8C/29 Group
10.5.3
10. Clock Generation Circuit
Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals continue operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 10.4
Interrupts to Exit Stop Mode and Usage Conditions
Interrupt
Key input interrupt
Usage Conditions
−
INT0, INT1, INT3 interrupt
Timer RA interrupt
Serial interface interrupt
Voltage monitor 1 interrupt(1)
Voltage monitor 2 interrupt
Can be used if there is no filter
When there is no filter and external pulse is counted in event counter
mode
When external clock is selected
Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set
to 1)
Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set
to 1)
NOTE:
1. For N, D version only.
10.5.3.1
Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode), the CM03 bit in the CM0 register is set to
1 (XCIN clock oscillator circuit drive capacity high), and the CM15 bit in the CM1 register is set to 1 (XIN
clock oscillator circuit drive capacity high).
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.5.3.2
Pin Status in Stop Mode
The status before wait mode was entered is maintained.
However, when the CM01 bit in the CM0 register is set to 0 (XIN clock) and the CM13 bit in the CM1 register
is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held “H”. When the CM13 bit is set to 0 (input ports P4_6
and P4_7), the P4_7(XOUT pin) is held in input status.
When the CM01 bit in the CM0 register is set to 1 (XCIN clock) and the CM04 bit in the CM0 register is set to
1 (XCIN clock oscillates), the XCOUT(P4_7) pin is held “H”. When the CM04 bit is set to 0 (XIN clock stops),
the P4_7(XOUT pin) is held in input status.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 93 of 441
R8C/28 Group, R8C/29 Group
10.5.3.3
10. Clock Generation Circuit
Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used
for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMR0 Register
Stop
mode
FMSTP Bit
Time until Flash Memory
is Activated (T2)
Time until CPU Clock
is Supplied (T3)
0
(flash memory operates)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of CPU clock
× 6 cycles
1
(flash memory stops)
Period of system clock
× 12 cycles
Same as above
Time for Interrupt
Sequence (T4)
Period of CPU clock Following total
time of T0 to T4 is
× 20 cycles
the time from stop
mode until an
interrupt handling
Same as above
is executed.
T0
T1
T2
T3
T4
Internal
power
stability time
Oscillation time of
CPU clock source
used immediately
before stop mode
Flash memory
activation sequence
CPU clock restart
sequence
Interrupt sequence
150 µs
Interrupt (max.)
request
generated
Figure 10.15
Time from Stop Mode to Interrupt Routine Execution
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 94 of 441
Remarks
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Figure 10.16 shows the State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is set
to 0 (XIN clock)). Figure 10.17 shows the State Transitions in Power Control Mode (When the CM01 bit in the
CM0 register is set to 1 (XCIN clock)).
State Transitions in Power Control Mode
(When the CM01 bit in the CM0 register is set to 0 (XIN clock))
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM14 = 0
OCD2 = 1
FRA01 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
High-speed clock mode
CM14 = 0
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
FRA00 = 1
FRA01 = 1
OCD2 = 1
FRA00 = 1
FRA01 = 1
CM05 = 0
CM13 = 1
OCD2 = 0
High-speed on-chip oscillator mode
OCD2 = 1
FRA00 = 1
FRA01 = 1
Interrupt
WAIT instruction
CM10 = 1
Interrupt
Wait mode
Stop mode
CPU operation stops
All oscillators stop
CM05: Bit in CM0 register
CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
Figure 10.16
State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is
set to 0 (XIN clock))
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 95 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
State Transitions in Power Control Mode
(When the CM01 bit in the CM0 register is set to 1 (XCIN clock)) (For N, D version only)
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM14 = 0
OCD2 = 1
FRA01 = 0
CM04 = 1
OCD2 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM14 = 0
FRA01 = 0
Low-speed clock mode
FRA00 = 1
FRA01 = 1
CM04 = 1
OCD2 = 0
CM04 = 1
OCD2 = 0
High-speed on-chip oscillator mode
OCD2 = 1
FRA00 = 1
FRA01 = 1
OCD2 = 1
FRA00 = 1
FRA01 = 1
Interrupt
WAIT instruction
CM10 = 1
Interrupt
Wait mode
Stop mode
CPU operation stops
All oscillators stop
CM04: Bit in CM0 register
CM14: Bit in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
Figure 10.17
State Transitions in Power Control Mode (When the CM01 bit in the CM0 register is
set to 1 (XCIN clock))
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 96 of 441
R8C/28 Group, R8C/29 Group
10.6
10. Clock Generation Circuit
Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop
detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the
following state if the XIN clock stops.
• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated.
Table 10.5
Specifications of Oscillation Stop Detection Function
Item
Oscillation stop detection clock and
frequency bandwidth
Enabled condition for oscillation stop
detection function
Operation at oscillation stop detection
10.6.1
Specification
f(XIN) ≥ 2 MHz
Set bits OCD1 to OCD0 to 11b
Oscillation stop detection interrupt is generated
How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt
and watchdog timer interrupt, the interrupt source needs to be determined.
Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.19 shows the Example of Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2
Interrupt (N, D Version). Figure 10.20 shows the Example of Determining Interrupt Source for Oscillation
Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt (J, K Version).
• When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU
clock and peripheral functions by a program.
Figure 10.18 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
• To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
• Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop
mode is selected or the CM05 bit is changed).
• This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1
to OCD0 to 00b.
• To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip
oscillator selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 97 of 441
R8C/28 Group, R8C/29 Group
Table 10.6
10. Clock Generation Circuit
Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source
Bit Showing Interrupt Cause
Oscillation stop detection
(a) OCD3 bit in OCD register = 1
((a) or (b))
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer
VW2C3 bit in VW2C register = 1
VW1C2 bit in VW1C register = 1
Voltage monitor 1(1)
Voltage monitor 2
VW2C2 bit in VW2C register = 1
NOTE:
1. For N, D version only.
Switch to XIN clock
NO
Multiple confirmations
that OCD3 bit is set to 0 (XIN
clock oscillates) ?
YES
Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0
(select XIN clock)
End
OCD3 to OCD0: Bits in OCD register
Figure 10.18
Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 98 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Interrupt sources judgement
OCD3 = 1 ?
(XIN clock stopped)
NO
YES
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock selected
as system clock) ?
NO
YES
VW2C3 = 1 ?
(Watchdog timer
underflow)
NO
YES
VW2C2 = 1 ?
(passing Vdet2)
NO
YES
Set OCD1 bit to 0 (oscillation stop
detection interrupt disabled).(1)
To oscillation stop detection
interrupt routine
To watchdog timer
interrupt routine
To voltage monitor 2
interrupt routine
To voltage monitor 1
interrupt routine
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C2, VW2C3: Bits in VW2C register
Figure 10.19
Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt (N, D Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 99 of 441
R8C/28 Group, R8C/29 Group
10. Clock Generation Circuit
Interrupt sources judgement
NO
OCD3 = 1 ?
(XIN clock stopped)
YES
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock selected
as system clock) ?
NO
YES
VW2C3 = 1 ?
(Watchdog timer
underflow)
NO
YES
Set OCD1 bit to 0 (oscillation stop
detection interrupt disabled). (1)
To oscillation stop detection
interrupt routine
To watchdog timer
interrupt routine
To voltage monitor 2
interrupt routine
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C3: Bit in VW2C register
Figure 10.20
Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt (J, K Version)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 100 of 441
R8C/28 Group, R8C/29 Group
10.7
10. Clock Generation Circuit
Notes on Clock Generation Circuit
10.7.1
Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001 :
NOP
NOP
NOP
NOP
10.7.2
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
1,FMR0
FSET
I
WAIT
NOP
NOP
NOP
NOP
10.7.3
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
10.7.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 101 of 441
R8C/28 Group, R8C/29 Group
11. Protection
11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, and VW2C
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
PRCR
Bit Symbol
Address
000Ah
Bit Name
Protect bit 0
PRC0
Protect bit 1
PRC1
—
(b2)
Set to 0.
Protect bit 3
Writing to registers VCA2, VW0C, VW1C, and
VW2C is enabled.
0 : Disables w riting
1 : Enables w riting
—
(b5-b4)
Reserved bits
Set to 0.
—
(b7-b6)
Reserved bits
When read, the content is 0.
PRCR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Writing to registers PM0 and PM1 is enabled.
0 : Disables w riting
1 : Enables w riting
Reserved bit
PRC3
Figure 11.1
After Reset
00h
Function
Writing to registers CM0, CM1, OCD, FRA0, FRA1,
and FRA2 is enabled.
0 : Disables w riting
1 : Enables w riting
Page 102 of 441
RW
RW
RW
RW
RW
RW
RO
R8C/28 Group, R8C/29 Group
12. Interrupts
12. Interrupts
12.1
Interrupt Overview
12.1.1
Types of Interrupts
Figure 12.1 shows the Types of Interrupts.
Software
(non-maskable interrupts)
Interrupts
Special
(non-maskable interrupts)
Hardware
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Single step(2)
Address break(2)
Address match
Peripheral functions(1)
(maskable interrupts)
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. Do not use this interrupt. This is for use with development tools only.
Figure 12.1
Types of Interrupts
• Maskable Interrupts:
• Non-Maskable Interrupts:
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
The interrupt enable flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
Page 103 of 441
R8C/28 Group, R8C/29 Group
12.1.2
12. Interrupts
Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
12.1.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
12.1.2.2
Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
12.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 104 of 441
R8C/28 Group, R8C/29 Group
12.1.3
12. Interrupts
Special Interrupts
Special interrupts are non-maskable.
12.1.3.1
Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3
Voltage Monitor 1 Interrupt (For N, D Version Only)
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4
Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5
Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by development tools only.
12.1.3.6
Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to
1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match
Interrupt.
12.1.4
Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to the descriptions of individual peripheral functions.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 105 of 441
R8C/28 Group, R8C/29 Group
12.1.5
12. Interrupts
Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low address
Mid address
Vector address (H)
Figure 12.2
12.1.5.1
0000
High address
0000
0000
Interrupt Vector
Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 19.3 Functions to Prevent Rewriting of Flash Memory.
Table 12.1
Fixed Vector Tables
Interrupt Source
Undefined instruction
Overflow
BRK instruction
Address match
Single step(1)
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1(2),
Voltage monitor 2
Address break(1)
(Reserved)
Reset
Vector Addresses
Remarks
Reference
Address (L) to (H)
0FFDCh to 0FFDFh Interrupt on UND
R8C/Tiny Series Software
instruction
Manual
0FFE0h to 0FFE3h Interrupt on INTO
instruction
0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
0FFE8h to 0FFEBh
12.4 Address Match
Interrupt
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
5. Resets
NOTES:
1. Do not use these interrupts. They are for use by development tools only.
2. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 106 of 441
R8C/28 Group, R8C/29 Group
12.1.5.2
12. Interrupts
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 12.2 lists the Relocatable Vector Tables.
Table 12.2
Relocatable Vector Tables
Vector Addresses(1)
Address (L) to Address (H)
Interrupt Source
BRK instruction(3)
(Reserved)
(Reserved)
Timer RC
(Reserved)
Timer RE
(Reserved)
Key input
A/D
Clock synchronous
serial I/O with chip
select / I2C bus
interface(2)
(Reserved)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
(Reserved)
Timer RA
(Reserved)
Timer RB
+0 to +3 (0000h to 0003h)
+28 to +31 (001Ch to 001Fh)
+40 to +43 (0028h to 002Bh)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
Software
Interrupt Control
Interrupt
Reference
Register
Number
0
−
R8C/Tiny Series Software
Manual
−
−
1 to 2
3 to 6
−
−
7
TRCIC
14.3 Timer RC
8 to 9
−
−
10
TREIC
14.4 Timer RE
−
−
11 to 12
13
KUPIC
12.3 Key Input Interrupt
14
ADIC
18. A/D Converter
15
SSUIC/IICIC
16.2 Clock Synchronous
Serial I/O with Chip
Select (SSU),
16.3 I2C bus Interface
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
16
17
18
19
20
21
22
23
24
25
−
S0TIC
S0RIC
S1TIC
S1RIC
−
TRAIC
−
TRBIC
INT1IC
INT3
(Reserved)
(Reserved)
+104 to +107 (0068h to 006Bh)
26
INT3IC
INT0
(Reserved)
(Reserved)
+116 to +119 (0074h to 0077h)
27
28
29
−
−
INT0IC
INT1
Software interrupt(3)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
+88 to +91 (0058h to 005Bh)
30
31
+128 to +131 (0080h to 0083h) to 32 to 63
+252 to +255 (00FCh to 00FFh)
NOTES:
1. These addresses are relative to those in the INTB register.
2. The IICSEL bit in the PMR register switches functions.
3. The I flag does not disable these interrupts.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 107 of 441
−
−
−
−
15. Serial Interface
−
14.1 Timer RA
−
14.2 Timer RB
12.2 INT Interrupt
−
−
12.2 INT Interrupt
−
−
R8C/Tiny Series Software
Manual
R8C/28 Group, R8C/29 Group
12.1.6
12. Interrupts
Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC and SSUIC/IICIC and
Figure 12.5 shows the INTiIC Register (i=0, 1, 3).
Interrupt Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREIC
KUPIC
ADIC
S0TIC
S0RIC
S1TIC
S1RIC
TRAIC
TRBIC
Bit Symbol
Address
004Ah
004Dh
004Eh
0051h
0052h
0053h
0054h
0056h
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
0058h
XXXXX000b
Bit Name
Interrupt priority level select bits
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL0
ILVL1
ILVL2
IR
—
(b7-b4)
Function
Interrupt request bit
RW
b2 b1 b0
0 : Requests no interrupt
1 : Requests interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
RW
RW
RW(1)
—
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
Figure 12.3
Interrupt Control Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 108 of 441
R8C/28 Group, R8C/29 Group
12. Interrupts
Interrupt Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCIC
SSUIC/IICIC(2)
Bit Symbol
Address
0047h
After Reset
XXXXX000b
004Fh
XXXXX000b
Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
IR
—
(b7-b4)
Interrupt request bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
0 : Requests no interrupt
1 : Requests interrupt
RO
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
RW
—
NOTES:
1. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
2. The IICSEL bit in the PMR register sw itches functions.
Figure 12.4
Registers TRCIC and SSUIC/IICIC
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 109 of 441
R8C/28 Group, R8C/29 Group
12. Interrupts
INTi Interrupt Control Register (i=0, 1, 3)(2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT1IC
Address
0059h
INT3IC
005Ah
INT0IC
Bit Symbol
005Dh
Bit Name
Interrupt priority level select bits
ILVL1
ILVL2
POL
—
(b5)
—
(b7-b6)
XX00X000b
XX00X000b
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL0
IR
After Reset
XX00X000b
RW
RW
RW
Interrupt request bit
0 : Requests no interrupt
1 : Requests interrupt
RW(1)
Polarity sw itch bit(4)
0 : Selects falling edge
1 : Selects rising edge(3)
RW
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
—
NOTES:
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt
Sources.
Figure 12.5
INTiIC Register (i=0, 1, 3)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 110 of 441
R8C/28 Group, R8C/29 Group
12.1.6.1
12. Interrupts
I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2
IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt and the I 2 C bus Interface Interrupt are different. Refer to 12.5 Timer RC Interrupt, Clock
Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with
Multiple Interrupt Request Sources).
12.1.6.3
Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3
Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits
000b
Table 12.4
IPL
Interrupt Priority Levels Enabled by
IPL
Interrupt Priority Level
Priority Order
Level 0 (interrupt disabled)
−
000b
Interrupt level 1 and above
Enabled Interrupt Priority Levels
Low
001b
Interrupt level 2 and above
001b
Level 1
010b
Level 2
010b
Interrupt level 3 and above
011b
Level 3
011b
Interrupt level 4 and above
100b
Level 4
100b
Interrupt level 5 and above
101b
Level 5
101b
Interrupt level 6 and above
110b
Level 6
110b
Interrupt level 7 and above
111b
Level 7
111b
All maskable interrupts are disabled
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
High
Page 111 of 441
R8C/28 Group, R8C/29 Group
12.1.6.4
12. Interrupts
Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).(2)
(2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
(4) The CPU’s internal temporary register(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CPU Clock
Address Bus
Data Bus
Address
0000h
Undefined
Interrupt
information
RD
Undefined
SP-2 SP-1
SP-4
SP-2
SP-1
SP-4
contents contents contents
SP-3
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
PC
VEC+2
contents
Undefined
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
Figure 12.6
Time Required for Executing Interrupt Sequence
NOTES:
1. This register cannot be accessed by the user.
2. Refer to 12.5 Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and
I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) for the IR bit
operations of the timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and the
I2C bus Interface Interrupt.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 112 of 441
R8C/28 Group, R8C/29 Group
12.1.6.5
12. Interrupts
Interrupt Response Time
Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in the interrupt routine. The interrupt response time
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Interrupt request is generated. Interrupt request is acknowledged.
Time
Instruction
(a)
Instruction in
interrupt routine
Interrupt sequence
20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor)
(b) 21 cycles for address match and single-step interrupts.
Figure 12.7
12.1.6.6
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the
IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5
IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source
Watchdog timer, oscillation stop detection, voltage monitor
voltage monitor 2, address break
Software, address match, single-step
NOTE:
1. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 113 of 441
1(1),
Value Set in IPL
7
Not changed
R8C/28 Group, R8C/29 Group
12.1.6.7
12. Interrupts
Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Stack
Address
Stack
Address
MSB
LSB
MSB
LSB
m−4
m−4
PCL
m−3
m−3
PCM
m−2
m−2
FLGL
m−1
m−1
m
Previous stack contents
m+1
Previous stack contents
[SP]
SP value before
interrupt is generated
m
m+1
Stack state before interrupt request
is acknowledged
FLGH
[SP]
New SP value
PCH
Previous stack contents
Previous stack contents
PCH
PCM
PCL
FLGH
FLGL
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
Stack state after interrupt request
is acknowledged
NOTE:
1. When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.8
Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Stack
Address
Sequence in which
order registers are
saved
[SP]−5
[SP]−4
PCL
(3)
[SP]−3
PCM
(4)
[SP]−2
FLGL
(1)
Saved, 8 bits at a time
[SP]−1
FLGH
PCH
(2)
[SP]
Completed saving
registers in four
operations.
PCH
PCM
PCL
FLGH
FLGL
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing software
number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is
ISP.
Figure 12.9
Register Saving Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 114 of 441
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
R8C/28 Group, R8C/29 Group
12.1.6.8
12. Interrupts
Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 12.10 shows the Priority Levels of Hardware Interrupts.
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the
instruction is executed.
Reset
High
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Peripheral function
Single step
Address match
NOTE:
1. For N, D version only.
Figure 12.10
Priority Levels of Hardware Interrupts
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 115 of 441
Low
R8C/28 Group, R8C/29 Group
12. Interrupts
12.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11.
Priority level of interrupt
Level 0 (default value)
Highest
INT3
Timer RB
Timer RA
INT0
INT1
Timer RC
Priority of peripheral function interrupts
(if priority levels are same)
UART1 receive
UART0 receive
A/D conversion
Timer RE
UART1 transmit
UART0 transmit
SSU / I2C bus(1)
Key input
IPL
Lowest
Interrupt request level
judgment output signal
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage monitor 1(2)
Voltage monitor 2
NOTE:
1. The IICSEL bit in the PMR register switches functions.
2. For N, D version only.
Figure 12.11
Interrupt Priority Level Judgement Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 116 of 441
Interrupt request
acknowledged
R8C/28 Group, R8C/29 Group
12.2
12. Interrupts
INT Interrupt
12.2.1
INTi Interrupt (i = 0, 1, 3)
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register.
Inputs can be passed through a digital filter with three different sampling clocks.
Table 12.6 lists the Pin Configuration of INT Interrupt. Figure 12.12 shows the INTEN Register. Figure 12.13
shows the INTF Register.
Pin Configuration of INT Interrupt
Table 12.6
Pin name
Input/Output
Function
INT0 (P4_5)
Input
INT0 interrupt input, Timer RB external trigger input,
Timer RC pulse output forced cutoff input
INT1 (P1_5 or P1_7)(1)
Input
INT1 interrupt input
INT3 (P3_3)
Input
INT3 interrupt input
NOTE:
1. The INT1 pin is selected by the INT1SEL bit in the PMR register and the TIOSEL bit in the TRAIOC
register. Refer to 7. Programmable I/O Ports for details.
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
INTEN
Bit Symbol
INT0EN
Address
00F9h
Bit Name
_____
INT0 input enable bit
RW
0 : One edge
1 : Both edges
RW
0 : Disable
1 : Enable
RW
INT1 input polarity select bit(1,2)
0 : One edge
1 : Both edges
RW
Reserved bits
Set to 0.
INT0 input polarity select bit(1,2)
_____
INT1EN
INT1 input enable bit
_____
INT1PL
—
(b5-b4)
_____
INT3EN
INT3 input enable bit
_____
INT3PL
RW
0 : Disable
1 : Enable
_____
INT0PL
After Reset
00h
Function
INT3 input polarity select bit(1,2)
RW
0 : Disable
1 : Enable
RW
0 : One edge
1 : Both edges
RW
NOTES:
1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4
Changing Interrupt Sources.
Figure 12.12
INTEN Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 117 of 441
R8C/28 Group, R8C/29 Group
12. Interrupts
______
INT0 Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
INTF
Bit Symbol
Address
00FAh
Bit Name
_____
INT0F0
INT0 input filter select bits
INT0F1
_____
INT1F0
INT1 input filter select bits
INT1F1
—
(b5-b4)
INT3F0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
b7 b6
Page 118 of 441
RW
RW
b3 b2
_____
INTF Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0.
INT3 input filter select bits
RW
b1 b0
Reserved bits
INT3F1
Figure 12.13
After Reset
00h
Function
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
RW
RW
RW
R8C/28 Group, R8C/29 Group
12.2.2
12. Interrupts
INTi Input Filter (i = 0, 1, 3)
The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register. The INTi level is sampled every sampling clock cycle and if the sampled input level matches three
times, the IR bit in the INTiIC register is set to 1 (interrupt requested).
Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi
Input Filter.
INTiF1 to INTiF0
f1
f8
f32
INTi
Port direction
register(1)
= 01b
= 10b
Sampling clock
= 11b
INTiEN
Digital filter
(input level
matches 3x)
Other than
INTiF1 to INTiF0
= 00b
= 00b
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0, 1, 3
INTi interrupt
INTiPL = 0
Both edges
detection
INTiPL = 1
circuit
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin
Port P1_7 direction register when using the P1_7 pin
INT3: Port P3_3 direction register
Figure 12.14
Configuration of INTi Input Filter
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 in program
This is an operation example when bits INTiF1 to INTiF0 in the
INTiF register are set to 01b, 10b, or 11b (digital filter enabled).
i = 0, 1, 3
Figure 12.15
Operating Example of INTi Input Filter
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 119 of 441
R8C/28 Group, R8C/29 Group
12.3
12. Interrupts
Key Input Interrupt
A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can
be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether or not the pins are used as KIi input. The KIiPL
bit in the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 12.16 shows a Block Diagram of Key Input Interrupt.
PU02 bit in PUR0 register
KUPIC register
Pull-up
transistor
PD1_3 bit in PD1 register
KI3EN bit
PD1_3 bit
KI3PL = 0
KI3
KI3PL = 1
Pull-up
transistor
KI2EN bit
PD1_2 bit
KI2PL = 0
Interrupt control
circuit
KI2
KI2PL = 1
Pull-up
transistor
Key input interrupt
request
KI1EN bit
PD1_1 bit
KI1PL = 0
KI1
KI1PL = 1
Pull-up
transistor
KI0EN bit
PD1_0 bit
KI0PL = 0
KI0
KI0PL = 1
Figure 12.16
Block Diagram of Key Input Interrupt
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 120 of 441
KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
R8C/28 Group, R8C/29 Group
12. Interrupts
Key Input Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIEN
Bit Symbol
KI0EN
KI0PL
KI1EN
KI1PL
KI2EN
KI2PL
KI3EN
KI3PL
Address
00FBh
Bit Name
KI0 input enable bit
After Reset
00h
Function
RW
KI0 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI1 input enable bit
0 : Disable
1 : Enable
RW
KI1 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI2 input enable bit
0 : Disable
1 : Enable
RW
KI2 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI3 input enable bit
0 : Disable
1 : Enable
RW
KI3 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
NOTE:
1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.17
KIEN Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : Disable
1 : Enable
Page 121 of 441
R8C/28 Group, R8C/29 Group
12.4
12. Interrupts
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
• Change the content of the stack and use the REIT instruction.
• Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.
Then use a jump instruction.
Table 12.7 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged.
Figure 12.18 shows Registers AIER and RMAD0 to RMAD1.
Table 12.7
Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2)
ADD.B:S
#IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest
STNZ
#IMM8,dest STZX
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest PUSHM src
POPM
dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (however, dest = A0 or A1)
Instructions other than the above
PC Value Saved(1)
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
NOTES:
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 12.8
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 122 of 441
R8C/28 Group, R8C/29 Group
12. Interrupts
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Bit Symbol
AIER0
AIER1
—
(b7-b2)
Address
0013h
Bit Name
Address match interrupt 0 enable bit 0 : Disable
1 : Enable
After Reset
00h
Function
RW
RW
Address match interrupt 1 enable bit 0 : Disable
1 : Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Address Match Interrupt Register i (i = 0 or 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
0012h-0010h
0016h-0014h
Function
Address setting register for address match interrupt
—
Nothing is assigned. If necessary, set to 0.
(b7-b4)
When read, the content is 0.
Figure 12.18
Registers AIER and RMAD0 to RMAD1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 123 of 441
After Reset
000000h
000000h
Setting Range
RW
00000h to FFFFFh
RW
—
R8C/28 Group, R8C/29 Group
12.5
12. Interrupts
Timer RC Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt
Request Sources)
The timer RC interrupt, clock synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt each
have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt
request factors and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these
peripheral functions has its own interrupt request source status register (status register) and interrupt request source
enable register (enable register) to control the generation of interrupt requests (change the IR bit in the interrupt
control register). Table 12.9 lists the Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O
with Chip Select Interrupt, and I2C bus Interface Interrupt and Figure 12.19 shows a Block Diagram of Timer RC
Interrupt.
Table 12.9
Registers Associated with Timer RC Interrupt, Clock Synchronous Serial I/O with
Chip Select Interrupt, and I2C bus Interface Interrupt
Status Register of
Enable Register of
Interrupt Control
Interrupt Request Source Interrupt Request Source
Register
Timer RC
TRCSR
TRCIER
TRCIC
Clock synchronous serial SSSR
SSER
SSUIC
I/O with chip select
ICSR
ICIER
IICIC
I2C bus interface
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
Figure 12.19
Block Diagram of Timer RC Interrupt
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 124 of 441
Timer RC
interrupt request
(IR bit in TRCIC register)
R8C/28 Group, R8C/29 Group
12. Interrupts
As with other maskable interrupts, the timer RC interrupt, clock synchronous serial I/O with chip select interrupt,
and I2C bus interface interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL.
However, since each interrupt source is generated by a combination of multiple interrupt request sources, the
following differences from other maskable interrupts apply:
• When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set
to 0 even if 0 is written to the IR bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
set to 1, the IR bit remains 1.
• When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
Refer to chapters of the individual peripheral functions (14.3 Timer RC, 16.2 Clock Synchronous Serial I/O with
Chip Select (SSU) and 16.3 I2C bus Interface) for the status register and enable register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 125 of 441
R8C/28 Group, R8C/29 Group
12.6
12. Interrupts
Notes on Interrupts
12.6.1
Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
12.6.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
12.6.3
External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V), Table
20.52 (VCC = 5V), Table 20.58 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3) Input.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 126 of 441
R8C/28 Group, R8C/29 Group
12.6.4
12. Interrupts
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 12.20 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts (2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute
two or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 12.20
Example of Procedure for Changing Interrupt Sources
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 127 of 441
R8C/28 Group, R8C/29 Group
12.6.5
12. Interrupts
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1:
Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
POPC
FLG
; Enable interrupts
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 128 of 441
R8C/28 Group, R8C/29 Group
13. Watchdog Timer
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Count Source Protection Mode.
Refer to 5.7 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows Registers OFS and WDC. Figure 13.3
shows Registers WDTR, WDTS, and CSPR.
Table 13.1
Count Source Protection Mode
Count Source Protection
Mode Disabled
CPU clock
Item
Count source
Count Source Protection
Mode Enabled
Low-speed on-chip oscillator
clock
Count operation
Count start condition
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition
Stop mode, wait mode
None
Reset condition of watchdog
• Reset
timer
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time of underflow Watchdog timer interrupt or
Watchdog timer reset
watchdog timer reset
Prescaler
1/16
WDC7 = 0
CSPRO = 0
1/128
CPU clock
PM12 = 0
Watchdog timer
interrupt request
Watchdog timer
WDC7 = 1
fOCO-S
CSPRO = 1
Write to WDTR register
Set to
7FFFh(1)
PM12 = 1
Watchdog
timer reset
Internal
reset signal
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Figure 13.1
Block Diagram of Watchdog Timer
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 129 of 441
R8C/28 Group, R8C/29 Group
13. Watchdog Timer
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
LVD1ON
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2, 4)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
Voltage detection 1
circuit start bit(5, 6)
0 : Voltage monitor 1 reset enabled after hardw are
reset
1 : Voltage monitor 1 reset disabled after hardw are
reset
RW
Count source protect
CSPROINI mode after reset select
bit
RW
RW
RW
RW
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
4. For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are
reset).
5. The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the
LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).
6. For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are
reset).
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
000Fh
WDC
Bit Symbol
Bit Name
—
High-order bits of w atchdog timer
(b4-b0)
—
(b5)
Reserved bit
Set to 0. When read, the content is undefined.
—
(b6)
Reserved bit
Set to 0.
Prescaler select bit
0 : Divide-by-16
1 : Divide-by-128
WDC7
Figure 13.2
Registers OFS and WDC
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
After Reset
00X11111b
Function
Page 130 of 441
RW
RO
RW
RW
RW
R8C/28 Group, R8C/29 Group
13. Watchdog Timer
Watchdog Timer Reset Register
b7
b0
Symbol
WDTR
Address
000Dh
After Reset
Undefined
Function
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)
RW
WO
NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000Eh
After Reset
Undefined
Function
The w atchdog timer starts counting after a w rite instruction to this register.
RW
WO
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Symbol
Address
001Ch
CSPR
Bit Symbol
Bit Name
Reserved Bits
—
(b6-b0)
CSPRO
After Reset(1)
00h
Function
Set to 0.
Count Source Protection Mode 0 : Count source protection mode disabled
Select Bit(2)
1 : Count source protection mode enabled
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. Write 0 before w riting 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
Figure 13.3
Registers WDTR, WDTS, and CSPR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 131 of 441
RW
RW
RW
R8C/28 Group, R8C/29 Group
13.1
13. Watchdog Timer
Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Specifications of Watchdog Timer (with Count Source Protection Mode Disabled).
Table 13.2
Specifications of Watchdog Timer (with Count Source Protection Mode Disabled)
Item
Specification
Count source
Count operation
Period
CPU clock
Decrement
Count start condition
The WDTON bit(2) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
The watchdog timer and prescaler start counting automatically after a
reset
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (Refer to 5.7 Watchdog Timer Reset)
Division ratio of prescaler (n) × count value of watchdog timer (32768)(1)
CPU clock
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divides by 16, the period is approximately 32.8 ms
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 132 of 441
R8C/28 Group, R8C/29 Group
13.2
13. Watchdog Timer
Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Specifications of Watchdog Timer (with Count Source Protection Mode Enabled).
Table 13.3
Specifications of Watchdog Timer (with Count Source Protection Mode Enabled)
Item
Specification
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed on-chip
oscillator clock frequency is 125 kHz
Count source
Count operation
Period
Count start condition
Reset condition of watchdog
timer
Count stop condition
Operation at time of underflow
Registers, bits
The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after reset)
The watchdog timer and prescaler start counting automatically after a
reset
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
None (The count does not stop in wait mode after the count starts. The
MCU does not enter stop mode.)
Watchdog timer reset (Refer to 5.7 Watchdog Timer Reset)
• When setting the CSPPRO bit in the CSPR register to 1 (count source
protection mode is enabled)(2), the following are set automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 133 of 441
R8C/28 Group, R8C/29 Group
14. Timers
14. Timers
The microcomputer contains two 8-bit timers with 8-bit prescaler, a 16-bit timer, and a timer with a 4-bit counter, and
an 8-bit counter. The two 8-bit timers with the 8-bit prescaler contain Timer RA and Timer RB. These timers contain a
reload register to memorize the default value of the counter. The 16-bit timer is Timer RC which contains the input
capture and output compare. The 4 and 8-bit counters are Timer RE which contains the output compare. All these
timers operate independently.
Table 14.1 lists Functional Comparison of Timers.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 134 of 441
R8C/28 Group, R8C/29 Group
Table 14.1
14. Timers
Functional Comparison of Timers
Item
Configuration
Count
Count source(1)
Timer RA
8-bit timer with 8bit prescaler (with
reload register)
Decrement
• f1
• f2
• f8
• fOCO
• fC32
Timer RB
8-bit timer with 8bit prescaler (with
reload register)
Decrement
• f1
• f2
• f8
• Timer RA
underflow
Function Timer Mode
provided
provided
provided
provided
Pulse Output Mode
Event Counter
Mode
Pulse Width
Measurement Mode
Pulse Period
Measurement Mode
Programmable
Waveform
Generation Mode
Programmable
One-Shot
generation Mode
Programmable Wait
One-Shot
Generation Mode
Input Capture Mode
Output Compare
Mode
PWM Mode
PWM2 Mode
Real-Time Clock
Mode
Input Pin
Output Pin
Related Interrupt
Timer Stop
not provided
not provided
Timer RC
16-bit free-run timer (with
input capture and output
compare)
Increment
• f1
• f2
• f4
• f8
• f32
• fOCO40M
• TRCCLK
provided
(input capture function,
output compare function)
not provided
not provided
not provided
not provided
provided
not provided
not provided
not provided
provided
not provided
not provided
not provided
not provided
provided
not provided
not provided
not provided
provided
not provided
not provided
not provided
provided
not provided
not provided
not provided
not provided
not provided
not provided
provided
provided
not provided
provided
not provided
not provided
not provided
not provided
not provided
not provided
provided
provided
not provided
not provided
not provided
provided(2)
TRAIO
INT0
INT0, TRCCLK, TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
TRAO
TRBO
TRCIOA, TRCIOB,
TRAIO
TRCIOC, TRCIOD
Timer RA interrupt Timer RB interrupt Compare Match / Input
INT1 interrupt
INT0 interrupt
Capture A to D interrupt
Overflow interrupt
INT0 interrupt
provided
provided
provided
NOTES:
1. For J, K version, fC4 and fC32 cannot be selected.
2. For N, D version only.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 135 of 441
Timer RE
4-bit counter
8-bit counter
Increment
• f4
• f8
• f32
• fC4
not provided
−
−
Timer RE
interrupt
provided
R8C/28 Group, R8C/29 Group
14.1
14. Timers
Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6
the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with timer
RA.
Timer RA has the following five operating modes:
• Timer mode:
The timer counts the internal count source.
• Pulse output mode:
The timer counts the internal count source and outputs pulses which
invert the polarity by underflow of the timer.
• Event counter mode:
The timer counts external pulses.
• Pulse width measurement mode:
The timer measures the pulse width of an external pulse.
• Pulse period measurement mode:
The timer measures the pulse period of an external pulse.
Data bus
TCK2 to TCK0 bit
f1
f8
fOCO
f2
fC32(1)
= 000b
= 001b
= 010b
= 011b
= 100b
TMOD2 to TMOD0
= other than 010b
TIPF1 to TIPF0 bits
TMOD2 to TMOD0
= 010b
= 01b
f1
= 10b
f8
= 11b
f32
TIPF1 to TIPF0 bits
TIOSEL = 0 = other than
Digital
000b
INT1/TRAIO (P1_7) pin
filter
INT1/TRAIO (P1_5) pin
TIOSEL = 1
Reload
register
TCKCUT TCSTF
bit
bit
Reload
register
Counter
TRAPRE register
(prescaler)
Counter
TRA register
(timer)
Underflow signal
Timer RA interrupt
TMOD2 to TMOD0
= 011b or 100b
Polarity
switching
Count control
circle
= 00b
TMOD2 to TMOD0 = 001b
TEDGSEL = 1
TOPCR bit
Q
TOENA bit
Q
TEDGSEL = 0
Measurement completion
signal
Toggle
flip-flop
CK
CLR
Write to TRAMR register
Write 1 to TSTOP bit
TRAO pin
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
NOTE:
1. For J, K version, fC32 cannot be selected.
Figure 14.1
Block Diagram of Timer RA
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 136 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA Control Register(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRACR
Bit Symbol
Address
0100h
Bit Name
Timer RA count start bit(1)
After Reset
00h
Function
RW
0 : Count stops
1 : Count starts
RW
TCSTF
Timer RA count status flag(1) 0 : Count stops
1 : During count
RO
TSTOP
Timer RA count forcible stop When this bit is set to 1, the count is forcibly
bit(2)
stopped. When read, its content is 0.
RW
TSTART
—
(b3)
TEDGF
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Active edge judgment
flag(3, 5)
0 : Active edge not received
1 : Active edge received
(end of measurement period)
—
RW
TUNDF
Timer RA underflow flag(3, 5) 0 : No underflow
1 : Underflow
RW
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Refer to 14.1.6 Notes on Tim er RA for precautions regarding bits TSTART and TCSTF.
2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TRAPRE and TRA are set to the values after a
reset.
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
Function varies depending on operating mode.
TRAIO output control bit
TRAO output enable bit
RW
RW
RW
RW
_____
TIOSEL
TIPF0
TIPF1
—
(b7-b6)
Figure 14.2
INT1/TRAIO select bit
TRAIO input filter select bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Registers TRACR and TRAIOC
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 137 of 441
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAMR
Bit Symbol
TMOD0
Address
0102h
Bit Name
Timer RA operating mode
select bits (1)
TMOD1
TMOD2
After Reset
00h
Function
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse w idth measurement mode
1 0 0 : Pulse period measurement mode
101:
1 1 0 : Do not set.
111:
—
(b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TCK0
Timer RA count source
select bits
TCK1
TCK2
TCKCUT
Timer RA count source
cutoff bit(2)
RW
b2 b1 b0
RW
RW
RW
—
b6 b5 b4
0 0 0 : f1
0 0 1 : f8
0 1 0 : fOCO
0 1 1 : f2
1 0 0 : fC32(2)
101:
1 1 0 : Do not set.
111:
RW
RW
RW
0 : Provides count source
1 : Cuts off count source
RW
NOTES:
1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
2. For J, K version, fC32 cannot be selected.
Timer RA Prescaler Register
b7
b0
Symbol
TRAPRE
Mode
Timer mode
Pulse output mode
Event counter mode
Pulse w idth
measurement mode
Address
0103h
Function
Counts an internal count source
Counts an external count source
Measure pulse w idth of input pulses from
external (counts internal count source)
Pulse period
measurement mode
Measure pulse period of input pulses from
external (counts internal count source)
After Reset
FFh(1)
Setting Range
00h to FFh
00h to FFh
00h to FFh
RW
RW
RW
RW
00h to FFh
RW
00h to FFh
RW
After Reset
FFh(1)
Setting Range
RW
00h to FFh
RW
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Timer RA Register
b7
b0
Symbol
TRA
Mode
All modes
Address
0104h
Function
Counts on underflow of timer RA prescaler
register
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
Figure 14.3
Registers TRAMR, TRAPRE, and TRA
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 138 of 441
R8C/28 Group, R8C/29 Group
14.1.1
14. Timers
Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 14.2 Specifications of
Timer Mode).
Figure 14.4 shows the TRAIOC Register in Timer Mode.
Table 14.2
Specifications of Timer Mode
Item
Count sources
Specification
fC32(1)
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
f1, f2, f8, fOCO,
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin function Programmable I/O port, or INT1 interrupt input
Programmable I/O port
TRAO pin function
Read from timer
Write to timer
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
NOTE:
1. For J, K version, fC32 cannot be selected.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TRAIO output control bit
TIPF0
TIPF1
—
(b7-b6)
Figure 14.4
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select bits Set to 0 in timer mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Page 139 of 441
RW
_____
INT1/TRAIO select bit
TRAIOC Register in Timer Mode
RW
RW
TRAO output enable bit
_____
TIOSEL
After Reset
00h
Function
Set to 0 in timer mode.
RW
RW
—
R8C/28 Group, R8C/29 Group
14.1.1.1
14. Timers
Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
Count source
After writing, the reload register is
written to at the first count source.
Reloads register of
timer RA prescaler
Previous value
New value (01h)
Reload at
second count
source
Counter of
timer RA prescaler
06h
05h
04h
01h
00h
Reload at
underflow
01h
00h
01h
00h
01h
00h
After writing, the reload register is
written to at the first underflow.
Reloads register of
timer RA
Previous value
New value (25h)
Reload at the second underflow
Counter of timer RA
IR bit in TRAIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow is
generated by a new value.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
Figure 14.5
Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 140 of 441
R8C/28 Group, R8C/29 Group
14.1.2
14. Timers
Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Specifications of Pulse
Output Mode).
Figure 14.6 shows the TRAIOC Register in Pulse Output Mode.
Table 14.3
Specifications of Pulse Output Mode
Item
Count sources
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
fC32(2)
f1, f2, f8, fOCO,
• Decrement
• When the timer underflows, the contents in the reload register is reloaded
and the count is continued.
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin function Pulse output, programmable output port, or INT1 interrupt(1)
TRAO pin function
Read from timer
Write to timer
Select functions
Programmable I/O port or inverted output of TRAIO(1)
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
• TRAIO signal polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of
pulse output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO
pin (selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC
register.
• INT1/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
NOTES:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
2. For J, K version, fC32 cannot be selected.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 141 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
RW
TRAIO output control bit
0 : TRAIO output
1 : Port P1_7 or P1_5
RW
TRAO output enable bit
0 : Port P3_7
1 : TRAO output (inverted TRAIO output from P3_7)
RW
_____
TIOSEL
TIPF0
TIPF1
—
(b7-b6)
Figure 14.6
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
_____
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select bits Set to 0 in pulse output mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Output Mode
Page 142 of 441
RW
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14.1.3
14. Timers
Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4
Specifications of Event Counter Mode).
Figure 14.7 shows the TRAIOC Register in Event Counter Mode.
Table 14.4
Specifications of Event Counter Mode
Item
Count source
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
External signal which is input to TRAIO pin (active edge selectable by a
program)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin function Count source input (INT1 interrupt input)
TRAO pin function
Read from timer
Write to timer
Programmable I/O port or pulse output(1)
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions
• INT1 input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the
count source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the
timer underflows (selectable by the TOENA bit in the TRAIOC register).(1)
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 143 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TEDGSEL
TOPCR
TOENA
After Reset
00h
Function
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”.
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”.
TRAIO output control bit
Set to 0 in event counter mode.
TRAO output enable bit
0 : Port P3_7
1 : TRAO output
_____
TIOSEL
TIPF0
—
(b7-b6)
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.7
TRAIOC Register in Event Counter Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 144 of 441
RW
RW
RW
_____
INT1/TRAIO select bit
TIPF1
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14.1.4
14. Timers
Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.5 Specifications of Pulse Width Measurement Mode).
Figure 14.8 shows the TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an
Operating Example of Pulse Width Measurement Mode.
Table 14.5
Specifications of Pulse Width Measurement Mode
Item
Count sources
Count operations
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
fC32(1)
f1, f2, f8, fOCO,
• Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
Write to timer
Select functions
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
• Measurement level select
The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTE:
1. For J, K version, fC32 cannot be selected.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 145 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
TRAIO output control bit
Set to 0 in pulse w idth measurement mode.
TRAO output enable bit
_____
TIOSEL
TIPF0
—
(b7-b6)
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Width Measurement Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 146 of 441
RW
RW
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.8
RW
_____
INT1/TRAIO select bit
TIPF1
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
FFFFh
Count start
Underflow
Content of counter (hex)
n
Count stop
Count stop
Count start
0000h
Count start
Period
Set to 1 by program
TSTART bit in
TRACR register
1
Measured pulse
(TRAIO pin input)
1
0
0
Set to 0 when interrupt request is acknowledged, or set by program
IR bit in TRAIC
register
1
0
Set to 0 by program
TEDGF bit in
TRACR register
1
0
Set to 0 by program
TUNDF bit in
TRACR register
1
0
The above applies under the following conditions.
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Figure 14.9
Operating Example of Pulse Width Measurement Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 147 of 441
R8C/28 Group, R8C/29 Group
14.1.5
14. Timers
Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.6 Specifications of Pulse Period Measurement Mode).
Figure 14.10 shows the TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an
Operating Example of Pulse Period Measurement Mode.
Table 14.6
Specifications of Pulse Period Measurement Mode
Item
Count sources
Count operations
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
fC32(2)
f1, f2, f8, fOCO,
• Decrement
• After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
1 (count start) is written to the TSTART bit in the TRACR register.
• 0 (count stop) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
Write to timer
Select functions
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
• Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTES:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
2. For J, K version, fC32 cannot be selected.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 148 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TEDGSEL
TOPCR
TOENA
TRAIO output control bit
TIPF0
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Period Measurement Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 149 of 441
RW
RW
RW
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.10
RW
_____
INT1/TRAIO select bit
TIPF1
—
(b7-b6)
Set to 0 in pulse period measurement mode.
TRAO output enable bit
_____
TIOSEL
After Reset
00h
Function
0 : Measures measurement pulse from one
rising edge to next rising edge
1 : Measures measurement pulse from one
falling edge to next falling edge
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Underflow signal of
timer RA prescaler
Set to 1 by program
TSTART bit in
TRACR register
1
0
Starts counting
Measurement pulse
(TRAIO pin input)
1
0
TRA reloads
TRA reloads
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
Contents of TRA
01h 00h 0Fh 0Eh
Underflow
Retained
Contents of read-out
buffer(1)
0Fh
Retained
0Dh
0Eh
0Bh 0Ah
09h
0Dh
01h 00h 0Fh 0Eh
TRA read(3)
(Note 2)
TEDGF bit in
TRACR register
(Note 2)
1
0
Set to 0 by program
(Note 4)
(Note 6)
TUNDF bit in
TRACR register
1
0
Set to 0 by program
IR bit in TRAIC
register
(Note 5)
1
0
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 14.11
Operating Example of Pulse Period Measurement Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 150 of 441
R8C/28 Group, R8C/29 Group
14.1.6
14. Timers
Notes on TImer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 151 of 441
R8C/28 Group, R8C/29 Group
14.2
14. Timers
Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 to 14.15 show the registers associated with timer
RB.
Timer RB has four operation modes listed as follows:
• Timer mode:
• Programmable waveform generation mode:
• Programmable one-shot generation mode:
• Programmable wait one-shot generation mode:
Reload
register
TCK1 to TCK0 bits
f1
f8
Timer RA underflow
f2
= 00b
The timer counts an internal count source (peripheral
function clock or timer RA underflows).
The timer outputs pulses of a given width successively.
The timer outputs a one-shot pulse.
The timer outputs a delayed one-shot pulse.
Data bus
TRBSC
register
Reload
register
TRBPR
register
Reload
register
TCKCUT bit
= 01b
= 10b
= 11b
Counter
TRBPRE register
(prescaler)
Timer RB interrupt
Counter (timer RB)
(Timer)
TMOD1 to TMOD0 bits
= 10b or 11b
TSTART bit
TOSSTF bit
INT0 interrupt
Input polarity
selected to be one
edge or both edges
Digital filter
INT0 pin
INT0PL bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
TRBOSEL=0
INT0EN bit
P1_3 bit in P1 register
TOCNT = 1
TSTART, TCSTF: Bits in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
TRBOSEL: Bit in PINSR2 register
Figure 14.12
Block Diagram of Timer RB
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
INOSEG bit
Page 152 of 441
INOSTG bit
TOPL = 1
TOCNT = 0
TRBO pin
TRBOSEL=1
Polarity
select
TOPL = 0
Q
Toggle
flip-flop
Q
CLR
CK
TCSTF bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBCR
Bit Symbol
TSTART
Address
0108h
Bit Name
Timer RB count start bit(1)
After Reset
00h
Function
0 : Count stops
1 : Count starts
RW
RW
TCSTF
Timer RB count status flag(1) 0 : Count stops
1 : During count(3)
RO
TSTOP
Timer RB count forcible stop When this bit is set to 1, the count is forcibly
bit(1, 2)
stopped. When read, its content is 0.
RW
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Refer to 14.2.5 Notes on Tim er RB for precautions regarding bits TSTART, TCSTF and TSTOP.
2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable oneshot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB One-Shot Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBOCR
Bit Symbol
TOSST
Address
0109h
Bit Name
Timer RB one-shot start bit
After Reset
00h
Function
When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
Timer RB one-shot stop bit
When this bit is set to 1, counting of one-shot
pulses (including programmable w ait one-shot
pulses) stops. When read, its content is 0.
RW
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
RO
TOSSP
TOSSTF
Timer RB one-shot status
flag(1)
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
NOTES:
1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
Figure 14.13
Registers TRBCR and TRBOCR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 153 of 441
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Address
After Reset
010Ah
00h
Bit Name
Function
Timer RB output level select Function varies depending on operating mode.
bit
Timer RB output sw itch bit
RW
RW
RW
One-shot trigger control bit
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Timer RB Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBMR
Bit Symbol
TMOD0
Address
010Bh
Bit Name
Timer RB operating mode
select bits (1)
TMOD1
—
(b2)
TWRC
TCK0
TCKCUT
0 0 : Timer mode
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable w ait one-shot generation mode
Timer RB w rite control bit(2)
0 : Write to reload register and counter
1 : Write to reload register only
Timer RB count source
select bits (1)
b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer RA underflow
1 1 : f2
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB count source
cutoff bit(1)
RW
b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TCK1
—
(b6)
After Reset
00h
Function
0 : Provides count source
1 : Cuts off count source
RW
RW
—
RW
RW
RW
—
RW
NOTES:
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
Figure 14.14
Registers TRBIOC and TRBMR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 154 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB Prescaler Register(1)
b7
b0
Symbol
TRBPRE
Mode
Timer mode
Address
010Ch
Function
Counts an internal count source or timer RA
underflow s
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
00h to FFh
Programmable one-shot
generation mode
00h to FFh
Programmable w ait one-shot
generation mode
00h to FFh
RW
RW
RW
RW
RW
NOTE:
1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Timer RB Secondary Register(3, 4)
b7
b0
Symbol
TRBSC
Mode
Timer mode
Address
010Dh
Function
Disabled
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
Counts timer RB prescaler underflow s (1)
00h to FFh
Programmable one-shot
generation mode
Disabled
00h to FFh
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode
(one-shot w idth is counted)
00h to FFh
RW
—
WO(2)
—
WO(2)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
4. To w rite to the TRBSC register, perform the follow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
Timer RB Primary Register(2)
b7
b0
Symbol
TRBPR
Mode
Timer mode
Address
010Eh
Function
Counts timer RB prescaler underflow s
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
Counts timer RB prescaler underflow s (1)
00h to FFh
Programmable one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode
(w ait period w idth is counted)
00h to FFh
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Figure 14.15
Registers TRBPRE, TRBSC, and TRBPR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 155 of 441
RW
RW
RW
RW
RW
R8C/28 Group, R8C/29 Group
14.2.1
14. Timers
Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
14.7 Specifications of Timer Mode). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 14.16 shows the TRBIOC Register in Timer Mode.
Table 14.7
Specifications of Timer Mode
Item
Count sources
Count operations
Specification
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
TRBO pin function
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
1 (count starts) is written to the TSTART bit in the TRBCR register.
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
When timer RB underflows [timer RB interrupt]
Programmable I/O port
INT0 pin function
Read from timer
Write to timer
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is
in progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 14.2.1.1 Timer Write Control during Count Operation.)
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Figure 14.16
Address
After Reset
010Ah
00h
Bit Name
Function
Timer RB output level select Set to 0 in timer mode.
bit
Timer RB output sw itch bit
One-shot trigger control bit
RW
RW
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
TRBIOC Register in Timer Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Page 156 of 441
R8C/28 Group, R8C/29 Group
14.2.1.1
14. Timers
Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload register.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten during Count Operation.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 157 of 441
R8C/28 Group, R8C/29 Group
14. Timers
When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
Counter of
timer RB prescaler
06h
05h
New value (01h)
04h
Reload with
the second
count source
Reload on
underflow
01h
01h
00h
00h
01h
00h
01h
00h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on the second
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
New value (01h)
Reload on
underflow
Counter of
timer RB prescaler
06h
05h
04h
03h
02h
01h
00h
01h
00h
01h
00h
01h
00h
01h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
01h
00h
25h
0
Only the prescaler values are updated,
extending the duration until timer RB underflow.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 14.17
Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 158 of 441
R8C/28 Group, R8C/29 Group
14.2.2
14. Timers
Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table
14.8 Specifications of Programmable Waveform Generation Mode). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 14.18 shows the TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows
an Operating Example of Timer RB in Programmable Waveform Generation Mode.
Table 14.8
Specifications of Programmable Waveform Generation Mode
Item
Count sources
Count operations
Width and period of
output waveform
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the contents of the primary reload and
secondary reload registers alternately before the count continues.
Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register, m: Value set in TRBPR register
p: Value set in TRBSC register
1 (count start) is written to the TSTART bit in the TRBCR register.
• 0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
In half a cycle of the count source, after timer RB underflows during the
secondary period (at the same time as the TRBO output change) [timer RB
interrupt]
TRBO pin function
Programmable output port or pulse output(4)
INT0 pin function
Read from timer
Programmable I/O port or INT0 interrupt input
Write to timer
Select functions
The count value can be read out by reading registers TRBPR and TRBPRE.(1)
• When registers TRBPRE, TRBSC, and TRBPR are written while the count is
stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(2)
• Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary
and secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P1_3 latch output is selected by the TOCNT bit in
the TRBIOC register.(3)
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after
writing to the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
• When counting starts.
• When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following
primary period.
4. Set the TRBOSEL bit in the PINSR2 register to 1 (enabled) before using timer RB.
Refer to 7. Programmable I/O Ports for details.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 159 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Figure 14.18
Address
010Ah
Bit Name
Timer RB output level select 0 : Outputs
bit
Outputs
Outputs
1 : Outputs
Outputs
Outputs
After Reset
00h
Function
“H” for primary period
“L” for secondary period
“L” w hen the timer is stopped
“L” for primary period
“H” for secondary period
“H” w hen the timer is stopped
RW
Timer RB output sw itch bit
0 : Outputs timer RB w aveform
1 : Outputs value in P1_3 port register
RW
One-shot trigger control bit
Set to 0 in programmable w aveform generation
mode.
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
TRBIOC Register in Programmable Waveform Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Page 160 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads
01h
Counter of timer RB
00h
02h
01h
Timer RB primary reloads
00h
01h
00h
02h
Set to 0 when interrupt
request is acknowledged,
or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in TRBIO
register
1
0
Waveform
output starts
Waveform output inverted
Waveform output starts
1
TRBO pin output
0
Initial output is the same level
as during secondary period.
Primary period
Secondary period
Primary period
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 14.19
Operating Example of Timer RB in Programmable Waveform Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 161 of 441
R8C/28 Group, R8C/29 Group
14.2.3
14. Timers
Programmable One-shot Generation Mode
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 14.9 Specifications of Programmable One-Shot
Generation Mode). When a trigger is generated, the timer starts operating from the point only once for a given
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 14.20 shows the TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows
an Operating Example of Programmable One-Shot Generation Mode.
Table 14.9
Specifications of Programmable One-Shot Generation Mode
Item
Count sources
Count operations
One-shot pulse output
time
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRBO pin function
INT0 pin functions
Read from timer
Write to timer
Select functions
Specification
f1, f2, f8, timer RA underflow
• Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register
before the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
(n+1)(m+1)/fi
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
• When reloading completes after timer RB underflows during primary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (stops counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops
counting).
In half a cycle of the count source, after the timer underflows (at the same time
as the TRBO output ends) [timer RB interrupt]
Pulse output(3)
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot
trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot
trigger enabled): external trigger (INT0 interrupt input)
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload).(1)
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
3. Set the TRBOSEL bit in the PINSR2 register to 1 (enabled) before using timer RB.
Refer to 7. Programmable I/O Ports for details.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 162 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
Address
010Ah
Bit Name
Timer RB Output Level
Select Bit
Timer RB Output Sw itch Bit
0 : Outputs
Outputs
1 : Outputs
Outputs
After Reset
00h
Function
one-shot pulse “H”
“L” w hen the timer is stopped
one-shot pulse “L”
“H” w hen the timer is stopped
Set to 0 in programmable one-shot generation
mode.
INOSTG
One-Shot Trigger Control
Bit(1)
INOSEG
One-Shot Trigger Polarity
Select Bit(1)
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, its content is 0.
0 : INT0 pin one-shot trigger disabled
_____
1 : INT0 pin one-shot trigger enabled
0 : Falling edge trigger
1 : Rising edge trigger
TRBIOC Register in Programmable One-Shot Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 163 of 441
RW
RW
_____
NOTE:
1. Refer to 14.2.3.1 One-Shot Trigger Selection.
Figure 14.20
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Set to 0 when
counting ends
Set to 1 by program
TOSSTF bit in TRBOCR
register
Set to 1 by INT0 pin
input trigger
1
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
01h
Counter of timer RB
Timer RB primary reloads
00h
Count starts
01h
Timer RB primary reloads
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Waveform output starts
Waveform output ends
Waveform output starts
1
TRBIO pin output
0
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.21
Operating Example of Programmable One-Shot Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 164 of 441
Waveform output ends
R8C/28 Group, R8C/29 Group
14.2.3.1
14. Timers
One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 165 of 441
R8C/28 Group, R8C/29 Group
14.2.4
14. Timers
Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Specifications of Programmable Wait
One-Shot Generation Mode). When a trigger is generated from that point, the timer outputs a pulse only once
for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of
time equal to the setting value in the TRBPR register.
Figure 14.22 shows the TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23
shows an Operating Example of Programmable Wait One-Shot Generation Mode.
Table 14.10
Specifications of Programmable Wait One-Shot Generation Mode
Item
Count sources
Count operations
Wait time
One-shot pulse
output time
Count start
conditions
Count stop
conditions
Interrupt request
generation timing
TRBO pin function
INT0 pin functions
Read from timer
Write to timer
Select functions
Specification
f1, f2, f8, timer RA underflow
• Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the contents of
timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents of
timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot
stops).
• When the count stops, the timer reloads the contents of the reload register before it
stops.
(n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register(2)
(n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is
generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (starts counting).
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).
In half a cycle of the count source after timer RB underflows during secondary period
(complete at the same time as waveform output from the TRBO pin) [timer RB interrupt]
Pulse output(3)
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE, TRBSC, and TRBPR are written while the count stops,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count operation,
values are written to the reload registers only.(1)
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse
waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
3. Set the TRBOSEL bit in the PINSR2 register to 1 (enabled) before using timer RB.
Refer to 7. Programmable I/O Ports for details.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 166 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
Address
010Ah
Bit Name
Timer RB output level select 0 : Outputs
bit
Outputs
w ait.
1 : Outputs
Outputs
w ait.
Timer RB output sw itch bit
After Reset
00h
Function
one-shot pulse “H”.
“L” w hen the timer stops or during
one-shot pulse “L”.
“H” w hen the timer stops or during
Set to 0 in programmable w ait one-shot generation
mode.
RW
RW
RW
_____
INOSTG
INOSEG
—
(b7-b4)
One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled
_____
1 : INT0 pin one-shot trigger enabled
0 : Falling edge trigger
One-shot trigger polarity
1 : Rising edge trigger
select bit(1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Refer to 14.2.3.1 One-Shot Trigger Selection.
Figure 14.22
TRBIOC Register in Programmable Wait One-Shot Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 167 of 441
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
TOSSTF bit in TRBOCR
register
Set to 0 when
counting ends
1
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
Counter of timer RB
01h
Timer RB secondary reloads
00h
04h
Timer RB primary reloads
03h
02h
01h
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Wait starts
Waveform output starts
Waveform output ends
1
TRBIO pin output
0
Wait
(primary period)
One-shot pulse
(secondary period)
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.23
Operating Example of Programmable Wait One-Shot Generation Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 168 of 441
R8C/28 Group, R8C/29 Group
14.2.5
14. Timers
Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
14.2.5.1
Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 169 of 441
R8C/28 Group, R8C/29 Group
14.2.5.2
14. Timers
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.24 and 14.25.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
IR bit in
TRBIC register
Primary period
(a)
Interrupt request is
acknowledged
Secondary period
Ensure sufficient time
(b)
Interrupt request
is generated
Instruction in
Interrupt
sequence interrupt routine
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 14.24
Workaround Example (a) When Timer RB interrupt is Used
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 170 of 441
R8C/28 Group, R8C/29 Group
14. Timers
• Workaround example (b):
As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
Primary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
is detected at the end of the
secondary period.
Figure 14.25
Upon detecting (i), set the secondary and
then the primary register immediately.
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 171 of 441
R8C/28 Group, R8C/29 Group
14.2.5.4
14. Timers
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 172 of 441
R8C/28 Group, R8C/29 Group
14.3
14. Timers
Timer RC
14.3.1
Overview
Timer RC is a 16-bit timer with four I/O pins.
Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.11 lists the Timer RC Operation Clock.
Table 14.11
Timer RC Operation Clock
Condition
Timer RC Operation Clock
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in f1
TRCCR1 register are set to a value from 000b to 101b)
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set fOCO40M
to 110b)
Table 14.12 lists the Timer RC I/O Pins, and Figure 14.26 shows a Timer RC Block Diagram.
Timer RC has three modes.
• Timer mode
- Input capture function
The counter value is captured to a register, using an external signal as the trigger.
- Output compare function Matches between the counter and register values are detected. (Pin output state
changes when a match is detected.)
The following two modes use the output compare function.
• PWM mode
Pulses of a given width are output continuously.
• PWM2 mode
A one-shot waveform or PWM waveform is output following the trigger after
the wait time has elapsed.
Input capture function, output compare function, and PWM mode settings may be specified independently for
each pin.
In PWM2 mode waveforms are output based on a combination of the counter or the register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 173 of 441
R8C/28 Group, R8C/29 Group
14. Timers
f1, f2, f4, f8, f32,
fOCO40M
TRCMR register
TRCCR1 register
TRCIER register
INT0
Count source
select circuit
TRCSR register
TRCIOR0 register
TRCIOA/TRCTRG
TRCIOR1 register
Data bus
TRCCLK
TRCIOB
Timer RC control circuit
TRC register
TRCGRA register
TRCIOC
TRCIOD
TRCGRB register
TRCGRC register
TRCGRD register
TRCCR2 register
TRCDF register
Timer RC interrupt
request
TRCOER register
Figure 14.26
Table 14.12
Timer RC Block Diagram
Timer RC I/O Pins
Pin Name
TRCIOA(P1_1)
TRCIOB(P1_2)
TRCIOC(P3_4)(1)
TRCIOD(P3_5)(1)
TRCCLK(P3_3)
TRCTRG(P1_1)
I/O
I/O
Function
Function differs according to the mode. Refer to descriptions of
individual modes for details
Input
Input
External clock input
PWM2 mode external trigger input
NOTE:
1. Set bits TRCIOCSEL and TRCIODSEL in the PINSR3 register to 1 (enabled) before using timer RC.
Refer to 7. Programmable I/O Ports for details.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 174 of 441
R8C/28 Group, R8C/29 Group
14.3.2
14. Timers
Registers Associated with Timer RC
Table 14.13 lists the Registers Associated with Timer RC. Figures 14.27 to 14.36 show details of the registers
associated with timer RC.
Table 14.13
Registers Associated with Timer RC
0120h
TRCMR
Mode
Timer
Input
Output
PWM
Capture Compare
Function Function
Valid
Valid
Valid
0121h
TRCCR1
Valid
Valid
Valid
Valid
0122h
TRCIER
Valid
Valid
Valid
Valid
0123h
TRCSR
Valid
Valid
Valid
Valid
0124h
TRCIOR0 Valid
Valid
−
−
0125h
TRCIOR1
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
TRC
Valid
Valid
Valid
Valid
TRCGRA
Valid
Valid
Valid
Valid
TRCCR2
−
−
−
Valid
0131h
TRCDF
Valid
−
−
Valid
0132h
TRCOER
−
Valid
Valid
Valid
Address
Symbol
PWM2
Valid
TRCGRB
Related Information
Timer RC mode register
Figure 14.27 TRCMR Register
Timer RC control register 1
Figure 14.28 TRCCR1 Register
Figure 14.49 TRCCR1 Register for Output
Compare Function
Figure 14.52 TRCCR1 Register in PWM Mode
Figure 14.56 TRCCR1 Register in PWM2 Mode
Timer RC interrupt enable register
Figure 14.29 TRCIER Register
Timer RC status register
Figure 14.30 TRCSR Register
Timer RC I/O control register 0, timer RC I/O
control register 1
Figure 14.36 Registers TRCIOR0 and TRCIOR1
Figure 14.43 TRCIOR0 Register for Input
Capture Function
Figure 14.44 TRCIOR1 Register for Input
Capture Function
Figure 14.47 TRCIOR0 Register for Output
Compare Function
Figure 14.48 TRCIOR1 Register for Output
Compare Function
Timer RC counter
Figure 14.31 TRC Register
Timer RC general registers A, B, C, and D
Figure 14.32 Registers TRCGRA, TRCGRB,
TRCGRC, and TRCGRD
TRCGRC
TRCGRD
− : Invalid
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 175 of 441
Timer RC control register 2
Figure 14.33 TRCCR2 Register
Timer RC digital filter function select register
Figure 14.34 TRCDF Register
Timer RC output mask enable register
Figure 14.35 TRCOER Register
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCMR
Bit Symbol
Address
0120h
Bit Name
PWM mode of TRCIOB select bit(2)
After Reset
01001000b
Function
RW
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRCIOD select bit
0 : Timer mode
1 : PWM mode
RW
PWM2 mode select bit
0 : PWM 2 mode
1 : Timer mode or PWM mode
RW
BFC
TRCGRC register function select
bit(3)
0 : General register
1 : Buffer register of TRCGRA register
RW
BFD
TRCGRD register function select
bit
0 : General register
1 : Buffer register of TRCGRB register
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWMB
(2)
PWMC
PWM mode of TRCIOC select bit
(2)
PWMD
PWM2
TSTART
TRC count start bit
0 : Count stops
1 : Count starts
NOTES:
1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode.
2. These bits are enabled w hen the PWM2 bit is set to 1 (timer mode or PWM mode).
3. Set the BFC bit to 0 (general register) in PWM2 mode.
Figure 14.27
TRCMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : Timer mode
1 : PWM mode
Page 176 of 441
—
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Function varies according to the
operating mode (function).(2)
RW
RW
(1)
TOB
TRCIOB output level select bit
RW
(1)
TOC
TRCIOC output level select bit
RW
(1)
TOD
TRCIOD output level select bit
Count source select bits
(1)
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
TCK1
TCK2
TRC counter clear select bit(2, 3)
CCLR
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
RW
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. Bits CCLR, TOA, TOB, TOC and TOD are disabled for the input capture function of the timer mode.
3. The TRC counter performs free-running operation for the input capture function of the timer mode independent of the
CCLR bit setting.
Figure 14.28
TRCCR1 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 177 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCIER
Address
0122h
After Reset
01110000b
Bit Symbol
Bit Name
Function
IMIEA
IMIEB
IMIEC
IMIED
—
(b6-b4)
Input capture / compare match
interrupt enable bit A
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
RW
Input capture / compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture / compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture / compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Overflow interrupt enable bit
OVIE
Figure 14.29
TRCIER Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Page 178 of 441
0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
—
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCSR
Bit Symbol
IMFA
Address
0123h
Bit Name
Input capture / compare match flag
A
After Reset
01110000b
Function
[Source for setting this bit to 0]
Write 0 after read.(1)
[Source for setting this bit to 1]
Refer to the table below .
Input capture / compare match flag
B
IMFC
Input capture / compare match flag
C
RW
IMFD
Input capture / compare match flag
D
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
Overflow flag
OVF
[Source for setting this bit to 0]
Write 0 after read.(1)
[Source for setting this bit to 1]
Refer to the table below .
NOTE:
1. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
IMFA
IMFB
IMFC
IMFD
OVF
Timer Mode
PWM Mode
PWM2 Mode
Input capture Function
Output Compare
Function
TRCIOA pin input edge(1)
When the values of the registers TRC and TRCGRA match.
TRCIOB pin input edge(1)
When the values of the registers TRC and TRCGRB match.
TRCIOC pin input edge(1)
When the values of the registers TRC and TRCGRC
match.(2)
TRCIOD pin input edge(1)
When the values of the registers TRC and TRCGRD
match.(2)
When the TRC register overflow s.
NOTES:
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA
and TRCGRB).
Figure 14.30
TRCSR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
IMFB
—
(b6-b4)
Bit Symbol
RW
Page 179 of 441
RW
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Counter(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRC
Address
0127h-0126h
Function
After Reset
0000h
Setting Range
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRCSR register is set to 1.
RW
0000h to FFFFh
RW
NOTE:
1. Access the TRC register in 16-bit units. Do not access it in 8-bit units.
Figure 14.31
TRC Register
Timer RC General Register A, B, C and D(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRCGRA
TRCGRB
TRCGRC
TRCGRD
Address
0129h-0128h
012Bh-012Ah
012Dh-012Ch
012Fh-012Eh
Function
Function varies according to the operating mode.
NOTE:
1. Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.
Figure 14.32
Registers TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 180 of 441
After Reset
FFFFh
FFFFh
FFFFh
FFFFh
RW
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR2
Address
0130h
After Reset
00011111b
Bit Symbol
Bit Name
Function
—
(b4-b0)
CSEL
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRC count operation select
bit(1, 2)
0 : Count continues at compare match w ith
the TRCGRA register
1 : Count stops at compare match w ith
the TRCGRA register
TRCTRG input edge select bits (3)
b7 b6
TCEG0
TCEG1
0 0 : Disable the trigger input from the
TRCTRG pin
0 1 : Rising edge selected
1 0 : Falling edge selected
1 1 : Both edges selected
RW
—
RW
RW
RW
NOTES:
1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode.
2. In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting).
3. In timer mode and PWM mode these bits are disabled.
Figure 14.33
TRCCR2 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 181 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Digital Filter Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCDF
Bit Symbol
DFA
Address
0131h
Bit Name
TRCIOA pin digital filter function
select bit(1)
After Reset
00h
Function
0 : Function is not used
1 : Function is used
RW
RW
DFB
TRCIOB pin digital filter function
select bit(1)
RW
DFC
TRCIOC pin digital filter function
select bit(1)
RW
DFD
TRCIOD pin digital filter function
select bit(1)
RW
DFTRG
TRCTRG pin digital filter function
select bit(2)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
—
(b5)
DFCK0
Clock select bits for digital filter
function(1, 2)
DFCK1
b7 b6
0
0
1
1
0 : f32
1 : f8
0 : f1
1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRCCR1 register)
RW
RW
NOTES:
1. These bits are enabled for the input capture function.
2. These bits are enabled w hen in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or
11b (TRCTRG trigger input enabled).
Figure 14.34
TRCDF Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 182 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Output Master Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCOER
Bit Symbol
Address
0132h
Bit Name
TRCIOA output disable bit(1)
EA
TRCIOB output disable bit(1)
EB
TRCIOC output disable bit(1)
EC
TRCIOD output disable bit(1)
ED
—
(b6-b4)
After Reset
01111111b
Function
RW
0 : Enable output
1 : Disable output (The TRCIOA pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRCIOB pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRCIOC pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRCIOD pin is
used as a programmable I/O port.)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
_____
PTO
INT0 of pulse output forced
cutoff signal input enabled
bit
0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(Bits EA, EB, EC, and ED are set to 1
(disable output) w hen “L” is applied to the
_____
INT0 pin)
NOTE:
1. These bits are disabled for input pins set to the input capture function.
Figure 14.35
TRCOER Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 183 of 441
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC I/O Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRCIOR0
0124h
Bit Symbol
Bit Name
IOA0
TRCGRA control bits
IOA1
TRCGRA mode select bit(2)
IOA2
IOA3
IOB0
IOB1
IOB2
—
(b7)
After Reset
10001000b
Function
Function varies according to the operating mode
(function).
RW
RW
RW
0 : Output compare function
1 : Input capture function
RW
TRCGRA input capture input
sw itch bit(4)
0 : fOCO128 signal
1 : TRCIOA pin input
RW
TRCGRB control bits
Function varies according to the operating mode
(function).
RW
RW
TRCGRB mode select bit(3)
0 : Output compare function
1 : Input capture function
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Timer RC I/O Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRCIOR1
0125h
Bit Symbol
Bit Name
IOC0
TRCGRC control bits
IOC1
TRCGRC mode select bit(2)
IOC2
After Reset
10001000b
Function
Function varies according to the operating mode
(function).
0 : Output compare function
1 : Input capture function
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
IOD0
IOD1
TRCGRD control bits
Function varies according to the operating mode
(function).
RW
RW
TRCGRD mode select bit(3)
0 : Output compare function
1 : Input capture function
RW
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Registers TRCIOR0 and TRCIOR1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
—
(b3)
IOD2
Figure 14.36
RW
RW
RW
Page 184 of 441
—
—
R8C/28 Group, R8C/29 Group
14.3.3
14. Timers
Common Items for Multiple Modes
14.3.3.1
Count Source
The method of selecting the count source is common to all modes.
Table 14.14 lists the Count Source Selection, and Figure 14.37 shows a Count Source Block Diagram.
Table 14.14
Count Source Selection
Count Source
f1, f2, f4, f8, f32
fOCO40M
Selection Method
Count source selected using bits TCK2 to TCK0 in TRCCR1 register
FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits
TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)
External signal input Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge
to TRCCLK pin
of external clock) and PD3_3 bit in PD3 register is set to 0 (input mode)
TCK2 to TCK0
f1
= 000b
= 001b
f2
= 010b
f4
Count source
= 011b
f8
TRC register
= 100b
f32
= 101b
TRCCLK
= 110b
fOCO40M
TCK2 to TCK0: Bits in TRCCR1 register
Figure 14.37
Count Source Block Diagram
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC
operation clock (refer to Table 14.11 Timer RC Operation Clock).
To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip
oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 185 of 441
R8C/28 Group, R8C/29 Group
14.3.3.2
14. Timers
Buffer Operation
Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer
register for the TRCGRA or TRCGRB register.
• Buffer register for TRCGRA register: TRCGRC register
• Buffer register for TRCGRB register: TRCGRD register
Buffer operation differs depending on the mode.
Table 14.15 lists the Buffer Operation in Each Mode, Figure 14.38 shows the Buffer Operation for Input
Capture Function, and Figure 14.39 shows the Buffer Operation for Output Compare Function.
Table 14.15
Buffer Operation in Each Mode
Function, Mode
Input capture function
Transfer Timing
Input capture signal input
Transfer Destination Register
Contents of TRCGRA (TRCGRB)
register are transferred to buffer
register
Contents of buffer register are
transferred to TRCGRA (TRCGRB)
register
Contents of buffer register (TRCGRD)
are transferred to TRCGRB register
Output compare function Compare match between TRC
register and TRCGRA (TRCGRB)
PWM mode
register
PWM2 mode
• Compare match between TRC
register and TRCGRA register
• TRCTRG pin trigger input
TRCIOA input
(input capture signal)
TRCGRC
register
TRCGRA
register
TRC
TRCIOA input
TRC register
n
n-1
n+1
Transfer
TRCGRA register
m
n
Transfer
TRCGRC register
(buffer)
m
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).
Figure 14.38
Buffer Operation for Input Capture Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 186 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Compare match signal
TRCGRC
register
TRC register
TRCGRA register
TRCGRA
register
Comparator
m
m-1
TRC
m+1
m
n
Transfer
TRCGRC register
(buffer)
n
TRCIOA output
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
Figure 14.39
Buffer Operation for Output Compare Function
Make the following settings in timer mode.
• To use the TRCGRC register as the buffer register for the TRCGRA register:
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
• To use the TRCGRD register as the buffer register for the TRCGRB register:
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 187 of 441
R8C/28 Group, R8C/29 Group
14.3.3.3
14. Timers
Digital Filter
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.
Figure 14.40 shows a Block Diagram of Digital Filter.
TCK2 to TCK0
f1
f2
f4
f8
f32
TRCCLK
DFCK1 to DFCK0
= 000b
= 00b
f32
= 001b
= 01b
f8
= 010b
= 10b
f1
= 011b
= 11b
Count source
= 100b
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
(or TCEG1 to TCEG0)
= 101b
= 110b
fOCO40M
Sampling clock
DFj (or DFTRG)
C
TRCIOj input signal
(or TRCTRG input
signal)
D
C
Q
Latch
C
D
Q
Latch
D
1
C
Q
Latch
D
Q
Match detect
circuit
Edge detect
circuit
Latch
0
Timer RC operation clock
f1 or fOCO40M
C
D
Q
Latch
Clock cycle selected by
TCK2 to TCK0
(or DFCK1 to DFCK0)
Sampling clock
TRCIOj input signal
(or TRCTRG input signal)
Three matches occur and a
signal change is confirmed.
Input signal after passing
through digital filter
Maximum signal transmission
delay is five sampling clock
pulses.
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
j = A, B, C, or D
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0: Bits in TRCCR2 register
Figure 14.40
Block Diagram of Digital Filter
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 188 of 441
R8C/28 Group, R8C/29 Group
14.3.3.4
14. Timers
Forced Cutoff of Pulse Output
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj output pin functions as the programmable I/O port). When one or two
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 14.11 Timer RC
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.
Make the following settings to use this function.
• Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H”
output) (refer to 7. Programmable I/O Ports).
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and
a change in the INT0 pin input (refer to 12.6 Notes on Interrupts).
For details on interrupts, refer to 12. Interrupts.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 189 of 441
R8C/28 Group, R8C/29 Group
14. Timers
EA bit
write value
INT0 input
EA bit
D Q
S
Timer RC
output data
TRCIOA
Port P1_1
output data
PTO bit
Port P1_1
input data
EB bit
write value
EB bit
D Q
S
Timer RC
output data
TRCIOB
Port P1_2
output data
Port P1_2
input data
EC bit
write value
EC bit
D Q
S
Timer RC
output data
TRCIOC
Port P3_4
output data
Port P3_4
input data
ED bit
write value
ED bit
D Q
S
Timer RC
output data
Port P3_5
output data
Port P3_5
input data
EA, EB, EC, ED, PTO: Bits in TRCOER register
Figure 14.41
Forced Cutoff of Pulse Output
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 190 of 441
TRCIOD
R8C/28 Group, R8C/29 Group
14.3.4
14. Timers
Timer Mode (Input Capture Function)
This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A,
B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj
register (input capture). The input capture function, or any other mode or function, can be selected for each
individual pin.
The TRCGRA register can also select fOCO128 signal as input-capture trigger input.
Table 14.16 lists the Specifications of Input Capture Function, Figure 14.42 shows a Block Diagram of Input
Capture Function, Figures 14.43 and 14.44 show the registers associated with the input capture function, Table
14.17 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 14.45 shows an
Operating Example of Input Capture Function.
Table 14.16
Specifications of Input Capture Function
Item
Count source
Count operation
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
1/fk × 65,536 fk: Count source frequency
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The TRC register retains a value before count stops.
• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows.
Programmable I/O port or input capture input (selectable individually by
pin)
Programmable I/O port or INT0 interrupt input
The count value can be read by reading TRC register.
The TRC register can be written to.
• Input capture input pin select
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selected
Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRCGRA register.
j = A, B, C, or D
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 191 of 441
R8C/28 Group, R8C/29 Group
fOCO
Divided
by 128
14. Timers
fOCO128
IOA3 = 0
Input capture signal(3)
TRCIOA
IOA3 = 1
(Note 1)
TRCGRA
register
TRC register
TRCGRC
register
TRCIOC
Input capture signal
Input capture signal
TRCIOB
(Note 2)
TRCGRB
register
TRCGRD
register
TRCIOD
Input capture signal
IOA3: Bit in TRCIOR0 register
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.
Figure 14.42
Block Diagram of Input Capture Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 192 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC I/O Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TRCIOR0
Bit Symbol
Address
0124h
Bit Name
TRCGRA control bits
IOA1
IOA3
RW
TRCGRA input capture input
sw itch bit(3)
0 : fOCO128 signal
1 : TRCIOA pin input
RW
TRCGRB control bits
b5 b4
0 0 : Input capture to the TRCGRB register
at the rising edge
0 1 : Input capture to the TRCGRB register
at the falling edge
1 0 : Input capture to the TRCGRB register
at both edges
1 1 : Do not set.
TRCGRB mode select bit(2)
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
3. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Figure 14.43
TRCIOR0 Register for Input Capture Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Set to 1 (input capture) in the input capture
function.
IOB1
—
(b7)
RW
TRCGRA mode select bit(1)
IOB0
IOB2
RW
b1 b0
0 0 : Input capture to the TRCGRA register
at the rising edge
0 1 : Input capture to the TRCGRA register
at the falling edge
1 0 : Input capture to the TRCGRA register
at both edges
1 1 : Do not set.
IOA0
IOA2
After Reset
10001000b
Function
Page 193 of 441
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC I/O Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TRCIOR1
Bit Symbol
Address
0125h
Bit Name
TRCGRC control bits
After Reset
10001000b
Function
0 0 : Input capture to the TRCGRC register
at the rising edge
0 1 : Input capture to the TRCGRC register
at the falling edge
1 0 : Input capture to the TRCGRC register
at both edges
1 1 : Do not set.
IOC0
IOC1
IOC2
—
(b3)
TRCGRC mode select bit(1)
RW
RW
RW
—
b5 b4
0 0 : Input capture to the TRCGRD register
at the rising edge
0 1 : Input capture to the TRCGRD register
at the falling edge
1 0 : Input capture to the TRCGRD register
at both edges
1 1 : Do not set.
IOD0
IOD1
—
(b7)
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRCGRD control bits
IOD2
RW
b1 b0
TRCGRD mode select bit(2)
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
RW
—
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Figure 14.44
Table 14.17
TRCIOR1 Register for Input Capture Function
Functions of TRCGRj Register when Using Input Capture Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
−
BFC = 0
BFD = 0
BFC = 1
BFD = 1
Input Capture
Input Pin
General register. Can be used to read the TRC register value TRCIOA
at input capture.
TRCIOB
General register. Can be used to read the TRC register value TRCIOC
at input capture.
TRCIOD
Buffer registers. Can be used to hold transferred value from TRCIOA
the general register. (Refer to 14.3.3.2 Buffer Operation.)
TRCIOB
Register Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 194 of 441
R8C/28 Group, R8C/29 Group
14. Timers
TRCCLK input
count source
TRC register
count value
FFFFh
0006h
0003h
0000h
TSTART bit in
TRCMR register
1
0
65536
TRCIOA input
TRCGRA register
0006h
Transfer
TRCGRC register
0003h
Transfer
0006h
IMFA bit in
TRCSR register
1
OVF bit in
TRCSR register
1
0
Set to 0 by a program
0
The above applies under the following conditions:
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
Figure 14.45
Operating Example of Input Capture Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 195 of 441
R8C/28 Group, R8C/29 Group
14.3.5
14. Timers
Timer Mode (Output Compare Function)
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The
output compare function, or other mode or function, can be selected for each individual pin.
Table 14.18 lists the Specifications of Output Compare Function, Figure 14.46 shows a Block Diagram of
Output Compare Function, Figures 14.47 to 14.49 show the registers associated with the output compare
function, Table 14.19 lists the Functions of TRCGRj Register when Using Output Compare Function, and
Figure 14.50 shows an Operating Example of Output Compare Function.
Table 14.18
Specifications of Output Compare Function
Item
Count source
Count operation
Count period
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
• The CCLR bit in the TRCCR1 register is set to 0 (free running
operation):
1/fk × 65,536
fk: Count source frequency
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to
0000h at TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
Compare match
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops,
the TRC register retains a value before count stops.
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port or output compare output (selectable individually
by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• Output compare output pin selected
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level select
“L” output, “H” output, or toggle output
• Initial output level select
Sets output level for period from count start to compare match
• Timing for clearing the TRC register to 0000h
Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
of Pulse Output.)
• Can be used as an internal timer by disabling timer RC output
j = A, B, C, or D
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 196 of 441
R8C/28 Group, R8C/29 Group
14. Timers
TRC
TRCIOA
TRCIOC
TRCIOB
TRCIOD
Figure 14.46
Output
control
Output
control
Output
control
Output
control
Compare match signal
TRCGRA
Comparator
TRCGRC
Comparator
TRCGRB
Comparator
TRCGRD
Compare match signal
Compare match signal
Compare match signal
Block Diagram of Output Compare Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Comparator
Page 197 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC I/O Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
TRCIOR0
Bit Symbol
Address
0124h
Bit Name
TRCGRA control bits
IOA1
IOA3
TRCGRA mode select bit(1)
Set to 0 (output compare) in the output compare
function.
TRCGRA input capture input
sw itch bit
Set to 1.
TRCGRB control bits
b5 b4
0 0 : Disable pin output by compare
match (TRCIOB pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRB register
1 0 : “H” output by compare match in
the TRCGRB register
1 1 : Toggle output by compare match
in the TRCGRB register
IOB0
IOB1
IOB2
—
(b7)
TRCGRB mode select bit(2)
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Figure 14.47
TRCIOR0 Register for Output Compare Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 198 of 441
RW
b1 b0
0 0 : Disable pin output by compare
match (TRCIOA pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRA register
1 0 : “H” output by compare match in
the TRCGRA register
1 1 : Toggle output by compare match
in the TRCGRA register
IOA0
IOA2
After Reset
10001000b
Function
RW
RW
RW
RW
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC I/O Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
TRCIOR1
Bit Symbol
Address
0125h
Bit Name
TRCGRC control bits
IOC1
—
(b3)
TRCGRC mode select bit(1)
IOD1
—
(b7)
TRCGRD mode select bit(2)
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Figure 14.48
TRCIOR1 Register for Output Compare Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 199 of 441
RW
RW
RW
—
b5 b4
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRD register
1 0 : “H” output by compare match in
the TRCGRD register
1 1 : Toggle output by compare match
in the TRCGRD register
IOD0
IOD2
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRCGRD control bits
RW
b1 b0
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRC register
1 0 : “H” output by compare match in
the TRCGRC register
1 1 : Toggle output by compare match
in the TRCGRC register
IOC0
IOC2
After Reset
10001000b
Function
RW
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1, 2)
After Reset
00h
Function
0 : Initial output “L”
1 : Initial output “H”
RW
RW
(1, 2)
TOB
TRCIOB output level select bit
RW
(1, 2)
TOC
TRCIOC output level select bit
RW
(1, 2)
TOD
TRCIOD output level select bit
Count source select bits
(1)
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
TCK1
TCK2
TRC counter clear select bit
CCLR
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
RW
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Tables 7.5 to 7.8 and Tables 7.16 to 7.19), the initial output
level is output w hen the TRCCR1 register is set.
Figure 14.49
Table 14.19
TRCCR1 Register for Output Compare Function
Functions of TRCGRj Register when Using Output Compare Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
Register Function
−
General register. Write a compare value to one of these
registers.
BFC = 0
BFD = 0
BFC = 1
BFD = 1
General register. Write a compare value to one of these
registers.
Buffer register. Write the next compare value to one of
these registers. (Refer to 14.3.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 200 of 441
Output Compare
Output Pin
TRCIOA
TRCIOB
TRCIOC
TRCIOD
TRCIOA
TRCIOB
R8C/28 Group, R8C/29 Group
14. Timers
Count source
TRC register value
m
n
p
Count
restarts
Count
stops
TSTART bit in
TRCMR register
1
0
m+1
m+1
Output level held
TRCIOA output
Output inverted at
compare match
Initial output “L”
IMFA bit in
TRCSR register
1
0
Set to 0 by a program
Output level held
n+1
TRCIOB output
“H” output at
compare match
Initial output “L”
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
P+1
Output level held
“L” output at compare match
TRCIOC output
Initial output “H”
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until
compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
Figure 14.50
Operating Example of Output Compare Function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 201 of 441
R8C/28 Group, R8C/29 Group
14.3.6
14. Timers
PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA
register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer
mode.)
Table 14.20 lists the Specifications of PWM Mode, Figure 14.51 shows a Block Diagram of PWM Mode,
Figure 14.52 shows the register associated with the PWM mode, Table 14.21 lists the Functions of TRCGRj
Register in PWM Mode, and Figures 14.53 and 14.54 show Operating Examples of PWM Mode.
Table 14.20
Specifications of PWM Mode
Item
Count source
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count operation
PWM waveform
m+1
n+1
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA pin function
TRCIOB, TRCIOC, and
TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
(“L” is active level)
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
• Compare match (contents of registers TRC and TRCGRh match)
• The TRC register overflows.
Programmable I/O port
Programmable I/O port or PWM output (selectable individually by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• One to three pins selectable as PWM output pins per channel
One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable by individual pin
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
of Pulse Output.)
j = B, C, or D
h = A, B, C, or D
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
m-n
Page 202 of 441
R8C/28 Group, R8C/29 Group
14. Timers
TRC
Compare match signal
Comparator
TRCIOB
TRCGRA
Compare match signal
(Note 1)
Output
control
TRCIOC
Comparator
TRCGRB
Comparator
TRCGRC
Compare match signal
TRCIOD
(Note 2)
Compare match signal
Comparator
TRCGRD
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
Figure 14.51
Block Diagram of PWM Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 203 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Disabled in PWM mode
TRCIOB output level select bit(1, 2)
0 : Active level “H”
(Initial output “L”
“H” output by compare match in
the TRCGRj register
“L” output by compare match in
the TRCGRA register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in
the TRCGRj register
“H” output by compare match in
the TRCGRA register
TOB
TRCIOC output level select bit(1, 2)
TOC
TRCIOD output level select bit(1, 2)
TOD
Count source select bits (1)
TCK1
TCK2
TRC counter clear select bit
CCLR
RW
RW
RW
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
RW
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
j = B, C or D
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Table 7.7, Table 7.8, and Tables 7.16 to 7.19), the initial
output level is output w hen the TRCCR1 register is set.
Figure 14.52
Table 14.21
TRCCR1 Register in PWM Mode
Functions of TRCGRj Register in PWM Mode
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
Setting
−
−
BFC = 0
BFD = 0
BFC = 1
TRCGRD
BFD = 1
Register Function
General register. Set the PWM period.
General register. Set the PWM output change point.
General register. Set the PWM output change point.
Buffer register. Set the next PWM period. (Refer to 14.3.3.2
Buffer Operation.)
Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.)
PWM Output Pin
−
TRCIOB
TRCIOC
TRCIOD
−
TRCIOB
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 204 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Count source
TRC register value
m
n
p
q
m+1
n+1
Active level is “H”
TRCIOB output
m-n
Inactive level is “L”
p+1
m-p
“L” initial output until
compare match
TRCIOC output
q+1
m-q
Active level is “L”
TRCIOD output
“H” initial output until
compare match
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
IMFD bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”).
Figure 14.53
Operating Example of PWM Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 205 of 441
R8C/28 Group, R8C/29 Group
14. Timers
TRC register value
p
m
q
n
0000h
TSTART bit in
TRCMR register
1
TRCIOB output does not switch to “L” because
no compare match with the TRCGRB register
has occurred
0
Duty 0%
TRCIOB output
n
TRCGRB register
q
p (p>m)
Rewritten by a program
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
TRC register value
m
p
n
0000h
TSTART bit in
TRCMR register
1
If compare matches occur simultaneously with registers TRCGRA and
TRCGRB, the compare match with the TRCGRB register has priority.
TRCIOB output switches to “L”. (In other words, no change).
0
Duty 100%
TRCIOB output
TRCIOB output switches to “L” at compare match with the
TRCGRB register. (In other words, no change).
TRCGRB register
m
n
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
p
Rewritten by
a program
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
The above applies under the following conditions:
• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).
• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).
Figure 14.54
Operating Example of PWM Mode (Duty 0% and Duty 100%)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 206 of 441
R8C/28 Group, R8C/29 Group
14.3.7
14. Timers
PWM2 Mode
This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the
pin output switches to active level. Then, after a given duration, the output switches back to inactive level.
Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use
PWM2 mode to output a programmable wait one-shot waveform.
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with
it.
Figure 14.55 shows a Block Diagram of PWM2 Mode, Table 14.22 lists the Specifications of PWM2 Mode,
Figure 14.56 shows the register associated with PWM2 mode, Table 14.23 lists the Functions of TRCGRj
Register in PWM2 Mode, and Figures 14.57 to 14.59 show Operating Examples of PWM2 Mode.
Trigger signal
Compare match signal
TRCTRG
TRCIOB
Input
control
Count clear signal
TRC
(Note 1)
Comparator
TRCGRA
Comparator
TRCGRB
Comparator
TRCGRC
TRCGRD
register
Output
control
NOTE:
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register).
Figure 14.55
Block Diagram of PWM2 Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 207 of 441
R8C/28 Group, R8C/29 Group
Table 14.22
14. Timers
Specifications of PWM2 Mode
Item
Count source
Count operation
PWM waveform
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRCTRG input
m+1
n+1
n+1
p+1
p+1
TRCIOB output
n-p
n-p
(TRCTRG: Rising edge, active level is “H”)
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
TRCIOC and TRCIOD
pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b
(TRCTRG trigger enabled) and the TSTART bit in the TRCMR register is set to 1
(count starts).
A trigger is input to the TRCTRG pin
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL
bit in the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB
bit in the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is
set to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt
input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selected
The edge or edges of the signal input to the TRCTRG pin can be used as the
PWM output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse
Output.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
j = A, B, or C
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 208 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Disabled in the PWM2 mode
TRCIOB output level select bit(1, 2)
0 : Active level “H”
(Initial output “L”
“H” output by compare match in the
TRCGRC register
“L” output by compare match in the
TRCGRB register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in the
TRCGRC register
“H” output by compare match in the
TRCGRB register
TOB
TOC
TOD
TRCIOC output level select bit(1)
Disabled in the PWM2 mode
TRCIOD output level select bit(1)
Count source select bits (1)
TCK1
TCK2
TRC counter clear select bit
CCLR
RW
RW
RW
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
RW
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Table 7.7 and Table 7.8), the initial output level is output
w hen the TRCCR1 register is set.
Figure 14.56
Table 14.23
TRCCR1 Register in PWM2 Mode
Functions of TRCGRj Register in PWM2 Mode
Register
TRCGRA
TRCGRB
TRCGRC
Setting
−
−
BFC = 0
TRCGRD
TRCGRD
BFD = 0
BFD = 1
Register Function
PWM2 Output Pin
General register. Set the PWM period.
TRCIOB pin
General register. Set the PWM output change point.
General register. Set the PWM output change point (wait time
after trigger).
(Not used in PWM2 mode)
−
Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin
14.3.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. Do not set the TRCGRB and TRCGRC registers to the same value.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 209 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Count source
TRC register value
FFFFh
TRC register cleared
at TRCGRA register
compare match
m
n
Previous value held if the
TSTRAT bit is set to 0
Set to 0000h
by a program
p
0000h
TSTART bit in
TRCMR register
Count stops
because the
CSEL bit is
set to 1
1
0
Set to 1 by
a program
CSEL bit in
TRCCR2 register
TSTART bit
is set to 0
1
0
m+1
n+1
p+1
“H” output at TRCGRC
register compare match
p+1
Return to initial output
if the TSTART bit is
set to 0
“L” initial output
TRCIOB output
“L” output at TRCGRB
register compare match
No change
No change
“H” output at TRCGRC register
compare match
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
0
Set to 0 by a program
Set to 0 by a program
0
TRCGRB register
n
Transfer
TRCGRD register
n
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 14.57
Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 210 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Count source
TRC register value
TRC register cleared
at TRCGRA register
compare match
FFFFh
m
TRC register (counter)
cleared at TRCTRG pin
trigger input
Previous value
held if the
TSTART bit is
set to 0
n
Set to 0000h
by a program
p
0000h
TRCTRG input
Count starts at
TRCTRG pin
trigger input
Count starts
when TSTART
bit is set to 1
TSTART bit in
TRCMR register
1
CSEL bit in
TRCCR2 register
1
Count stops
because the
CSEL bit is
set to 1
Changed by a program
The TSTART
bit is set to 0
0
Set to 1 by
a program
0
m+1
n+1
n+1
p+1
p+1
“H” output at
TRCGRC register
compare match
“L” output at
TRCGRB register
compare match
“L” initial output
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
TRCGRB register
p+1
Inactive level so
TRCTRG input is
enabled
Return to initial value if the
TSTART bit is set to 0
Active level so TRCTRG
input is disabled
0
Set to 0 by
a program
0
Set to 0 by
a program
Set to 0 by
a program
Set to 0 by
a program
0
n
n
n
Transfer
TRCGRD register
Transfer
n
Transfer from buffer register to general register
n
Transfer
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the
TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
Figure 14.58
Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 211 of 441
R8C/28 Group, R8C/29 Group
14. Timers
• TRCGRB register setting value greater than TRCGRA
register setting value
TRC register value
• TRCGRC register setting value greater than TRCGRA
register setting value
TRC register value
n
p
m
m
n
p
0000h
0000h
TSTART bit in
TRCMR register
1
TSTART bit in
TRCMR register
0
n+1
m+1
m+1
TRCIOB output
“H” output at TRCGRC register
compare match
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
“L” initial
output
0
0
1
0
p+1
No compare match with
TRCGRB register, so
“H” output continues
IMFA bit in
TRCSR register
1
No compare match
with TRCGRC register,
so “L” output continues
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
Set to 0 by a
program
0
“L” output at
TRCGRB register
compare match
with no change
“L” initial
output
0
0
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 14.59
Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 212 of 441
R8C/28 Group, R8C/29 Group
14.3.8
14. Timers
Timer RC Interrupt
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single
TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 14.24 lists the Registers Associated with Timer RC Interrupt, and Figure 14.60 shows a Block Diagram of
Timer RC Interrupt.
Table 14.24
Registers Associated with Timer RC Interrupt
Timer RC Status Register
TRCSR
Timer RC Interrupt Enable Register
TRCIER
Timer RC Interrupt Control Register
TRCIC
IMFA bit
IMIEA bit
Timer RC interrupt request
(IR bit in TRCIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
Figure 14.60
Block Diagram of Timer RC Interrupt
Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.
• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to
1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt request) when the bit in the TRCSR register or the corresponding bit in
the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained
if the IR bit is once set to 1 but the interrupt is not acknowledged.
• If after the IR bit is set to 1 another interrupt source is triggered, the IR bit remains set to 1 and does not
change.
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
interrupt request.
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them
to 0 within the interrupt routine. Refer to Figure 14.30 TRCSR Register, for the procedure for setting
these bits to 0.
Refer to Figure 14.29 TRCIER Register, for details of the TRCIER register.
Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 213 of 441
R8C/28 Group, R8C/29 Group
14.3.9
14. Timers
Notes on Timer RC
14.3.9.1
TRC Register
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.W
#XXXXh, TRC
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.W
TRC,DATA
;Read
14.3.9.2
TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.B
#XXh, TRCSR
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.B
TRCSR,DATA
;Read
14.3.9.3
Count Source Switching
• Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
14.3.9.4
Input Capture Function
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
(refer to Table 14.11 Timer RC Operation Clock).
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
14.3.9.5
TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 214 of 441
R8C/28 Group, R8C/29 Group
14.4
14. Timers
Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
• Real-time clock mode
Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
• Output compare mode
Count a count source and detect compare matches.
(For J, K version, timer RE can be used only in output compare mode.)
The count source for timer RE is the operating clock that regulates the timing of timer operations.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 215 of 441
R8C/28 Group, R8C/29 Group
14.4.1
14. Timers
Real-Time Clock Mode (For N, D Version Only)
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 14.61 shows
a Block Diagram of Real-Time Clock Mode and Table 14.25 lists the Specifications of Real-Time Clock Mode.
Figures 14.62 to 14.66 and 14.68 and 14.69 show the registers associated with real-time clock mode. Table
14.26 lists the Interrupt Sources, Figure 14.67 shows the Definition of Time Representation and Figure 14.70
shows the Operating Example in Real-Time Clock Mode.
1/2
fC4
(1/16)
(1/256)
4-bit counter
8-bit counter
(1s)
Overflow
Data bus
Overflow
TRESEC
register
Overflow
TREMIN
register
Overflow
TREHR
register
H12_H24
bit
TREWK
register
000
PM
bit
WKIE
DYIE
Timing
control
HRIE
INT
bit
MNIE
SEIE
BSY
bit
H12_H24, PM, INT: Bits in TRECR1 register
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.61
Block Diagram of Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 216 of 441
Timer RE interrupt
R8C/28 Group, R8C/29 Group
Table 14.25
14. Timers
Specifications of Real-Time Clock Mode
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request
generation timing
Read from timer
Write to timer
Select function
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Specification
fC4
Increment
1 (count starts) is written to TSTART bit in TRECR1 register
0 (count stops) is written to TSTART bit in TRECR1 register
Select any one of the following:
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN, and
TREHR are represented by the BCD code.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
• 12-hour mode/24-hour mode switch function
Page 217 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Second Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
After Reset
00h
Bit Symbol
Bit Name
Function
SC00
SC01
SC02
SC03
SC10
SC11
SC12
1st digit of second count bits
Count 0 to 9 every second. When the 0 to 9
digit moves up, 1 is added to the 2nd (BCD
digit of second.
code)
2nd digit of second count bits
When counting 0 to 5, 60 seconds
are counted.
Timer RE busy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
Figure 14.62
Setting
Range
0 to 5
(BCD
code)
RW
RW
RW
RW
RW
RW
RW
RW
RO
TRESEC Register in Real-Time Clock Mode
Timer RE Minute Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
After Reset
00h
Bit Symbol
Bit Name
Function
MN00
MN01
MN02
MN03
MN10
MN11
MN12
1st digit of minute count bits
Count 0 to 9 every minute. When the 0 to 9
digit moves up, 1 is added to the 2nd (BCD
digit of minute.
code)
2nd digit of minute count bits
When counting 0 to 5, 60 minutes are 0 to 5
counted.
(BCD
code)
Timer RE busy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
Figure 14.63
TREMIN Register in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Setting
Range
Page 218 of 441
RW
RW
RW
RW
RW
RW
RW
RW
RO
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Hour Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREHR
Address
011Ah
After Reset
00h
Bit Symbol
Bit Name
Function
HR00
HR01
HR02
HR03
HR10
1st digit of hour count bits
Count 0 to 9 every hour. When the
0 to 9
digit moves up, 1 is added to the 2nd (BCD
digit of hour.
code)
2nd digit of hour count bits
Count 0 to 1 w hen the H12_H24 bit is 0 to 2
set to 0 (12-hour mode).
(BCD
Count 0 to 2 w hen the H12_H24 bit is code)
set to 1 (24-hour mode).
HR11
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
BSY
Figure 14.64
Setting
Range
RW
RW
RW
RW
RW
RW
RW
—
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RO
TREHR Register in Real-Time Clock Mode
Timer RE Day of Week Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREWK
Address
011Bh
After Reset
00h
Bit Symbol
Bit Name
Function
Day of w eek count bits
WK1
WK2
—
(b6-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
BSY
Figure 14.65
TREWK Register in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
b2 b1 b0
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
1 1 1 : Do not set
WK0
Page 219 of 441
RW
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RW
RW
RW
—
RO
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECR1
Address
011Ch
After Reset
00h
Bit Symbol
Bit Name
Function
—
(b0)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TCSTF
—
(b2)
INT
Timer RE count status flag
0 : Count stopped
1 : Counting
Reserved bit
Set to 0.
Interrupt request timing bit
Set to 1 in real-time clock mode.
Timer RE reset bit
When setting this bit to 0, after setting it to 1, the
follow ings w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
When the H12_H24 bit is set to 0
(12-hour mode) (1)
0 : a.m.
1 : p.m.
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
RW
Operating mode select bit
0 : 12-hour mode
1 : 24-hour mode
RW
Timer RE count start bit
0 : Count stops
1 : Count starts
RW
TRERST
A.m./p.m. bit
PM
H12_H24
TSTART
—
RO
RW
RW
NOTE:
1. This bit is automatically modified w hile timer RE counts.
Figure 14.66
TRECR1 Register in Real-Time Clock Mode
Noon
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H12_H24 bit = 0
(12-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
0 (a.m.)
Contents of PM bit
1 (p.m.)
000 (Sunday)
Contents in TREWK register
Date changes
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
18
19
20
21
22
23
0
1
2
3
⋅⋅⋅
H12_H24 bit = 0
(12-hour mode)
6
7
8
9
10
11
0
1
2
3
⋅⋅⋅
Contents of PM bit
Contents in TREWK register
1 (p.m.)
0 (a.m.)
⋅⋅⋅
000 (Sunday)
001 (Monday)
⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 14.67
Definition of Time Representation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 220 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECR2
Address
011Dh
After Reset
00h
Bit Symbol
Bit Name
Function
SEIE
MNIE
HRIE
DYIE
WKIE
COMIE
—
(b7-b6)
RW
Periodic interrupt triggered every
second enable bit(1)
0 : Disable periodic interrupt triggered
every second
1 : Enable periodic interrupt triggered
every second
RW
Periodic interrupt triggered every
minute enable bit(1)
0 : Disable periodic interrupt triggered
every minute
1 : Enable periodic interrupt triggered
every minute
RW
Periodic interrupt triggered every
hour enable bit(1)
0 : Disable periodic interrupt triggered
every hour
1 : Enable periodic interrupt triggered
every hour
RW
Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered
enable bit(1)
every day
1 : Enable periodic interrupt triggered
every day
RW
Periodic interrupt triggered every
w eek enable bit(1)
0 : Disable periodic interrupt triggered
every w eek
1 : Enable periodic interrupt triggered
every w eek
Compare match interrupt enable bit
Set to 0 in real-time clock mode.
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTE:
1. Do not set multiple enable bits to 1 (enable interrupt).
Figure 14.68
Table 14.26
TRECR2 Register in Real-Time Clock Mode
Interrupt Sources
Factor
Periodic interrupt
triggered every week
Periodic interrupt
triggered every day
Periodic interrupt
triggered every hour
Periodic interrupt
triggered every minute
Periodic interrupt
triggered every second
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Interrupt Source
Value in TREWK register is set to 000b (Sunday)
(1-week period)
TREWK register is updated (1-day period)
Interrupt Enable Bit
WKIE
DYIE
TREHR register is updated (1-hour period)
HRIE
TREMIN register is updated (1-minute period)
MNIE
TRESEC register is updated (1-second period)
SEIE
Page 221 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
1 0 0 0
Symbol
TRECSR
Address
011Eh
After Reset
00001000b
Bit Symbol
Bit Name
Function
RCS0
Count source select bits
Set to 00b in real-time clock mode.
RCS1
RCS2
RCS3
—
(b4)
—
(b6-b5)
—
(b7)
Figure 14.69
RW
RW
4-bit counter select bit
Set to 0 in real-time clock mode.
Real-time clock mode select bit
Set to 1 in real-time clock mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bits
Set to 00b.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRECSR Register in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Page 222 of 441
RW
RW
—
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
1s
Approx.
62.5 ms
Approx.
62.5 ms
BSY bit
Bits SC12 to SC00 in
TRESEC register
58
59
Bits MN12 to MN00 in
TREMIN register
03
Bits HR11 to HR00 in
TREHR register
(Not changed)
PM bit in
TRECR1 register
IR bit in TREIC register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
IR bit in TREIC register
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
(Not changed)
0
(Not changed)
1
0
1
0
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.70
Operating Example in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
04
1
Bits WK2 to WK0 in
TREWK register
Page 223 of 441
00
Set to 0 by acknowledgement
of interrupt request
or a program
R8C/28 Group, R8C/29 Group
14.4.2
14. Timers
Output Compare Mode
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and
compare value match is detected with the 8-bit counter. Figure 14.71 shows a Block Diagram of Output
Compare Mode and Table 14.27 lists the Specifications of Output Compare Mode. Figures 14.72 to 14.76 show
the registers associated with output compare mode, and Figure 14.77 shows the Operating Example in Output
Compare Mode.
f4
f8
f32
fC4(1)
RCS1 to RCS0
= 00b
= 01b
4-bit
counter
1/2
= 10b
RCS2 = 1
8-bit
counter
= 11b
T Q
R
Reset
RCS2 = 0
TRERST bit
Comparison
circuit
Match
signal
COMIE
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2: Bits in TRECSR register
TRESEC
Timer RE interrupt
TREMIN
Data bus
NOTE:
1. For J, K version, fC4 cannot be selected.
Figure 14.71
Block Diagram of Output Compare Mode
Table 14.27
Specifications of Output Compare Mode
Item
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request
generation timing
Read from timer
Write to timer
Select functions
Specification
fC4(1)
f4, f8, f32,
• Increment
• When the 8-bit counter content matches with the TREMIN register content,
the value returns to 00h and count continues. The count value is held while
count stops.
• When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
1 (count starts) is written to the TSTART bit in the TRECR1 register
0 (count stops) is written to the TSTART bit in the TRECR1 register
When the 8-bit counter content matches with the TREMIN register content
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Select use of 4-bit counter
NOTE:
1. For J, K version, fC4 cannot be selected.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 224 of 441
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Counter Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
Function
After Reset
00h
RW
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
Figure 14.72
RO
TRESEC Register in Output Compare Mode
Timer RE Compare Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
Function
8-bit compare data is stored.
Figure 14.73
TREMIN Register in Output Compare Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 225 of 441
After Reset
00h
RW
RW
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
TRECR1
Address
011Ch
After Reset
00h
Bit Symbol
Bit Name
Function
—
(b0)
TCSTF
—
(b2)
INT
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
PM
H12_H24
TSTART
Figure 14.74
—
Timer RE count status flag
0 : Count stopped
1 : Counting
Reserved bit
Set to 0.
Interrupt request timing bit
Set to 0 in output compare mode.
Timer RE reset bit
When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
TRERST
A.m./p.m. bit
Operating mode select bit
Timer RE count start bit
RW
RO
RW
Set to 0 in output compare mode.
0 : Count stops
1 : Count starts
RW
RW
RW
RW
RW
TRECR1 Register in Output Compare Mode
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
TRECR2
Address
011Dh
After Reset
00h
Bit Symbol
Bit Name
Function
SEIE
Periodic interrupt triggered every
second enable bit
MNIE
Periodic interrupt triggered every
minute enable bit
RW
HRIE
Periodic interrupt triggered every
hour enable bit
RW
DYIE
Periodic interrupt triggered every
day enable bit
RW
WKIE
Periodic interrupt triggered every
w eek enable bit
RW
COMIE
—
(b7-b6)
Figure 14.75
Compare match interrupt enable bit
0 : Disable compare match interrupt
1 : Enable compare match interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRECR2 Register in Output Compare Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Set to 0 in output compare mode.
RW
Page 226 of 441
RW
RW
—
R8C/28 Group, R8C/29 Group
14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
TRECSR
Address
011Eh
After Reset
00001000b
Bit Symbol
Bit Name
Function
b1 b0
Count source select bits
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : fC4(1)
RCS0
RCS1
RCS2
RCS3
—
(b4)
—
(b6-b5)
—
(b7)
RW
4-bit counter select bit
RW
RW
0 : Not used
1 : Used
RW
Real-time clock mode select bit
Set to 0 in output compare mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bits
Set to 00b.
RW
—
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTE:
1. For J, K version, fC4 cannot be selected.
Figure 14.76
TRECSR Register in Output Compare Mode
8-bit counter content
(hexadecimal number)
Count starts
Matched
TREMIN register
setting value
Matched
Matched
00h
Time
Set to 1 by a program
TSTART bit in
TRECR1 register
1
0
2 cycles of maximum count source
TCSTF bit in
TRECR1 register
IR bit in
TREIC register
1
0
Set to 0 by acknowledgement of interrupt request or a program
1
0
The above applies under the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Figure 14.77
Operating Example in Output Compare Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 227 of 441
R8C/28 Group, R8C/29 Group
14.4.3
14. Timers
Notes on Timer RE
14.4.3.1
Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
14.4.3.2
Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 14.78 shows a Setting Example in Real-Time Clock Mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 228 of 441
R8C/28 Group, R8C/29 Group
14. Timers
TSTART in TRECR1 = 0
Stop timer RE operation
TCSTF in TRECR1 = 0?
TREIC ← 00h
(disable timer RE interrupt)
TRERST in TRECR1 = 1
Timer RE register
and control circuit reset
TRERST in TRECR1 = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Setting of TREIC (IR bit ← 0,
select interrupt priority level)
TSTART in TRECR1 = 1
Start timer RE operation
TCSTF in TRECR1 = 1?
Figure 14.78
Setting Example in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 229 of 441
R8C/28 Group, R8C/29 Group
14.4.3.3
14. Timers
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 230 of 441
R8C/28 Group, R8C/29 Group
15. Serial Interface
15. Serial Interface
The serial interface consists of two channels (UART0 and UART1). Each UARTi (i = 0 or 1) has an exclusive timer to
generate the transfer clock and operates independently.
Figure 15.1 shows a UARTi (i = 0 or 1) Block Diagram. Figure 15.2 shows a UARTi Transmit/Receive Unit.
UART0 has 2 modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
UART1 has only clock asynchronous serial I/O mode (UART mode).
Figures 15.3 to 15.7 show the registers associated with UARTi.
(UART0)
RXD0
TXD0
CLK1 to CLK0
f1
f8
f32
CKDIR = 0
Internal
= 00b
= 01b
1/16
Clock
synchronous type
U0BRG register
= 10b
1/(n0+1)
UART reception
1/16
Reception control
circuit
UART transmission
Transmission
control circuit
Clock
synchronous type
External
CKDIR = 1
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR = 0
CKDIR = 1
CLK
polarity
switch
circuit
CLK0
(UART1)
U1PINSEL
RXD1
TXD1
1/16
UART reception
Reception control
circuit
Receive
clock
CLK1 to CLK0
f1
f8
f32
= 00b
U1BRG register
= 01b
1/(n0+1)
1/16
UART transmission
= 10b
Figure 15.1
UARTi (i = 0 or 1) Block Diagram
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 231 of 441
Transmission
control circuit
Transmit
clock
Transmit/
receive
unit
R8C/28 Group, R8C/29 Group
15. Serial Interface
1SP
RXDi
SP
SP
Clock
synchronous
type
PRYE = 0
Clock
PAR
disabled synchronous
type
UART (7 bits)
UART (8 bits)
UART (7 bits)
UARTi receive register
PAR
PAR
UART
enabled
PRYE = 1
2SP
UART (9 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0 UiRB register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D8
PRYE = 1
PAR
enabled
2SP
SP
SP
UART (9 bits)
UART
D6
D5
D4
D3
D2
D1
TXDi
Clock
PAR
disabled synchronous
PRYE = 0 type
0
UARTi Transmit/Receive Unit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
D0 UiTB register
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
PAR
1SP
Figure 15.2
D7
Page 232 of 441
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
i = 0 or 1
SP: Stop bit
PAR: Parity bit
R8C/28 Group, R8C/29 Group
15. Serial Interface
UARTi Transmit Buffer Register (i = 0 or 1)(1, 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
Address
00A3h-00A2h
00ABh-00AAh
Function
After Reset
Undefined
Undefined
RW
—
(b8-b0)
Transmit data
—
(b15-b9)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
WO
—
NOTES:
1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
2. Use the MOV instruction to w rite to this register.
UARTi Receive Buffer Register (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0RB
U1RB
Bit Symbol
—
(b7-b0)
Address
00A7h-00A6h
00AFh-00AEh
Bit Name
—
—
(b8)
—
(b11-b9)
—
Overrun error flag
(2)
FER
Framing error flag
(2)
PER
Parity error flag
(2)
SUM
Receive data (D8)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(2)
OER
After Reset
Undefined
Undefined
Function
Receive data (D7 to D0)
Error sum flag
RW
RO
RO
—
0 : No overrun error
1 : Overrun error
RO
0 : No framing error
1 : Framing error
RO
0 : No parity error
1 : Parity error
RO
0 : No error
1 : Error
RO
NOTES:
1. Read out the UiRB register in 16-bit units.
2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
Figure 15.3
Registers U0TB to U1TB and U0RB to U1RB
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 233 of 441
R8C/28 Group, R8C/29 Group
15. Serial Interface
UARTi Bit Rate Register (i = 0 or 1)(1, 2, 3)
b7
b0
Symbol
U0BRG
U1BRG
Address
00A1h
00A9h
After Reset
Undefined
Undefined
Function
Setting Range
Assuming the set value is n, UiBRG divides the count source by n+1
00h to FFh
RW
WO
NOTES:
1. Write to this register w hile the serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to w rite to this register.
3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
UARTi Transmit/Receive Mode Register (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0MR
U1MR
Bit Symbol
Address
00A0h
00A8h
Bit Name
Serial I/O mode select bits (2)
SMD0
SMD2
STPS
—
(b7)
RW
RW
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
RW
Odd/even parity select bit
Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
RW
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
Reserved bit
Set to 0.
Registers U0BRG to U1BRG and U0MR to U1MR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : Internal clock
1 : External clock(1)
NOTES:
1. Set the PD1_6 bit in the PD1 register to 0 (input).
2. Do not set bits SMD2 to SMD0 in the U1MR register to any values other than 000b, 100b, 101b, and 110b.
3. Set bit 3 in the U1MR register to 0.
Figure 15.4
RW
Internal/external clock select
bit(3)
PRY
PRYE
RW
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
SMD1
CKDIR
After Reset
00h
00h
Function
Page 234 of 441
RW
R8C/28 Group, R8C/29 Group
15. Serial Interface
UARTi Transmit/Receive Control Register 0 (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C0
U1C0
Bit Symbol
CLK0
CLK1
—
(b2)
TXEPT
—
(b4)
NCH
Address
00A4h
00ACh
Bit Name
BRG count source select b1 b0
0 0 : Selects f1
bits (1)
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
Reserved bit
Set to 0.
Transmit register empty
flag
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RO
—
RW
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
RW
Transfer format select bit 0 : LSB first
1 : MSB first
Registers U0C0 to U1C0
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open drain output
NOTE:
1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 15.5
RW
Data output select bit
CKPOL
UFORM
After Reset
00001000b
00001000b
Function
Page 235 of 441
RW
R8C/28 Group, R8C/29 Group
15. Serial Interface
UARTi Transmit/Receive Control Register 1 (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1
U1C1
Bit Symbol
Address
00A5h
00ADh
Bit Name
Transmit enable bit(1)
After Reset
00000010b
00000010b
Function
0 : Disables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Data in UiTB register
1 : No data in UiTB register
RO
Receive enable bit
0 : Disables reception
1 : Enables reception
RW
Receive complete flag(1)
0 : No data in UiRB register
1 : Data in UiRB register
RO
UiIRS
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1)
RW
UiRRM
UARTi continuous receive mode
enable bit(2)
0 : Disables continuous receive mode
1 : Enables continuous receive mode
RW
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TE
TI
RE
RI
NOTES:
1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
Figure 15.6
Registers U0C1 to U1C1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 236 of 441
RW
RW
—
R8C/28 Group, R8C/29 Group
15. Serial Interface
Pin Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 1
Symbol
PINSR1
Bit Symbol
Address
00F5h
Bit Name
TXD1/RXD1 pin select bit(1)
After Reset
00h
Function
RW
b1 b0
0 0 : P3_7(TXD1/RXD1)
0 1 : P3_7(TXD1), P4_5(RXD1)
1 0 : Do not set.
1 1 : Do not set.
UART1SEL0
UART1SEL1
—
(b2)
Reserved bit
Set to 1. When read, the content is 0.
—
(b7-b3)
Reserved bits
Set to 0. When read, the content is 0.
RW
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN in the PMR register.
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
00F8h
PMR
Bit Symbol
Bit Name
—
Reserved bit
(b0)
—
(b2-b1)
SSISEL
U1PINSEL
TXD1SEL
TXD1EN
IICSEL
After Reset
00h
Function
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
SSI pin select bit
0 : P3_3
1 : P1_6
TXD1 pin sw itch bit(1)
Set to 1 to use UART1.
Port/TXD1 pin sw itch bit(1)
0 : Programmable I/O port
1 : TXD1
RW
TXD1/RXD1 select bit(1)
0 : RXD1
1 : TXD1
RW
SSU / I2C bus pin sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN, and bits UART1SEL1 and UART1SEL0 in the
PINSR1 register.
PINSR1 Register
UART1SEL1,
UART1SEL0 bit
00b
01b
Pin Function
PMR Register
TXD1SEL bit
TXD1EN bit
P3_7(TXD1)
P3_7(RXD1)
×
P3_7(TXD1)
1
P4_5(RXD1)
×
×: 0 or 1
Figure 15.7
Registers PINSR1 and PMR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 237 of 441
1
0
×
R8C/28 Group, R8C/29 Group
15.1
15. Serial Interface
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Specifications of Clock Synchronous Serial I/O Mode. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode.
Table 15.1
Specifications of Clock Synchronous Serial I/O Mode
Item
Transfer data format
Transfer clocks
Specification
• Transfer data length: 8 bits
• CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin
Transmit start conditions
• Before transmission starts, the following requirements must be met(1)
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
Receive start conditions
• Before reception starts, the following requirements must be met(1)
- The RE bit in the U0C1 register is set to 1 (reception enabled)
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
• When transmitting, one of the following conditions can be selected
- The U0IRS bit is set to 0 (transmit buffer empty):
When transferring data from the U0TB register to UART0 transmit
register (when transmission starts).
- The U0IRS bit is set to 1 (transmission completes):
When completing data transmission from UART0 transmit register.
• When receiving
When data transfer from the UART0 receive register to the U0RB register
(when reception completes).
Interrupt request
generation timing
Error detection
Select functions
• Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receives the 7th bit of the next data.
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with
the rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the U0RB register.
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 238 of 441
R8C/28 Group, R8C/29 Group
Table 15.2
Register
U0TB
U0RB
U0BRG
U0MR
U0C0
U0C1
15. Serial Interface
Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
U0IRS
U0RRM
Function
Set data transmission
Data reception can be read
Overrun error flag
Set bit rate
Set to 001b
Select the internal clock or external clock
Select the count source in the UiBRG register
Transmit register empty flag
Select TXD0 pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to 1 to enable transmission/reception
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the UART0 transmit interrupt source
Set this bit to 1 to use continuous receive mode
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level
between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel opendrain output), this pin is in a high-impedance state.)
Table 15.3
I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Function
Output serial data
Input serial data
Selection Method
(Outputs dummy data when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
Page 239 of 441
R8C/28 Group, R8C/29 Group
15. Serial Interface
• Example of transmit timing (when internal clock is selected)
TC
Transfer clock
TE bit in U0C1
register
1
0
TI bit in U0C1
register
1
0
Set data in U0TB register
Transfer from U0TB register to UART0 transmit register
TCLK
Stop pulsing because the TE bit is set to 0
CLK0
D0
TXD0
TXEPT bit in
U0C0 register
1
0
IR bit in S0TIC
register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Set to 0 when interrupt request is acknowledged, or set by a program
TC = TCLK = 2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
The above applies under the following settings:
n: Setting value to UiBRG register
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
• Example of receive timing (when external clock is selected)
RE bit in U0C1
register
1
0
TE bit in U0C1
register
1
0
TI bit in U0C1
register
1
0
Write dummy data to U0TB register
Transfer from U0TB register to UART0 transmit register
1/fEXT
CLK0
Receive data is taken in
D0
RXD0
RI bit in U0C1
register
1
0
IR bit in S0RIC
register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
Transfer from UART0 receive register to
U0RB register
D2
D3
D4
D5
Read out from U0RB register
Set to 0 when interrupt request is acknowledged, or set by a program
The above applies under the following settings:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLK0 pin before receiving data:
• TE bit in U0C1 register = 1 (enables transmit)
• RE bit in U0C1 register = 1 (enables receive)
• Write dummy data to the U0TB register
fEXT: Frequency of external clock
Figure 15.8
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 240 of 441
R8C/28 Group, R8C/29 Group
15.1.1
15. Serial Interface
Polarity Select Function
Figure 15.9 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer
clock polarity.
• When the CKPOL bit in the U0C0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
CLK0(1)
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
• When the CKPOL bit in the U0C0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
CLK0(2)
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. When not transferring, the CLK0 pin level is “H”.
2. When not transferring, the CLK0 pin level is “L”.
Figure 15.9
15.1.2
Transfer Clock Polarity
LSB First/MSB First Select Function
Figure 15.10 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.
• When UFORM bit in U0C0 register = 0 (LSB first)(1)
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
• When UFORM bit in U0C0 register = 1 (MSB first)(1)
CLK0
TXD0
D7
D6
D5
D4
D3
D2
D1
D0
RXD0
D7
D6
D5
D4
D3
D2
D1
D0
NOTE:
1. The above applies when the CKPOL bit in the U0C0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
Figure 15.10
Transfer Format
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 241 of 441
R8C/28 Group, R8C/29 Group
15.1.3
15. Serial Interface
Continuous Receive Mode
Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (enables continuous
receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data in the
U0TB register). When the U0RRM bit is set to 1, do not write dummy data to the U0TB register by a program.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 242 of 441
R8C/28 Group, R8C/29 Group
15.2
15. Serial Interface
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 15.4 lists the Specifications of UART Mode. Table 15.5 lists the Registers Used and Settings for UART
Mode.
Table 15.4
Specifications of UART Mode
Item
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Specification
• Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
• Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
• Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
• When transmitting, one of the following conditions can be selected
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
• Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
i = 0 or 1
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 243 of 441
R8C/28 Group, R8C/29 Group
Table 15.5
Registers Used and Settings for UART Mode
Register
UiTB
0 to 8
UiRB
0 to 8
UiBRG
UiMR
UiC0
UiC1
15. Serial Interface
Bit
Function
Set transmit
data(1)
Receive data can be read(1, 2)
OER, FER, PER, SUM Error flag
0 to 7
Set a bit rate
SMD2 to SMD0
Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
CKDIR
Select the internal clock or external clock
STPS
Select the stop bit
PRY, PRYE
Select whether parity is included and whether odd or even
CLK0 to CLK1
Select the count source for the UiBRG register
TXEPT
Transmit register empty flag
NCH
Select TXDi pin output mode
CKPOL
Set to 0
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
TE
Set to 1 to enable transmit
TI
Transmit buffer empty flag
RE
Set to 1 to enable receive
RI
Receive complete flag
UiIRS
Select the source of UARTi transmit interrupt
UiRRM
Set to 0
i = 0 or 1
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the
TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a highimpedance state) until transfer starts.)
Table 15.6
Pin name
TXD0 (P1_4)
RXD0 (P1_5)
CLK0 (P1_6)
TXD1 (P3_7)
RXD1 (either
P3_7 or P4_5)
I/O Pin Functions in UART Mode
Function
Output serial data
Input serial data
Selection Method
(Cannot be used as a port when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing transmission only)
Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
Output serial data
Set registers PINSR1 and PMR (refer to Figure 15.7 Registers
PINSR1 and PMR)
(Cannot be used as a port when performing reception only)
Input serial data
Set registers PINSR1 and PMR (refer to Figure 15.7 Registers
PINSR1 and PMR)
Corresponding bit in each port direction register = 0
(Can be used as an input port when performing transmission only)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 244 of 441
R8C/28 Group, R8C/29 Group
15. Serial Interface
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Start
bit
TXDi
ST
TXEPT bit in
UiC0 register
1
0
IR bit SiTIC
register
1
0
Stop pulsing because the TE bit is set to 0
Parity Stop
bit
bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
Set to 0 when interrupt request is acknowledged, or set by a program
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
fj: Frequency of UiBRG count source (f1, f8, f32)
• STPS bit in UiMR register = 0 (1 stop bit)
fEXT: Frequency of UiBRG count source (external clock)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
n: Setting value to UiBRG register
i = 0 or 1
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Stop Stop
bit
bit
Start
bit
TXDi
ST
TXEPT bit in
UiC0 register
1
0
IR bit in SiTIC
register
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
Figure 15.11
Transmit Timing in UART Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 245 of 441
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 or 1
D1
R8C/28 Group, R8C/29 Group
15. Serial Interface
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register
RE bit
1
0
Stop bit
Start bit
RXDi
D0
D1
D7
Determined to be “L” Receive data taken in
Transfer clock
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
RI bit
1
0
SiRIC register
IR bit
1
0
Transferred from UARTi receive
register to UiRB register
Set to 0 when interrupt request is accepted, or set by a program
The above timing diagram applies when the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
i = 0 or 1
Figure 15.12
Receive Timing Example in UART Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 246 of 441
R8C/28 Group, R8C/29 Group
15.2.1
15. Serial Interface
Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register.
UART mode
• Internal clock selected
UiBRG register setting value =
fj
Bit Rate × 16
-1
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
• External clock selected
UiBRG register setting value =
fEXT
Bit Rate × 16
-1
fEXT: Count source frequency of the UiBRG register (external clock)
i = 0 or 1
Figure 15.13
Calculation Formula of UiBRG (i = 0 or 1) Register Setting Value
Table 15.7
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate
(bps)
UiBRG
Count
Source
1200
2400
4800
9600
14400
19200
28800
38400
57600
115200
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
System Clock = 20 MHz
System Clock = 18.432 MHz(1)
UiBRG
Setting UiBRG
Setting
Actual Time
Actual Time
Setting
Error
Setting
Error
(bps)
(bps)
Value
(%)
Value
(%)
129 (81h)
1201.92
0.16 119 (77h)
1200.00
0.00
64 (40h)
2403.85
0.16 59 (3Bh)
2400.00
0.00
32 (20h)
4734.85 -1.36 29 (1Dh)
4800.00
0.00
129 (81h)
9615.38
0.16 119 (77h)
9600.00
0.00
86 (56h)
14367.82 -0.22 79 (4Fh)
14400.00
0.00
64 (40h)
19230.77
0.16 59 (3Bh)
19200.00
0.00
42 (2Ah)
29069.77
0.94 39 (27h)
28800.00
0.00
32 (20h)
37878.79 -1.36 29 (1Dh)
38400.00
0.00
21 (15h)
56818.18 -1.36 19 (13h)
57600.00
0.00
10 (0Ah) 113636.36 -1.36
9 (09h) 115200.00
0.00
System Clock = 8 MHz
UiBRG
Actual Setting
Setting
Time
Error
Value
(bps)
(%)
51 (33h) 1201.92
0.16
25 (19h) 2403.85
0.16
12 (0Ch) 4807.69
0.16
51 (33h) 9615.38
0.16
34 (22h) 14285.71 -0.79
25 (19h) 19230.77
0.16
16 (10h) 29411.76
2.12
12 (0Ch) 38461.54
0.16
8 (08h) 55555.56 -3.55
−
−
−
i = 0 or 1
NOTE:
1. For the high-speed on-chip oscillator, the correction value in the FRA7 register should be written into the FRA1
register (for N, D version only).
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in
the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 20. Electrical Characteristics.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 247 of 441
R8C/28 Group, R8C/29 Group
15.3
15. Serial Interface
Notes on Serial Interface
• When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W
00A6H,R0
; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B
#XXH,00A2H ; Write the low-order byte of U0TB register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 248 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
16. Clock Synchronous Serial Interface
The clock synchronous serial interface is configured as follows.
Clock synchronous serial interface
Clock synchronous serial I/O with chip select (SSU)
Clock synchronous communication mode
4-wire bus communication mode
I2C bus Interface
I2C bus interface mode
Clock synchronous serial mode
The clock synchronous serial interface uses the registers at addresses 00B8h to 00BFh. Registers, bits, symbols, and
functions vary even for the same addresses depending on the mode. Refer to the register diagrams of each function for
details.
Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the
options of the transfer clock, clock output format, and data output format.
16.1
Mode Selection
The clock synchronous serial interface has four modes.
Table 16.1lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and the
sections that follow for details of each mode.
Table 16.1
IICSEL Bit
in PMR
Register
Mode Selections
Bit 7 in 00B8h
(ICE Bit in ICCR1
Register)
0
0
0
1
0
1
1
1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Bit 0 in 00BDh
(SSUMS Bit in
Function
SSMR2 Register, FS
Bit in SAR Register)
0
Clock synchronous
serial I/O with chip
select
1
0
1
Page 249 of 441
I2C bus interface
Mode
Clock synchronous communication
mode
4-wire bus communication mode
I2C bus interface mode
Clock synchronous serial mode
R8C/28 Group, R8C/29 Group
16.2
16. Clock Synchronous Serial Interface
Clock Synchronous Serial I/O with Chip Select (SSU)
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 lists the Specifications of Clock Synchronous Serial I/O with Chip Select and Figure 16.1 shows a
Block Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show the registers
associated with clock synchronous serial I/O with chip select.
Table 16.2
Specifications of Clock Synchronous Serial I/O with Chip Select
Item
Transfer data format
Operating modes
Master/slave device
I/O pins
Transfer clocks
Receive error
detection
Multimaster error
detection
Interrupt requests
Select functions
Specification
• Transfer data length: 8 bits
Continuous transmission and reception of serial data are supported since both
transmitter and receiver have buffer structures.
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Selectable
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
• When the MSS bit in the SSCRH register is set to 0 (operates as slave device),
external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8
and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
• Overrun error
Overrun error occurs during reception and completes in error. While the RDRF
bit in the SSSR register is set to 1 (data in the SSRDR register) and when next
serial data receive is completed, the ORER bit is set to 1.
• Conflict error
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the CE
bit in the SSSR register is set to 1 if “L” applies to the SCS pin input. When the
SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication
mode), the MSS bit in the SSCRH register is set to 0 (operates as slave
device) and the SCS pin input changes state from “L” to “H”, the CE bit in the
SSSR register is set to 1.
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error).(1)
• Data transfer direction
Selects MSB-first or LSB-first
• SSCK clock polarity
Selects “L” or “H” level when clock stops
• SSCK clock phase
Selects edge of data change and data download
• SSI pin select function
The SSISEL bit in the PMR register can select P3_3 or P1_6 as SSI pin.
NOTE:
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 250 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
f1
Internal clock (f1/i)
Internal clock
generation
circuit
Multiplexer
SSCK
SSMR register
SSCRL register
SSCRH register
Transmit/receive
control circuit
SCS
SSER register
SSMR2 register
SSTDR register
SSO
Selector
SSTRSR register
SSI
SSRDR register
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
i = 4, 8, 16, 32, 64, 128, or 256
Figure 16.1
Block Diagram of Clock Synchronous Serial I/O with Chip Select
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 251 of 441
Data bus
SSSR register
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Control Register H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSCRH
Bit Symbol
Address
00B8h
Bit Name
Transfer clock rate select bits (1)
CKS1
CKS2
MSS
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Master/slave device select bit
(3)
Receive single stop bit
RSSTP
—
(b7)
(2)
RW
b2 b1 b0
0 0 0 : f1/256
0 0 1 : f1/128
0 1 0 : f1/64
0 1 1 : f1/32
1 0 0 : f1/16
1 0 1 : f1/8
1 1 0 : f1/4
1 1 1 : Do not set.
CKS0
—
(b4-b3)
After Reset
00h
Function
RW
RW
RW
—
0 : Operates as slave device
1 : Operates as master device
RW
0 : Maintains receive operation after
receiving 1 byte of data
1 : Completes receive operation after
receiving 1 byte of data
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. The set clock is used w hen the internal clock is selected.
2. The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device).
The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conflict error
occurs).
3. The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device).
Figure 16.2
SSCRH Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 252 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Control Register L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
00B9h
SSCRL
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b0)
When read, the content is 1.
SRES
—
(b3-b2)
SOLP
SOL
Clock synchronous
serial I/O w ith chip
select control part
reset bit
After Reset
01111101b
Function
When this bit is set to 1, the clock synchronous serial
I/O w ith chip select control block and SSTRSR register
are reset.
The values of the registers (1) in the clock synchronous
serial I/O w ith chip select register are maintained.
RW
—
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
SOL w rite protect bit(2) The output level can be changed by the SOL bit w hen
this bit is set to 0.
The SOLP bit remains unchanged even if 1 is w ritten to
it. When read, the content is 1.
RW
Serial data output value When read
setting bit
0 : The serial data output is set to “L”
1 : The serial data output is set to “H”
When w ritten(2,3)
0 : The data output is “L” after the serial data output
1 : The data output is “H” after the serial data output
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
2. The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When
w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
3. Do not w rite to the SOL bit during data transfer.
Figure 16.3
SSCRL Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 253 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
SSMR
Bit Symbol
Address
00BAh
Bit Name
Bits counter 2 to 0
After Reset
00011000b
Function
0 0 0 : 8 bits left
0 0 1 : 1 bit left
0 1 0 : 2 bits left
0 1 1 : 3 bits left
1 0 0 : 4 bits left
1 0 1 : 5 bits left
1 1 0 : 6 bits left
1 1 1 : 7 bits left
BC0
BC1
BC2
Set to 1.
When read, the content is 1.
—
(b3)
Reserved bit
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
(1)
RO
RO
RW
—
RW
SSCK clock polarity select bit(1)
0 : “H” w hen clock stops
1 : “L” w hen clock stops
RW
MSB first/LSB first select bit
0 : Transfers data MSB first
1 : Transfers data LSB first
RW
CPHS
MLS
RO
0 : Change data at odd edge
(Dow nload data at even edge)
1 : Change data at even edge
(Dow nload data at odd edge)
SSCK clock phase select bit
CPOS
RW
b2 b1 b0
NOTE:
1. Refer to 16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
and CPOS bits.
Figure 16.4
SSMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 254 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSER
Bit Symbol
CEIE
—
(b2-b1)
RE
TE
Address
After Reset
00BBh
00h
Bit Name
Function
Conflict error interrupt enable bit 0 : Disables conflict error interrupt request
1 : Enables conflict error interrupt request
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Receive enable bit
0 : Disables receive
1 : Enables receive
RW
Transmit enable bit
0 : Disables transmit
1 : Enables transmit
RW
Receive interrupt enable bit
0 : Disables receive data full and overrun
error interrupt request
1 : Enables receive data full and overrun
error interrupt request
RW
RIE
TEIE
Transmit end interrupt enable bit 0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
Transmit interrupt enable bit
TIE
Figure 16.5
SSER Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
Page 255 of 441
0 : Disables transmit data empty interrupt
request
1 : Enables transmit data empty interrupt
request
RW
RW
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSSR
Bit Symbol
CE
—
(b1)
ORER
—
(b4-b3)
RDRF
Address
00BCh
Bit Name
Conflict error flag(1)
After Reset
00h
Function
0 : No conflict errors generated
1 : Conflict errors generated(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Overrun error flag(1)
0 : No overrun errors generated
1 : Overrun errors generated(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Receive data register full
(1,4)
(1, 5)
Transmit end
TEND
Transmit data empty (1, 5, 6)
TDRE
RW
RW
—
RW
—
0 : No data in SSRDR register
1 : Data in SSRDR register
RW
0 : The TDRE bit is set to 0 w hen transmitting
the last bit of transmit data
1 : The TDRE bit is set to 1 w hen transmitting
the last bit of transmit data
RW
0 : Data is not transferred from registers SSTDR to
SSTRSR
1 : Data is transferred from registers SSTDR to
SSTRSR
RW
NOTES:
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.
2. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and_____
the MSS bit in the SSCRH register
is set to 1 (operates as master device), the CE bit is set
_____
to 1 if “L” is applied to the SCS pin input. Refer to 16.2.7 SCS Pin Control and Arbitration for more information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire
bus communication mode), the MSS bit in the
_____
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H” during
transfer, the CE bit is set to 1.
3. Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the
ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.
4.
5.
6.
7.
The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.
Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register.
The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled).
When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.6
SSSR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 256 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSMR2
Bit Symbol
SSUMS
Address
After Reset
00BDh
00h
Bit Name
Function
Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode
1 : Four-w ire bus communication mode
chip select mode select bit(1)
_____
CSOS
SOOS
SCKOS
SCS pin open drain output
select bit
Serial data pin open output drain
select bit(1)
0 : CMOS output
1 : N-channel open drain output
0 : CMOS output(5)
1 : N-channel open drain output
SSCK pin open drain output
select bit
0 : CMOS output
1 : N-channel open drain output
RW
RW
RW
RW
RW
_____
SCS pin select bits (2)
b5 b4
0 0 : Functions
0 1 : Functions
1 0 : Functions
1 1 : Functions
CSS0
CSS1
SCKS
SSCK pin select bit
(1, 4)
Bidirectional mode enable bit
BIDE
as
as
as
as
port
_____
SCS input pin
_____
SCS output pin(3)
_____
SCS output pin(3)
RW
RW
0 : Functions as port
1 : Functions as serial clock pin
RW
0 : Standard mode (communication using 2
pins of data input and data output)
1 : Bidirectional mode (communication using
1 pin of data input and data output)
RW
NOTES:
1. Refer to 16.2.2.1 Association betw een Data I/O Pins and SS Shift Register for information on combinations of
data I/O pins.
_____
2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 w hen the SSUMS
bit is set to 0 (clock synchronous
communication mode).
_____
3. This bit functions as the SCS input pin before starting transfer.
4. The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode).
5. The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0
(CMOS output).
Figure 16.7
SSMR2 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 257 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SS Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSTDR
Address
00BEh
After Reset
FFh
Function
RW
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from RW
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
SS Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSRDR
Address
00BFh
After Reset
FFh
Function
Store the receive data.(1)
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
RW
RO
NOTE:
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Figure 16.8
Registers SSTDR and SSRDR
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 258 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
00F8h
PMR
Bit Symbol
Bit Name
—
Reserved bit
(b0)
—
(b2-b1)
SSISEL
U1PINSEL
TXD1SEL
TXD1EN
IICSEL
After Reset
00h
Function
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
SSI pin select bit
0 : P3_3
1 : P1_6
TXD1 pin sw itch bit(1)
Set to 1 to use UART1.
Port/TXD1 pin sw itch bit(1)
0 : Programmable I/O port
1 : TXD1
RW
TXD1/RXD1 select bit(1)
0 : RXD1
1 : TXD1
RW
SSU / I2C bus pin sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN, and bits UART1SEL1 and UART1SEL0 in the
PINSR1 register.
PINSR1 Register
UART1SEL1,
UART1SEL0 bit
00b
01b
Pin Function
PMR Register
TXD1SEL bit
TXD1EN bit
P3_7(TXD1)
P3_7(RXD1)
P3_7(TXD1)
1
P4_5(RXD1)
×
×: 0 or 1
Figure 16.9
PMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
×
Page 259 of 441
1
0
×
R8C/28 Group, R8C/29 Group
16.2.1
16. Clock Synchronous Serial Interface
Transfer Clock
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
16.2.1.1
Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 260 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd
edge), and CPOS bit = 0 (“H” when clock stops)
SSCK
SSO, SSI
b1
b0
b2
b3
b4
b5
b6
b7
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
SCS
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
SCS
CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register
Figure 16.10
Association between Transfer Clock Polarity, Phase, and Transfer Data
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 261 of 441
R8C/28 Group, R8C/29 Group
16.2.2
16. Clock Synchronous Serial Interface
SS Shift Register (SSTRSR)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
16.2.2.1
Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 16.11 shows the Association between Data I/O Pins and SSTRSR Register.
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
• SSUMS = 0
(clock synchronous communication mode)
SSTRSR register
SSO
SSTRSR register
SSI
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
SSTRSR register
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 1 (bidirectional mode)
SSTRSR register
SSI
Figure 16.11
Association between Data I/O Pins and SSTRSR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 262 of 441
SSO
SSO
SSI
R8C/28 Group, R8C/29 Group
16.2.3
16. Clock Synchronous Serial Interface
Interrupt Requests
Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock
synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.
Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests.
Table 16.3
Clock Synchronous Serial I/O with Chip Select Interrupt Requests
Interrupt Request
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
Abbreviation
TXI
TEI
RXI
OEI
CEI
Generation Condition
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation conditions in Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request
is generated. Set each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 263 of 441
R8C/28 Group, R8C/29 Group
16.2.4
16. Clock Synchronous Serial Interface
Communication Modes and Pin Functions
Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication
mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 16.4 shows the Association between Communication Modes and I/O Pins.
Table 16.4
Association between Communication Modes and I/O Pins
Communication Mode
Clock synchronous
communication mode
Bit Setting
SSUMS
BIDE
MSS
TE
0
Disabled 0
0
1
4-wire bus
communication mode
1
0
0
1
4-wire bus
1
(bidirectional)
communication mode(2)
1
0
1
RE
1
SSI
Input
−(1)
Input
Input
1
0
0
1
1
1
0
0
1
1
1
0
Output
0
1
1
Output
Input
1
0
0
1
1
−(1)
Input
1
−(1)
Input
−(1)
Pin State
SSO
−(1)
Output
Output
Page 264 of 441
Input
−(1)
Input
Output
Output
Output
Output
Input
Output
Input
−(1)
Input
Input
−(1)
Input
Output
Output
Output
−(1)
Output
Input
Output
Input
0
−(1)
Output
Input
0
1
−(1)
Input
Output
1
0
−(1)
Output
Output
NOTES:
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
SSCK
Input
R8C/28 Group, R8C/29 Group
16.2.5
16. Clock Synchronous Serial Interface
Clock Synchronous Communication Mode
16.2.5.1
Initialization in Clock Synchronous Communication Mode
Figure 16.12 shows the Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit
in the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or
reception.
Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format.
Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR
register.
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 0
SSMR2 register
SSMR register
CPHS bit ← 0
CPOS bit ← 0
Set MLS bit
SSCRH register
SCKS bit ← 1
Set SOOS bit
SSMR2 register
SSCRH register
Set bits CKS0 to CKS2
Set RSSTP bit
SSSR register
SSER register
Set MSS bit
ORER bit ← 0(1)
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.12
Initialization in Clock Synchronous Communication Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 265 of 441
R8C/28 Group, R8C/29 Group
16.2.5.2
16. Clock Synchronous Serial Interface
Data Transmission
Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode). During data transmission, clock synchronous serial
I/O with chip select operates as described below.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and
data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized
with the input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)
and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at
odd numbers), and CPOS = 0 (“H” when clock stops)
SSCK
SSO
b0
b1
b7
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b1
b7
1 frame
TEI interrupt request
generation
0
TXI interrupt request generation
0
Processing
by program
Figure 16.13
b0
Write data to SSTDR register
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 266 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
Data
transmission
continues?
(2)
Yes
(2) Determine whether data transmission continues.
No
(3)
Read TEND bit in SSSR register
TEND = 1 ?
(3) When data transmission is completed, the TEND
bit is set to 1. Set the TEND bit to 0 and the TE bit
to 0 and complete transmit mode.
No
Yes
SSSR register
TEND bit ← 0(1)
SSER register
TE bit ← 0
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.14
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 267 of 441
R8C/28 Group, R8C/29 Group
16.2.5.3
16. Clock Synchronous Serial Interface
Data Reception
Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode).
During data reception, clock synchronous serial I/O with chip select operates as described below. When clock
synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and inputs
data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data synchronized
with the input clock.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 16.16 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at
even edges), and CPOS bit = 0 (“H” when clock stops)
SSCK
b7
b0
SSI
b0
b7
1
RSSTP bit in
SSCRH register
1
Processing
by program
Figure 16.15
b7
1 frame
1 frame
RDRF bit in
SSSR register
b0
0
RXI interrupt request
generation
RXI interrupt request
generation
RXI interrupt request
generation
0
Dummy read in
SSRDR register
Read data in SSRDR
register
Set RSSTP bit to 1
Read data in
SSRDR register
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 268 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Dummy read of SSRDR register
(2)
Last data
received?
Yes
(1) After setting each register in the clock synchronous
serial I/O with chip select register, a dummy read of
the SSRDR register is performed and the receive
operation is started.
(2) Determine whether it is the last 1 byte of data to be
received. If so, set to stop after the data is received.
No
Read ORER bit in SSSR register
Yes
(3) If a receive error occurs, perform error
(6) Processing after reading the ORER bit. Then set
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
ORER = 1 ?
(3)
No
Read RDRF bit in SSSR register
(4)
No
(4) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
RDRF = 1 ?
Yes
Read receive data in SSRDR register
(5)
SSCRH register
RSSTP bit ← 1
(5) Before the last 1 byte of data is received, set the
RSSTP bit to 1 and stop after the data is
received.
Read ORER bit in SSSR register
ORER = 1 ?
(6)
Yes
No
Read RDRF in SSSR register
No
RDRF = 1 ?
(7)
Yes
SSCRH register
RSSTP bit ← 0
SSER register
RE bit ← 0
(7) Confirm that the RDRF bit is set to 1. When the
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
Overrun
error
processing
Read receive data in SSRDR register
End
Figure 16.16
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 269 of 441
R8C/28 Group, R8C/29 Group
16.2.5.4
16. Clock Synchronous Serial Interface
Data Transmission/Reception
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if
transmit/receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of
the following:
- First set the RE bit to 0, and then set the TE bit to 0.
- Set bits TE and RE at the same time.
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the clock synchronous serial interface control unit and the SSTRSR register. Then, set the RE bit to
1.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 270 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
(2)
Read RDRF bit in SSSR register
No
RDRF = 1 ?
(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
Yes
Read receive data in SSRDR register
Data
transmission(2)
continues?
(3)
Yes
(3) Determine whether the data transmission
continues
No
(4)
Read TEND bit in SSSR register
TEND = 1 ?
(4) When the data transmission is completed, the
TEND bit in the SSSR register is set to 1.
No
Yes
(5)
(6)
SSSR register
TEND bit ← 0(1)
SSER register
RE bit ← 0
TE bit ← 0
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
receive mode.
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.17
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 271 of 441
R8C/28 Group, R8C/29 Group
16.2.6
16. Clock Synchronous Serial Interface
Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,
and a chip select line is used for communication. This mode includes bidirectional mode in which the data input
line and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and
the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS
Shift Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in
the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and
Data.
When this MCU is set as the master device, the chip select line controls output. When clock synchronous serial
I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master
device, the chip select line controls output of the SCS pin or controls output of a general port according to the
setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets
the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is
performed MSB-first.
16.2.6.1
Initialization in 4-Wire Bus Communication Mode
Figure 16.18 shows the Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the clock synchronous serial I/O with chip select.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 272 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 1
SSMR2 register
(1)
SSMR register
Set bits CPHS and CPOS
MLS bits ← 0
SSCRH register
SSMR2 register
(2)
SSCRH register
Set MSS bit
SCKS bit ← 1
Set bits SOOS, CSS0 to
CSS1, and BIDE
(2) Set the BIDE bit to 1 in bidirectional mode and
set the I/O of the SCS pin by bits CSS0 and
CSS1.
Set bits CKS0 to CKS2
Set RSSTP bit
ORER bit ← 0(1)
SSSR register
SSER register
(1) The MLS bit is set to 0 for MSB-first transfer.
The clock polarity and phase are set by bits
CPHS and CPOS.
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.18
Initialization in 4-Wire Bus Communication Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 273 of 441
R8C/28 Group, R8C/29 Group
16.2.6.2
16. Clock Synchronous Serial Interface
Data Transmission
Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous
serial I/O with chip select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”.
When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the
TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the
data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from
registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI
interrupt request is generated.
After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR
to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1,
TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set
to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests
enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is
held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the
SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in
high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.14
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 274 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
SSO
b6
b7
b7
b0
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request
is generated
TXI interrupt request
is generated
0
Data write to SSTDR register
Processing
by program
• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
b7
SSO
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
b7
b6
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request
is generated
TXI interrupt request
is generated
0
Processing
by program
Data write to SSTDR register
CPHS, CPOS: Bits in SSMR register
Figure 16.19
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 275 of 441
R8C/28 Group, R8C/29 Group
16.2.6.3
16. Clock Synchronous Serial Interface
Data Reception
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip
select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF
bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 16.20 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some
point during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.16
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 276 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
SSI
b0
b7
b7
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
b7
b0
b0
1 frame
0
RXI interrupt request
is generated
RXI interrupt request
is generated
0
Data read in SSRDR
register
Dummy read in
SSRDR register
Processing
by program
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
b7
SSI
b0
b7
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
Processing
by program
b0
b7
b0
1 frame
0
RXI interrupt request
is generated
RXI interrupt request
is generated
0
Dummy read in
SSRDR register
Data read in SSRDR
register
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
CPHS and CPOS: Bit in SSMR register
Figure 16.20
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 277 of 441
R8C/28 Group, R8C/29 Group
16.2.7
16. Clock Synchronous Serial Interface
SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If clock synchronous
serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit
in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.21 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
SCS input
Internal SCS
(synchronization)
MSS bit in
SSCRH register
1
0
Transfer start
Data write to
SSTDR register
CE
High-impedance
SCS output
Maximum time of SCS internal
synchronization
During arbitration detection
Figure 16.21
Arbitration Check Timing
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 278 of 441
R8C/28 Group, R8C/29 Group
16.2.8
16. Clock Synchronous Serial Interface
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 279 of 441
R8C/28 Group, R8C/29 Group
16.3
16. Clock Synchronous Serial Interface
I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I2C bus.
Table 16.5 lists the Specifications of I2C bus Interface, Figure 16.22 shows a Block Diagram of I2C bus Interface,
and Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.30
show the registers associated with the I2C bus interface.
* I2C bus is a trademark of Koninklijke Philips Electronics N. V.
Table 16.5
Specifications of I2C bus Interface
Item
Specification
2
Communication formats • I C bus format
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
- Start/stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
I/O pins
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks
• When the MST bit in the ICCR1 register is set to 0
The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
2
Interrupt sources
• I C bus format ................................ 6 sources(1)
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
• Clock synchronous serial format .... 4 sources(1)
Transmit data empty, transmit ends, receive data full and overrun error
2
Select functions
• I C bus format
- Selectable output level for acknowledge signal during reception
• Clock synchronous serial format
- MSB-first or LSB-first selectable as data transfer direction
NOTE:
1. All sources use one interrupt vector for I2C bus interface.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 280 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
f1
Transfer clock
generation
circuit
SCL
Output
control
ICCR1 register
Transmit/receive
control circuit
Noise
canceller
ICCR2 register
ICMR register
ICDRT register
SAR register
Output
control
ICDRS register
Noise
canceller
Address comparison
circuit
Data bus
SDA
ICDRR register
Bus state judgment
circuit
Arbitration judgment
circuit
ICSR register
ICIER register
Interrupt generation
circuit
Interrupt request
(TXI, TEI, RXI, STPI, NAKI)
Figure 16.22
Block Diagram of I2C bus Interface
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 281 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
VCC
VCC
SCL
SCL
SDA
SDA
SCL input
SCL output
SDA input
SDA output
SCL
(Master)
SCL
SCL input
SCL input
SCL output
SCL output
SDA
SDA input
SDA output
SDA output
(Slave 1)
Figure 16.23
SDA
SDA input
(Slave 2)
External Circuit Connection Example of Pins SCL and SDA
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 282 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICCR1
Bit Symbol
CKS0
CKS1
CKS2
CKS3
TRS
Address
00B8h
Bit Name
Transmit clock select bits 3 to b3 b2 b1 b0
0 0 0 0 : f1/28
0(1)
0 0 0 1 : f1/40
0 0 1 0 : f1/48
0 0 1 1 : f1/64
0 1 0 0 : f1/80
0 1 0 1 : f1/100
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
1 1 1 0 : f1/224
1 1 1 1 : f1/256
Transfer/receive select
bit(2, 3, 6)
Master/slave select bit(5, 6)
MST
Receive disable bit
RCVD
IIC bus interface enable bit
ICE
After Reset
00h
Function
RW
RW
RW
RW
RW
b5 b4
0 0 : Slave Receive Mode(4)
0 1 : Slave Transmit Mode
1 0 : Master Receive Mode
1 1 : Master Transmit Mode
After reading the ICDRR register w hile the TRS bit
is set to 0
0 : Maintains the next receive operation
1 : Disables the next receive operation
0 : This module is halted
(Pins SCL and SDA are set to port function)
1 : This module is enabled for transfer
operations
(Pins SCL and SDA are bus drive state)
RW
RW
RW
RW
NOTES:
1. Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Exam ples for the
transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode. The time is 10Tcyc
w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
2. Rew rite the TRS bit betw een transfer frames.
3. When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
4. In master mode w ith the I2C bus format, w hen arbitration is lost, bits MST and TRS are set to 0 and the IIC enters
slave receive mode.
5. When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit is set to 0
and the IIC enters slave receive mode.
6. In multimaster operation use the MOV instruction to set bits TRS and MST.
Figure 16.24
ICCR1 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 283 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
00B9h
ICCR2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b0)
When read, the content is 1.
IIC control part reset bit
IICRST
—
(b2)
SCLO
SDAOP
SDAO
SCP
After Reset
01111101b
Function
When hang-up occurs due to communication failure
during I2C bus interface operation, w rite 1, to reset the
control block of the I2C bus interface w ithout setting
ports or initializing registers.
SCL monitor flag
SDAO w rite protect bit
RW
—
0 : SCL pin is set to “L”
1 : SCL pin is set to “H”
RO
(1)
When rew rite to SDAO bit, w rite 0 simultaneously.
When read, the content is 1.
SDA output value control When read
bit
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w ritten(1,2)
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
(“H” output via external pull-up resistor)
RW
RW
Start/stop condition
generation disable bit
When w riting to the to BBSY bit, w rite 0
simultaneously.(3)
When read, the content is 1.
Writing 1 is invalid.
RW
Bus busy bit(4)
When read
0 : Bus is in released state
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
1 : Bus is in occupied state
(SDA signal changes from “H” to “L” w hile SCL
signal is in “H” state)
When w ritten(3)
0 : Generates stop condition
1 : Generates start condition
RW
NOTES:
1. When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
2. Do not w rite during a transfer operation.
3. This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
4. This bit is disabled w hen the clock synchronous serial format is used.
ICCR2 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
BBSY
Figure 16.25
RW
Page 284 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
IIC bus Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ICMR
Bit Symbol
Address
00BAh
Bit Name
Bits counter 2 to 0
After Reset
00011000b
Function
I2C bus format (remaining transfer bit count w hen
read out and data bit count of next transfer w hen
w ritten).(1,2)
RW
b2 b1 b0
0 0 0 : 9 bits (3)
0 0 1 : 2 bits
0 1 0 : 3 bits
0 1 1 : 4 bits
1 0 0 : 5 bits
1 0 1 : 6 bits
1 1 0 : 7 bits
1 1 1 : 8 bits
Clock synchronous serial format (w hen read, the
remaining transfer bit count and w hen w ritten
000b).
BC0
BC1
RW
RW
b2 b1 b0
0 0 0 : 8 bits
0 0 1 : 1 bit
0 1 0 : 2 bits
0 1 1 : 3 bits
1 0 0 : 4 bits
1 0 1 : 5 bits
1 1 0 : 6 bits
1 1 1 : 7 bits
BC2
BC w rite protect bit
BCWP
When rew riting bits BC0 to BC2, w rite 0
simultaneously.(2,4)
When read, the content is 1.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
(b5)
Reserved bit
Set to 0.
Wait insertion bit(5)
0 : No w ait
(Transfer data and acknow ledge bit
consecutively)
1 : Wait
(After the clock falls for the final
data bit, “L” period is extended for tw o
transfer clocks cycles)
RW
0 : Data transfer w ith MSB-first(6)
1 : Data transfer w ith LSB-first
RW
MLS
MSB-first/LSB-first select
bit
NOTES:
1. Rew rite betw een transfer frames. When w riting values other than 000b, w rite w hen the SCL signal is “L”.
2. When w riting to bits BC0 to BC2, w rite 0 to the BCWP bit using the MOV instruction.
3. After data including the acknow ledge bit is transferred, these bits are automatically set to 000b. When the start
condition is detected, these bits are automatically set to 000b.
4. Do not rew rite w hen the clock synchronous serial format is used.
5. The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C
bus format or w hen the clock synchronous serial format is used.
6. Set to 0 w hen the I2C bus format is used.
ICMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
—
(b4)
WAIT
Figure 16.26
RW
Page 285 of 441
—
RW
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
IIC bus Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICIER
Bit Symbol
ACKBT
Address
00BBh
Bit Name
Transmit acknow ledge
select bit
After Reset
00h
Function
0 : 0 is transmitted as acknow ledge bit in
receive mode.
1 : 1 is transmitted as acknow ledge bit in
receive mode.
Receive acknow ledge bit
0 : Acknow ledge bit received from
receive device in transmit mode is set to 0.
1 : Acknow ledge bit received from
receive device in transmit mode is set to 1.
ACKBR
ACKE
Acknow ledge bit judgment 0 : Value of receive acknow ledge bit is ignored
select bit
and continuous transfer is performed.
1 : When receive acknow ledge bit is set to 1,
continuous transfer is halted.
RW
RW
RO
RW
Stop condition detection
interrupt enable bit
0 : Disables stop condition detection interrupt
request
1 : Enables stop condition detection interrupt
request(2)
RW
NACK receive interrupt
enable bit
0 : Disables NACK receive interrupt request and
arbitration lost/overrun error interrupt request
1 : Enables NACK receive interrupt request and
arbitration lost/overrun error interrupt request(1)
RW
Receive interrupt enable
bit
0 : Disables receive data full and overrun
error interrupt request
1 : Enables receive data full and overrun
error interrupt request(1)
RW
TEIE
Transmit end interrupt
enable bit
0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
RW
TIE
Transmit interrupt enable
bit
0 : Disables transmit data empty interrupt request
1 : Enables transmit data empty interrupt request
RW
STIE
NAKIE
RIE
NOTES:
1. An overrun error interrupt request is generated w hen the clock synchronous format is used.
2. Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
Figure 16.27
ICIER Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 286 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
IIC bus Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICSR
Bit Symbol
ADZ
AAS
Address
00BCh
Bit Name
General call address
recognition flag(1,2)
Slave address recognition This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
flag(1)
SAR register in slave receive mode. (Detect the
slave address and generate call address)
RDRF
RW
RW
RW
When the stop condition is detected after the frame
is transferred, this flag is set to 1
RW
No acknow ledge detection When no acknow ledge is detected from the receive
flag(1,4)
device after transmission, this flag is set to 1
RW
Receive data register
full(1,5)
When receive data is transferred from in registers
ICDRS to ICDRR , this flag is set to 1
RW
Transmit end(1,6)
When the 9th clock cycle of the SCL signal in the I2C
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
RW
In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
and the ICDRT register is empty
• When setting the TRS bit in the ICCR1
register to 1 (transmit mode)
• When generating the start condition
(including retransmit)
• When changing from slave receive mode to
slave transmit mode
RW
AL
NACKF
RW
When the I2C bus format is used, this flag indicates
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1.(3)
• When the internal SDA signal and SDA pin
level do not match at the rise of the SCL signal
in master transmit mode
• When the start condition is detected and the
SDA pin is held “H” in master transmit/receive mode
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
• When the last bit of the next data item is
received w hile the RDRF bit is set to 1
Arbitration lost
flag/overrun error flag(1)
STOP
After Reset
0000X000b
Function
When the general call address is detected, this flag
is set to 1.
Stop condition detection
flag(1)
TEND
Transmit data empty (1,6)
TDRE
NOTES:
1. Each bit is set to 0 by reading 1 before w riting 0.
2. This flag is enabled in slave receive mode of the I2C bus format.
3. When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface
monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the
bus is occupied by another master.
4. The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is
set to 1, transfer is halted).
5. The RDRF bit is set to 0 w hen reading data from the ICDRR register.
6. Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.
7. When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.28
ICSR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 287 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Slave Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SAR
Bit Symbol
FS
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
Address
00BDh
Bit Name
Format select bit
Slave address 6 to 0
After Reset
00h
Function
RW
0 : I2C bus format
1 : Clock synchronous serial format
RW
Set an address different from that of the other
slave devices w hich are connected to the I2C
bus. When the 7 high-order bits of the first
frame transmitted after the starting condition
match bits SVA0 to SVA6 in slave mode of the
I2C bus format, the MCU operates as a slave
device.
RW
RW
RW
RW
RW
RW
RW
IIC bus Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRT
Address
00BEh
After Reset
FFh
Function
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
RW
RW
IIC bus Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRR
Address
00BFh
After Reset
FFh
Function
Store receive data
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
RW
RO
IIC bus Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRS
Function
This register is used to transmit and receive data.
The transmit data is transferred from registers ICRDT to the ICDRS and data is transmitted
from the SDA pin w hen transmitting.
After 1 byte of data received, data is transferred from registers ICDRS to ICDRR w hile
receiving.
Figure 16.29
Registers SAR, ICDRT, ICDRR, and ICDRS
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 288 of 441
RW
—
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
00F8h
PMR
Bit Symbol
Bit Name
—
Reserved bit
(b0)
—
(b2-b1)
SSISEL
U1PINSEL
TXD1SEL
TXD1EN
IICSEL
After Reset
00h
Function
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
SSI pin select bit
0 : P3_3
1 : P1_6
TXD1 pin sw itch bit(1)
Set to 1 to use UART1.
Port/TXD1 pin sw itch bit(1)
0 : Programmable I/O port
1 : TXD1
RW
TXD1/RXD1 select bit(1)
0 : RXD1
1 : TXD1
RW
SSU / I2C bus pin sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
RW
RW
RW
NOTE:
1. The UART1 pins can be selected by using bits TXD1SEL and TXD1EN, and bits UART1SEL1 and UART1SEL0 in the
PINSR1 register.
PINSR1 Register
UART1SEL1,
UART1SEL0 bit
00b
01b
Pin Function
PMR Register
TXD1SEL bit
TXD1EN bit
P3_7(TXD1)
P3_7(RXD1)
P3_7(TXD1)
1
P4_5(RXD1)
×
×: 0 or 1
Figure 16.30
PMR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
×
Page 289 of 441
1
0
×
R8C/28 Group, R8C/29 Group
16.3.1
16. Clock Synchronous Serial Interface
Transfer Clock
When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL
pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits
CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.
Table 16.6 lists the Transfer Rate Examples.
Table 16.6
Transfer Rate Examples
ICCR1 Register
Transfer
CKS3 CKS2 CKS1 CKS0 Clock f1 = 5 MHz
0
0
0
0
f1/28
179 kHz
1
f1/40
125 kHz
1
0
f1/48
104 kHz
1
f1/64
78.1 kHz
1
0
0
f1/80
62.5 kHz
1
f1/100
50.0 kHz
1
0
f1/112
44.6 kHz
1
f1/128
39.1 kHz
1
0
0
0
f1/56
89.3 kHz
1
f1/80
62.5 kHz
1
0
f1/96
52.1 kHz
1
f1/128
39.1 kHz
1
0
0
f1/160
31.3 kHz
1
f1/200
25.0 kHz
1
0
f1/224
22.3 kHz
1
f1/256
19.5 kHz
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 290 of 441
f1 = 8 MHz
286 kHz
200 kHz
167 kHz
125 kHz
100 kHz
80.0 kHz
71.4 kHz
62.5 kHz
143 kHz
100 kHz
83.3 kHz
62.5 kHz
50.0 kHz
40.0 kHz
35.7 kHz
31.3 kHz
Transfer Rate
f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz
357 kHz
571 kHz
714 kHz
250 kHz
400 kHz
500 kHz
208 kHz
333 kHz
417 kHz
156 kHz
250 kHz
313 kHz
125 kHz
200 kHz
250 kHz
100 kHz
160 kHz
200 kHz
89.3 kHz
143 kHz
179 kHz
78.1 kHz
125 kHz
156 kHz
179 kHz
286 kHz
357 kHz
125 kHz
200 kHz
250 kHz
104 kHz
167 kHz
208 kHz
78.1 kHz
125 kHz
156 kHz
62.5 kHz
100 kHz
125 kHz
50.0 kHz
80.0 kHz
100 kHz
44.6 kHz
71.4 kHz
89.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
R8C/28 Group, R8C/29 Group
16.3.2
16. Clock Synchronous Serial Interface
Interrupt Requests
I2 C
The
bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests
when the clock synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I2C bus Interface.
Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source
bit by bit is necessary.
Table 16.7
Interrupt Requests of I2C bus Interface
Interrupt Request
Generation Condition
Format
I2C bus
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
TXI
TEI
RXI
STPI
NAKI
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Clock
Synchronous
Serial
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When the generation conditions listed in Table 16.7 are met, an I2C bus interface interrupt request is generated.
Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, bits TDRE and
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 291 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
I2C bus Interface Mode
16.3.3
I2C bus Format
16.3.3.1
Setting the FS bit in the SAR register to 0 enables communication in I2C bus format.
Figure 16.31 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of
8 bits.
(1) I2C bus format
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
Transfer bit count (n = 1 to 8)
1
m
Transfer frame count (m = from 1)
(b) I2C bus format (when start condition is retransmitted, FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
1
m1
m2
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
(2) I2C bus timing
SDA
SCL
1 to 7
S
SLA
8
R/W
9
1 to 7
A
8
DATA
9
1 to 7
A
8
DATA
9
A
Explanation of symbols
S
: Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A
: Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit / receive data
P
: Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
Figure 16.31
I2C bus Format and Bus Timing
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 292 of 441
P
R8C/28 Group, R8C/29 Group
16.3.3.2
16. Clock Synchronous Serial Interface
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.32 and 16.33 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1
(transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to
CKS3 in the ICCR1 register (initial setting).
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the
ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit
and 0 to the SCP bit by the MOV instruction.
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers
ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W
are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred
from registers ICDRT to ICDRS, and the TDRE bit is set to 1 again.
(4) When transmission of 1 byte of data is completed while the TDRE bit is set to 1, the TEND bit in the
ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER
register, and confirm that the slave is selected. Write the 2nd byte of data to the ICDRT register. Since
the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The
stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV
instruction. The SCL signal is held “L” until data is available and the stop condition is generated.
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is
set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to
1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive
acknowledge bit is set to 1, transfer is halted). Then generate the stop condition before setting bits
TEND and NACKF to 0.
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 293 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
SCL
(master output)
1
2
3
4
5
6
7
8
SDA
(master output)
b7
b6
b5
b4
b3
b2
b1
b0
Slave address
9
2
b7
b6
R/W
SDA
(slave output)
TDRE bit in
ICSR register
1
A
1
0
TEND bit in
ICSR register
1
0
ICDRT register
Address + R/W
ICDRS register
(2) Instruction of
start condition
generation
Processing
by program
Figure 16.32
Data 1
Address + R/W
(3) Data write to ICDRT
register (1st byte)
Data 2
Data 1
(5) Data write to ICDRT
register (3rd byte)
(4) Data write to ICDRT
register (2nd byte)
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)
SCL
(master output)
9
SDA
(master output)
SDA
(slave output)
TDRE bit in
ICSR register
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
A
9
A/A
1
0
TEND bit in
ICSR register
1
0
ICDRT register
Data n
ICDRS register
Processing
by program
Figure 16.33
Data n
(3) Data write to ICDRT
register
(6) Generate stop condition and
set TEND bit to 0
(7) Set to slave receive mode
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 294 of 441
R8C/28 Group, R8C/29 Group
16.3.3.3
16. Clock Synchronous Serial Interface
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 16.34 and 16.35 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR
register to 0.
(2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive
clock is output in synchronization with the internal clock and data is received. The master device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle of the receive clock.
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the
RDRF bit is set to 0 simultaneously.
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set
to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables
the next receive operation) before reading the ICDRR register, stop condition generation is enabled after
the next receive operation.
(6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0
(maintain the following receive operation).
(8) Return to slave receive mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 295 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Master transmit mode
SCL
(master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
1
A
SDA
(slave output)
TDRE bit in
ICSR register
9
A
b7
b6
b5
b4
b3
b2
b1
b7
b0
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
RDRF bit in
ICSR register
1
0
1
0
ICDRS register
Data 1
ICDRR register
Processing
by program
Figure 16.34
Data 1
(1) Set TEND and TRS bits to 0 before
setting TDRE bits to 0
(2) Read ICDRR register
(3) Read ICDRR register
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 296 of 441
R8C/28 Group, R8C/29 Group
SCL
(master output)
9
SDA
(master output)
A
1
RCVD bit in
ICCR1 register
2
3
4
5
6
7
8
9
A/A
SDA
(slave output)
RDRF bit in
ICSR register
16. Clock Synchronous Serial Interface
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
Data n-1
ICDRS register
Data n
Data n-1
ICDRR register
Processing
by program
(5) Set RCVD bit to 1 before
reading ICDRR register
Data n
(6) Stop condition
generation
(7) Read ICDRR register before
setting RCVD bit to 0
(8) Set to slave receive mode
Figure 16.35
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 297 of 441
R8C/28 Group, R8C/29 Group
16.3.3.4
16. Clock Synchronous Serial Interface
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.36 and 16.37 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
register to end the process.
(5) Set the TDRE bit to 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 298 of 441
R8C/28 Group, R8C/29 Group
Slave receive mode
SCL
(master output)
16. Clock Synchronous Serial Interface
Slave transmit mode
9
1
2
3
4
5
6
7
8
1
9
SDA
(master output)
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
A
b6
b7
b5
b4
b3
b2
b1
b7
b0
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
1
0
ICDRT register
Data 1
ICDRS register
Data 3
Data 2
Data 1
Data 2
ICDRR register
(1) Data write to ICDRT
register (data 1)
Processing
by program
Figure 16.36
(2) Data write to ICDRT
register (data 2)
(2) Data write to ICDRT
register (data 3)
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 299 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Slave receive
mode
Slave transmit mode
SCL
(master output)
9
SDA
(master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
b7
b6
b5
b4
b3
b2
b1
b0
1
0
TEND bit in
ICSR register
1
0
TRS bit in
ICCR1 register
1
0
ICDRT register
Data n
Data n
ICDRS register
ICDRR register
Processing
by program
Figure 16.37
(3) Set the TEND bit to 0
(4) Dummy read of ICDRR register
after setting TRS bit to 0
(5) Set TDRE bit to 0
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 300 of 441
R8C/28 Group, R8C/29 Group
16.3.3.5
16. Clock Synchronous Serial Interface
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.38 and 16.39 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the
read data is unnecessary because it indicates the slave address and R/W).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the
RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of
the acknowledge signal returned to the master device before reading the ICDRR register takes affect
from the following transfer frame.
(4) Reading the last byte is performed by reading the ICDRR register in like manner.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 301 of 441
R8C/28 Group, R8C/29 Group
SCL
(master output)
16. Clock Synchronous Serial Interface
9
1
SDA
(master output)
2
3
b6
b7
4
5
b4
b5
6
7
b2
b3
8
9
b7
b0
b1
1
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Processing
by program
Figure 16.38
Data 1
(2) Read ICDRR register
(2) Dummy read of ICDRR register
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1)
SCL
(master output)
9
SDA
(master output)
1
b7
3
2
b6
b5
4
5
b4
b3
6
b2
7
b1
8
9
b0
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Processing
by program
Figure 16.39
Data 1
(3) Set ACKBT bit to 1
(3) Read ICDRR register
(4) Read ICDRR register
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 302 of 441
R8C/28 Group, R8C/29 Group
16.3.4
16. Clock Synchronous Serial Interface
Clock Synchronous Serial Mode
16.3.4.1
Clock Synchronous Serial Format
Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication.
Figure 16.40 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during transfer standby.
SCL
SDA
Figure 16.40
b0
b1
b2
b3
b4
b5
Transfer Format of Clock Synchronous Serial Format
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 303 of 441
b6
b7
R8C/28 Group, R8C/29 Group
16.3.4.2
16. Clock Synchronous Serial Interface
Transmit Operation
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 16.41 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
ICCR1 register to 1.
(3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous
transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When
switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SCL
1
SDA
(output)
TRS bit in
ICCR1 register
TDRE bit in
ICSR register
b0
7
2
b1
b6
8
b7
1
b0
7
b6
8
1
b7
b0
1
0
1
0
ICDRT register
ICDRS register
Processing
by program
Data 2
Data 1
Data 1
(3) Data write to
ICDRT register
Data 3
Data 3
Data 2
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(2) Set TRS bit to 1
Figure 16.41
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 304 of 441
R8C/28 Group, R8C/29 Group
16.3.4.3
16. Clock Synchronous Serial Interface
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.42 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
output.
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
SCL
1
SDA
(input)
MST bit in
ICCR1 register
TRS bit in
ICCR1 register
b0
2
b1
7
b6
8
b7
1
b0
7
b6
8
1
b7
2
b0
1
0
1
0
RDRF bit in
ICSR register
1
0
Data 1
ICDRS register
Data 1
ICDRR register
Processing
by program
Figure 16.42
Data 2
(2) Set MST bit to 1
(when transfer clock is output)
(3) Read ICDRR register
Data 3
Data 2
(3) Read ICDRR register
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 305 of 441
R8C/28 Group, R8C/29 Group
16.3.5
16. Clock Synchronous Serial Interface
Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.43 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
C
SCL or SDA
input signal
D
C
Q
D
Latch
Period of f1
f1 (sampling clock)
Figure 16.43
Block Diagram of Noise Canceller
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 306 of 441
Q
Latch
Match
detection
circuit
Internal SCL
or SDA signal
R8C/28 Group, R8C/29 Group
16.3.6
16. Clock Synchronous Serial Interface
Bit Synchronization Circuit
When setting the I2C bus interface to master mode, the high-level period may become shorter in the following
two cases:
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.44 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
Reference clock of
SCL monitor timing
SCL
VIH
Internal SCL
Figure 16.44
Timing of Bit Synchronization Circuit
Table 16.8
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register
CKS3
0
1
Time for Monitoring SCL
CKS2
0
1
0
1
1Tcyc = 1/f1(s)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 307 of 441
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
R8C/28 Group, R8C/29 Group
16.3.7
16. Clock Synchronous Serial Interface
Examples of Register Setting
Figures 16.45 to 16.48 show Examples of Register Setting When Using I2C bus interface.
Start
• Set the STOP bit in the ICSR register to 0
• Set the IICSEL bit in the PMR register to 1
Initial setting
Read BBSY bit in ICCR2 register
(1) Judge the state of the SCL and SDA lines
No
(1)
(2) Set to master transmit mode
BBSY = 0 ?
(3) Generate the start condition
Yes
ICCR1 register
TRS bit ← 1
MST bit ← 1
(2)
ICCR2 register
SCP bit ← 0
BBSY bit ← 1
(3)
(4) Set the transmit data of the 1st byte
(slave address + R/W)
(5) Wait for 1 byte to be transmitted
Write transmit data to ICDRT register
(4)
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty
Read TEND bit in ICSR register
(9) Set the transmit data of the last byte
No
(5)
TEND = 1 ?
(10) Wait for end of transmission of the last byte
(11) Set the TEND bit to 0
Yes
Read ACKBR bit in ICIER register
(12) Set the STOP bit to 0
(13) Generate the stop condition
ACKBR = 0 ?
No
(6)
(15) Set to slave receive mode
Set the TDRE bit to 0
Yes
Transmit
mode ?
(14) Wait until the stop condition is generated
No
Master receive
mode
Yes
Write transmit data to ICDRT register
(7)
Read TDRE bit in ICSR register
No
(8)
TDRE = 1 ?
Yes
No
Last byte ?
(9)
Yes
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
(10)
TEND = 1 ?
Yes
ICSR register
TEND bit ← 0
(11)
ICSR register
STOP bit ← 0
(12)
ICCR2 register
SCP bit ← 0
BBSY bit ← 0
(13)
Read STOP bit in ICSR register
No
(14)
STOP = 1 ?
Yes
ICCR1 register
TRS bit ← 0
MST bit ← 0
(15)
ICSR register
TDRE bit ← 0
End
Figure 16.45
Example of Register Setting in Master Transmit Mode (I2C bus Interface Mode).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 308 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Master receive mode
TEND bit ← 0
ICSR register
TRS bit ← 0
ICCR1 register
ICSR register
TDRE bit ← 0
ICIER register
ACKBT bit ← 0
Dummy read in ICDRR register
(1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0(1,2)
(1)
(2) Set the ACKBT bit to the transmit device(1)
(3) Dummy read the ICDRR register(1)
(2)
(3)
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable
continuous receive operation (RCVD = 1)(2)
Read RDRF bit in ICSR register
No
(4)
(8) Read the receive data of (last byte - 1)
RDRF = 1 ?
(9) Wait until the last byte is received
Yes
(10) Set the STOP bit to 0
Yes
Last receive
-1?
(5)
(12) Wait until the stop condition is generated
No
Read ICDRR register
(11) Generate the stop condition
(6)
(13) Read the receive data of the last byte
(14) Set the RCVD bit to 0
ACKBT bit ← 1
ICIER register
(15) Set to slave receive mode
(7)
ICCR1 register
RCVD bit ← 1
Read ICDRR register
(8)
Read RDRF bit in ICSR register
No
(9)
RDRF = 1 ?
Yes
STOP bit ← 0
ICSR register
SCP bit ← 0
BBSY bit ← 0
ICCR2 register
(10)
(11)
Read STOP bit in ICSR register
(12)
No
STOP = 1 ?
Yes
Read ICDRR register
(13)
ICCR1 register
RCVD bit ← 0
(14)
ICCR1 register
MST bit ← 0
(15)
End
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.46
Example of Register Setting in Master Receive Mode (I2C bus Interface Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 309 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Slave transmit mode
AAS bit ← 0
ICSR register
(1) Set the AAS bit to 0
(1)
(2) Set the transmit data (except the last byte)
Write transmit data to ICDRT register
(2)
(3) Wait until the ICRDT register is empty
(4) Set the transmit data of the last byte
Read TDRE bit in ICSR register
(5) Wait until the last byte is transmitted
No
TDRE = 1 ?
(3)
(7) Set to slave receive mode
Yes
No
(6) Set the TEND bit to 0
(8) Dummy read the ICDRR register to release the
SCL signal
Last byte ?
(4)
Yes
(9) Set the TDRE bit to 0
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
TEND = 1 ?
ICSR register
ICCR1 register
Yes
TEND bit ← 0
(6)
TRS bit ← 0
(7)
Dummy read in ICDRR register
ICSR register
(5)
TDRE bit ← 0
(8)
(9)
End
Figure 16.47
Example of Register Setting in Slave Transmit Mode (I2C bus Interface Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 310 of 441
R8C/28 Group, R8C/29 Group
16. Clock Synchronous Serial Interface
Slave receive mode
AAS bit ← 0
(1)
ICIER register ACKBT bit ← 0
(2)
ICSR register
(1) Set the AAS bit to 0 (1)
(2) Set the ACKBT bit to the transmit device
(3) Dummy read the ICDRR register
Dummy read ICDRR register
(3)
(4) Wait until 1 byte is received
(5) Judge (last receive - 1)
Read RDRF bit in ICSR register
(6) Read the receive data
No
(4)
(7) Set the ACKBT bit of the last byte(1)
RDRF = 1 ?
(8) Read the receive data of (last byte - 1)
Yes
(9) Wait until the last byte is received
Last receive
-1?
Yes
(5)
(10) Read the receive data of the last byte
No
Read ICDRR register
(6)
ACKBT bit ← 1
(7)
Read ICDRR register
(8)
ICIER register
Read RDRF bit in ICSR register
No
(9)
RDRF = 1 ?
Yes
Read ICDRR register
(10)
End
NOTE:
1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.48
Example of Register Setting in Slave Receive Mode (I2C bus Interface Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 311 of 441
R8C/28 Group, R8C/29 Group
16.3.8
16. Clock Synchronous Serial Interface
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
16.3.8.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
16.3.8.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 312 of 441
R8C/28 Group, R8C/29 Group
17. Hardware LIN
17. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1
Features
The hardware LIN has the features listed below.
Figure 17.1 shows a Block Diagram of Hardware LIN.
Master mode
• Generates Synch Break
• Detects bus collision
Slave mode
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision
NOTE:
1. The WakeUp function is detected by INT1.
Hardware LIN
Synch Field
control
circuit
RXD0 pin
Timer RA
TIOSEL = 0
RXD data
LSTART bit
SBE bit
LINE bit
RXD0 input
control
circuit
Timer RA
underflow signal
TIOSEL = 1
Bus collision
detection
circuit
Timer RA
interrupt
Interrupt
control
circuit
UART0
BCIE, SBIE,
and SFIE bits
UART0 transfer clock
UART0 TE bit
Timer RA output pulse
MST bit
UART0 TXD data
TXD0 pin
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
Figure 17.1
Block Diagram of Hardware LIN
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 313 of 441
R8C/28 Group, R8C/29 Group
17.2
17. Hardware LIN
Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 17.1.
Table 17.1
Pin Configuration
Name
Abbreviation
Input/Output
Receive data input
RXD0
Input
Transmit data output
TXD0
Output
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 314 of 441
Function
Receive data input pin of the hardware LIN
Transmit data output pin of the hardware LIN
R8C/28 Group, R8C/29 Group
17.3
17. Hardware LIN
Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 17.2 and 17.3.
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
LIN Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINCR
Bit Symbol
SFIE
Address
0106h
Bit Name
Synch Field measurementcompleted interrupt enable bit
After Reset
00h
Function
0 : Disables Synch Field measurementcompleted interrupt
1 : Enables Synch Field measurementcompleted interrupt
RW
RW
SBIE
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt
enable bit
1 : Enables Synch Break detection interrupt
RW
BCIE
Bus collision detection interrupt 0 : Disables bus collision detection interrupt
enable bit
1 : Enables bus collision detection interrupt
RW
RXDSF
LSTART
SBE
RXD0 input status flag
RO
Synch Break detection start bit(1) When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
When read, the content is 0.
RW
RXD0 input unmasking timing
0 : Unmasked after Synch Break is detected
select bit (effective only in slave 1 : Unmasked after Synch Field measurement
mode)
is completed
RW
LIN operation mode setting bit(2)
MST
LINE
0 : RXD0 input enabled
1 : RXD0 input disabled
LIN operation start bit
0 : Slave mode
(Synch Break detection circuit actuated)
1 : Master mode
(Timer RA output OR’ed w ith TXD0)
RW
0 : Causes LIN to stop
1 : Causes LIN to start operating(3)
RW
NOTES:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Exam ple of
Header Field Transm ission Flow chart (1) and Figure 17.9 Exam ple of Header Field Reception Flow chart
(2) .)
Figure 17.2
LINCR Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 315 of 441
R8C/28 Group, R8C/29 Group
17. Hardware LIN
LIN Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINST
Bit Symbol
SFDCT
SBDCT
BCDCT
B0CLR
B1CLR
B2CLR
—
(b7-b6)
Figure 17.3
Address
0107h
Bit Name
Synch Field measurementcompleted flag
After Reset
00h
Function
1 show s Synch Field measurement completed.
Synch Break detection flag
1 show s Synch Break detected or Synch Break
generation completed.
Bus collision detection flag
1 show s Bus collision detected.
SFDCT bit clear bit
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
RW
SBDCT bit clear bit
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
RW
BCDCT bit clear bit
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
LINST Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 316 of 441
RW
RO
RO
RO
—
R8C/28 Group, R8C/29 Group
17.4
17. Hardware LIN
Functional Description
17.4.1
Master Mode
Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 17.5 and 17.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Synch Break
TXD0 pin
SBDCT flag in the
LINST register
IR bit in the TRAIC
register
Synch Field
1
0
Set by writing 1 to the
B1CLR bit in the LINST
register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
1
0
(1)
(2)
(3)
Shown above is the case where
LINE = 1, MST = 1, SBIE = 1
Figure 17.4
IDENTIFIER
Typical Operation when Sending a Header Field
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 317 of 441
(4)
(5)
R8C/28 Group, R8C/29 Group
17. Hardware LIN
Timer RA Set to timer mode
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
UART0
Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0
Set the BRG count source (f1, f8, f32)
Bits CLK0 to CLK2 in U0C0 register
UART0
Set the bit rate
U0BRG register
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
Figure 17.5
Example of Header Field Transmission Flowchart (1)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 318 of 441
During master mode, the
Synch Field measurementcompleted interrupt cannot be
used.
R8C/28 Group, R8C/29 Group
17. Hardware LIN
A
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
TCSTF = 1 ?
NO
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
SBDCT = 1 ?
NO
YES
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0 ?
NO
YES
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
UART0 Communication via UART0
U0TB register ← ID field
Figure 17.6
Timer RA generates Synch Break.
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
The timer RA interrupt may be used
to terminate generation of Synch
Break.
One to two cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
Transmit the ID field.
Example of Header Field Transmission Flowchart (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 319 of 441
R8C/28 Group, R8C/29 Group
17.4.2
17. Hardware LIN
Slave Mode
Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
17.8 through Figure 17.10 show an Example of Header Field Transmission Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via
UART0.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Synch Break
RXD0 pin
1
0
RXD0 input for
UART0
1
0
RXDSF flag in the
LINCR register
SBDCT flag in the
LINST register
Synch Field
IDENTIFIER
Set by writing 1 to
the LSTART bit in
the LINCR register
1
0
Cleared to 0 when Synch
Field measurement
finishes
Set by writing 1 to
the B1CLR bit in
the LINST register
1
0
Measure this period
SFDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Cleared to 0 upon
acceptance of
interrupt request or
by a program
(1)
(2)
(3)
(4)
Shown above is the case where
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 17.7
Typical Operation when Receiving a Header Field
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Set by writing 1 to the
B0CLR bit in the LINST
register
Page 320 of 441
(5)
(6)
R8C/28 Group, R8C/29 Group
17. Hardware LIN
Timer RA Set to pulse width measurement mode
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in the TRAIOC register ← 1
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
A
Figure 17.8
Example of Header Field Reception Flowchart (1)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 321 of 441
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
R8C/28 Group, R8C/29 Group
17. Hardware LIN
A
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register ← 1
Timer RA waits until the timer starts
counting.
Timer RA Read the count status flag
TCSTF flag in the TRACR register
TCSTF = 1 ?
NO
YES
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
RXDSF = 1 ?
NO
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1 ?
NO
YES
B
Figure 17.9
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set
to 1.
Hardware LIN waits until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
One to two cycles of the CPU clock and
zero to one cycle of the timer RA count
source are required after the LSTART
bit is set to 1 before the RXDSF flag is
set to 1. After this, input to timer RA and
UART0 is enabled.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
When Synch Break is detected, timer
RA is reloaded with the initially set count
value.
Even if the duration of the input “L” level
is shorter than the set period, timer RA
is reloaded with the initially set count
value and waits until the next “L” level is
input.
One to two cycles of the CPU clock are
required after Synch Break detection
before the SBDCT flag is set to 1.
When the SBE bit in the LINCR register
is set to 0 (unmasked after Synch Break
is detected), timer RA can be used in
timer mode after the SBDCT flag in the
LINST register is set to 1 and the
RXDSF flag is set to 0.
Example of Header Field Reception Flowchart (2)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 322 of 441
R8C/28 Group, R8C/29 Group
17. Hardware LIN
B
YES
Hardware LIN Read the Synch Field measurementcompleted flag
SFDCT flag in the LINST register
SFDCT = 1 ?
NO
YES
UART0 Set the UART0 communication rate
U0BRG register
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
Figure 17.10
Example of Header Field Reception Flowchart (3)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 323 of 441
Hardware LIN measures the Synch
Field.
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit
in the LINST register is set to 1.
Set a communication rate based on
the Synch Field measurement
result.
Communication via UART0
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
R8C/28 Group, R8C/29 Group
17.4.3
17. Hardware LIN
Bus Collision Detection Function
The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1
register = 1).
Figure 17.11 shows the Typical Operation when a Bus Collision is Detected.
TXD0 pin
1
0
RXD0 pin
1
0
Transfer clock
1
0
LINE bit in the
LINCR register
1
0
TE bit in the U0C1
register
1
0
Set to 1 by a program
Set to 1 by a program
BCDCT flag in the
LINST register
IR bit in the TRAIC
register
Figure 17.11
Set by writing 1 to
the B2CLR bit in the
LINST register
1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
1
0
Typical Operation when a Bus Collision is Detected
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 324 of 441
R8C/28 Group, R8C/29 Group
17.4.4
17. Hardware LIN
Hardware LIN End Processing
Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
• If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA
Timer RA
Set the timer to stop counting
TSTART bit in TRACR register ← 0
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0 ?
NO
Set the timer to stop counting.
Zero to one cycle of the timer
RA count source is required
after timer RA starts counting
before the TCSTF flag is set to
1.
YES
UART0 Complete transmission via UART0
Hardware LIN
Hardware LIN
Figure 17.12
Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 0
When the bus collision
detection function is not used,
end processing for the UART0
transmission is not required.
After clearing hardware LIN
status flag, stop the hardware
LIN operation.
Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Example of Hardware LIN Communication Completion Flowchart
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 325 of 441
R8C/28 Group, R8C/29 Group
17.5
17. Hardware LIN
Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 17.2 lists the Interrupt Requests of Hardware LIN.
Table 17.2
Interrupt Requests of Hardware LIN
Interrupt Request
Synch Break detection
Status Flag
Cause of Interrupt
SBDCT
Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Synch Break generation
completed
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field
measurement completed
SFDCT
Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
Bus collision detection
BCDCT
Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 326 of 441
R8C/28 Group, R8C/29 Group
17.6
17. Hardware LIN
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 327 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P1_0 to P1_3. Therefore, when using these pins, ensure that the corresponding
port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no
current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.3 show the A/D converter-related registers.
Table 18.1
Performance of A/D converter
Item
A/D conversion method
Performance
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
Analog input voltage(1)
4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.2 V ≤ AVCC < 4.2 V f2, f4, fOCO-F (N, D version)
2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F (J, K version)
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
AVCC = Vref = 2.2 V, φAD = 5 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
Operating clock φAD(2)
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
One-shot and repeat(3)
4 pins (AN8 to AN11)
Software trigger
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
• Without sample and hold function
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
NOTES:
1. The analog input voltage does not depend on use of a sample and hold function.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
3. In repeat mode, only 8-bit mode can be used.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 328 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
fOCO-F
f1
CKS0 = 1
A/D conversion rate selection
CKS1 = 1
CKS0 = 0
CKS0 = 1
φAD
f2
CKS1 = 0
f4
CKS0 = 0
VCUT = 0
AVSS
VCUT = 1
VREF
Resistor ladder
Successive conversion register
ADCON0
Vcom
AD register
Decoder
Comparator
VIN
Data bus
ADGSEL0 = 0
ADGSEL0 = 1
P1_0/AN8
P1_1/AN9
P1_2/AN10
P1_3/AN11
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register
CKS1, VCUT: Bits in ADCON1 register
Figure 18.1
Block Diagram of A/D Converter
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 329 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1
Symbol
ADCON0
Bit Symbol
CH0
Address
00D6h
Bit Name
Analog input pin select
bits (2)
CH1
CH2
MD
ADGSEL0
—
(b5)
ADST
After Reset
00h
Function
b2 b1 b0
1 0 0 : AN8
1 0 1 : AN9
1 1 0 : AN10
1 1 1 : AN11
Other than above : Do not set.
A/D operating mode select 0 : One-shot mode
bit(3)
1 : Repeat mode
RW
RW
RW
RW
RW
A/D input group select bit
0 : Disabled
1 : Enabled (AN8 to AN11)
Reserved bit
Set to 0.
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(4)
1 : Selects fOCO-F
RW
CKS0
RW
RW
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Bits CH0 to CH2 are enabled w hen the ADGSEL0 bit is set to 1. Write to bits CH0 to CH2 after setting the ADGSEL0 bit
to 1.
3. When changing A/D operating mode, set the analog input pin again.
4. Set øAD frequency to 10 MHz or below .
Figure 18.2
ADCON0 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 330 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
Symbol
Address
00D7h
ADCON1
Bit Symbol
Bit Name
—
Reserved bits
(b2-b0)
BITS
CKS1
VCUT
—
(b6-b7)
After Reset
00h
Function
RW
Set to 0.
RW
8/10-bit mode select bit(2)
0 : 8-bit mode
1 : 10-bit mode
RW
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function.
RW
VREF connect bit(3)
0 : VREF not connected
1 : VREF connected
RW
Reserved bits
Set to 0.
RW
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting
A/D conversion.
A/D Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
ADCON2
Bit Symbol
Address
00D4h
Bit Name
A/D conversion method select bit
After Reset
00h
Function
0 : Without sample and hold
1 : With sample and hold
—
(b3-b1)
Reserved bits
Set to 0.
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
SMP
RW
RW
RW
—
NOTE:
1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.
A/D Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
AD
Address
00C1h-00C0h
After Reset
Undefined
Function
When BITS bit in ADCON1 register is
set to 1 (10-bit mode).
8 low -order bits in A/D conversion result
2 high-order bits in A/D conversion result
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 18.3
Registers ADCON1, ADCON2, and AD
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 331 of 441
When BITS bit in ADCON1 register is
set to 0 (8-bit mode).
A/D conversion result
When read, the content is undefined.
RW
RO
RO
—
R8C/28 Group, R8C/29 Group
18.1
18. A/D Converter
One-Shot Mode
In one-shot mode, the input voltage of one selected pin is A/D converted once.
Table 18.2 lists the Specifications of One-Shot Mode. Figure 18.4 shows the ADCON0 Register in One-Shot Mode
and Figure 18.5 shows the ADCON1 Register in One-Shot Mode.
Table 18.2
Specifications of One-Shot Mode
Item
Specification
The input voltage of one pin selected by bits CH2 to CH0 is A/D converted
once
Set the ADST bit to 1 (A/D conversion starts)
• A/D conversion completes (ADST bit is set to 0)
• Set the ADST bit to 0
A/D conversion completes
Function
Start condition
Stop condition
Interrupt request
generation timing
Input pin
Select one of AN8 to AN11
Reading of A/D conversion Read AD register
result
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1
Symbol
ADCON0
Bit Symbol
CH0
Address
00D6h
Bit Name
Analog input pin select
bits (2)
CH1
CH2
MD
ADGSEL0
—
(b5)
ADST
After Reset
00h
Function
b2 b1 b0
1 0 0 : AN8
1 0 1 : AN9
1 1 0 : AN10
1 1 1 : AN11
Other than above : Do not set.
A/D operating mode select 0 : One-shot mode
bit(3)
RW
RW
RW
RW
RW
A/D input group select bit
0 : Disabled
1 : Enabled (AN8 to AN11)
Reserved bit
Set to 0.
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(4)
1 : Selects fOCO-F
RW
CKS0
RW
RW
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Bits CH0 to CH2 are enabled w hen the ADGSEL0 bit is set to 1. Write to bits CH0 to CH2 after setting the ADGSEL0 bit
to 1.
3. When changing A/D operation mode, set the analog input pin again.
4. Set øAD frequency to 10 MHz or below .
Figure 18.4
ADCON0 Register in One-Shot Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 332 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0 0 0
Symbol
Address
00D7h
ADCON1
Bit Symbol
Bit Name
Reserved bits
—
(b2-b0)
BITS
CKS1
—
(b6-b7)
Set to 0.
RW
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function.
RW
VREF connect bit
1 : VREF connected
Reserved bits
Set to 0.
ADCON1 Register in One-Shot Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
RW
0 : 8-bit mode
1 : 10-bit mode
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.5
RW
8/10-bit mode select bit
(2)
VCUT
After Reset
00h
Function
Page 333 of 441
RW
RW
R8C/28 Group, R8C/29 Group
18.2
18. A/D Converter
Repeat Mode
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 18.3 lists the Specifications of Repeat Mode. Figure 18.6 shows the ADCON0 Register in Repeat Mode and
Figure 18.7 shows the ADCON1 Register in Repeat Mode.
Table 18.3
Specifications of Repeat Mode
Item
Function
Start conditions
Stop condition
Interrupt request
generation timing
Input pin
Reading of result of A/D
converter
Specification
The Input voltage of one pin selected by bits CH2 to CH0 is A/D converted
repeatedly
Set the ADST bit to 1 (A/D conversion starts)
Set the ADST bit to 0
Not generated
Select one of AN8 to AN11
Read AD register
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1
Symbol
ADCON0
Bit Symbol
CH0
Address
00D6h
Bit Name
Analog input pin select
bits (2)
CH1
CH2
MD
ADGSEL0
—
(b5)
ADST
After Reset
00h
Function
b2 b1 b0
1 0 0 : AN8
1 0 1 : AN9
1 1 0 : AN10
1 1 1 : AN11
Other than above : Do not set.
A/D operating mode select 1 : Repeat mode
bit(3)
RW
RW
RW
RW
RW
A/D input group select bit
0 : Disabled
1 : Enabled (AN8 to AN11)
Reserved bit
Set to 0.
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(4)
1 : Do not set.
RW
CKS0
RW
RW
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Bits CH0 to CH2 are enabled w hen the ADGSEL0 bit is set to 1. Write to bits CH0 to CH2 after setting the ADGSEL0 bit
to 1.
3. When changing A/D operation mode, set the analog input pin again.
4. Set øAD frequency to 10 MHz or below .
Figure 18.6
ADCON0 Register in Repeat Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 334 of 441
R8C/28 Group, R8C/29 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0 0 0 0
Symbol
Address
00D7h
ADCON1
Bit Symbol
Bit Name
Reserved bits
—
(b2-b0)
BITS
CKS1
VCUT
—
(b6-b7)
After Reset
00h
Function
Set to 0.
8/10-bit mode select bit(2)
0 : 8-bit mode
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function.
VREF connect bit(3)
1 : VREF connected
Reserved bits
Set to 0.
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Set the BITS bit to 0 (8-bit mode) in repeat mode.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting
A/D conversion.
Figure 18.7
ADCON1 Register in Repeat Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 335 of 441
RW
RW
RW
RW
RW
RW
R8C/28 Group, R8C/29 Group
18.3
18. A/D Converter
Sample and Hold
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after
selecting whether the sample and hold circuit is to be used or not.
Figure 18.8 shows a Timing Diagram of A/D Conversion.
Sample and hold
disabled
Conversion time of 1st bit
Sampling time
4ø AD cycles
2nd bit
Comparison Sampling time Comparison Sampling time Comparison
2.5ø AD cycles
2.5ø AD cycles
time
time
time
* Repeat until conversion ends
Sample and hold
enabled
2nd bit
Conversion time of 1st bit
Sampling time
4ø AD cycles
Comparison
time
Comparison Comparison Comparison
time
time
time
* Repeat until conversion ends
Figure 18.8
18.4
Timing Diagram of A/D Conversion
A/D Conversion Cycles
Figure 18.9 shows the A/D Conversion Cycles.
Conversion time at the 1st bit
A/D Conversion Mode
Conversion
Time
Sampling
Time
Comparison
Time
Conversion time at the 2nd
bit and the follows
Sampling
Time
End process
Comparison
End process
Time
Without Sample & Hold
8 bits
49φAD
4φAD
2.0φAD
2.5φAD
2.5φAD
8.0φAD
Without Sample & Hold
10 bits
59φAD
4φAD
2.0φAD
2.5φAD
2.5φAD
8.0φAD
With Sample & Hold
8 bits
28φAD
4φAD
2.5φAD
0.0φAD
2.5φAD
4.0φAD
With Sample & Hold
10 bits
33φAD
4φAD
2.5φAD
0.0φAD
2.5φAD
4.0φAD
Figure 18.9
A/D Conversion Cycles
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 336 of 441
R8C/28 Group, R8C/29 Group
18.5
18. A/D Converter
Internal Equivalent Circuit of Analog Input
Figure 18.10 shows the Internal Equivalent Circuit of Analog Input.
VCC
VCC VSS
AVCC
ON Resistor
Approx. 2kΩ Wiring Resistor
Approx. 0.2kΩ
Parasitic Diode
AN0
SW1
ON Resistor
Approx. 0.6kΩ
Analog Input
Voltage
SW2
Parasitic Diode
i Ladder-type
Switches
i=4
AMP
VIN
ON Resistor
Approx. 5kΩ
Sampling
Control Signal
VSS
C = Approx.1.5pF
SW3
SW4
i Ladder-type
Wiring Resistors
AVSS
ON Resistor
Approx. 2kΩ Wiring Resistor
Approx. 0.2kΩ
Chopper-type
Amplifier
AN11
SW1
b4 b2 b1 b0
A/D Control Register 0
Reference
Control Signal
A/D Successive
Conversion Register
Vref
VREF
Resistor
ladder
SW5
Comparison
voltage
ON Resistor
Approx. 0.6k f
A/D Conversion
Interrupt Request
AVSS
Comparison reference voltage
(Vref) generator
Sampling Comparison
SW1 conducts only on the ports selected for analog input.
Connect to
SW2 and SW3 are open when A/D conversion is not in progress;
their status varies as shown by the waveforms in the diagrams on the left.
Control signal
for SW2
Connect to
SW4 conducts only when A/D conversion is not in progress.
Connect to
Control signal
for SW3
Connect to
SW5 conducts when compare operation is in progress.
NOTE:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 18.10
Internal Equivalent Circuit of Analog Input
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 337 of 441
R8C/28 Group, R8C/29 Group
18.6
18. A/D Converter
Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
VC is generally
And when t = T,
1
– -------------------------C ( R0 + R )

VC = VIN  1 – e

t



X
X
VC = VIN – ---- VIN = VIN  1 – ----

Y
Y
1
– --------------------------T
C
(
R0
+ R) = X
---e
Y
1
– -------------------------T = ln X
---C ( R0 + R )
Y
Hence,
T
R0 = – ------------------–R
X
C • ln ---Y
Figure 18.11 shows the Analog Input Pin and External Sensor Equivalent Circuit. When the difference between
VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample and hold. Output impedance R0
for sufficiently charging capacitor C within time T is determined as follows.
T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
3
3
0.25 × 10 – 6
R0 = – -------------------------------------------------- – 2.8 ×10 ≈ 1.7 ×10
0.1 6.0 × 10 –12 • ln ----------1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately 1.7 kΩ. maximum.
MCU
Sensor equivalent
circuit
R0
R (2.8 kΩ)
VIN
C (6.0 pF)
VC
NOTE:
1. The capacity of the terminal is assumed to be 4.5 pF.
Figure 18.11
Analog Input Pin and External Sensor Equivalent Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 338 of 441
R8C/28 Group, R8C/29 Group
18.7
18. A/D Converter
Notes on A/D Converter
• Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
• After changing the A/D operating mode, select an analog input pin again.
• When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
Do not select the fOCO-F for the φAD.
• If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 339 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
19. Flash Memory
19.1
Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,
standard serial I/O, and parallel I/O.
Table 19.1 lists the Flash Memory Performance (refer to Tables 1.1 and 1.2 Functions and Specifications for
items not listed in Table 19.1).
Table 19.1
Flash Memory Performance
Item
Flash memory operating mode
Division of erase block
Programming method
Erase method
Programming and erasure control method(3)
Rewrite control method
Specification
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Refer to Figures 19.1 and 19.2
Byte unit
Block erase
Program and erase control by software command
Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0 register
Rewrite control for block 0 by FMR15 bit and block 1 by FMR16 bit in
FMR1 register
Number of commands
5 commands
Programming and Blocks 0 and 1 (program R8C/28 Group: 100 times; R8C/29 Group: 1,000 times
erasure
ROM)
endurance(1)
10,000 times
Blocks A and B (data
flash)(2)
ID code check function
Standard serial I/O mode supported
ROM code protect
Parallel I/O mode supported
NOTES:
1. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to different addresses in block A, a 1-Kbyte block, and then the block is erased, the programming/
erasure endurance still stands at one. When performing 100 or more rewrites, the actual erase count can be
reduced by executing programming operations in such a way that all blank areas are used before performing an
erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure
endurance of the blocks. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
2. Blocks A and B are implemented only in the R8C/29 group.
3. To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Table 19.2
Flash Memory Rewrite Modes
Flash memory
Rewrite mode
Function
Standard Serial I/O
Mode
User ROM area is rewritten by executing User ROM area is
rewritten by a
software commands from the CPU.
dedicated serial
EW0 mode: Rewritable in the RAM
EW1 mode: Rewritable in flash memory programmer.
User ROM area
User ROM area
CPU Rewrite Mode
Areas which can
be rewritten
Operating mode
Single chip mode
ROM Programmer None
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 340 of 441
Boot mode
Serial programmer
Parallel I/O Mode
User ROM area is
rewritten by a
dedicated parallel
programmer.
User ROM area
Parallel I/O mode
Parallel programmer
R8C/28 Group, R8C/29 Group
19.2
19. Flash Memory
Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area).
Figure 19.1 shows the Flash Memory Block Diagram for R8C/28 Group. Figure 19.2 shows a Flash Memory Block
Diagram for R8C/29 Group.
The user ROM area of the R8C/29 Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
16 Kbyte ROM product
0C000h
Block 0: 16 Kbytes(1)
8 Kbyte ROM product
0E000h
Block 0: 8 Kbytes(1)
User ROM area
User ROM area
0E000h
8 Kbytes
0FFFFh
0FFFFh
0FFFFh
Program ROM
Boot ROM area
(reserved area)(2)
32 Kbytes ROM product
08000h
Block 1: 16 Kbytes(1)
Program ROM
0BFFFh
0C000h
Block 0: 16 Kbytes(1)
0FFFFh
0E000h
8 Kbytes
0FFFFh
User ROM area
Boot ROM area
(reserved area)(2)
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU
rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.1
Flash Memory Block Diagram for R8C/28 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 341 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
16 Kbytes ROM product
02400h
Block A: 1 Kbyte
8 Kbytes ROM product
02400h
Block A: 1 Kbyte
Data flash
02BFFh
Block B: 1 Kbyte
02BFFh
Block B: 1 Kbyte
0C000h
Program ROM
Block 0: 16 Kbytes(1)
0E000h
0FFFFh
Block 0: 8 Kbytes(1)
0FFFFh
User ROM area
User ROM area
0E000h
8 Kbytes
0FFFFh
Boot ROM area
(reserved area)(2)
32 Kbytes ROM product
02400h
Block A: 1 Kbyte
Data flash
02BFFh
Block B: 1 Kbyte
08000h
Block 1: 16 Kbytes(1)
Program ROM
0BFFFh
0C000h
Block 0: 16 Kbytes(1)
0E000h
0FFFFh
8 Kbytes
0FFFFh
User ROM area
Boot ROM area
(reserved area)(2)
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU
rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.2
Flash Memory Block Diagram for R8C/29 Group
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 342 of 441
R8C/28 Group, R8C/29 Group
19.3
19. Flash Memory
Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
19.3.1
ID Code Check Function
This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write
them to the flash memory.
Address
00FFDFh to 00FFDCh
ID1
Undefined instruction vector
00FFE3h to 00FFE0h
ID2
Overflow vector
BRK instruction vector
00FFE7h to 00FFE4h
00FFEBh to 00FFE8h
ID3
Address match vector
00FFEFh to 00FFECh
ID4
Single step vector
00FFF3h to 00FFF0h
ID5
00FFF7h to 00FFF4h
ID6
00FFFBh to 00FFF8h
ID7
00FFFFh to 00FFFCh
(Note 1)
Oscillation stop detection/watchdog
timer/voltage monitor 1 and voltage
monitor 2 vector
Address break
(Reserved)
Reset vector
4 bytes
NOTE:
1. The OFS register is assigned to 00FFFFh.
Refer to Figure 19.4 OFS Register for OFS register details.
Figure 19.3
Address for Stored ID Code
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 343 of 441
R8C/28 Group, R8C/29 Group
19.3.2
19. Flash Memory
ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode.
Figure 19.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
LVD1ON
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2, 4)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
RW
Voltage detection 1
circuit start bit(5, 6)
0 : Voltage monitor 1 reset enabled after hardw are
reset
1 : Voltage monitor 1 reset disabled after hardw are
reset
RW
Count source protect
CSPROINI mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
RW
RW
RW
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. The LVD0ON bit setting is valid only by a hardw are reset. To use the pow er-on reset, set the LVD0ON bit to 0
(voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
4. For N, D version only. For J, K version, set the LVD0ON bit to 1 (voltage monitor 0 reset disabled after hardw are
reset).
5. The LVD1ON bit setting is valid only by a hardw are reset. When the pow er-on reset function is used, set the
LVD1ON bit to 0 (voltage monitor 1 reset enabled after hardw are reset).
6. For J, K version only. For N, D version, set the LVD1ON bit to 1 (voltage monitor 1 reset disabled after hardw are
reset).
Figure 19.4
OFS Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 344 of 441
R8C/28 Group, R8C/29 Group
19.4
19. Flash Memory
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in
CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erasesuspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module
has a program-suspend function which performs the interrupt process after the auto-program operation is
suspended. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode).
Table 19.3 lists the Differences between EW0 Mode and EW1 Mode.
Table 19.3
Differences between EW0 Mode and EW1 Mode
Item
Operating mode
Areas in which a rewrite
control program can be
located
Areas in which a rewrite
control program can be
executed
Areas which can be
rewritten
EW0 Mode
Single-chip mode
User ROM area
Necessary to transfer to any area other
Executing directly in user ROM or RAM
than the flash memory (e.g., RAM) before area possible
executing
User ROM area
User ROM area
However, blocks which contain a rewrite
control program are excluded(1)
None
• Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Read status register mode
Read array mode
Software command
restrictions
Modes after program or
erase
Modes after read status
register
CPU status during autowrite and auto-erase
Flash memory status
detection
Read status register mode
Do not execute this command
Operating
Conditions for transition to
erase-suspend
Conditions for transitions to
program-suspend
CPU clock
EW1 Mode
Single-chip mode
User ROM area
Hold state (I/O ports hold state before the
command is executed)
• Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in
the FMR0 register by a program
in the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set
register to 1 by a program.
to 1 and the interrupt request of the
enabled maskable interrupt is generated
Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set
register to 1 by a program.
to 1 and the interrupt request of the
enabled maskable interrupt is generated
5 MHz or below
No restriction (on clock frequency to be
used)
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting
the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enabled).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 345 of 441
R8C/28 Group, R8C/29 Group
19.4.1
19. Flash Memory
EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erasesuspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read
enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the
FMR42 bit to 0 (program restarts).
19.4.2
EW1 Mode
The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine when program and erase operations complete. Do not execute
commands that use the read status register in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is
acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt
process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts)
To enable the program-suspend function during auto-programming, execute the program command after setting
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is
acknowledged.
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and
the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0)
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0
(programming restarts).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 346 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Figure 19.5 shows the FMR0 Register, Figure 19.6 shows the FMR1 Register and Figure 19.7 shows the FMR4
Register.
19.4.2.1
FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure
(including suspend periods), or erase-suspend mode; otherwise, it is 1.
19.4.2.2
FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
19.4.2.3
FMR02 Bit
Rewriting of block 0 and block 1 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of block 0 and block 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite
enabled).
19.4.2.4
FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
• To provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock mode (XIN clock stops).
Figure 19.11 shows the Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode, LowSpeed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode (XIN Clock Stops). Handle
according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled,
the FMR0 register does not need to be set because the power for the flash memory is automatically turned off
and is turned back on again after returning from stop or wait mode.
19.4.2.5
FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program
error occurs; otherwise, it is cleared to 0. For details, refer to the description in 19.4.5 Full Status Check.
19.4.2.6
FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error
occurs; otherwise, it is set to 0. Refer to 19.4.5 Full Status Check for details.
19.4.2.7
FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
19.4.2.8
FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
19.4.2.9
FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 347 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
19.4.2.10 FMR40 Bit
The suspend function is enabled by setting the FMR40 bit to 1 (enable).
19.4.2.11 FMR41 Bit
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is
generated in EW1 mode, and then the MCU enters erase-suspend mode.
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
19.4.2.12 FMR42 Bit
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
19.4.2.13 FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit
remains set to 1 (erase execution in progress) during erase-suspend operation.
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
19.4.2.14 FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44
bit remains set to 1 (program execution in progress) during program-suspend operation.
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
19.4.2.15 FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading
enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.
19.4.2.16 FMR47 Bit
Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in
low-speed clock mode (XIN clock stops) and low-speed on-chip oscillator mode (XIN clock stops).
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 348 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
FMR0
Bit Symbol
FMR00
FMR01
FMR02
Address
01B7h
___
Bit Name
RY/BY status flag
FMR06
FMR07
Function
0 : Busy (w riting or erasing in progress)
1 : Ready
RW
RO
CPU rew rite mode select bit(1)
0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
RW
Block 0, 1 rew rite enable bit(2, 6)
0 : Disables rew rite
1 : Enables rew rite
RW
Flash memory stop bit(3, 5)
0 : Enables flash memory operation
1 : Stops flash memory
(enters low -pow er consumption state
and flash memory is reset)
RW
FMSTP
—
(b5-b4)
After Reset
00000001b
Reserved bits
Set to 0.
Program status flag(4)
0 : Completed successfully
1 : Terminated by error
RO
Erase status flag(4)
0 : Completed successfully
1 : Terminated by error
RO
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
3. Set this bit by a program transferred to the RAM.
4. This bit is set to 0 by executing the clear status command.
5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0,
w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er
consumption state nor is it reset.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
Figure 19.5
FMR0 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 349 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0
Symbol
Address
01B5h
FMR1
Bit Symbol
Bit Name
—
Reserved bit
(b0)
After Reset
1000000Xb
Function
When read, the content is undefined.
(1, 2)
FMR11
—
(b4-b2)
FMR15
FMR16
—
(b7)
EW1 mode select bit
0 : EW0 mode
1 : EW1 mode
Reserved bits
Set to 0.
Block 0 rew rite disable bit
(2,3)
Block 1 rew rite disable bit
(2,3)
Reserved bit
RW
RO
RW
RW
0 : Enables rew rite
1 : Disables rew rite
RW
0 : Enables rew rite
1 : Disables rew rite
RW
Set to 1.
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable) . Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
2. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
Figure 19.6
FMR1 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 350 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR4
Bit Symbol
FMR40
FMR41
Address
01B3h
Bit Name
Erase-suspend function
enable bit(1)
After Reset
01000000b
Function
RW
0 : Erase restart
1 : Erase-suspend request
RW
Program-suspend request bit
0 : Program restart
1 : Program-suspend request
RW
Erase command flag
0 : Erase not executed
1 : Erase execution in progress
RO
Program command flag
0 : Program not executed
1 : Program execution in progress
RO
Reserved bit
Set to 0.
Read status flag
0 : Disables reading
1 : Enables reading
Erase-suspend request bit
(2)
(3)
FMR42
FMR43
FMR44
—
(b5)
FMR46
FMR47
RW
0 : Disable
1 : Enable
Low -pow er consumption read 0 : Disable
1 : Enable
mode enable bit (1, 4, 5)
RO
RO
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than the above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).
3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.
4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er-consumption read mode.
Figure 19.7
FMR4 Register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 351 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Figure 19.8 shows the Timing of Suspend Operation.
Erasure
starts
Erasure
suspends
Programming Programming Programming Programming Erasure
starts
suspends
restarts
ends
restarts
During erasure
FMR00 bit in
FMR0 register
1
FMR46 bit in
FMR4 register
1
FMR44 bit in
FMR4 register
1
FMR43 bit in
FMR4 register
1
During programming
During programming
Erasure
ends
During erasure
Remains 0 during suspend
0
0
0
0
Remains 1 during suspend
Check that the
FMR43 bit is set to 1
(during erase
execution), and that
the erase-operation
has not ended.
Check that the
FMR44 bit is set to 1
(during program
execution), and that
the program has not
ended.
Check the status,
and that the
programming ends
normally.
Check the status,
and that the
erasure ends
normally.
The above figure shows an example of the use of program-suspend during programming following erase-suspend.
NOTE:
1. If program-suspend is entered during erase-suspend, always restart programming.
Figure 19.8
Timing of Suspend Operation
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 352 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Figure 19.9 shows the How to Set and Exit EW0 Mode. Figure 19.10 shows the How to Set and Exit EW1
Mode.
EW0 Mode Operating Procedure
Rewrite control program
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Set registers(1) CM0 and CM1
Execute software commands
Transfer a rewrite control program which uses CPU
rewrite mode to the RAM.
Execute the read array command(3)
Jump to the rewrite control program which has been
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a specified address in the flash memory
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
Figure 19.9
How to Set and Exit EW0 Mode
EW1 Mode Operating Procedure
Program in ROM
Write 0 to the FMR01 bit before writing 1 (CPU
rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
NOTE:
1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
Figure 19.10
How to Set and Exit EW1 Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 353 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
High-speed on-chip oscillator mode,
low-speed on-chip oscillator mode
(XIN clock stops), and low-speed
clock mode (XIN clock stops)
program
Transfer a high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program to
the RAM.
Jump to the high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program
which has been transferred to the RAM.
(The subsequent processing is executed by the
program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)
Write 1 to the FMSTP bit (flash memory stops.
low power consumption mode)(1)
Switch the clock source for the CPU clock.
Turn XIN off
Process in high-speed on-chip oscillator
mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock
mode (XIN clock stops)
Turn XIN clock on → wait until oscillation
stabilizes → switch the clock source for CPU
clock(2)
Write 0 to the FMSTP bit
(flash memory operation)
NOTES:
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the
FMSTP bit to 1.
2. Before switching to a different clock source for the CPU, make sure
the designated clock is stable.
3. Insert a 30 µs wait time in a program. Do not access to the flash
memory during this wait time.
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes
(30 µs)(3)
Jump to a specified address in the flash memory
Figure 19.11
Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode,
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode
(XIN Clock Stops)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 354 of 441
R8C/28 Group, R8C/29 Group
19.4.3
19. Flash Memory
Software Commands
The software commands are described below. Read or write commands and data in 8-bit units.
Table 19.4
Software Commands
First Bus Cycle
Command
Read array
Read status register
Clear status register
Program
Block erase
Mode
Write
Write
Write
Write
Write
Address
×
×
×
WA
×
Data
Mode
(D7 to D0)
FFh
70h
Read
50h
40h
Write
20h
Write
Second Bus Cycle
Address
Data
(D7 to D0)
×
SRD
WA
BA
WD
D0h
SRD: Status register data (D7 to D0)
WA: Write address (ensure the address specified in the first bus cycle is the same address as the write
address specified in the second bus cycle.)
WD: Write data (8 bits)
BA: Given block address
×: Any specified address in the user ROM area
19.4.3.1
Read Array Command
The read array command reads the flash memory.
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since the MCU remains in read array mode until another command is written, the contents of multiple
addresses can be read continuously.
In addition, the MCU enters read array mode after a reset.
19.4.3.2
Read Status Register Command
The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 19.4.4
Status Registers). When reading the status register, specify an address in the user ROM area.
Do not execute this command in EW1 mode.
The MCU remains in read status register mode until the next read array command is written.
19.4.3.3
Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the
status register are set to 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 355 of 441
R8C/28 Group, R8C/29 Group
19.4.3.4
19. Flash Memory
Program Command
The program command writes data to the flash memory in 1-byte units.
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the
same address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed.
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when autoprogramming completes.
When suspend function enabled, the FMR44 bit is set to 1 during auto-programming and set to 0 when autoprogramming completes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been
finished (refer to 19.4.5 Full Status Check).
Do not write additions to the already programmed addresses.
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), program commands targeting
block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), program commands
targeting block 1 are not acknowledged.
Figure 19.12 shows the Program Command (When Suspend Function Disabled). Figure 19.13 shows the
Program Command (When Suspend Function Enabled).
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register
mode until the next read array command is written. The status register can be read to determine the result of
auto-programming after auto-programming has completed.
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
No
Yes
Full status check
Program completed
Figure 19.12
Program Command (When Suspend Function Disabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 356 of 441
R8C/28 Group, R8C/29 Group
EW0 Mode
19. Flash Memory
Maskable interrupt(1)
Start
FMR40 = 1
FMR44 = 1 ?
No
Yes
Write the command code 40h
to the write address
FMR42 = 1(4)
I = 1 (enable interrupt)(3)
FMR46 = 1 ?
Write data to the write address
Yes
No
Access flash memory
Access flash memory
FMR44 = 0 ?
No
FMR42 = 0
Yes
Full status check
REIT
Program completed
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
REIT
Write the command code 40h
I = 1 (enable interrupt)
Write data to the write address
FMR42 = 0
FMR44 = 0 ?
No
Yes
Full status check
Program completed
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Figure 19.13
Program Command (When Suspend Function Enabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 357 of 441
R8C/28 Group, R8C/29 Group
19.4.3.5
19. Flash Memory
Block Erase
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus
cycle, an auto-erase operation (erase and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has
completed (refer to 19.4.5 Full Status Check).
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands
targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), the block erase
commands targeting block 1 are not acknowledged.
Do not use the block erase command during program-suspend.
Figure 19.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 19.15 shows
the Block Erase Command (When Erase-Suspend Function Enabled).
In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read
array command is written.
Start
Write the command code 20h
Write D0h to a given block
address
FMR00 = 1?
No
Yes
Full status check
Block erase completed
Figure 19.14
Block Erase Command (When Erase-Suspend Function Disabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 358 of 441
R8C/28 Group, R8C/29 Group
EW0 Mode
19. Flash Memory
Maskable interrupt(1)
Start
FMR40 = 1
FMR43 = 1 ?
No
Yes
Write the command code 20h
FMR41 = 1(4)
I = 1 (enable interrupt)(3)
FMR46 = 1 ?
Write D0h to any block
address
No
Access flash memory
Yes
Access flash memory
FMR00 = 1 ?
No
FMR41 = 0
Yes
Full status check
REIT
Block erase completed
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
Write the command code 20h
REIT
I = 1 (enable interrupt)
Write D0h to any block
address
FMR41 = 0
FMR00 = 1 ?
No
Yes
Full status check
Block erase completed
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.
Figure 19.15
Block Erase Command (When Erase-Suspend Function Enabled)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 359 of 441
R8C/28 Group, R8C/29 Group
19.4.4
19. Flash Memory
Status Registers
The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 19.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
• When a given address in the user ROM area is read after writing the read status register command
• When a given address in the user ROM area is read after executing program or block erase command but
before executing the read array command.
19.4.4.1
Sequencer Status (Bits SR7 and FMR00)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during autoprogramming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.
19.4.4.2
Erase Status (Bits SR5 and FMR07)
Refer to 19.4.5 Full Status Check.
19.4.4.3
Program Status (Bits SR4 and FMR06)
Refer to 19.4.5 Full Status Check.
Table 19.5
Status Register Bits
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4)
FMR0 Register
Bit
−
−
−
−
FMR06
Reserved
Reserved
Reserved
Reserved
Program status
SR5 (D5)
FMR07
Erase status
SR6 (D6)
SR7 (D7)
−
FMR00
Reserved
Sequencer
status
Status Register Bit
Status Name
Description
0
−
−
−
−
Completed
normally
Completed
normally
−
Busy
Value After
Reset
1
−
−
−
−
Error
−
−
−
−
0
Error
0
−
Ready
−
1
D0 to D7: Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot
be accepted.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 360 of 441
R8C/28 Group, R8C/29 Group
19.4.5
19. Flash Memory
Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
Table 19.6
Errors and FMR0 Register Status
FMR0 Register (Status
Register) Status
Error
FMR07 (SR5) FMR06 (SR4)
1
1
Command
sequence
error
1
0
Erase error
0
1
Program error
Error Occurrence Condition
• When a command is not written correctly
• When invalid data other than that which can be written
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)(1)
• When the program command or block erase command
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write to a block for which rewriting
is disabled during write command input.
• When the block erase command is executed but autoerasure does not complete correctly
• When the program command is executed but not autoprogramming does not complete.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 361 of 441
R8C/28 Group, R8C/29 Group
19. Flash Memory
Command sequence error
Full status check
Execute the clear status register command
(set these status flags to 0)
FMR06 = 1
and
FMR07 = 1?
Yes
Command sequence error
Check if command is properly input
No
Re-execute the command
FMR07 = 1?
Yes
Erase error
Erase error
No
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
FMR06 = 1?
Yes
Program error
No
Yes
Re-execute block erase command
No
Program error
Execute the clear status register
command
(set these status flags to 0)
Full status check completed
Specify the other address besides the
write address where the error occurs for
the program address(1)
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Figure 19.16
Re-execute program command
Full Status Check and Handling Procedure for Individual Errors
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 362 of 441
Block targeting for erasure
cannot be used
R8C/28 Group, R8C/29 Group
19.5
19. Flash Memory
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of Standard serial I/O modes:
• Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.
Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.
Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial
programmer for instructions on how to use it.
Table 19.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 19.8 lists the Pin Functions
(Flash Memory Standard Serial I/O Mode 3), and Figure 19.17 shows the Pin Connections for Standard Serial I/O
Mode 3.
After processing the pins shown in Table 19.8 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
19.5.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match (refer to 19.3 Functions to Prevent Rewriting of Flash Memory).
Table 19.7
Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin
VCC,VSS
Name
Power input
I/O
RESET
P4_6/XIN/XCIN
P4_7/XOUT/XCOUT
P1_0 to P1_7
P3_3 to P3_5
P4_2/VREF
MODE
P3_7
P4_5
Reset input
I
P4_6 input/clock input
P4_7 input/clock output
Input port P1
Input port P3
Input port P4
MODE
TXD output
RXD input
I
I/O
I
I
I
I/O
O
I
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 363 of 441
Description
Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
Reset input pin.
Connect a ceramic resonator or crystal oscillator
between the XIN/XCIN and XOUT/XCOUT pins.
Input “H” or “L” level signal or leave the pin open.
Input “L”.
Serial data output pin.
Serial data input pin.
R8C/28 Group, R8C/29 Group
Table 19.8
19. Flash Memory
Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin
VCC,VSS
Name
Power input
I/O
Description
Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
Reset input pin.
RESET
P4_6/XIN/XCIN
Reset input
I
P4_6 input/clock input
I
P1_0 to P1_7
P3_3 to P3_5, P3_7
P4_2/VREF, P4_5
MODE
Input port P1
Input port P3
Input port P4
MODE
I
Input “H” or “L” level signal or leave the pin open.
I
I
I/O Serial data I/O pin. Connect to the flash
programmer.
Connect a ceramic resonator or crystal oscillator
between the XIN/XCIN and XOUT/XCOUT pins
P4_7/XOUT/XCOUT P4_7 input/clock output I/O when connecting external oscillator. Apply “H” and
“L” or leave the pin open when using as input port.
1
20
2
19
3
18
VSS
5
6
7
VCC
8
MODE
R8C/28 Group
R8C/29 Group
4
Connect
oscillator
circuit(1)
17
16
15
14
13
9
12
10
11
Mode setting
Figure 19.17
Signal
Value
MODE
Voltage from programmer
RESET
VSS → VCC
Package: PLSP0020JB-A (20P2F-A)
NOTE:
1. It is not necessary to connect an oscillating circuit
when operating with the on-chip oscillator clock.
Pin Connections for Standard Serial I/O Mode 3
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 364 of 441
R8C/28 Group, R8C/29 Group
19.5.1.1
19. Flash Memory
Example of Circuit Application in Standard Serial I/O Mode
Figure 19.18 shows an Example of Pin Processing in Standard Serial I/O Mode 2, Figure 19.19 shows an
Example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the
programmer, refer to the manual of your serial programmer for details.
MCU
Data Output
TXD
Data Input
RXD
MODE
NOTES:
1. In this example, modes are switched between single-chip mode and
standard serial I/O mode by controlling the MODE input with a switch.
2. Connecting the oscillation is necessary. Set the main clock frequency 1
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example with
M16C Flash Starter (M3A-0806).
Figure 19.18
Example of Pin Processing in Standard Serial I/O Mode 2
MCU
MODE I/O
MODE
Reset input
RESET
User reset signal
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
Figure 19.19
Example of Pin Processing in Standard Serial I/O Mode 3
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 365 of 441
R8C/28 Group, R8C/29 Group
19.6
19. Flash Memory
Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figures 19.1 and 19.2 can be rewritten in parallel I/O mode.
19.6.1
ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 19.3
Functions to Prevent Rewriting of Flash Memory.)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 366 of 441
R8C/28 Group, R8C/29 Group
19.7
19. Flash Memory
Notes on Flash Memory
19.7.1
CPU Rewrite Mode
19.7.1.1
Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register.
This does not apply to EW1 mode.
19.7.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
19.7.1.3
Interrupts
Table 19.9 lists the EW0 Mode Interrupts and Table 19.10 lists the EW1 Mode Interrupts.
Table 19.9
Mode
EW0 Mode Interrupts
When Maskable Interrupt
Request is Acknowledged
Status
EW0 During auto-erasure
Any interrupt can be used by
allocating a vector in RAM
Auto-programming
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 367 of 441
R8C/28 Group, R8C/29 Group
Table 19.10
Mode
19. Flash Memory
EW1 Mode Interrupts
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Auto-erasure is suspended after Once an interrupt request is
acknowledged, auto-programming or
td (SR-SUS) and interrupt
auto-erasure is forcibly stopped
handling is executed. Autoimmediately and the flash memory is
erasure can be restarted by
reset. Interrupt handling starts after the
setting the FMR41 bit in the
FMR4 register to 0 (erase restart) fixed period and the flash memory
restarts. Since the block during autoafter interrupt handling
erasure or the address during autocompletes.
Auto-erasure has priority and the programming is forcibly stopped, the
normal value may not be read. Execute
interrupt request
auto-erasure again and ensure it
acknowledgement is put on
completes normally.
standby. Interrupt handling is
Since the watchdog timer does not stop
executed after auto-erasure
during the command operation,
completes.
Auto-programming is suspended interrupt requests may be generated.
Reset the watchdog timer regularly
after td (SR-SUS) and interrupt
using the erase-suspend function.
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
When Maskable Interrupt
Request is Acknowledged
Status
EW1 During auto-erasure
(erase-suspend
function enabled)
During auto-erasure
(erase-suspend
function disabled)
During autoprogramming
(program suspend
function enabled)
During autoprogramming
(program suspend
function disabled)
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 368 of 441
R8C/28 Group, R8C/29 Group
19.7.1.4
19. Flash Memory
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
19.7.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
19.7.1.6
Program
Do not write additions to the already programmed address.
19.7.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
19.7.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 369 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
20. Electrical Characteristics
20.1
N, D Version
Table 20.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
-0.3 to 6.5
V
Input voltage
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd
Power dissipation
500
mW
Topr
Operating ambient temperature
-20 to 85 (N version) /
-40 to 85 (D version)
°C
Tstg
Storage temperature
-65 to 150
°C
VCC/AVCC
Supply voltage
VI
Table 20.2
IOH(sum)
IOH(peak)
Sum of all pins IOH(peak)
Min.
2.2
−
0.8 VCC
0
−
Standard
Typ.
−
0
−
−
−
Max.
5.5
−
VCC
0.2 VCC
-160
Sum of all pins IOH(avg)
−
−
-80
mA
Except P1_0 to P1_7
P1_0 to P1_7
Except P1_0 to P1_7
P1_0 to P1_7
Sum of all pins IOL(peak)
−
−
−
−
−
−
−
−
−
−
-10
-40
-5
-20
160
mA
mA
mA
mA
mA
−
−
80
mA
−
−
−
−
0
0
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
125
10
40
5
20
20
10
5
70
20
10
5
−
mA
mA
mA
mA
MHz
MHz
MHz
kHz
MHz
MHz
MHz
kHz
−
−
20
MHz
−
−
10
MHz
−
−
5
MHz
Parameter
Supply voltage
Supply voltage
Input “H” voltage
Input “L” voltage
Peak sum output
“H” current
Average sum
output “H” current
Peak output “H”
current
IOH(avg)
Average output
“H” current
IOL(sum)
Peak sum output
“L” currents
Average sum
Sum of all pins IOL(avg)
output “L” currents
Peak output “L”
Except P1_0 to P1_7
currents
P1_0 to P1_7
Average output
Except P1_0 to P1_7
“L” current
P1_0 to P1_7
XIN clock input oscillation frequency
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
f(XCIN)
−
Topr = 25°C
Recommended Operating Conditions
Symbol
VCC/AVCC
VSS/AVSS
VIH
VIL
IOH(sum)
Condition
XCIN clock input oscillation frequency
System clock
OCD2 = 0
XlN clock selected
OCD2 = 1
On-chip oscillator clock
selected
Conditions
3.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 3.0 V
2.2 V ≤ VCC < 2.7 V
2.2 V ≤ VCC ≤ 5.5 V
3.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 3.0 V
2.2 V ≤ VCC < 2.7 V
FRA01 = 0
Low-speed on-chip
oscillator clock selected
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 370 of 441
Unit
V
V
V
V
mA
R8C/28 Group, R8C/29 Group
Table 20.3
20. Electrical Characteristics
A/D Converter Characteristics
Symbol
Parameter
−
Resolution
−
Absolute
accuracy
Conditions
Standard
Min.
Typ.
Max.
Unit
Vref = AVCC
−
−
10
Bits
10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±3
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±2
LSB
10-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±5
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±2
LSB
10-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±5
LSB
8-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±2
LSB
Rladder
Resistor ladder
Vref = AVCC
10
−
40
kΩ
tconv
Conversion time 10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
3.3
−
−
µs
φAD = 10 MHz, Vref = AVCC = 5.0 V
2.8
−
−
µs
2.2
−
AVCC
V
0
−
AVCC
V
0.25
−
10
MHz
8-bit mode
Vref
Reference voltage
VIA
Analog input voltage(2)
−
A/D operating
clock frequency
Without sample and hold
Vref = AVCC = 2.7 to 5.5 V
With sample and hold
Vref = AVCC = 2.7 to 5.5 V
1
−
10
MHz
Without sample and hold
Vref = AVCC = 2.2 to 5.5 V
0.25
−
5
MHz
With sample and hold
Vref = AVCC = 2.2 to 5.5 V
1
−
5
MHz
NOTES:
1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P1
P3
30pF
P4
Figure 20.1
Ports P1, P3, and P4 Timing Measurement Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 371 of 441
R8C/28 Group, R8C/29 Group
Table 20.4
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
20. Electrical Characteristics
Parameter
Program/erase endurance(2)
Conditions
Standard
Unit
Min.
Typ.
Max.
R8C/28 Group
100(3)
−
−
times
R8C/29 Group
1,000(3)
−
−
times
µs
−
Byte program time
−
50
400
−
Block erase time
−
0.4
9
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97 + CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3 + CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time(7)
20
−
−
year
Ambient temperature = 55°C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 372 of 441
R8C/28 Group, R8C/29 Group
Table 20.5
20. Electrical Characteristics
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
10,000(3)
−
−
times
Byte program time
(program/erase endurance ≤ 1,000 times)
−
50
400
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
65
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
9
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97 + CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3 + CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
-20(8)
−
85
°C
−
Data hold time(9)
20
−
−
year
−
Program/erase endurance(2)
−
Ambient temperature = 55°C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 373 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
Figure 20.2
Table 20.6
Time delay until Suspend
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet0
Voltage detection level
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(2)
Vccmin
MCU operating voltage minimum value
VCA25 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.2
2.3
2.4
V
−
0.9
−
µA
−
−
300
µs
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 20.7
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Vdet1
Parameter
Condition
Voltage detection level(4)
−
Voltage monitor 1 interrupt request generation
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
time(2)
VCA26 = 1, VCC = 5.0 V
Standard
Min.
Typ.
Max.
2.70
2.85
3.00
Unit
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
Table 20.8
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
Parameter
Condition
Voltage detection level
−
Voltage monitor 2 interrupt request generation
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
time(2)
VCA27 = 1, VCC = 5.0 V
Standard
Min.
Typ.
Max.
3.3
3.6
3.9
Unit
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 374 of 441
R8C/28 Group, R8C/29 Group
Table 20.9
20. Electrical Characteristics
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage(4)
−
−
0.1
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
−
Vdet0
V
trth
External power VCC rise gradient(2)
20
−
−
mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet0(3)
Vdet0(3)
2.2 V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
Figure 20.3
Reset Circuit Electrical Characteristics
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 375 of 441
R8C/28 Group, R8C/29 Group
Table 20.10
20. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
fOCO40M
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register(4)
−
Value in FRA1 register after reset
−
Oscillation frequency adjustment unit of highspeed on-chip oscillator
−
Oscillation stability time
−
Self power consumption at oscillation
Condition
Standard
Unit
Min.
Typ.
Max.
VCC = 4.75 to 5.25 V
0°C ≤ Topr ≤ 60°C(2)
39.2
40
40.8
MHz
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2)
38.8
40
41.2
MHz
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2)
38.4
40
41.6
MHz
VCC = 2.7 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2)
38
40
42
MHz
VCC = 2.7 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2)
37.6
40
42.4
MHz
VCC = 2.2 to 5.5 V
-20°C ≤ Topr ≤ 85°C(3)
35.2
40
44.8
MHz
VCC = 2.2 to 5.5 V
-40°C ≤ Topr ≤ 85°C(3)
34
40
46
MHz
VCC = 5.0 V ± 10%
-20°C ≤ Topr ≤ 85°C(2)
38.8
40
40.8
MHz
VCC = 5.0 V ± 10%
-40°C ≤ Topr ≤ 85°C(2)
38.4
40
40.8
MHz
−
36.864
−
MHz
-3%
−
3%
%
08h(3)
−
F7h(3)
−
Adjust FRA1 register
(value after reset) to -1
−
+0.3
−
MHz
−
10
100
µs
VCC = 5.0 V, Topr = 25°C
−
400
−
µA
VCC = 5.0 V, Topr = 25°C
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.
4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 20.11
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
30
125
250
−
Oscillation stability time
−
10
100
µs
−
Self power consumption at oscillation
−
15
−
µA
VCC = 5.0 V, Topr = 25°C
kHz
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 20.12
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
1
−
2000
µs
td(R-S)
STOP exit time(3)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 376 of 441
R8C/28 Group, R8C/29 Group
Table 20.13
Symbol
20. Electrical Characteristics
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter
Conditions
Standard
Min.
Typ.
Unit
Max.
tSUCYC
SSCK clock cycle time
4
−
−
tCYC(2)
tHI
SSCK clock “H” width
0.4
−
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC(2)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC(2)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC(2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
−
−
1
tCYC(2)
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 377 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 20.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 378 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 20.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 379 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 20.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 380 of 441
R8C/28 Group, R8C/29 Group
Table 20.14
20. Electrical Characteristics
Timing Requirements of I2C bus Interface(1)
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
Standard
Typ.
−
12tCYC + 600(2)
−
3tCYC + 300(2)
tSCLL
SCL input “L” width
500(2)
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC(2)
−
1tCYC(2)
−
tSTAH
Start condition input hold time
3tCYC(2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC(2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC(2)
−
−
ns
tSDAS
Data input setup time
−
−
ns
tSDAH
Data input hold time
1tCYC + 20(2)
0
−
−
ns
Symbol
Parameter
Condition
Min.
5tCYC +
−
−
Unit
Max.
−
ns
−
ns
−
ns
−
300
−
ns
ns
−
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 20.7
I/O Timing of I2C bus Interface
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 381 of 441
P(2)
tSDAS
tSDAH
ns
R8C/28 Group, R8C/29 Group
Table 20.15
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
Parameter
Output “H” voltage
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
XOUT
VOL
Output “L” voltage
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
XOUT
VT+-VT-
20. Electrical Characteristics
Hysteresis
Condition
IOH = -5 mA
IOH = -200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
IOL = 5 mA
IOL = 200 µA
Drive capacity HIGH
Drive capacity LOW
Drive capacity HIGH
Drive capacity LOW
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, SSI, SCL,
SDA, SSO
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
IOL = 20 mA
IOL = 5 mA
IOL = 1 mA
IOL = 500 µA
Standard
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
0.5
Max.
VCC
VCC
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
2.0
2.0
−
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
0.1
1.0
−
V
−
−
−
XIN
30
−
50
1.0
5.0
-5.0
167
−
µA
−
µA
kΩ
MΩ
XCIN
−
18
−
MΩ
1.8
−
−
V
RESET
IIH
IIL
RPULLUP
RfXIN
IOH = -20 mA
IOH = -5 mA
IOH = -1 mA
IOH = -500 µA
Min.
VCC - 2.0
VCC - 0.5
VCC - 2.0
VCC - 2.0
VCC - 2.0
VCC - 2.0
−
−
−
−
−
−
0.1
VI = 5 V, VCC = 5V
VI = 0 V, VCC = 5V
VI = 0 V, VCC = 5V
During stop mode
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 382 of 441
R8C/28 Group, R8C/29 Group
Table 20.16
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 3.3 to 5.5 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
Page 383 of 441
Min.
−
Standard
Typ.
Max.
10
17
Unit
mA
−
9
15
mA
−
6
−
mA
−
5
−
mA
−
4
−
mA
−
2.5
−
mA
−
10
15
mA
−
4
−
mA
−
5.5
10
mA
−
2.5
−
mA
−
130
300
µA
−
130
300
µA
−
30
−
µA
R8C/28 Group, R8C/29 Group
Table 20.17
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (3) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current Wait mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are open,
other pins are VSS
Stop mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 384 of 441
Min.
−
Standard
Typ.
Max.
25
75
Unit
µA
−
23
60
µA
−
4.0
−
µA
−
2.2
−
µA
−
0.8
3.0
µA
−
1.2
−
µA
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 20.18
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
25
−
25
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 20.8
Table 20.19
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.9
TRAIO Input Timing Diagram when VCC = 5 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 385 of 441
Unit
ns
ns
ns
VCC = 5 V
R8C/28 Group, R8C/29 Group
Table 20.20
20. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
−
100
−
100
−
−
50
0
−
50
−
90
−
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 5 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 20.10
Table 20.21
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 1, 3) Input
INTi input “H” width
Standard
Min.
Max.
−
250(1)
INTi input “L” width
250(2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 20.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 386 of 441
R8C/28 Group, R8C/29 Group
Table 20.22
Electrical Characteristics (3) [VCC = 3 V]
Symbol
VOH
20. Electrical Characteristics
Parameter
Output “H” voltage
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
Output “L” voltage
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Max.
VCC
Unit
V
VCC - 0.5
−
VCC
V
IOH = -1 mA
VCC - 0.5
−
VCC
V
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 5 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, SSI, SCL,
SDA, SSO
0.1
0.3
−
V
RESET
0.1
0.4
−
V
−
−
−
66
−
−
1.8
160
3.0
18
−
4.0
-4.0
500
−
−
−
µA
−
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
Hysteresis
Standard
Typ.
−
IOH = -5 mA
XOUT
VT+-VT-
IOH = -1 mA
Min.
VCC - 0.5
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
XOUT
VOL
Condition
VI = 3 V, VCC = 3V
VI = 0 V, VCC = 3V
VI = 0 V, VCC = 3V
XIN
XCIN
During stop mode
µA
kΩ
MΩ
MΩ
V
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 387 of 441
R8C/28 Group, R8C/29 Group
Table 20.23
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 388 of 441
Min.
−
Standard
Typ.
Max.
6
−
Unit
mA
−
2
−
mA
−
5
9
mA
−
2
−
mA
−
130
300
µA
−
130
300
µA
−
30
−
µA
−
25
70
µA
−
23
55
µA
−
3.8
−
µA
−
2.0
−
µA
−
0.7
3.0
µA
−
1.1
−
µA
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Table 20.24
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
100
−
40
−
40
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 20.12
Table 20.25
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.13
TRAIO Input Timing Diagram when VCC = 3 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 389 of 441
Unit
ns
ns
ns
VCC = 3 V
R8C/28 Group, R8C/29 Group
Table 20.26
20. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
−
150
−
150
−
−
80
0
−
70
−
90
−
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 3 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 20.14
Table 20.27
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 1, 3) Input
INTi input “H” width
Standard
Min.
Max.
−
380(1)
INTi input “L” width
380(2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
−
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 20.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 390 of 441
R8C/28 Group, R8C/29 Group
Table 20.28
Electrical Characteristics (5) [VCC = 2.2 V]
Symbol
VOH
20. Electrical Characteristics
Parameter
Output “H” voltage
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
Output “L” voltage
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
Feedback resistance
RAM hold voltage
Max.
VCC
V
−
VCC
V
IOH = -1 mA
VCC - 0.5
−
VCC
V
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 2 mA
−
−
0.5
V
IOL = 1 mA
−
−
0.5
V
IOL = 0.1 mA
−
−
0.5
V
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, SSI, SCL,
SDA, SSO
0.05
0.3
−
V
RESET
0.05
0.15
−
V
−
−
−
100
−
−
1.8
200
5
35
−
4.0
-4.0
600
−
−
−
µA
−
VI = 2.2 V
VI = 0 V
VI = 0 V
XIN
XCIN
During stop mode
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Unit
VCC - 0.5
Except P1_0 to P1_7,
XOUT
P1_0 to P1_7
Hysteresis
Standard
Typ.
−
IOH = -2 mA
XOUT
VT+-VT-
IOH = -1 mA
Min.
VCC - 0.5
Drive capacity
HIGH
Drive capacity
LOW
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
XOUT
VOL
Condition
Page 391 of 441
µA
kΩ
MΩ
MΩ
V
R8C/28 Group, R8C/29 Group
Table 20.29
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.2 to 2.7 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 392 of 441
Min.
−
Standard
Typ.
Max.
3.5
−
Unit
mA
−
1.5
−
mA
−
3.5
−
mA
−
1.5
−
mA
−
100
230
µA
−
100
230
µA
−
25
−
µA
−
22
60
µA
−
20
55
µA
−
3.0
−
µA
−
1.8
−
µA
−
0.7
3.0
µA
−
1.1
−
µA
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
Table 20.30
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
−
90
−
90
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 2.2 V
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Figure 20.16
Table 20.31
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
500
−
200
−
200
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.17
TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 393 of 441
Unit
ns
ns
ns
VCC = 2.2 V
R8C/28 Group, R8C/29 Group
Table 20.32
20. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
−
400
−
400
−
−
200
0
−
150
−
90
−
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 2.2 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 20.18
Table 20.33
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0, 1, 3) Input
tW(INH)
INTi input “H” width
Standard
Min.
Max.
(1)
−
1000
tW(INL)
INTi input “L” width
1000(2)
Symbol
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 20.19
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 394 of 441
R8C/28 Group, R8C/29 Group
20.2
20. Electrical Characteristics
J, K Version
Table 20.34
Absolute Maximum Ratings
Symbol
VCC/AVCC
VI
VO
Pd
Parameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Table 20.35
IOH(peak)
IOH(avg)
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
−
-40 °C ≤ Topr ≤ 85 °C
85 °C ≤ Topr ≤ 125 °C
Rated Value
-0.3 to 6.5
-0.3 to VCC + 0.3
-0.3 to VCC + 0.3
300
125
-40 to 85 (J version) /
-40 to 125 (K version)
-65 to 150
Unit
V
V
V
mW
mW
°C
°C
Recommended Operating Conditions
Symbol
VCC/AVCC
VSS/AVSS
VIH
VIL
IOH(sum)
Condition
Parameter
Supply voltage
Supply voltage
Input “H” voltage
Input “L” voltage
Peak sum output Sum of all pins
“H” current
IOH(peak)
Peak output “H”
current
Average output
“H” current
Peak sum output Sum of all pins
“L” currents
IOL(peak)
Peak output “L”
currents
Average output
“L” current
XIN clock input oscillation frequency
System clock
OCD2 = 0
XlN clock selected
OCD2 = 1
On-chip oscillator
clock selected
Conditions
3.0 V ≤ VCC ≤ 5.5 V (other than K
version)
3.0 V ≤ VCC ≤ 5.5 V (K version)
2.7 V ≤ VCC < 3.0 V
3.0 V ≤ VCC ≤ 5.5 V (other than K
version)
3.0 V ≤ VCC ≤ 5.5 V (K version)
2.7 V ≤ VCC < 3.0 V
FRA01 = 0
Low-speed on-chip oscillator clock
selected
FRA01 = 1
High-speed on-chip oscillator clock
selected (other than K version)
FRA01 = 1
High-speed on-chip oscillator clock
selected
Min.
2.7
−
0.8 VCC
0
−
Standard
Typ.
−
0
−
−
−
Max.
5.5
−
VCC
0.2 VCC
-60
−
−
-10
mA
−
−
-5
mA
−
−
60
mA
−
−
10
mA
−
−
5
mA
0
−
20
MHz
0
0
0
−
16
10
20
MHz
MHz
MHz
0
0
−
−
125
16
10
−
MHz
MHz
kHz
−
−
20
MHz
−
−
10
MHz
−
−
−
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 395 of 441
Unit
V
V
V
V
mA
R8C/28 Group, R8C/29 Group
Table 20.36
A/D Converter Characteristics
Symbol
−
−
Rladder
tconv
Vref
VIA
−
20. Electrical Characteristics
Parameter
Resolution
Absolute
accuracy
Conditions
Vref = AVCC
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 3.3 V
φAD = 10 MHz, Vref = AVCC = 3.3 V
Vref = AVCC
φAD = 10 MHz, Vref = AVCC = 5.0 V
φAD = 10 MHz, Vref = AVCC = 5.0 V
10-bit mode
8-bit mode
10-bit mode
8-bit mode
Resistor ladder
Conversion time 10-bit mode
8-bit mode
Reference voltage
Analog input voltage(2)
A/D operating
Without sample and hold
clock frequency With sample and hold
Min.
−
−
−
−
−
10
3.3
2.8
2.7
0
0.25
1
Standard
Typ.
Max.
−
10
−
±3
−
±2
−
±5
−
±2
−
40
−
−
−
−
−
AVCC
−
AVCC
−
−
10
10
Unit
Bits
LSB
LSB
LSB
LSB
kΩ
µs
µs
V
V
MHz
MHz
NOTES:
1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P1
P3
30pF
P4
Figure 20.20
Ports P1, P3, and P4 Timing Measurement Circuit
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 396 of 441
R8C/28 Group, R8C/29 Group
Table 20.37
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
−
Parameter
Program/erase endurance(2)
−
Byte program time
Block erase time
Time delay from suspend request until
suspend
Interval from erase start/restart until
following suspend request
Interval from program start/restart until
following suspend request
Time from suspend until program/erase
restart
Program, erase voltage
Read voltage
Program, erase temperature
−
Data hold time(7)
−
td(SR-SUS)
−
−
−
−
−
20. Electrical Characteristics
Conditions
Min.
Standard
Typ.
−
Unit
Max.
−
times
R8C/28 Group
100(3)
R8C/29 Group
1,000(3)
−
−
−
−
−
times
50
0.4
−
µs
650
−
400
9
97 + CPU clock
× 6 cycles
−
µs
0
−
−
ns
−
−
µs
2.7
2.7
0
20
−
3 + CPU clock
× 4 cycles
5.5
5.5
60
−
Ambient temperature = 55°C
−
−
−
s
µs
V
V
°C
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 397 of 441
R8C/28 Group, R8C/29 Group
Table 20.38
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
−
Parameter
−
Program/erase endurance(2)
Byte program time
(program/erase endurance ≤ 1,000 times)
Byte program time
(program/erase endurance > 1,000 times)
Block erase time
(program/erase endurance ≤ 1,000 times)
Block erase time
(program/erase endurance > 1,000 times)
Time delay from suspend request until
suspend
Interval from erase start/restart until
following suspend request
Interval from program start/restart until
following suspend request
Time from suspend until program/erase
restart
Program, erase voltage
Read voltage
Program, erase temperature
−
Data hold time(9)
−
−
−
−
td(SR-SUS)
−
−
−
−
−
20. Electrical Characteristics
Conditions
Min.
Unit
Max.
−
times
50
400
µs
−
65
−
µs
−
0.2
9
s
−
0.3
−
s
−
−
µs
650
−
97 + CPU clock
× 6 cycles
−
µs
0
−
−
ns
−
−
µs
2.7
2.7
−
3 + CPU clock
× 4 cycles
5.5
5.5
-40
20
−
10,000(3)
−
Ambient temperature = 55°C
Standard
Typ.
−
−
−
85(8)
−
V
V
°C
year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. 125°C for K version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 398 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
Figure 20.21
Table 20.39
Time delay until Suspend
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Vdet1
Voltage detection level(2, 4)
td(Vdet1-A)
Voltage monitor 1 reset generation time(5)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(3)
MCU operating voltage minimum value
−
td(E-A)
Vccmin
Condition
VCA26 = 1, VCC = 5.0 V
Min.
2.70
Standard
Typ.
Max.
2.85
3.0
Unit
V
−
40
200
µs
−
0.6
−
−
100
µA
−
2.70
−
−
V
µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter,
its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the
voltage passes Vdet1 when the power supply falls.
Table 20.40
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
td(Vdet2-A)
−
td(E-A)
Parameter
Voltage detection level(2)
Voltage monitor 2 reset/interrupt request generation
time(3., 5)
Voltage detection circuit self power consumption
Waiting time until voltage detection circuit operation
starts(4)
Condition
VCA27 = 1, VCC = 5.0 V
Min.
3.3
Standard
Typ.
Max.
3.6
3.9
Unit
V
−
40
200
µs
−
0.6
−
−
100
µA
−
µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
3. Time until the voltage monitor 2 reset/interrupt request is generated after the voltage passes Vdet2.
4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this time
until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 399 of 441
R8C/28 Group, R8C/29 Group
Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics(3)
Table 20.41
Symbol
Vpor1
20. Electrical Characteristics
trth
Standard
Typ.
−
Max.
0.1
0
−
Vdet1
VCC ≤ 3.6 V
20(2)
−
−
mV/msec
VCC > 3.6 V
20(2)
−
2,000
mV/msec
Condition
Power-on reset valid voltage(4)
Power-on reset or voltage monitor 1 reset valid
voltage
External power VCC rise gradient
Vpor2
Min.
−
Parameter
Unit
V
V
NOTES:
1. The measurement condition is Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the
VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet1(3)
Vdet1(3)
trth
trth
2.0 V
External
power VCC
td(Vdet1-A)
Vpor2
Vpor1
tw(por1)
Sampling time(1, 2)
Internal reset
signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection
Circuit for details.
Figure 20.22
Reset Circuit Electrical Characteristics
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 400 of 441
R8C/28 Group, R8C/29 Group
Table 20.42
20. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
fOCO40M
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
−
Value in FRA1 register after reset
Oscillation frequency adjustment unit of highspeed on-chip oscillator
Oscillation stability time
Self power consumption at oscillation
−
−
−
Condition
VCC = 4.75 to 5.25 V
0°C ≤ Topr ≤ 60°C(2)
VCC = 3.0 to 5.5 V
-20°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 to 5.5 V
-40°C ≤ Topr ≤ 125°C(2)
VCC = 2.7 to 5.5 V
-40°C ≤ Topr ≤ 125°C(2)
Adjust FRA1 register
(value after reset) to -1
Min.
39.2
Standard
Typ.
40
Max.
40.8
MHz
38.8
40
41.2
MHz
38.4
40
41.6
MHz
38
40
42
MHz
37.6
40
42.4
MHz
08h
−
−
+0.3
F7h
−
−
MHz
−
10
400
100
−
µA
VCC = 5.0 V, Topr = 25°C
−
Unit
µs
NOTES:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
Table 20.43
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
fOCO-S
−
−
Low-speed on-chip oscillator frequency
Oscillation stability time
Self power consumption at oscillation
Condition
VCC = 5.0 V, Topr = 25°C
Standard
Typ.
125
10
15
Min.
40
−
−
Max.
250
100
−
Unit
kHz
µs
µA
NOTE:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
Table 20.44
Power Supply Circuit Timing Characteristics
Symbol
Parameter
td(P-R)
Time for internal power supply stabilization during
power-on(2)
td(R-S)
STOP exit time(3)
Condition
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 401 of 441
Min.
1
−
Standard
Typ.
Max.
−
2000
−
150
Unit
µs
µs
R8C/28 Group, R8C/29 Group
Table 20.45
Symbol
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter
tSUCYC
SSCK clock cycle time
tHI
tLO
tRISE
SSCK clock “H” width
SSCK clock “L” width
SSCK clock rising
time
tFALL
20. Electrical Characteristics
SSCK clock falling
time
Conditions
Standard
Typ.
−
−
Unit
Max.
−
−
−
−
−
−
−
100
1
−
1
−
−
tCYC(2)
µs
ns
−
−
tCYC(2)
Slave
1tCYC + 50
−
−
ns
Slave
1tCYC + 50
−
−
ns
−
−
1
−
−
−
−
1.5tCYC + 100
1.5tCYC + 100
tCYC(2)
ns
ns
Master
Slave
Master
Slave
SSO, SSI data input setup time
SSO, SSI data input hold time
tLEAD
SCS setup time
tOD
SCS hold time
SSO, SSI data output delay time
tSA
tOR
SSI slave access time
SSI slave out open time
−
0.6
0.6
1
1
1
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
tCYC(2)
tSUCYC
tSUCYC
0.4
0.4
−
tSU
tH
tLAG
Min.
4
Page 402 of 441
tCYC(2)
µs
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 20.23
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 403 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 20.24
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 404 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 20.25
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 405 of 441
R8C/28 Group, R8C/29 Group
Table 20.46
20. Electrical Characteristics
Timing Requirements of I2C bus Interface(1)
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
Standard
Typ.
−
12tCYC + 600(2)
−
3tCYC + 300(2)
tSCLL
SCL input “L” width
500(2)
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC(2)
−
1tCYC(2)
−
tSTAH
Start condition input hold time
3tCYC(2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC(2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC(2)
−
−
ns
tSDAS
Data input setup time
−
−
ns
tSDAH
Data input hold time
1tCYC + 20(2)
0
−
−
ns
Symbol
Parameter
Condition
Min.
5tCYC +
−
−
Unit
Max.
−
ns
−
ns
−
ns
−
300
−
ns
ns
−
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 20.26
I/O Timing of I2C bus Interface
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 406 of 441
P(2)
tSDAS
tSDAH
ns
R8C/28 Group, R8C/29 Group
Table 20.47
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
Parameter
Output “H” voltage
Except XOUT
XOUT
VOL
Output “L” voltage
Except XOUT
XOUT
VT+-VT-
20. Electrical Characteristics
Hysteresis
Condition
IOH = -5 mA
IOH = -200 µA
Drive capacity HIGH
Drive capacity LOW
IOL = 5 mA
IOL = 200 µA
Drive capacity HIGH
Drive capacity LOW
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, SSI, SCL,
SDA, SSO
RESET
IIH
IIL
RPULLUP
RfXIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
RAM hold voltage
VI = 5 V, VCC = 5V
VI = 0 V, VCC = 5V
VI = 0 V, VCC = 5V
XIN
During stop mode
IOH = -1 mA
IOH = -500 µA
IOL = 1 mA
IOL = 500 µA
Min.
VCC - 2.0
VCC - 0.3
VCC - 2.0
VCC - 2.0
−
−
−
−
0.1
Standard
Typ.
−
−
−
−
−
−
−
−
0.5
Max.
VCC
VCC
VCC
VCC
2.0
0.45
2.0
2.0
−
Unit
V
V
V
V
V
V
V
V
V
0.1
1.0
−
V
−
−
−
30
−
50
1.0
5.0
-5.0
167
−
µA
−
µA
kΩ
MΩ
2.0
−
−
V
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 407 of 441
R8C/28 Group, R8C/29 Group
Table 20.48
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 3.3 to 5.5 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Wait mode
Stop mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
Min.
−
Standard
Typ.
Max.
10
17
Unit
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
9
15
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−
6
−
mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
5
−
mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
4
−
mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
2.5
−
mA
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz (J version)
Low-speed on-chip oscillator on = 125 kHz
No division
−
10
15
mA
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz (J version)
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
4
−
mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−
5.5
10
mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−
2.5
−
mA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−
130
300
µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
25
75
µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
−
23
60
µA
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−
0.8
3.0
µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−
1.2
−
µA
XIN clock off, Topr = 125°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
−
4.0
−
µA
Page 408 of 441
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 20.49
XIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
Standard
Min.
Max.
50
−
25
−
25
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
tC(XIN)
Unit
ns
ns
ns
VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 20.27
Table 20.50
XIN Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.28
TRAIO Input Timing Diagram when VCC = 5 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 409 of 441
Unit
ns
ns
ns
VCC = 5 V
R8C/28 Group, R8C/29 Group
Table 20.51
20. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
−
100
−
100
−
−
50
0
−
50
−
90
−
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 5 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 20.29
Table 20.52
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 1, 3) Input
INTi input “H” width
Standard
Min.
Max.
−
250(1)
INTi input “L” width
250(2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 20.30
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 410 of 441
R8C/28 Group, R8C/29 Group
Table 20.53
Electrical Characteristics (3) [VCC = 3 V]
Symbol
VOH
VOL
VT+-VT-
IIH
IIL
RPULLUP
RfXIN
VRAM
20. Electrical Characteristics
Parameter
Output “H” voltage
Except XOUT
XOUT
Output “L” voltage
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance
RAM hold voltage
IOH = -1 mA
Drive capacity
HIGH
Drive capacity
LOW
IOL = 1 mA
Drive capacity
HIGH
Drive capacity
LOW
Standard
Typ.
−
−
Max.
VCC
VCC
Unit
IOH = -0.1 mA
Min.
VCC - 0.5
VCC - 0.5
IOH = -50 µA
VCC - 0.5
−
VCC
V
V
V
−
−
IOL = 0.1 mA
−
−
0.5
0.5
V
V
IOL = 50 µA
−
−
0.5
V
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, SSI, SCL,
SDA, SSO
0.1
0.3
−
V
RESET
0.1
0.4
−
V
−
−
−
66
−
2.0
160
3.0
−
4.0
-4.0
500
−
−
µA
−
Except XOUT
XOUT
Hysteresis
Condition
VI = 3 V, VCC = 3V
VI = 0 V, VCC = 3V
VI = 0 V, VCC = 3V
XIN
During stop mode
µA
kΩ
MΩ
V
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 411 of 441
R8C/28 Group, R8C/29 Group
Table 20.54
Symbol
ICC
20. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Wait mode
Stop mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 125°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 412 of 441
Min.
−
Standard
Typ.
Max.
6
−
Unit
mA
−
2
−
mA
−
5
9
mA
−
2
−
mA
−
130
300
µA
−
25
70
µA
−
23
55
µA
−
0.7
3.0
µA
−
1.1
−
µA
−
3.8
−
µA
R8C/28 Group, R8C/29 Group
20. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
XIN Input
Table 20.55
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
tC(XIN)
Unit
ns
ns
ns
VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 20.31
XIN Input Timing Diagram when VCC = 3 V
Table 20.56
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 20.32
TRAIO Input Timing Diagram when VCC = 3 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 413 of 441
Unit
ns
ns
ns
VCC = 3 V
R8C/28 Group, R8C/29 Group
Table 20.57
20. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
−
150
−
150
−
−
80
0
−
70
−
90
−
Parameter
CLK0 input cycle time
CLK0 input “H” width
CLK0 Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 or 1
VCC = 3 V
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 or 1
Figure 20.33
Table 20.58
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 1, 3) Input
INTi input “H” width
Standard
Min.
Max.
−
380(1)
INTi input “L” width
380(2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
−
ns
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 20.34
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 414 of 441
R8C/28 Group, R8C/29 Group
21. Usage Notes
21. Usage Notes
21.1
Notes on Clock Generation Circuit
21.1.1
Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001 :
NOP
NOP
NOP
NOP
21.1.2
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
1,FMR0
FSET
I
WAIT
NOP
NOP
NOP
NOP
21.1.3
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
21.1.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 415 of 441
R8C/28 Group, R8C/29 Group
21.2
21. Usage Notes
Notes on Interrupts
21.2.1
Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
21.2.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
21.2.3
External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V), Table
20.52 (VCC = 5V), Table 20.58 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3) Input.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 416 of 441
R8C/28 Group, R8C/29 Group
21.2.4
21. Usage Notes
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 21.1 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts (2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute
two or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 21.1
Example of Procedure for Changing Interrupt Sources
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 417 of 441
R8C/28 Group, R8C/29 Group
21.2.5
21. Usage Notes
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1:
Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
POPC
FLG
; Enable interrupts
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 418 of 441
R8C/28 Group, R8C/29 Group
21.3
21.3.1
21. Usage Notes
Notes on Timers
Notes on TImer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 419 of 441
R8C/28 Group, R8C/29 Group
21.3.2
21. Usage Notes
Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-shot), the timer reloads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
21.3.2.1
Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 420 of 441
R8C/28 Group, R8C/29 Group
21.3.2.2
21. Usage Notes
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 21.2 and 21.3.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 21.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
IR bit in
TRBIC register
Primary period
(a)
Interrupt request is
acknowledged
Secondary period
Ensure sufficient time
(b)
Interrupt request
is generated
Instruction in
Interrupt
sequence interrupt routine
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 21.2
Workaround Example (a) When Timer RB interrupt is Used
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 421 of 441
R8C/28 Group, R8C/29 Group
21. Usage Notes
• Workaround example (b):
As shown in Figure 21.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
Primary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
is detected at the end of the
secondary period.
Figure 21.3
Upon detecting (i), set the secondary and
then the primary register immediately.
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
21.3.2.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 422 of 441
R8C/28 Group, R8C/29 Group
21.3.2.4
21. Usage Notes
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 423 of 441
R8C/28 Group, R8C/29 Group
21.3.3
21. Usage Notes
Notes on Timer RC
21.3.3.1
TRC Register
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.W
#XXXXh, TRC
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.W
TRC,DATA
;Read
21.3.3.2
TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.B
#XXh, TRCSR
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.B
TRCSR,DATA
;Read
21.3.3.3
Count Source Switching
• Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
21.3.3.4
Input Capture Function
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
(refer to Table 14.11 Timer RC Operation Clock).
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
21.3.3.5
TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 424 of 441
R8C/28 Group, R8C/29 Group
21.3.4
21. Usage Notes
Notes on Timer RE
21.3.4.1
Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
21.3.4.2
Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 21.4 shows a Setting Example in Real-Time Clock Mode.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 425 of 441
R8C/28 Group, R8C/29 Group
21. Usage Notes
TSTART in TRECR1 = 0
Stop timer RE operation
TCSTF in TRECR1 = 0?
TREIC ← 00h
(disable timer RE interrupt)
TRERST in TRECR1 = 1
Timer RE register
and control circuit reset
TRERST in TRECR1 = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Setting of TREIC (IR bit ← 0,
select interrupt priority level)
TSTART in TRECR1 = 1
Start timer RE operation
TCSTF in TRECR1 = 1?
Figure 21.4
Setting Example in Real-Time Clock Mode
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 426 of 441
R8C/28 Group, R8C/29 Group
21.3.4.3
21. Usage Notes
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 427 of 441
R8C/28 Group, R8C/29 Group
21.4
21. Usage Notes
Notes on Serial Interface
• When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W
00A6H,R0
; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B
#XXH,00A2H ; Write the low-order byte of U0TB register
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 428 of 441
R8C/28 Group, R8C/29 Group
21.5
21. Usage Notes
Notes on Clock Synchronous Serial Interface
21.5.1
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
21.5.2
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
21.5.2.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
21.5.2.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 429 of 441
R8C/28 Group, R8C/29 Group
21.6
21. Usage Notes
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 430 of 441
R8C/28 Group, R8C/29 Group
21.7
21. Usage Notes
Notes on A/D Converter
• Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
• After changing the A/D operating mode, select an analog input pin again.
• When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
• When using the repeat mode, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
Do not select the fOCO-F for the φAD.
• If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
• Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
• Do not enter stop mode during A/D conversion.
• Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 431 of 441
R8C/28 Group, R8C/29 Group
21.8
21. Usage Notes
Notes on Flash Memory
21.8.1
CPU Rewrite Mode
21.8.1.1
Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register.
This does not apply to EW1 mode.
21.8.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
21.8.1.3
Interrupts
Table 21.1 lists the EW0 Mode Interrupts and Table 21.2 lists the EW1 Mode Interrupts.
Table 21.1
Mode
EW0 Mode Interrupts
When Maskable Interrupt
Request is Acknowledged
Status
EW0 During auto-erasure
Any interrupt can be used by
allocating a vector in RAM
Auto-programming
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt handling starts after the
fixed period and the flash memory
restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 432 of 441
R8C/28 Group, R8C/29 Group
Table 21.2
Mode
21. Usage Notes
EW1 Mode Interrupts
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Auto-erasure is suspended after Once an interrupt request is
acknowledged, auto-programming or
td (SR-SUS) and interrupt
auto-erasure is forcibly stopped
handling is executed. Autoimmediately and the flash memory is
erasure can be restarted by
reset. Interrupt handling starts after the
setting the FMR41 bit in the
FMR4 register to 0 (erase restart) fixed period and the flash memory
restarts. Since the block during autoafter interrupt handling
erasure or the address during autocompletes.
Auto-erasure has priority and the programming is forcibly stopped, the
normal value may not be read. Execute
interrupt request
auto-erasure again and ensure it
acknowledgement is put on
completes normally.
standby. Interrupt handling is
Since the watchdog timer does not stop
executed after auto-erasure
during the command operation,
completes.
Auto-programming is suspended interrupt requests may be generated.
Reset the watchdog timer regularly
after td (SR-SUS) and interrupt
using the erase-suspend function.
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
When Maskable Interrupt
Request is Acknowledged
Status
EW1 During auto-erasure
(erase-suspend
function enabled)
During auto-erasure
(erase-suspend
function disabled)
During autoprogramming
(program suspend
function enabled)
During autoprogramming
(program suspend
function disabled)
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 433 of 441
R8C/28 Group, R8C/29 Group
21.8.1.4
21. Usage Notes
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
21.8.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
21.8.1.6
Program
Do not write additions to the already programmed address.
21.8.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
21.8.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 434 of 441
R8C/28 Group, R8C/29 Group
21.9
21. Usage Notes
Notes on Noise
21.9.1
Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
21.9.2
Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 435 of 441
R8C/28 Group, R8C/29 Group
22. Notes on On-Chip Debugger
22. Notes on On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/28 Group and R8C/29 Group take note
of the following.
(1)
(2)
(3)
(4)
(5)
Do not access the registers associated with UART1.
Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
Do not use the BRK instruction in a user system.
Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for
details.
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 436 of 441
R8C/28 Group, R8C/29 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LSSOP20-4.4x6.5-0.65
RENESAS Code
PLSP0020JB-A
MASS[Typ.]
0.1g
11
*1
E
20
HE
Previous Code
20P2F-A
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
F
1
Index mark
10
c
A1
Reference
Symbol
D
A
L
*2
A2
*3
e
bp
y
Detail F
D
E
A2
A
A1
bp
c
HE
e
y
L
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 437 of 441
Dimension in Millimeters
Min
6.4
4.3
Nom Max
6.5 6.6
4.4 4.5
1.15
1.45
0.1 0.2
0
0.17 0.22 0.32
0.13 0.15 0.2
0°
10°
6.2 6.4 6.6
0.53 0.65 0.77
0.10
0.3 0.5 0.7
R8C/28 Group, R8C/29 Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator
Appendix 2. Connection Examples between Serial Writer and On-Chip
Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2
shows a Connection Example with E8 Emulator (R0E000080KCE00).
VCC
TXD
20
2
19
3
18
R8C/28 Group
R8C/29 Group
RESET
1
4
Connect oscillation circuit(1)
5
VSS
6
7
MODE
17
16
15
14
8
13
9
12
10
11
10
TXD
7 VSS
RXD 4
1 VCC
M16C Flash Starter
(M3A-0806)
RXD
NOTE:
1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock.
Appendix Figure 2.1
Connection Example with M16C Flash Starter (M3A-0806)
VCC
Open collector buffer
4.7kΩ or more
User logic
VSS
20
2
19
3
18
4
5
6
7
4.7kΩ ±10%
14
13
12
RESET
VCC
15
14
13
9
12
10
11
7 MODE
4
2
VSS
E8 emulator
(R0E000080KCE00)
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
16
8
6
Appendix Figure 2.2
17
MODE
10
8
R8C/28 Group
R8C/29 Group
Connect oscillation circuit
(1)
1
NOTE:
1. It is not necessary to connect an oscillation circuit when
operating with the on-chip oscillator clock.
Connection Example with E8 Emulator (R0E000080KCE00)
Page 438 of 441
R8C/28 Group, R8C/29 Group
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
VCC
Connect
oscillation
circuit
20
2
19
3
18
4
VSS
5
6
7
8
R8C/28 Group
R8C/29 Group
RESET
1
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
15
14
13
12
10
11
Example of Oscillation Evaluation Circuit
Page 439 of 441
16
9
NOTE:
1. After reset, the XIN and XCIN clocks stop.
Write a program to oscillate the XIN and XCIN clocks.
Appendix Figure 3.1
17
R8C/28 Group, R8C/29 Group
Index
Index
[A]
AD ....................................................................................... 331
ADCON0 ............................................................................. 330
ADCON1 ............................................................................. 331
ADCON2 ............................................................................. 331
ADIC .................................................................................... 108
AIER .................................................................................... 123
[C]
CM0 ....................................................................................... 74
CM1 ....................................................................................... 75
CPSRF .................................................................................. 79
CSPR .................................................................................. 131
[F]
FMR0 .................................................................................. 349
FMR1 .................................................................................. 350
FMR4 .................................................................................. 351
FRA0 ..................................................................................... 77
FRA1 ..................................................................................... 77
FRA2 ..................................................................................... 78
FRA4 ..................................................................................... 78
FRA6 ..................................................................................... 78
FRA7 ..................................................................................... 78
[I]
ICCR1 ................................................................................. 283
ICCR2 ................................................................................. 284
ICDRR ................................................................................. 288
ICDRS ................................................................................. 288
ICDRT ................................................................................. 288
ICIER ................................................................................... 286
ICMR ................................................................................... 285
ICSR .................................................................................... 287
IICIC .................................................................................... 109
INT0IC ................................................................................. 110
INT1IC ................................................................................. 110
INT3IC ................................................................................. 110
INTEN ................................................................................. 117
INTF .................................................................................... 118
[K]
KIEN .................................................................................... 121
KUPIC ................................................................................. 108
[L]
LINCR ................................................................................. 315
LINST .................................................................................. 316
[O]
OCD ...................................................................................... 76
OFS ....................................................................... 25, 130, 344
[P]
P1DRR .................................................................................. 60
PDi (i = 1, 3, 4) ...................................................................... 57
Pi (i = 1, 3, 4) ......................................................................... 57
PINSR1 ......................................................................... 58, 237
PINSR2 ................................................................................. 58
PINSR3 ................................................................................. 58
PM0 ....................................................................................... 70
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 440 of 441
PM1 ....................................................................................... 70
PMR ............................................................... 59, 237, 259, 289
PRCR .................................................................................. 102
PUR0 ..................................................................................... 60
PUR1 ..................................................................................... 60
[R]
RMAD0 ................................................................................ 123
RMAD1 ................................................................................ 123
[S]
S0RIC .................................................................................. 108
S0TIC .................................................................................. 108
S1RIC .................................................................................. 108
S1TIC ................................................................................... 108
SAR ..................................................................................... 288
SSCRH ................................................................................ 252
SSCRL ................................................................................. 253
SSER ................................................................................... 255
SSMR .................................................................................. 254
SSMR2 ................................................................................ 257
SSRDR ................................................................................ 258
SSSR ................................................................................... 256
SSTDR ................................................................................ 258
SSUIC .................................................................................. 109
[T]
TRA ..................................................................................... 138
TRACR ................................................................................ 137
TRAIC .................................................................................. 108
TRAIOC ....................................... 137, 139, 142, 144, 146, 149
TRAMR ................................................................................ 138
TRAPRE .............................................................................. 138
TRBCR ................................................................................ 153
TRBIC .................................................................................. 108
TRBIOC ............................................... 154, 156, 160, 163, 167
TRBMR ................................................................................ 154
TRBOCR ............................................................................. 153
TRBPR ................................................................................ 155
TRBPRE .............................................................................. 155
TRBSC ................................................................................ 155
TRC ..................................................................................... 180
TRCCR1 ...................................................... 177, 200, 204, 209
TRCCR2 .............................................................................. 181
TRCDF ................................................................................ 182
TRCGRA ............................................................................. 180
TRCGRB ............................................................................. 180
TRCGRC ............................................................................. 180
TRCGRD ............................................................................. 180
TRCIC .................................................................................. 109
TRCIER ............................................................................... 178
TRCIOR0 ............................................................. 184, 193, 198
TRCIOR1 ............................................................. 184, 194, 199
TRCMR ................................................................................ 176
TRCOER ............................................................................. 183
TRCSR ................................................................................ 179
TRECR1 ...................................................................... 220, 226
TRECR2 ...................................................................... 221, 226
TRECSR ...................................................................... 222, 227
TREHR ................................................................................ 219
TREIC .................................................................................. 108
TREMIN ....................................................................... 218, 225
TRESEC ...................................................................... 218, 225
TREWK ................................................................................ 219
R8C/28 Group, R8C/29 Group
[U]
U0BRG ................................................................................ 234
U0C0 ................................................................................... 235
U0C1 ................................................................................... 236
U0MR .................................................................................. 234
U0RB ................................................................................... 233
U0TB ................................................................................... 233
U1BRG ................................................................................ 234
U1C0 ................................................................................... 235
U1C1 ................................................................................... 236
U1MR .................................................................................. 234
U1RB ................................................................................... 233
U1TB ................................................................................... 233
[V]
VCA1 ..................................................................................... 37
VCA2 ................................................................... 37, 38, 79, 80
VW0C .................................................................................... 39
VW1C .............................................................................. 40, 41
VW2C .................................................................................... 42
[W]
WDC .................................................................................... 130
WDTR ................................................................................. 131
WDTS .................................................................................. 131
Rev.2.10 Sep 26, 2008
REJ09B0279-0210
Page 441 of 441
Index
REVISION HISTORY
REVISION HISTORY
R8C/28 Group, R8C/29 Group Hardware Manual
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Rev.
Date
0.10
Feb 24, 2006
−
First Edition issued
0.20
Apr 27, 2006
−
“J, K version” added
1
1.1 revised
2
Table 1.1 revised
3
Table 1.2 revised
4
Figure 1.1; NOTE3 added
5
Table 1.3 and Figure 1.2 revised
6
Table 1.4 and Figure 1.3 revised
7
Figure 1.4; NOTE3 added
8
Table 1.5 revised
9
Table 1.6; NOTE2 added
13
Figure 3.1; “R5F21284JSP, R5F21284KSP” added
14
Figure 3.2; “R5F21294JSP, R5F21294KSP” added
15
Table 4.1;
0032h, 0036h, 0038h revised
NOTES 2 to 5 revised and NOTES 6 to 8 added
18
Table 4.4; 00FDh: revised
19
Table 4.5; NOTE2 added
68
Table 7.23 NOTE2 revised
101
Figure 12.1 NOTE2 deleted
126
Figure 13.1 revised
256
Figure 16.8 SS Transmit Data Register: The last NOTE1 deleted
Page
Summary
264, 268, 16.2.5.2, 16.2.5.4, 16.2.6.2; “When setting the MCU is .... the master
272
device, continuous transmit is enabled.” deleted
265, 269 Figure 16.14, Figure 16.17; NOTE2 deleted
1.00
Nov 08, 2006
326
Table 18.1 revised
337
18.7 added
393
Table 20.35; System clock Conditions: revised
413
21.1.1 revised
All pages “PRELIMINARY” deleted
1
1 “J and K versions are under development...notice.” added
2
Table 1.1 revised
3
Table 1.2 revised
4
Figure 1.1 revised
5
Table 1.3 revised
6
Table 1.4 revised
C-1
REVISION HISTORY
Rev.
Date
1.00
Nov 08, 2006
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
15
Table 4.1;
• “0000h to 003Fh” → “0000h to 002Fh” revised
• 000Fh: “000XXXXXb” → “00X11111b” revised
• 001Ch: “00h” → “00h, 10000000b” revised
• 0029h: “High-Speed On-Chip Oscillator Control Register 4, FRA4,
When shipping” added
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6, FRA6,
When shipping” added
• NOTE2 revised, NOTE3 added
16
Table 4.2; “0040h to 007Fh” → “0030h to 007Fh” revised
18
Table 4.4; 00E1h, 00E5h, 00E8h “XXh” → “00h” revised
24
Table 5.2 Table title revised
25
Figure 5.5 revised
26
5.1.1 (2), 5.1.2 (4) revised
27
Figure 5.6, Figure 5.7 revised
28
Figure 5.8 revised
29
Figure 5.9 revised
30
5.3, 5.5 revised
37
Figure 6.7; VCA2 register NOTE6 revised
39
Figure 6.8 revised
40
Figure 6.10 revised
59
Figure 7.9 revised
65
Table 7.15 revised
68
Table 7.24 revised
69
Table 7.25 revised
73
Table 10.1 NOTE5 revised
74
Figure 10.1 revised
75
Figure 10.2 revised
77
Figure 10.4 revised
78
Figure 10.5; FRA0 register NOTE2 and FRA1 register NOTE1 revised
79
Figure 10.6; FRA2 register revised, FRA4 and FRA6 registers added
80
Figure 10.5 revised
82
Figure 10.10 NOTE1 revised
83
10.2.2 revised
85
10.4.3 revised, 10.4.8 added
86
Table 10.2 revised
88
10.5.2.2, 10.5.2.3 revised
89
10.5.2.4, Table 10.3 revised
90
Figure 10.12 added
91
10.5.2.5 added, Figure 10.13 revised
C-2
REVISION HISTORY
Rev.
Date
1.00
Nov 08, 2006
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
93
10.5.3.3 revised, Figure 10.14 added
96
10.6.1 revised
97
Figure 10.17 revised
98
Figure 10.18 revised
99
Figure 10.19 revised
100
10.7.1 revised, 10.7.2 added, 10.7.4 fOCO40M deleted
101
Figure 11.1 revised
102
Figure 12.1 revised
109
Figure 12.5 NOTE3 revised
112
Table 12.5 revised
114
Figure 12.10 revised
117
Figure 12.13 revised
123
Table 12.8 revised
127
12.6.7 deleted
129
Figure 13.2 revised
132
Table 13.3 NOTE2 revised
133
14 revised
135
14.1, Figure 14.1 revised
136
Figure 14.2 revised
137
Figure 14.3 revised
138
Table 14.2, Figure 14.4 revised
139
14.1.1.1, Figure 14.5 added
140
Table 14.3 revised
141
Figure 14.6 revised
142
Table 14.4 revised
143
Figure 14.7 revised
144
Table 14.5 revised
145
Figure 14.8 revised
146
Figure 14.9 revised
147
Table 14.6 revised
148
Figure 14.10 revised
149
Figure 14.11 revised
151
14.2, Figure 14.12 revised
152
Figure 14.13 revised
153
Figure 14.14 revised
154
Figure 14.15 revised
155
Table 14.7, Figure 14.16 revised
156
14.2.1.1 added
157
Figure 14.17 added
C-3
REVISION HISTORY
Rev.
Date
1.00
Nov 08, 2006
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
158
Table 14.8 revised
159
Figure 14.18 revised
160
Figure 14.19 revised
161
Table 14.9 revised
162
Figure 14.20 revised
164
14.2.3.1 added
165
Table 14.10 revised
166
Figure 14.22 revised
167
Figure 14.23 revised
168
14.2.5 revised
184
Figure 14.38 revised
188
Figure 14.40 revised
196
Figure 14.47 revised
200
Figure 14.50 revised
204
Table 14.22 revised
205
Figure 14.54 revised
209
Table 14.24 revised
211
14.4 revised
212
Figure 14.59 revised
220
Figure 14.69 revised
232
Figure 15.6 revised
233
Figure 15.7; PMR register revised
234
Table 15.1 NOTE2 revised
236
Figure 15.8 revised
239
Table 15.4 NOTE1 revised
241
Figure 15.11 revised
249
Figure 16.3 revised
250
Figure 16.4 revised
253
Figure 16.7 revised
255
Figure 16.9 revised
278
Figure 16.23 revised
279
Figure 16.24 NOTE1 revised
281
Figure 16.26 NOTE3 revised
286
Figure 16.31 revised
289
Figure 16.32 revised
291
Figure 16.33, Figure 16.34 revised
293
Figure 16.35 revised
294
Figure 16.36 revised
C-4
REVISION HISTORY
Rev.
1.00
Date
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
Nov 08, 2006 305 to 308 Figure 16.47 revised
Figure 16.46 to Figure 16.49 figure title revised
301 to 324 17 “Sync” → “Synch” revised
312
Figure 17.2 revised
314
Figure 17.4 revised
315
Figure 17.5 revised
316
Figure 17.6 revised
317
17.4.2 (5), Figure 17.7 revised
318
Figure 17.8 revised
319
Figure 17.9 revised
320
Figure 17.10 revised
321
Figure 17.11 revised
322
17.4.4, Figure 17.12 added
323
17.5, Table 17.2 revised
325
Table 18.1 revised
326
Figure 18.1 revised
332
Figure 18.6 revised
333
18.3 revised
335
18.6 revised
336
18.7 revised
337
Table 19.1 revised
338
19.2 and Figure 19.1 NOTE1 revised
339
Figure 19.2 NOTE1 revised
341
Figure 19.4 revised
342
Table 19.3 revised
344
19.4.2.1, 19.4.2.3 revised and 19.4.2.9 deleted
346
Figure 19.5 revised
347
Figure 19.6 revised
348
Figure 19.7 revised
349
Figure 19.8 revised
352
19.4.3.1, 19.4.3.2 revised
353
19.4.3.4 revised, Figure 19.12 title revised
354
Figure 19.13 added
355
19.4.3.5 revised, Figure 19.14 title revised
356
Figure 19.15 revised
358
Table 19.6 revised
359
Figure 19.16 revised
366
19.7.1.7 deleted
367
Table 20.2 revised
C-5
REVISION HISTORY
Rev.
Date
1.00
Nov 08, 2006
1.10
May 17, 2007
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
368
Figure 20.1 figure titile revised
369
Table 20.4 revised
370
Table 20.5 revised
371
Figure 20.2 figure titile revised and Table 20.7 NOTE4 added
372
Table 20.9 revised, Figure 20.3 revised
373
Table 20.10, Table 20.11revised
379
Table 20.15 revised
380
Table 20.16 revised
381
Table 20.17 revised
384
Table 20.22 revised
385
Table 20.23 revised
389
Table 20.29 revised
392
20.2 “J and K versions are under development...notice.” added
Table 20.34, Table 20.35 revised
393
Table 20.36 revised, Figure 20.20 figure title revised
396
Figure 20.21 figure title revised
397
Table 20.41, Figure 20.22 revised
398
Table 20.42, Table 20.43 revised
404
Table 20.47 revised
405
Table 20.48 revised
408
Table 20.53 revised
409
Table 20.54 revised
412
21.1.1 revised, 21.1.2 added, 21.1.4 fOCO40M deleted
415
21.2.7 deleted
417
21.3.2 revised
424
21.6 revised
425
21.7 revised
428
21.8.1.7 deleted
430
22 (2) revised, (5) deleted
431
Appendix 1; “Diagrams showing the latest...website.” added
−
“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A164A/E, TN-16C-A165A/E, TN-16C-A166A/E,
TN-16C-A167A/E
2
Table 1.1 revised
3
Table 1.2 revised
5
Table 1.3 and Figure 1.2 revised
6
Table 1.4 and Figure 1.3 revised
7
Figure 1.4 NOTE4 added
13
Figure 3.1 revised
C-6
REVISION HISTORY
Rev.
Date
1.10
May 17, 2007
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
14
Figure 3.2 revised
18
Table 4.4 NOTE2 added
24
Figure 5.4 revised
28
5.2 and Figure 5.8 revised
29
Figure 5.9 revised
41
Figure 6.11 revised
52
Figure 7.1 revised
53
Figure 7.2 revised
62
Table 7.10 revised
73
10 and Table 10.1 revised
75
Figure 10.2 NOTE3 revised
78
Figure 10.5 FRA1 register revised
80
Figure 10.8 NOTE6 revised
81
Figure 10.9 NOTE5 revised
82
Figure 10.10 added
88
10.5.1.2 and 10.5.1.4 revised
90
Table 10.3 revised
91
10.5.2.4 and Figure 10.13 revised
92
10.5.2.5 and Figure 10.14 revised
94
Figure 10.15 revised
97
10.6.1 revised
101
10.7.1 and 10.7.2 revised
105
12.1.3.1 revised
117
12.2.1 revised
122
Table 12.6 revised
126
12.6.3 revised, 12.6.4 deleted
127
Figure 12.20 NOTE2 revised
134
14 “two 16-bit timers” → “a 16-bit timer” revised
140
Figure 14.5 revised
151
14.1.6 revised
154
Figure 14.14 TRBMR register revised
158
Figure 14.17 revised
162
Table 14.9 NOTE2 added
166
Table 14.10 revised
169 to 172 14.2.5.1 to 14.2.5.4 added
196
Table 14.18 revised
208
Table 14.22 revised
211
Figure 14.58 revised
243
Table 15.4 NOTE1 revised
C-7
REVISION HISTORY
Rev.
Date
1.10
May 17, 2007
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
244
Table 15.5 NOTE2 added
248
15.3 revised
252
Figure 16.2 NOTE4 deleted
253
Figure 16.3 NOTE4 deleted
254
Figure 16.4 NOTE2 deleted
255
Figure 16.5 NOTE1 deleted
256
Figure 16.6 NOTE2 revised and NOTE7 deleted
257
Figure 16.7 NOTE5 revised
258
Figure 16.8 Registers SSTDR and SSRDR; NOTE1 deleted
279
16.2.8.1 deleted
283
Figure 16.24 NOTE6 revised
284
Figure 16.25 NOTE5 deleted
285
Figure 16.26 NOTE7 deleted
286
Figure 16.27 NOTE3 deleted
287
Figure 16.28 NOTE7 deleted
288
Figure 16.29 Registers SAR, ICDRT, and ICDRR; NOTE1 deleted
312
16.3.8.1 deleted, 16.3.8.1 and 16.3.8.2 added
324
Figure 17.11; The flag name revised
339
18.7 revised
340
Table 19.2 revised
345
Table 19.3 revised
346
19.4.1 and 19.4.2; “td(SR-ES)” → “td(SR-SUS)” revised
347
19.4.2.4 revised
348
19.4.2.14 revised
349
Figure 19.5 NOTES 3 and 5 revised
351
Figure 19.7 NOTE5 revised
353
Figure 19.9 revised
354
Figure 19.11 revised
356
19.4.3.4 revised
357
Figure 19.13 revised
359
Figure 19.15 revised
361
Table 19.6; The register name revised
376
Table 20.10 revised
399
Table 20.39 NOTE4 added
401
Table 20.42 revised
415
21.1.1 and 21.1.2 revised
416
21.2.3 revised, 21.2.4 deleted
417
Figure 21.1 NOTE2 revised
419
21.3.1 revised
C-8
REVISION HISTORY
Rev.
1.10
2.00
Date
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
May 17, 2007 420 to 423 21.3.2.1 to 21.3.2.4 added
Mar 14, 2008
428
21.4 revised
429
21.5.1.2 and 21.5.2.1 deleted, 21.5.2.1 and 21.5.2.2 added
431
21.7 revised
438
Appendix Figure 2.1 NOTE2 deleted
439
Appendix Figure 3.1 NOTE1 revised
1, 395
1.1, 20.2 “J and K versions are ...” deleted
5
Table 1.3, Figure 1.2 revised
6
Table 1.4, Figure 1.3 revised
13, 14
Figure 3.1, Figure 3.2 revised
15
Table 4.1 “002Ch” added
16
Table 4.2 “0036h”; J, K version “0100X000b” → “0100X001b”
25, 130, Figure 5.5, Figure 13.2, Figure 19.4; “OFS Register” revised
344
61
Table 7.6 revised
64
Table 7.16 revised
65
Table 7.18 revised
73
Figure 10.1 revised
74
Figure 10.2 “Set to 0.” → “Do not set to 1.”
78
Figure 10.6 “FRA7 Register” added
83
10.2.2 revised
86
10.4.9 added
88
10.5.1.4 “... clock ...” → “... on-chip oscillator ...”
107
Table 12.2 “Reference” revised
117
12.2.1 “The INT0 pin is shared ...” deleted
Table 12.6 added
135
Table 14.1 “• fC32” deleted
136
Figure 14.1 “TSTART” → “TCSTF”
152
14.2 “The reload register and ...” deleted
Figure 14.12 revised
155
Figure 14.15 revised
159
Table 14.8; “..or P3_1” → “..or P1_3”, NOTE4 added
162, 166 Table 14.9 and Table 14.10; NOTE3 added
163
Figure 14.20 “... When write, ...” → “.. If necessary, ...”
169
14.2.5 NOTE revised
174
Table 14.12 NOTE1 added
181
Figure 14.33 revised
184
Figure 14.36; TRCIOR0: b3 revised, NOTE4 added
C-9
REVISION HISTORY
Rev.
Date
2.00
Mar 14, 2008
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
191
14.3.4 “The TRCGRA register can also select fOCO128 ...” added
Table 14.16 revised
192
Figure 14.42 revised
193
Figure 14.43; b3 revised, NOTE3 added
198
Figure 14.47 b3 revised
201
Figure 14.50 “• The CCLR bit ... 0 ...” → “• The CCLR bit ... 1 ...”
202
Table 14.20 revised
208
Table 14.22 revised
229
Figure 14.78 revised
236
Figure 15.6 “(b7-b4)” → “(b7-b6)”
247
Table 15.7 revised
253
Figure 16.3 “Cannot write to this.” → “The SOLP bit ...”
256
Figure 16.6 NOTE7 added
273
Figure 16.18 revised
287
Figure 16.28 NOTE7 added
313
Figure 17.1 revised
318
Figure 17.5 revised
319
Figure 17.6 revised
320
Figure 17.7 revised
322
Figure 17.9 revised
325
Figure 17.12 revised
337
Figure 18.10 revised
340
Table 19.1 revised
341
19.2, Figure 19.1 revised
342
Figure 19.2 revised
345
Table 19.3 NOTE1 revised
347
19.4.2.3 revised
19.4.2.9 added
349
Figure 19.5 revised
350
Figure 19.6; b6, NOTE3 revised
356
19.4.3.4 “... program commands targeting block 1 ...” added
358
19.4.3.5 “... block erase commands targeting block 1 ...” added
361
Table 19.6 revised
370, 395 Table 20.2, Table 20.35; NOTE2 revised
2.10
Sep 26, 2008
376
Table 20.10 revised, NOTE4 added
426
Figure 21.4 revised
438
Appendix Figure 2.2 revised
−
“RENESAS TECHNICAL UP DATE” reflected: TN-16C-A172A/E
29
Figure 5.9 revised
C - 10
REVISION HISTORY
Rev.
Date
2.10
Sep 26, 2008
R8C/28 Group, R8C/29 Group Hardware Manual
Description
Page
Summary
57
Figure 7.6, Figure 7.7 NOTE2 revised
136
Figure 14.1 revised
270
16.2.5.4 “When exiting transmit/receive mode .... Then, set the RE bit
to 1.” added
340
Table 19.1 NOTE1 revised
372, 398 Table 20.4, Table 20.37 NOTE2, NOTE4 revised
373, 397 Table 20.5, Table 20.38 NOTE2, NOTE5 revised
399
Table 20.39 Parameter: Voltage monitor 1 reset generation time added
NOTE5 added
Table 20.40 revised
400
Table 20.41 revised
Figure 20.22 revised
C - 11
R8C/28 Group, R8C/29 Group Hardware Manual
Publication Date:
Published by:
Rev.0.10
Rev.2.10
Feb 24, 2006
Sep 26, 2008
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
R8C/28 Group, R8C/29 Group
Hardware Manual
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
REJ09B0279-0210