RENESAS R5F212B8SNFP

REJ09B0324-0200
16
R8C/2A Group, R8C/2B Group
Hardware Manual
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
Rev.2.00
Revision Date: Nov 26, 2007
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1.
Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/2A Group, R8C/2B Group. Make sure to refer to the latest versions of
these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web
site.
Document Type
Datasheet
Description
Document Title
Document No.
REJ03B0182
Hardware overview and electrical characteristics R8C/2A Group,
R8C/2B Group
Group Datasheet
R8C/2A Group,
This hardware
Hardware manual Hardware specifications (pin assignments,
R8C/2B Group
manual
memory maps, peripheral function
Hardware Manual
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
Software manual Description of CPU instruction set
R8C/Tiny Series
REJ09B0001
Software Manual
Available from Renesas
Application note Information on using peripheral functions and
Technology Web site.
application examples
Sample programs
Information on writing programs in assembly
language and C
Renesas
Product specifications, updates on documents,
technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1)
Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2)
Notation of Numbers
The indication “b” is appended to numeric values given in binary format. However, nothing is appended to the
values of single bits. The indication “h” is appended to numeric values given in hexadecimal format. Nothing
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 1234
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7
b6
b5
b4
b3
*1
b2
b1
b0
Symbol
XXX
0
Bit Symbol
XXX0
Address
XXX
Bit Name
XXX bits
XXX1
After Reset
00h
Function
RW
1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
RW
RW
(b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(b3)
Reserved bits
Set to 0.
RW
XXX bits
Function varies according to the operating
mode.
RW
XXX4
*3
XXX5
WO
XXX6
RW
XXX7
XXX bit
*2
b1 b0
0: XXX
1: XXX
*4
RO
*1
Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2
RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3
• Reserved bit
Reserved bit. Set to specified value.
*4
• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation
ACIA
bps
CRC
DMA
DMAC
GSM
Hi-Z
IEBus
I/O
IrDA
LSB
MSB
NC
PLL
PWM
SFR
SIM
UART
VCO
Full Form
Asynchronous Communication Interface Adapter
bits per second
Cyclic Redundancy Check
Direct Memory Access
Direct Memory Access Controller
Global System for Mobile Communications
High Impedance
Inter Equipment bus
Input/Output
Infrared Data Association
Least Significant Bit
Most Significant Bit
Non-Connection
Phase Locked Loop
Pulse Width Modulation
Special Function Registers
Subscriber Identity Module
Universal Asynchronous Receiver/Transmitter
Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1
1.
Overview ......................................................................................................................................... 1
1.1
1.1.1
1.1.2
1.2
1.3
1.4
1.5
2.
Features ..................................................................................................................................................... 1
Applications .......................................................................................................................................... 1
Specifications ........................................................................................................................................ 2
Product List ............................................................................................................................................... 6
Block Diagram ....................................................................................................................................... 10
Pin Assignment ........................................................................................................................................ 11
Pin Functions ........................................................................................................................................... 15
Central Processing Unit (CPU) ..................................................................................................... 17
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.8.5
2.8.6
2.8.7
2.8.8
2.8.9
2.8.10
3.
Data Registers (R0, R1, R2, and R3) ......................................................................................................
Address Registers (A0 and A1) ...............................................................................................................
Frame Base Register (FB) .......................................................................................................................
Interrupt Table Register (INTB) ..............................................................................................................
Program Counter (PC) .............................................................................................................................
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..................................................................
Static Base Register (SB) ........................................................................................................................
Flag Register (FLG) ................................................................................................................................
Carry Flag (C) .....................................................................................................................................
Debug Flag (D) ...................................................................................................................................
Zero Flag (Z) .......................................................................................................................................
Sign Flag (S) .......................................................................................................................................
Register Bank Select Flag (B) ............................................................................................................
Overflow Flag (O) ..............................................................................................................................
Interrupt Enable Flag (I) .....................................................................................................................
Stack Pointer Select Flag (U) ..............................................................................................................
Processor Interrupt Priority Level (IPL) .............................................................................................
Reserved Bit ........................................................................................................................................
18
18
18
18
18
18
18
18
18
18
18
18
18
18
19
19
19
19
Memory ......................................................................................................................................... 20
3.1
3.2
R8C/2A Group ........................................................................................................................................ 20
R8C/2B Group ......................................................................................................................................... 21
4.
Special Function Registers (SFRs) ............................................................................................... 22
5.
Resets ........................................................................................................................................... 34
5.1
5.1.1
5.1.2
5.2
5.3
5.4
5.5
5.6
5.7
Hardware Reset .......................................................................................................................................
When Power Supply is Stable .............................................................................................................
Power On ............................................................................................................................................
Power-On Reset Function .......................................................................................................................
Voltage Monitor 0 Reset .........................................................................................................................
Voltage Monitor 1 Reset .........................................................................................................................
Voltage Monitor 2 Reset .........................................................................................................................
Watchdog Timer Reset ............................................................................................................................
Software Reset .........................................................................................................................................
A-1
37
37
37
39
40
40
40
41
41
6.
Voltage Detection Circuit .............................................................................................................. 42
6.1
6.1.1
6.1.2
6.1.3
6.2
6.3
6.4
7.
VCC Input Voltage ..................................................................................................................................
Monitoring Vdet0 ...............................................................................................................................
Monitoring Vdet1 ...............................................................................................................................
Monitoring Vdet2 ...............................................................................................................................
Voltage Monitor 0 Reset .........................................................................................................................
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset .....................................................................
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset .....................................................................
49
49
49
49
50
51
53
Programmable I/O Ports ............................................................................................................... 55
7.1
7.2
7.3
7.4
7.5
8.
Functions of Programmable I/O Ports .....................................................................................................
Effect on Peripheral Functions ................................................................................................................
Pins Other than Programmable I/O Ports ................................................................................................
Port settings .............................................................................................................................................
Unassigned Pin Handling ........................................................................................................................
55
56
56
72
89
Processor Mode ............................................................................................................................ 90
8.1
Processor Modes ...................................................................................................................................... 90
9.
Bus ................................................................................................................................................ 91
10.
Clock Generation Circuit ............................................................................................................... 93
10.1
10.2
10.2.1
10.2.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.4.9
10.5
10.5.1
10.5.2
10.5.3
10.6
10.6.1
10.7
10.7.1
10.7.2
10.7.3
10.7.4
XIN Clock .............................................................................................................................................
On-Chip Oscillator Clocks ....................................................................................................................
Low-Speed On-Chip Oscillator Clock ..............................................................................................
High-Speed On-Chip Oscillator Clock .............................................................................................
XCIN Clock ...........................................................................................................................................
CPU Clock and Peripheral Function Clock ...........................................................................................
System Clock ....................................................................................................................................
CPU Clock ........................................................................................................................................
Peripheral Function Clock (f1, f2, f4, f8, and f32) ...........................................................................
fOCO .................................................................................................................................................
fOCO40M .........................................................................................................................................
fOCO-F .............................................................................................................................................
fOCO-S .............................................................................................................................................
fOCO128 ...........................................................................................................................................
fC4 and fC32 .....................................................................................................................................
Power Control ........................................................................................................................................
Standard Operating Mode .................................................................................................................
Wait Mode ........................................................................................................................................
Stop Mode .........................................................................................................................................
Oscillation Stop Detection Function .....................................................................................................
How to Use Oscillation Stop Detection Function .............................................................................
Notes on Clock Generation Circuit .......................................................................................................
Stop Mode .........................................................................................................................................
Wait Mode ........................................................................................................................................
Oscillation Stop Detection Function .................................................................................................
Oscillation Circuit Constants ............................................................................................................
A-2
103
104
104
104
105
106
106
106
106
106
106
106
106
106
107
108
108
110
114
117
117
120
120
120
120
120
11.
Protection .................................................................................................................................... 121
12.
Interrupts ..................................................................................................................................... 122
12.1
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
12.2
12.2.1
12.2.2
12.3
12.4
12.5
12.6
12.6.1
12.6.2
12.6.3
12.6.4
12.6.5
13.
13.1
13.2
14.
Interrupt Overview ................................................................................................................................ 122
Types of Interrupts ............................................................................................................................ 122
Software Interrupts ........................................................................................................................... 123
Special Interrupts .............................................................................................................................. 124
Peripheral Function Interrupt ............................................................................................................ 124
Interrupts and Interrupt Vectors ........................................................................................................ 125
Interrupt Control ............................................................................................................................... 127
INT Interrupt ......................................................................................................................................... 136
INTi Interrupt (i = 0 to 3) .................................................................................................................. 136
INTi Input Filter (i = 0 to 3) .............................................................................................................. 139
Key Input Interrupt ................................................................................................................................ 140
Address Match Interrupt ........................................................................................................................ 142
Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and
I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) ................................ 144
Notes on Interrupts ................................................................................................................................ 146
Reading Address 00000h .................................................................................................................. 146
SP Setting .......................................................................................................................................... 146
External Interrupt and Key Input Interrupt ....................................................................................... 146
Changing Interrupt Sources .............................................................................................................. 147
Changing Interrupt Control Register Contents ................................................................................. 148
Watchdog Timer .......................................................................................................................... 149
Count Source Protection Mode Disabled .............................................................................................. 153
Count Source Protection Mode Enabled ............................................................................................... 154
Timers ......................................................................................................................................... 155
14.1
Timer RA ...............................................................................................................................................
14.1.1 Timer Mode ......................................................................................................................................
14.1.2 Pulse Output Mode ...........................................................................................................................
14.1.3 Event Counter Mode .........................................................................................................................
14.1.4 Pulse Width Measurement Mode ......................................................................................................
14.1.5 Pulse Period Measurement Mode .....................................................................................................
14.1.6 Notes on Timer RA ...........................................................................................................................
14.2
Timer RB ...............................................................................................................................................
14.2.1 Timer Mode ......................................................................................................................................
14.2.2 Programmable Waveform Generation Mode ....................................................................................
14.2.3 Programmable One-shot Generation Mode ......................................................................................
14.2.4 Programmable Wait One-Shot Generation Mode .............................................................................
14.2.5 Notes on Timer RB ...........................................................................................................................
14.3
Timer RC ...............................................................................................................................................
14.3.1 Overview ...........................................................................................................................................
14.3.2 Registers Associated with Timer RC ................................................................................................
14.3.3 Common Items for Multiple Modes .................................................................................................
14.3.4 Timer Mode (Input Capture Function) .............................................................................................
14.3.5 Timer Mode (Output Compare Function) .........................................................................................
14.3.6 PWM Mode .......................................................................................................................................
A-3
158
161
163
165
167
170
173
174
178
181
183
187
191
195
195
197
207
213
218
224
14.3.7 PWM2 Mode .....................................................................................................................................
14.3.8 Timer RC Interrupt ...........................................................................................................................
14.3.9 Notes on Timer RC ...........................................................................................................................
14.4
Timer RD ...............................................................................................................................................
14.4.1 Count Sources ...................................................................................................................................
14.4.2 Buffer Operation ...............................................................................................................................
14.4.3 Synchronous Operation .....................................................................................................................
14.4.4 Pulse Output Forced Cutoff ..............................................................................................................
14.4.5 Input Capture Function .....................................................................................................................
14.4.6 Output Compare Function ................................................................................................................
14.4.7 PWM Mode .......................................................................................................................................
14.4.8 Reset Synchronous PWM Mode .......................................................................................................
14.4.9 Complementary PWM Mode ............................................................................................................
14.4.10 PWM3 Mode .....................................................................................................................................
14.4.11 Timer RD Interrupt ...........................................................................................................................
14.4.12 Notes on Timer RD ...........................................................................................................................
14.5
Timer RE ...............................................................................................................................................
14.5.1 Real-Time Clock Mode ....................................................................................................................
14.5.2 Output Compare Mode .....................................................................................................................
14.5.3 Notes on Timer RE ...........................................................................................................................
14.6
Timer RF ...............................................................................................................................................
14.6.1 Input Capture Mode ..........................................................................................................................
14.6.2 Output Compare Mode .....................................................................................................................
14.6.3 Notes on Timer RF ...........................................................................................................................
15.
Serial Interface ............................................................................................................................ 374
15.1
Clock Synchronous Serial I/O Mode .....................................................................................................
15.1.1 Polarity Select Function ....................................................................................................................
15.1.2 LSB First/MSB First Select Function ...............................................................................................
15.1.3 Continuous Receive Mode ................................................................................................................
15.2
Clock Asynchronous Serial I/O (UART) Mode ....................................................................................
15.2.1 Bit Rate .............................................................................................................................................
15.3
Notes on Serial Interface .......................................................................................................................
16.
229
235
236
237
242
243
245
246
248
263
281
295
306
321
335
337
343
344
352
358
361
366
369
373
381
385
385
386
387
392
393
Clock Synchronous Serial Interface ............................................................................................ 394
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.5
16.2.6
16.2.7
16.2.8
16.3
16.3.1
16.3.2
16.3.3
Mode Selection ......................................................................................................................................
Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................
Transfer Clock ..................................................................................................................................
SS Shift Register (SSTRSR) .............................................................................................................
Interrupt Requests .............................................................................................................................
Communication Modes and Pin Functions .......................................................................................
Clock Synchronous Communication Mode ......................................................................................
Operation in 4-Wire Bus Communication Mode ..............................................................................
SCS Pin Control and Arbitration ......................................................................................................
Notes on Clock Synchronous Serial I/O with Chip Select ...............................................................
I2C bus Interface ....................................................................................................................................
Transfer Clock ..................................................................................................................................
Interrupt Requests .............................................................................................................................
I2C bus Interface Mode .....................................................................................................................
A-4
394
395
404
406
407
408
409
416
422
423
424
434
435
436
16.3.4
16.3.5
16.3.6
16.3.7
16.3.8
17.
447
450
454
455
456
Hardware LIN .............................................................................................................................. 457
17.1
17.2
17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
17.5
17.6
18.
Clock Synchronous Serial Mode ......................................................................................................
Examples of Register Setting ............................................................................................................
Noise Canceller .................................................................................................................................
Bit Synchronization Circuit ..............................................................................................................
Notes on I2C bus Interface ................................................................................................................
Features .................................................................................................................................................
Input/Output Pins ..................................................................................................................................
Register Configuration ..........................................................................................................................
Functional Description ..........................................................................................................................
Master Mode .....................................................................................................................................
Slave Mode .......................................................................................................................................
Bus Collision Detection Function .....................................................................................................
Hardware LIN End Processing .........................................................................................................
Interrupt Requests ..................................................................................................................................
Notes on Hardware LIN ........................................................................................................................
457
458
459
461
461
464
468
469
470
471
A/D Converter ............................................................................................................................. 472
18.1
18.2
18.3
18.4
18.5
18.6
18.7
One-Shot Mode .....................................................................................................................................
Repeat Mode 0 .......................................................................................................................................
Sample and Hold ...................................................................................................................................
A/D Conversion Cycles .........................................................................................................................
Internal Equivalent Circuit of Analog Input ..........................................................................................
Output Impedance of Sensor under A/D Conversion ............................................................................
Notes on A/D Converter ........................................................................................................................
477
480
483
483
484
485
486
19.
D/A Converter ............................................................................................................................. 487
20.
Flash Memory ............................................................................................................................. 489
20.1
20.2
20.3
20.3.1
20.3.2
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.5
20.5.1
20.6
20.6.1
20.7
20.7.1
Overview ...............................................................................................................................................
Memory Map .........................................................................................................................................
Functions to Prevent Rewriting of Flash Memory ................................................................................
ID Code Check Function ..................................................................................................................
ROM Code Protect Function ............................................................................................................
CPU Rewrite Mode ...............................................................................................................................
EW0 Mode ........................................................................................................................................
EW1 Mode ........................................................................................................................................
Software Commands .........................................................................................................................
Status Registers .................................................................................................................................
Full Status Check ..............................................................................................................................
Standard Serial I/O Mode ......................................................................................................................
ID Code Check Function ..................................................................................................................
Parallel I/O Mode ..................................................................................................................................
ROM Code Protect Function ............................................................................................................
Notes on Flash Memory ........................................................................................................................
CPU Rewrite Mode ...........................................................................................................................
A-5
489
490
492
492
493
494
495
495
504
509
510
512
512
516
516
517
517
21.
Electrical Characteristics ............................................................................................................ 520
22.
Usage Notes ............................................................................................................................... 545
22.1
22.1.1
22.1.2
22.1.3
22.1.4
22.2
22.2.1
22.2.2
22.2.3
22.2.4
22.2.5
22.3
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
22.3.6
22.4
22.5
22.5.1
22.5.2
22.6
22.7
22.8
22.8.1
22.9
22.9.1
Notes on Clock Generation Circuit ....................................................................................................... 545
Stop Mode ......................................................................................................................................... 545
Wait Mode ........................................................................................................................................ 545
Oscillation Stop Detection Function ................................................................................................. 545
Oscillation Circuit Constants ............................................................................................................ 545
Notes on Interrupts ................................................................................................................................ 546
Reading Address 00000h .................................................................................................................. 546
SP Setting .......................................................................................................................................... 546
External Interrupt and Key Input Interrupt ....................................................................................... 546
Changing Interrupt Sources .............................................................................................................. 547
Changing Interrupt Control Register Contents ................................................................................. 548
Notes on Timers .................................................................................................................................... 549
Notes on Timer RA ........................................................................................................................... 549
Notes on Timer RB ........................................................................................................................... 550
Notes on Timer RC ........................................................................................................................... 554
Notes on Timer RD ........................................................................................................................... 555
Notes on Timer RE ........................................................................................................................... 561
Notes on Timer RF ........................................................................................................................... 564
Notes on Serial Interface ....................................................................................................................... 565
Notes on Clock Synchronous Serial Interface ....................................................................................... 566
Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 566
Notes on I2C bus Interface ................................................................................................................ 566
Notes on Hardware LIN ........................................................................................................................ 567
Notes on A/D Converter ........................................................................................................................ 568
Notes on Flash Memory ........................................................................................................................ 569
CPU Rewrite Mode ........................................................................................................................... 569
Notes on Noise ...................................................................................................................................... 572
Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ............................................................................................................................................ 572
22.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 572
23.
Notes on On-Chip Debugger ...................................................................................................... 573
24.
Notes on Emulator Debugger ..................................................................................................... 574
Appendix 1. Package Dimensions ........................................................................................................ 575
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 577
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 578
Index ..................................................................................................................................................... 579
A-6
SFR Page Reference
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
NOTE:
1.
Register
Symbol
Page
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
PM0
PM1
CM0
CM1
MSTCR
Protect Register
PRCR
121
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
98
151
151
151
143
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
143
143
Count Source Protection Mode Register
90
90
96
97
198, 250,
265, 283,
297, 308,
323, 396,
426
CSPR
152
High-Speed On-Chip Oscillator Control Register 0 FRA0
High-Speed On-Chip Oscillator Control Register 1 FRA1
High-Speed On-Chip Oscillator Control Register 2 FRA2
99
99
100
Clock Prescaler Reset Flag
101
CPSRF
High-Speed On-Chip Oscillator Control Register 6 FRA6
High-Speed On-Chip Oscillator Control Register 7 FRA7
100
100
Voltage Detection Register 1
Voltage Detection Register 2
VCA1
VCA2
45
45, 101
Voltage Monitor 1 Circuit Control Register
Voltage Monitor 2 Circuit Control Register
Voltage Monitor 0 Circuit Control Register
VW1C
VW2C
VW0C
47
48
46
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
The blank regions are reserved. Do not access locations in these
regions.
B-1
Register
Symbol
Page
Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
128
128
128
127
127
127
127
SSU/IIC Interrupt Control Register
Compare 1 Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
SSUIC/IICIC
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
128
127
127
127
127
127
129
127
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer RF Interrupt Control Register
Compare 0 Interrupt Control Register
INT0 Interrupt Control Register
A/D Conversion Interrupt Control Register
Capture Interrupt Control Register
TRBIC
INT1IC
INT3IC
TRFIC
CMP0IC
INT0IC
ADIC
CAPIC
127
129
129
127
127
129
127
127
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
NOTE:
1.
Register
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
Symbol
U0MR
U0BRG
U0TB
Page
377
377
378
UART0 Transmit / Receive Control Register 0 U0C0
UART0 Transmit / Receive Control Register 1 U0C1
UART0 Receive Buffer Register
U0RB
378
379
379
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
377
377
378
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
378
379
379
SS Control Register H / IIC bus Control Register 1
SS Control Register L / IIC bus Control Register 2
SS Mode Register / IIC bus Mode Register
SS Enable Register / IIC bus Interrupt Enable
Register
SS Status Register / IIC bus Status Register
SS Mode Register 2 / Slave Address Register
SS Transmit Data Register/IIC Bus Transmit
Data Register
SS Receive Data Register/IIC Bus Receive
Data Register
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
397, 427
398, 428
399, 429
400, 430
SSSR/ICSR
SSMR2/SAR
SSTDR/ICDRT
401, 431
402, 432
403, 432
SSRDR/ICDRR
403, 433
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
The blank regions are reserved. Do not access locations in these
regions.
B-2
Register
Symbol
Page
D/A Register 0
DA0
488
D/A Register 1
DA1
488
D/A Control Register
DACON
488
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
69
69
68
68
69
69
68
68
69
69
68
68
69
Port P6 Direction Register
PD6
68
Port P2 Drive Capacity Control Register
UART1 Function Select Register
P2DRR
U1SR
70
380
Port Mode Register
PMR
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
INTEN
INTF
KIEN
PUR0
PUR1
70, 136, 380,
403, 433
137
138
141
71
71
Address
Register
0100h Timer RA Control Register
0101h Timer RA I/O Control Register
Symbol
TRACR
TRAIOC
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
TRBMR
TRBPRE
TRBSC
TRBPR
0118h
Timer RE Second Data Register / Counter
Data Register
Timer RE Minute Data Register / Compare
Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Clock Source Select Register
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
NOTE:
1.
Page
159
159, 161, 164,
166, 168, 171
160
160
160
459
459
460
175
175
176, 178, 182,
184, 189
176
177
177
177
Address
Register
0130h Timer RC Control Register 2
0131h Timer RC Digital Filter Function Select
Register
0132h Timer RC Output Master Enable Register
0133h
0134h
0135h
0136h
0137h Timer RD Start Register
346, 354
TREMIN
346, 354
TREHR
TREWK
TRECR1
TRECR2
TRECSR
347
347
348, 355
349, 355
350, 356
Timer RC Mode Register
Timer RC Control Register 1
TRCMR
TRCCR1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
198
199, 222, 226,
231
200
201
206, 215, 220
206, 216, 221
202
Timer RC General Register A
TRCGRA
202
Timer RC General Register B
TRCGRB
202
Timer RC General Register C
TRCGRC
202
Timer RC General Register D
TRCGRD
202
The blank regions are reserved. Do not access locations in these
regions.
Page
203
204
TRCOER
205
TRDSTR
0138h
Timer RD Mode Register
TRDMR
0139h
013Ah
Timer RD PWM Mode Register
Timer RD Function Control Register
TRDPMR
TRDFCR
013Bh
Timer RD Output Master Enable Register 1
TRDOER1
013Ch
Timer RD Output Master Enable Register 2
TRDOER2
013Dh
013Eh
TRDOCR
TRDDF0
TRDDF1
254
0140h
Timer RD Output Control Register
Timer RD Digital Filter Function Select
Register 0
Timer RD Digital Filter Function Select
Register 1
Timer RD Control Register 0
251, 266, 284,
298, 309, 324
251, 266, 284,
298, 310, 325
252, 267, 285
253, 268, 286,
299, 311, 326
269, 287, 300,
312, 327
269, 287, 300,
312, 327
270, 288, 328
254
0141h
0142h
0143h
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
0144h
Timer RD Interrupt Enable Register 0
0145h
Timer RD PWM Mode Output Level Control
Register 0
Timer RD Counter 0
013Fh
TRESEC
Symbol
TRCCR2
TRCDF
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
B-3
255, 271, 288,
301, 313, 329
TRDIORA0
256, 272
TRDIORC0
257, 273
TRDSR0
258, 274, 289,
302, 314, 330
TRDIER0
259, 275, 290,
303, 315, 331
TRDPOCR0
291
TRD0
259, 276, 291,
303, 316, 331
Timer RD General Register A0
TRDGRA0
260, 276, 292,
304, 316, 332
Timer RD General Register B0
TRDGRB0
260, 276, 292,
304, 316, 332
Timer RD General Register C0
TRDGRC0
260, 276, 292,
304, 332
Timer RD General Register D0
TRDGRD0
260, 276, 292,
304, 316, 332
Timer RD Control Register 1
TRDCR1
0151h
0152h
0153h
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
0154h
Timer RD Interrupt Enable Register 1
0155h
Timer RD PWM Mode Output Level Control
Register 1
Timer RD Counter 1
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
TRDCR0
255, 271, 288,
313
TRDIORA1
256, 272
TRDIORC1
257, 273
TRDSR1
258, 274, 289,
302, 314, 330
TRDIER1
259, 275, 290,
303, 315, 331
TRDPOCR1
291
TRD1
259, 276, 291,
316
Timer RD General Register A1
TRDGRA1
260, 276, 292,
304, 316, 332
Timer RD General Register B1
TRDGRB1
260, 276, 292,
304, 316, 332
Timer RD General Register C1
TRDGRC1
260, 276, 292,
304, 316, 332
Timer RD General Register D1
TRDGRD1
260, 276, 292,
304, 316, 332
Address
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
NOTE:
1.
Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
Symbol
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
Page
377
377
378
378
379
379
Address
Register
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4
01B4h
01B5h Flash Memory Control Register 1
01B6h
01B7h Flash Memory Control Register 0
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
The blank regions are reserved. Do not access locations in these
regions.
B-4
Symbol
Page
FMR4
500
FMR1
499
FMR0
498
Address
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
NOTE:
1.
Register
Symbol
Page
Address
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
The blank regions are reserved. Do not access locations in these
regions.
B-5
Register
Symbol
Page
Address
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
NOTE:
1.
Register
Timer RF Register
Symbol
TRF
Page
363
Timer RF Control Register 0
Timer RF Control Register 1
Capture / Compare 0 Register
TRFCR0
TRFCR1
TRFM0
364
365
363
Compare 1 Register
TRFM1
363
Address
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
The blank regions are reserved. Do not access locations in these
regions.
B-6
Register
Symbol
Page
A/D Register 0
AD0
474
A/D Control Register 2
ADCON2
474
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
475
476
Address
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
FFFFh
NOTE:
1.
Register
Symbol
Page
Port P8 Direction Register
PD8
68
Port P8 Register
P8
69
Pull-Up Control Register 2
PUR2
71
Timer RF Output Control Register
TRFOUT
365
Option Function Select Register
OFS
36, 152, 493
The blank regions are reserved. Do not access locations in these
regions.
B-7
R8C/2A Group, R8C/2B Group
RENESAS MCU
1.
REJ09B0324-0200
Rev.2.00
Nov 26, 2007
Overview
1.1
Features
The R8C/2A Group and R8C/2B Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2B Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2A Group and R8C/2B Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 1 of 580
R8C/2A Group, R8C/2B Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2A Group and Tables 1.3 and 1.4 outlines the
Specifications for R8C/2B Group.
Table 1.1
Item
CPU
Specifications for R8C/2A Group (1)
Function
Central processing
unit
Memory
Power Supply
Voltage
Detection
I/O Ports
ROM, RAM
Voltage detection
circuit
Clock
Clock generation
circuits
Programmable I/O
ports
Interrupts
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RF
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.5 Product List for R8C/2A Group.
• Power-on reset
• Voltage detection 2
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Page 2 of 580
R8C/2A Group, R8C/2B Group
Table 1.2
1. Overview
Specifications for R8C/2A Group (2)
Item
Function
Serial
UART0, UART1,
Interface
UART2
Clock Synchronous Serial I/O with
Chip Select (SSU)
I2C bus(1)
LIN Module
A/D Converter
D/A Converter
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 3
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function
8-bit resolution × 2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 3 of 580
R8C/2A Group, R8C/2B Group
Table 1.3
Item
CPU
1. Overview
Specifications for R8C/2B Group (1)
Function
Central processing
unit
Memory
Power Supply
Voltage
Detection
I/O Ports
ROM, RAM
Voltage detection
circuit
Clock
Clock generation
circuits
Programmable I/O
ports
Interrupts
Watchdog Timer
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
Timer RF
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.6 Product List for R8C/2B Group.
• Power-on reset
• Voltage detection 2
• Input-only: 2 pins
• CMOS I/O ports: 55, selectable pull-up resistor
• High current drive ports: 8
3 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment function),
XCIN clock oscillation circuit (32 kHz)
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• External: 5 sources, Internal: 23 sources, Software: 4 sources
• Priority levels: 7 levels
15 bits × 1 (with prescaler), reset start selectable
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
16 bits × 1 (with capture/compare register pin and compare register pin)
Input capture mode, output compare mode
Page 4 of 580
R8C/2A Group, R8C/2B Group
Table 1.4
1. Overview
Specifications for R8C/2B Group (2)
Item
Function
Serial
UART0, UART1,
Interface
UART2
Clock Synchronous Serial I/O with
Chip Select (SSU)
I2C bus(1)
LIN Module
A/D Converter
D/A Converter
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 3
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function
8-bit resolution × 2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
12 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
5.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
2.1 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
0.65 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version)(2)
-20 to 105°C (Y version)(3)
64-pin LQFP
• Package code: PLQP0064KB-A (previous code: 64P6Q-A)
• Package code: PLQP0064GA-A (previous code: 64P6U-A)
64-pin FLGA
• Package code: PTLG0064JA-A (previous code: 64F0G)
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D version if D version functions are to be used.
3. Please contact Renesas Technology sales offices for the Y version.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 5 of 580
R8C/2A Group, R8C/2B Group
1.2
1. Overview
Product List
Table 1.5 lists Product List for R8C/2A Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2A Group, Table 1.6 lists Product List for R8C/2B Group, and Figure 1.2 shows a Part Number, Memory
Size, and Package of R8C/2B Group.
Table 1.5
Product List for R8C/2A Group
Part No.
R5F212A7SNFP
R5F212A7SNFA
R5F212A7SNLG
R5F212A8SNFP
R5F212A8SNFA
R5F212A8SNLG
R5F212AASNFP
R5F212AASNFA
R5F212AASNLG
R5F212ACSNFP
R5F212ACSNFA
R5F212ACSNLG
R5F212A7SDFP
R5F212A7SDFA
R5F212A8SDFP
R5F212A8SDFA
R5F212AASDFP
R5F212AASDFA
R5F212ACSDFP
R5F212ACSDFA
R5F212A7SNXXXFP
R5F212A7SNXXXFA
R5F212A7SNXXXLG
R5F212A8SNXXXFP
R5F212A8SNXXXFA
R5F212A8SNXXXLG
R5F212AASNXXXFP
R5F212AASNXXXFA
R5F212AASNXXXLG
R5F212ACSNXXXFP
R5F212ACSNXXXFA
R5F212ACSNXXXLG
R5F212A7SDXXXFP
R5F212A7SDXXXFA
R5F212A8SDXXXFP
R5F212A8SDXXXFA
R5F212AASDXXXFP
R5F212AASDXXXFA
R5F212ACSDXXXFP
R5F212ACSDXXXFA
ROM Capacity
48 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
128 Kbytes
48 Kbytes
48 Kbytes
64 Kbytes
64 Kbytes
96 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
RAM Capacity
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
NOTE:
1. The user ROM is programmed before shipment.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 6 of 580
Current of Nov. 2007
Package Type
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLTG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N version
D version
N version
D version
Factory
programming
product(1)
R8C/2A Group, R8C/2B Group
Part No.
1. Overview
R 5 F 21 2A 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2A Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
Figure 1.1
Part Number, Memory Size, and Package of R8C/2A Group
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 7 of 580
R8C/2A Group, R8C/2B Group
Table 1.6
1. Overview
Product List for R8C/2B Group
Part No.
R5F212B7SNFP
R5F212B7SNFA
R5F212B7SNLG
R5F212B8SNFP
R5F212B8SNFA
R5F212B8SNLG
R5F212BASNFP
R5F212BASNFA
R5F212BASNLG
R5F212BCSNFP
R5F212BCSNFA
R5F212BCSNLG
R5F212B7SDFP
R5F212B7SDFA
R5F212B8SDFP
R5F212B8SDFA
R5F212BASDFP
R5F212BASDFA
R5F212BCSDFP
R5F212BCSDFA
R5F212B7SNXXXFP
R5F212B7SNXXXFA
R5F212B7SNXXXLG
R5F212B8SNXXXFP
R5F212B8SNXXXFA
R5F212B8SNXXXLG
R5F212BASNXXXFP
R5F212BASNXXXFA
R5F212BASNXXXLG
R5F212BCSNXXXFP
R5F212BCSNXXXFA
R5F212BCSNXXXLG
R5F212B7SDXXXFP
R5F212B7SDXXXFA
R5F212B8SDXXXFP
R5F212B8SDXXXFA
R5F212BASDXXXFP
R5F212BASDXXXFA
R5F212BCSDXXXFP
R5F212BCSDXXXFA
ROM Capacity
Program ROM Data flash
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
96 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
128 Kbytes
1 Kbyte × 2
NOTE:
1. The user ROM is programmed before shipment.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 8 of 580
Current of Nov. 2007
RAM
Capacity
Package Type
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
7.5 Kbytes
2.5 Kbytes
2.5 Kbytes
3 Kbytes
3 Kbytes
7 Kbytes
7 Kbytes
7.5 Kbytes
7.5 Kbytes
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PTLG0064JA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N version
D version
N version
D version
Factory
programming
product(1)
R8C/2A Group, R8C/2B Group
Part No.
1. Overview
R 5 F 21 2B 7 S N XXX FP
Package type:
FP: PLQP0064KB-A (0.5 mm pin-pitch, 10 mm square body)
FA: PLQP0064GA-A (0.8 mm pin-pitch, 14 mm square body)
LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
Y: Operating ambient temperature -20°C to 105°C (1)
S: Low-voltage version
ROM capacity
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/2B Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
NOTE:
1: Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Part Number, Memory Size, and Package of R8C/2B Group
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 9 of 580
R8C/2A Group, R8C/2B Group
1.3
1. Overview
Block Diagram
Figure 1.3 shows a Block Diagram.
I/O ports
8
8
8
8
Port P0
Port P1
Port P2
Port P3
3
2
5
Port P4
Port P5
LIN module
Watchdog timer
(15 bits)
A/D converter
(10 bits × 12 channels)
D/A converter
(8 bits × 2)
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
A0
A1
FB
SB
Memory
ROM(1)
USP
ISP
INTB
RAM(2)
PC
FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.3
Block Diagram
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 10 of 580
7
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
I2C bus or SSU
(8 bits × 1)
Port P8
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
Timer RF (16 bits × 1)
System clock
generation circuit
8
UART or
clock synchronous serial I/O
(8 bits × 3)
Timers
Port P6
Peripheral functions
R8C/2A Group, R8C/2B Group
1.4
1. Overview
Pin Assignment
P8_1/TRFO01
P8_0/TRFO00
P6_0/TREO
P4_5/INT0
P6_6/INT2/TXD1
P6_7/INT3/RXD1
P6_5/(CLK1)/CLK2 (2)
P6_4/RXD2
P6_3/TXD2
P3_1/TRBO
P3_0/TRAO
P3_6/(INT1)(2)
P3_2/(INT2)(2)
P1_3/Kl3/AN11
P1_2/Kl2/AN10
P1_1/Kl1/AN9
Figure 1.4 shows 64-pin LQFP Package Pin Assignment (Top View). Figure 1.5 shows 64-pin FLGA Package Pin
Assignment (Top Perspective View). Tables 1.7 and 1.8 outlines the Pin Name Information by Pin Number.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
R8C/2A Group
R8C/2B Group
56
57
58
59
25
24
23
22
PLQP0064KB-A(64P6Q-A)
PLQP0064GA-A(64P6U-A)
(top view)
60
61
62
21
20
19
8
9
P4_4/XCOUT
RESET
P4_7/XOUT (1)
VSS/AVSS
P4_6/XIN
P8_2/TRFO02
P8_3/TRFO10/TRFI
P8_4/TRFO11
P8_5/TRFO12
P8_6
P1_4/TXD0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0
P1_7/TRAIO/INT1
P2_0/TRDIOA0/TRDCLK
P2_1/TRDIOB0
P2_2/TRDIOC0
P2_3/TRDIOD0
P2_4/TRDIOA1
P2_5/TRDIOB1
P2_6/TRDIOC1
10 11 12 13 14 15 16
P2_7/TRDIOD1
7
P5_0/TRCCLK
6
P5_1/TRCIOA/TRCTRG
5
P5_2/TRCIOB
4
P5_3/TRCIOC
3
P5_4/TRCIOD
2
VCC/AVCC
1
P4_3/XCIN
17
MODE
18
64
P3_3/SSI
63
P3_4/SDA/SCS
P1_0/Kl0/AN8
P0_0/AN7
P0_1/AN6
P0_2/AN5
P0_3/AN4
P0_4/AN3
P6_2
P6_1
P0_5/AN2/CLK1
P0_6/AN1/DA0
VSS/AVSS
P0_7/AN0/DA1
VREF
VCC/AVCC
P3_7/SSO
P3_5/SCL/SSCK
NOTES:
1. P4_7/XOUT are an input-only port.
2. Can be assigned to the pin in parentheses by a program.
3. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4
64-pin LQFP Package Pin Assignment (Top View)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 11 of 580
R8C/2A Group, R8C/2B Group
A
8
7
6
5
2
B
C
D
E
F
G
H
P3_3/SSI
P0_1/AN6
P5_0/
TRCCLK
P0_6/AN1/ P6_0/TREO
DA0
P3_4/SDA/
SCS
P0_0/AN7
P5_2/
TRCIOB
P0_7/AN0/
DA1
VREF
P3_0/TRAO P6_5/CLK2/
(CLK1)(2)
P5_3/
TRCIOC
MODE
P3_7/SSO
P0_4/AN3
P6_1
P0_5/AN2/
CLK1
P3_6/
(INT1)(2)
P3_1/TRBO
P4_3/XCIN
P3_5/SCL/
SSCK
P6_2
P3_2/
(INT2)(2)
P6_3/TXD2
P1_3/KI3/
AN11
VCC/AVCC
P4_7/
XOUT(1)
RESET P8_3/
P6_4/RXD2
TRFO10/TRFI
P1_2/KI2/
AN10
P4_4/XCOUT P2_5/
TRDIOB1
4
3
1. Overview
P5_4/
TRCIOD
VSS/AVSS
VCC/AVCC
VSS/AVSS
P5_1/TRCIOA/ P4_6/XIN
TRCTRG
1
P2_7/
TRDIOD1
A
B
P2_3/
P1_7/TRAIO/ P1_6/CLK0
TRDIOD0 INT
C
D
P0_2/AN5
P8_4/
TRFO11
P1_0/KI0/
AN8
P1_1/KI1/
AN9
P8_2/
TRFO02
P8_1/
TRFO01
P1_4/TXD0
P6_6/INT2/
TXD1
P8_0/
TRFO00
P8_5/
TRFO12
P4_5/INT0
P6_7/INT3/
RXD1
G
H
P1_5/RXD0/
P2_4/
P2_1/
TRDIOA1 TRDIOB0 (TRAIO)/(INT1)(2)
P2_2/
P2_0/TRDIOA0/ P8_6
TRDIOC0 TRDCLK
P2_6/
TRDIOC1
P0_3/AN4
E
F
Package: PTLG0064JA-A (64F0G)
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a
program.
R5F212A7
SNLG
JAPAN
Pin assignments (top view)
Figure 1.5
64-pin FLGA Package Pin Assignment (Top Perspective View)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 12 of 580
8
7
6
5
4
3
2
1
R8C/2A Group, R8C/2B Group
Table 1.7
Pin Name Information by Pin Number (1)
Pin
Control Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1. Overview
Port
Interrupt
P3_3
P3_4
MODE
XCIN
XCOUT
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
I/O Pin Functions for of Peripheral Modules
Serial
Timer
SSU
I2C bus
Interface
SSI
SCS
SDA
P4_3
P4_4
P4_7
P4_6
P5_4
P5_3
P5_2
P5_1
P5_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
INT1
TRCIOD
TRCIOC
TRCIOB
TRCIOA/TRCTRG
TRCCLK
TRDIOD1
TRDIOC1
TRDIOB1
TRDIOA1
TRDIOD0
TRDIOC0
TRDIOB0
TRDIOA0/TRDCLK
TRAIO
25
26
P1_6
P1_5
(INT1)(1)
(TRAIO)(1)
27
28
29
30
31
32
33
34
35
36
37
38
P1_4
P8_6
P8_5
P8_4
P8_3
P8_2
P8_1
P8_0
P6_0
P4_5
P6_6
P6_7
39
P6_5
40
41
42
43
44
P6_4
P6_3
P3_1
P3_0
P3_6
(INT1)(1)
45
P3_2
(INT2)(1)
TXD0
INT0
INT2
INT3
TRFO12
TRFO11
TRFO10/TRFI
TRFO02
TRFO01
TRFO00
TREO
INT0
TXD1
RXD1
(CLK1)(1)/
CLK2
RXD2
TXD2
TRBO
TRAO
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
CLK0
RXD0
Page 13 of 580
A/D Converter,
D/A Converter
R8C/2A Group, R8C/2B Group
Table 1.8
Pin Name Information by Pin Number (2)
Pin
Control Pin
Number
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1. Overview
Port
P1_3
P1_2
P1_1
P1_0
P0_0
P0_1
P0_2
P0_3
P0_4
P6_2
P6_1
P0_5
P0_6
Interrupt
I/O Pin Functions for of Peripheral Modules
Serial
Timer
SSU
I2C bus
Interface
Kl3
KI2
KI1
KI0
CLK1
A/D Converter,
D/A Converter
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1/DA0
VSS/AVSS
P0_7
AN0/DA1
VREF
VCC/AVCC
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
P3_7
P3_5
Page 14 of 580
SSO
SSCK
SCL
R8C/2A Group, R8C/2B Group
1.5
1. Overview
Pin Functions
Tables 1.9 and 1.10 list Pin Functions.
Table 1.9
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input
VCC, VSS
−
Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins(1). To use an external clock, input it
to the XIN pin and leave the XOUT pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT3
I
INT interrupt input pins.
INT0 is timer RD input pin. INT1 is timer RA input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
I/O
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins(1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RA I/O pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
External clock input pin
Timer RE
TREO
O
Divided clock output pin
Timer RF
TRFI
I
Timer RF input pin
TRFO00 to TRFO02,
TRFO10 to TRFO12
O
Timer RF output pins
CLK0, CLK1, CLK2
I/O
RXD0, RXD1, RXD2
I
Serial data input pins
Serial interface
I2C bus
SSU
Reference voltage
input
Transfer clock I/O pins
TXD0, TXD1, TXD2
O
Serial data output pins
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
VREF
I
Reference voltage input pin to A/D converter and D/A
converter
I: Input
O: Output
I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 15 of 580
R8C/2A Group, R8C/2B Group
Table 1.10
1. Overview
Pin Functions (2)
Item
Pin Name
I/O Type
Description
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
D/A converter
DA0 to DA1
O
D/A converter output pins
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_5,
P5_0 to P5_4,
P6_0 to P6_7,
P8_0 to P8_6
I/O
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P2_0 to P2_7 also function as LED drive ports.
Input port
P4_6, P4_7
I: Input
O: Output
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
I
I/O: Input and output
Page 16 of 580
Input-only ports
R8C/2A Group, R8C/2B Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
A0
A1
FB
b19
b15
Address registers(1)
Frame base register(1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 17 of 580
R8C/2A Group, R8C/2B Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 18 of 580
R8C/2A Group, R8C/2B Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 19 of 580
R8C/2A Group, R8C/2B Group
3.
3. Memory
Memory
3.1
R8C/2A Group
Figure 3.1 is a Memory Map of R8C/2A Group. The R8C/2A group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal
ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
03000h
0FFDCh
Internal RAM
Undefined instruction
Overflow
BRK instruction
Address match
Single step
0WWWWh
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
Expanded area
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
Address 0WWWWh
48 Kbytes
04000h
−
2.5 Kbytes
00DFFh
−
64 Kbytes
96 Kbytes
04000h
04000h
13FFFh
1BFFFh
3 Kbytes
7 Kbytes
00FFFh
011FFh
−
03DFFh
128 Kbytes
04000h
23FFFh
7.5 Kbytes
011FFh
03FFFh
Figure 3.1
Memory Map of R8C/2A Group
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 20 of 580
R8C/2A Group, R8C/2B Group
3.2
3. Memory
R8C/2B Group
Figure 3.2 is a Memory Map of R8C/2B Group. The R8C/2B group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte
internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but
also for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM
(data flash)(1)
02BFFh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
03000h
Internal RAM
0WWWWh
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
(Reserved)
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
Expanded area
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
Internal ROM
Size
Address 0YYYYh
48 Kbytes
04000h
64 Kbytes
04000h
96 Kbytes
04000h
128 Kbytes
04000h
Figure 3.2
Internal RAM
Address ZZZZZh
Size
Address 0XXXXh
Address 0WWWWh
−
2.5 Kbytes
00DFFh
−
13FFFh
3 Kbytes
00FFFh
−
1BFFFh
7 Kbytes
011FFh
03DFFh
23FFFh
7.5 Kbytes
011FFh
03FFFh
Memory Map of R8C/2B Group
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 21 of 580
R8C/2A Group, R8C/2B Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
SFR Information (1)(1)
Register
Symbol
After reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Operation Enable Register
PM0
PM1
CM0
CM1
MSTCR
00h
00h
01101000b
00100000b
00h
Protect Register
PRCR
00h
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
OCD
WDTR
WDTS
WDC
RMAD0
Address Match Interrupt Enable Register
Address Match Interrupt Register 1
AIER
RMAD1
00000100b
XXh
XXh
00X11111b
00h
00h
00h
00h
00h
00h
00h
Count Source Protection Mode Register
CSPR
00h
10000000b(6)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
FRA0
FRA1
FRA2
00h
When shipping
00h
Clock Prescaler Reset Flag
CPSRF
00h
High-Speed On-Chip Oscillator Control Register 6
High-Speed On-Chip Oscillator Control Register 7
FRA6
FRA7
When Shipping
When Shipping
0030h
0031h
0032h
Voltage Detection Register 1(2)
Voltage Detection Register 2(2)
VCA1
VCA2
00001000b
00h(3)
00100000b(4)
0033h
0034h
0035h
0036h
0037h
0038h
Voltage Monitor 1 Circuit Control Register(5)
Voltage Monitor 2 Circuit Control Register(5)
Voltage Monitor 0 Circuit Control Register(2)
VW1C
VW2C
VW0C
00001000b
00h
0000X000b(3)
0100X001b(4)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
0039h
003Ah
003Eh
003Fh
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset.
5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
6. The CSPROINI bit in the OFS register is set to 0.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 22 of 580
R8C/2A Group, R8C/2B Group
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Registers (SFRs)
SFR Information (2)(1)
Register
Symbol
After reset
Timer RC Interrupt Control Register
Timer RD0 Interrupt Control Register
Timer RD1 Interrupt Control Register
Timer RE Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
SSU/IIC Interrupt Control Register(2)
Compare 1 Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
INT2 Interrupt Control Register
Timer RA Interrupt Control Register
SSUIC / IICIC
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
Timer RB Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer RF Interrupt Control Register
Compare 0 Interrupt Control Register
INT0 Interrupt Control Register
A/D Conversion Interrupt Control Register
Capture Interrupt Control Register
TRBIC
INT1IC
INT3IC
TRFIC
CMP0IC
INT0IC
ADIC
CAPIC
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
XXXXX000b
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 23 of 580
R8C/2A Group, R8C/2B Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3)(1)
Register
Symbol
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Register
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
SS Control Register H / IIC bus Control Register 1(2)
SS Control Register L / IIC bus Control Register 2(2)
SS Mode Register / IIC bus Mode Register(2)
SS Enable Register / IIC bus Interrupt Enable Register(2)
SS Status Register / IIC bus Status Register(2)
SS Mode Register 2 / Slave Address Register(2)
SS Transmit Data Register / IIC bus Transmit Data Register(2)
SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
SSTDR / ICDRT
SSRDR / ICDRR
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Selected by the IICSEL bit in the PMR register.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 24 of 580
After reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FFh
FFh
R8C/2A Group, R8C/2B Group
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
4. Special Function Registers (SFRs)
SFR Information (4)(1)
Register
Symbol
After reset
D/A Register 0
DA0
00h
D/A Register 1
DA1
00h
D/A Control Register
DACON
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
Port P6 Direction Register
PD6
00h
Port P2 Drive Capacity Control Register
UART1 Function Select Register
P2DRR
U1SR
00h
000000XXb
Port Mode Register
External Input Enable Register
INT Input Filter Select Register
Key Input Enable Register
Pull-Up Control Register 0
Pull-Up Control Register 1
PMR
INTEN
INTF
KIEN
PUR0
PUR1
00h
00h
00h
00h
00h
XX000000b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 25 of 580
R8C/2A Group, R8C/2B Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
NOTE:
1.
4. Special Function Registers (SFRs)
SFR Information (5)(1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Clock Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
TRCCR2
TRCDF
TRCOER
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011111b
00h
01111111b
Timer RD Start Register
Timer RD Mode Register
Timer RD PWM Mode Register
Timer RD Function Control Register
Timer RD Output Master Enable Register 1
Timer RD Output Master Enable Register 2
Timer RD Output Control Register
Timer RD Digital Filter Function Select Register 0
Timer RD Digital Filter Function Select Register 1
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
The blank regions are reserved. Do not access locations in these regions
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 26 of 580
After reset
R8C/2A Group, R8C/2B Group
Table 4.6
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
4. Special Function Registers (SFRs)
SFR Information (6)(1)
Register
Timer RD Control Register 0
Timer RD I/O Control Register A0
Timer RD I/O Control Register C0
Timer RD Status Register 0
Timer RD Interrupt Enable Register 0
Timer RD PWM Mode Output Level Control Register 0
Timer RD Counter 0
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
Timer RD General Register A0
TRDGRA0
Timer RD General Register B0
TRDGRB0
Timer RD General Register C0
TRDGRC0
Timer RD General Register D0
TRDGRD0
Timer RD Control Register 1
Timer RD I/O Control Register A1
Timer RD I/O Control Register C1
Timer RD Status Register 1
Timer RD Interrupt Enable Register 1
Timer RD PWM Mode Output Level Control Register 1
Timer RD Counter 1
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
Timer RD General Register A1
TRDGRA1
Timer RD General Register B1
TRDGRB1
Timer RD General Register C1
TRDGRC1
Timer RD General Register D1
TRDGRD1
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 27 of 580
After reset
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
R8C/2A Group, R8C/2B Group
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
4. Special Function Registers (SFRs)
SFR Information (7)(1)
Register
Symbol
After reset
Flash Memory Control Register 4
FMR4
01000000b
Flash Memory Control Register 1
FMR1
1000000Xb
Flash Memory Control Register 0
FMR0
00000001b
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 28 of 580
R8C/2A Group, R8C/2B Group
Table 4.8
SFR Information (8)(1)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 29 of 580
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.9
SFR Information (9)(1)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 30 of 580
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.10
SFR Information (10)(1)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
0271h
0272h
0273h
0274h
0275h
0276h
0277h
0278h
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
NOTE:
1.
4. Special Function Registers (SFRs)
Register
The blank regions are reserved. Do not access locations in these regions.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 31 of 580
Symbol
After reset
R8C/2A Group, R8C/2B Group
Table 4.11
Address
0280h
0281h
0282h
0283h
0284h
0285h
0286h
0287h
0288h
0289h
028Ah
028Bh
028Ch
028Dh
028Eh
028Fh
0290h
0291h
0292h
0293h
0294h
0295h
0296h
0297h
0298h
0299h
029Ah
029Bh
029Ch
029Dh
029Eh
029Fh
02A0h
02A1h
02A2h
02A3h
02A4h
02A5h
02A6h
02A7h
02A8h
02A9h
02AAh
02ABh
02ACh
02ADh
02AEh
02AFh
02B0h
02B1h
02B2h
02B3h
02B4h
02B5h
02B6h
02B7h
02B8h
02B9h
02BAh
02BBh
02BCh
02BDh
02BEh
02BFh
4. Special Function Registers (SFRs)
SFR Information (11)(1)
Register
Symbol
After reset
Timer RF Register
TRF
00h
00h
Timer RF Control Register 0
Timer RF Control Register 1
Capture / Compare 0 Register
TRFCR0
TRFCR1
TRFM0
Compare 1 Register
TRFM1
00h
00h
0000h(2)
FFFFh(3)
FFh
FFh
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. After input capture mode.
3. After output compare mode.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 32 of 580
R8C/2A Group, R8C/2B Group
Table 4.12
Address
02C0h
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02E4h
02E5h
02E6h
02E7h
02E8h
02E9h
02EAh
02EBh
02ECh
02EDh
02EEh
02EFh
02F0h
02F1h
02F2h
02F3h
02F4h
02F5h
02F6h
02F7h
02F8h
02F9h
02FAh
02FBh
02FCh
02FDh
02FEh
02FFh
FFFFh
4. Special Function Registers (SFRs)
SFR Information (12)(1)
Register
Symbol
After reset
A/D Register 0
AD0
XXh
XXh
A/D Control Register 2
ADCON2
00001000b
A/D Control Register 0
A/D Control Register 1
ADCON0
ADCON1
00000011b
00h
Port P8 Direction Register
PD8
00h
Port P8 Register
P8
XXh
Pull-Up Control Register 2
PUR2
XXX00000b
Timer RF Output Control Register
TRFOUT
00h
Option Function Select Register
OFS
(Note 2)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
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Page 33 of 580
R8C/2A Group, R8C/2B Group
5.
5. Resets
Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset,
voltage monitor 2 reset, watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources.
Table 5.1
Reset Names and Sources
Reset Name
Source
Hardware reset
Power-on reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
Watchdog timer reset
Software reset
Input voltage of RESET pin is held “L”
VCC rises
VCC falls (monitor voltage: Vdet0)
VCC falls (monitor voltage: Vdet1)
VCC falls (monitor voltage: Vdet2)
Underflow of watchdog timer
Write 1 to PM03 bit in PM0 register
Hardware reset
RESET
SFRs
Bits VCA25,
VW0C0, and
VW0C6
SFRs
Power-on reset
circuit
VCC
Voltage
detection
circuit
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2
reset
Watchdog
timer
CPU
Bits VCA25,
VW0C0, and
VW0C6
Power-on reset
SFRs
Bits VCA13, VCA26, VCA27,
VW1C2, VW1C3,
VW2C2, VW2C3,
VW0C1, VW0F0,
VW0F1, and VW0C7
Watchdog timer
reset
Pin, CPU, and
SFR bits other than
those listed above
Software reset
VCA13: Bit in VCA1 register
VCA25, VCA26, VCA27: Bits in VCA2 register
VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Figure 5.1
Block Diagram of Reset Circuit
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REJ09B0324-0200
Page 34 of 580
R8C/2A Group, R8C/2B Group
5. Resets
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Table 5.2
Pin Functions while RESET Pin Level is “L”
Pin Name
P0 to P3
P4_3 to P4_7
P5_0 to P5_4
P6
P8_0 to P8_6
Pin Functions
Input port
Input port
Input port
Input port
Input port
b15
b0
0000h
Data register(R0)
0000h
Data register(R1)
0000h
Data register(R2)
0000h
0000h
0000h
0000h
Data register(R3)
b19
Address register(A0)
Address register(A1)
Frame base register(FB)
b0
00000h
Content of addresses 0FFFEh to 0FFFCh
b15
b0
User stack pointer(USP)
0000h
Interrupt stack pointer(ISP)
0000h
Static base register(SB)
b0
Flag register(FLG)
0000h
b8
IPL
Figure 5.2
b7
b0
U I O B S Z D C
CPU Register Status after Reset
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Program counter(PC)
0000h
b15
b15
Interrupt table register(INTB)
Page 35 of 580
R8C/2A Group, R8C/2B Group
5. Resets
fOCO-S
RESET pin
10 cycles or more are needed(1)
fOCO-S clock × 32 cycles(2)
Internal reset
signal
Start time of flash memory
(CPU clock × 14 cycles)
CPU clock × 28 cycles
CPU clock
0FFFCh
0FFFEh
Address
(internal address
signal)
0FFFDh
Content of reset vector
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset signal to “H” at the same.
Figure 5.3
Reset Sequence
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
—
(b6)
CSPROINI
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
Reserved bit
Set to 1.
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 5.4
OFS Register
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Page 36 of 580
R8C/2A Group, R8C/2B Group
5.1
5. Resets
Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the supply voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1
When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs or more.
(3) Apply “H” to the RESET pin.
5.1.2
Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 21. Electrical
Characteristics).
(4) Wait for 10 µs or more.
(5) Apply “H” to the RESET pin.
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REJ09B0324-0200
Page 37 of 580
R8C/2A Group, R8C/2B Group
5. Resets
VCC
2.2 V
VCC
0V
RESET
RESET
0.2 VCC or below
0V
td(P-R) + 10 µs or more
NOTE:
1. Refer to 21. Electrical Characteristics.
Figure 5.5
Example of Hardware Reset Circuit and Operation
Supply voltage
detection circuit
RESET
5V
VCC
2.2 V
VCC
0V
5V
RESET
0V
td(P-R) + 10 µs or more
Example when
VCC = 5 V
NOTE:
1. Refer to 21. Electrical Characteristics.
Figure 5.6
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage
Detection Circuit) and Operation
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 38 of 580
R8C/2A Group, R8C/2B Group
5.2
5. Resets
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
The voltage monitor 0 reset is enabled after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
VCC
4.7 kΩ
(reference)
RESET
Vdet0(3)
2.2V
trth
External
Power VCC
Vdet0(3)
trth
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
4. Refer to 21. Electrical Characteristics.
5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS
register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the
VCA2 register to 1.
Figure 5.7
Example of Power-On Reset Circuit and Operation
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REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
5.3
5. Resets
Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet0.
When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset.
When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock
start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held “H”
and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is
automatically selected as the CPU clock after reset.
The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware
reset. Setting the LVD0ON bit is only valid after a hardware reset.
To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register
to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register
to 1.
The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset
enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh
using a flash programmer.
Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4
Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5
Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
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R8C/2A Group, R8C/2B Group
5.6
5. Resets
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined.
Refer to 13. Watchdog Timer for details of the watchdog timer.
5.7
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
6.
6. Voltage Detection Circuit
Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC
input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset,
voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures
6.5 to 6.8 show the Associated Registers.
Table 6.1
VCC Monitor
Specifications of Voltage Detection Circuit
Item
Voltage to monitor
Detection target
Monitor
Process
Reset
When Voltage
is Detected
Interrupt
Digital Filter
Switch
enabled/disabled
Sampling time
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Voltage Detection 0
Vdet0
Whether passing
through Vdet0 by rising
or falling
None
Voltage Detection 1
Voltage Detection 2
Vdet1
Vdet2
Passing through Vdet1 by Passing through Vdet2 by
rising or falling
rising or falling
VW1C3 bit in VW1C
register
Whether VCC is higher or
lower than Vdet1
Voltage monitor 0 reset Voltage monitor 1 reset
Reset at Vdet0 > VCC; Reset at Vdet1 > VCC;
restart CPU operation at restart CPU operation
VCC > Vdet0
after a specified time
None
Voltage monitor 1 interrupt
Interrupt request at Vdet1
> VCC and VCC > Vdet1
when digital filter is
enabled;
interrupt request at Vdet1
> VCC or VCC > Vdet1
when digital filter is
disabled
Available
Available
VCA13 bit in VCA1
register
Whether VCC is higher or
lower than Vdet2
Voltage monitor 2 reset
Reset at Vdet2 > VCC;
restart CPU operation
after a specified time
Voltage monitor 2 interrupt
Interrupt request at Vdet2
> VCC and VCC > Vdet2
when digital filter is
enabled;
interrupt request at Vdet2
> VCC or VCC > Vdet2
when digital filter is
disabled
Available
(Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S)
×4
×4
n: 1, 2, 4, and 8
n: 1, 2, 4, and 8
(Divide-by-n of fOCO-S)
×4
n: 1, 2, 4, and 8
Page 42 of 580
R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
VCA27
VCC
-
Voltage detection 2
signal
Noise
filter
+
Internal
reference
voltage
≥ Vdet2
VCA1 register
b3
VCA13 bit
VCA26
-
Voltage detection 1
signal
Noise
filter
+
≥ Vdet1
VW1C register
b3
VW1C3 bit
VCA25
Voltage detection 0
signal
+
-
Figure 6.1
≥ Vdet0
Block Diagram of Voltage Detection Circuit
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0
= 00b
= 01b
Voltage detection 0 circuit
= 10b
fOCO-S
1/2
1/2
1/2
= 11b
VCA25
VW0C1
VCC
Internal
reference
voltage
+
Digital
filter
Voltage
detection 0
signal
-
Voltage detection 0
signal is held “H” when
VCA25 bit is set to 0
(disabled)
Voltage monitor 0
reset signal
VW0C1
VW0C0
VW0C7
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register
VCA25: Bit in VCA2 register
Figure 6.2
Block Diagram of Voltage Monitor 0 Reset Generation Circuit
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REJ09B0324-0200
Page 43 of 580
VW0C6
R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0
= 00b
= 01b
Voltage detection 1 circuit
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
= 10b
fOCO-S
1/2
1/2
1/2
= 11b
VCA26
VW1C1
VW1C3
VCC
+
Noise filter
Internal
reference
voltage
(Filter width: 200 ns)
Digital
filter
Voltage
detection
1 signal
Watchdog
timer interrupt
signal
VW1C2
Voltage detection 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Voltage monitor 1
interrupt signal
VW1C1
Non-maskable
interrupt signal
Oscillation stop
detection
interrupt signal
VW1C7
VW1C0
VW1C6
Voltage monitor 1
reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register
VCA26: Bit in VCA2 register
Figure 6.3
Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Voltage monitor 2 interrupt/reset generation circuit
VW2F1 to VW2F0
= 00b
= 01b
Voltage detection 2 circuit
= 10b
fOCO-S
1/2
1/2
1/2
VW2C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
= 11b
VCA27
VW2C1
VCA13
VCC
Internal
reference
voltage
+
Noise filter
(Filter width: 200 ns)
Digital
filter
Voltage
detection
2 signal
Watchdog
timer interrupt
signal
VW2C2
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Voltage monitor 2
interrupt signal
VW2C1
Non-maskable
interrupt signal
Oscillation stop
detection
interrupt signal
Watchdog timer block
VW2C3
VW2C7
Watchdog timer
underflow signal
This bit is set to 0 (not detected) by writing 0
by a program.
VW2C0
VW2C6
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
Figure 6.4
Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 44 of 580
Voltage monitor 2
reset signal
R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
0 0 0
Symbol
Address
0031h
VCA1
Bit Symbol
Bit Name
Reserved bits
—
(b2-b0)
VCA13
—
(b7-b4)
After Reset(2)
00001000b
Function
Set to 0.
Voltage detection 2 signal monitor
flag(1)
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled
Reserved bits
Set to 0.
RW
RW
RO
RW
NOTES:
1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled).
The VCA13 bit is set to 1 (VCC ≥ Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2
circuit disabled).
2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
VCA2
Bit Symbol
Address
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
: 00100000b
0032h
Bit Name
Internal pow er low
consumption enable bit(6)
Function
0 : Disables low consumption
1 : Enables low consumption
Reserved bits
Set to 0.
VCA25
Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled
RW
VCA26
Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
VCA20
—
(b4-b1)
RW
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 6.5
Registers VCA1 and VCA2
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Page 45 of 580
R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
VW0C
Bit Symbol
VW0C0
VW0C1
VW0C2
—
(b3)
VW0F0
0038h
Bit Name
Voltage monitor 0 reset
enable bit(3)
VW0C7
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 0000X000b
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is set
to 0, and hardw are reset
: 0100X001b
Function
0 : Disable
1 : Enable
Reserved bit
Set to 0.
Reserved bit
When read, the content is undefined.
Sampling clock select bits
b5 b4
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
RW
RW
Voltage monitor 0 digital filter 0 : Digital filter enabled mode
(digital filter circuit enabled)
disable mode select bit
1 : Digital filter disabled mode
(digital filter circuit disabled)
VW0F1
VW0C6
After Reset(2)
Address
RW
RW
1
2
4
8
RO
RW
RW
Voltage monitor 0 circuit
mode select bit
When the VW0C0 bit is set to 1 (voltage monitor 0
reset enabled), set to 1.
RW
Voltage monitor 0 reset
generation condition select
bit(4)
When the VW0C1 bit is set to 1 (digital filter
disabled mode), set to 1.
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register.
2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage
monitor 2 reset.
3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit
enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled).
4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Figure 6.6
VW0C Register
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R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW1C
Bit Symbol
Address
0036h
Bit Name
Voltage monitor 1 interrupt/reset
enable bit(6)
After Reset(8)
00001000b
Function
RW
0 : Disable
1 : Enable
RW
Voltage monitor 1 digital filter
disable mode select bit(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
VW1C2
Voltage change detection
flag(3, 4, 8)
0 : Not detected
1 : Vdet1 crossing detected
RW
VW1C3
Voltage detection 1 signal monitor 0 : VCC < Vdet1
1 : VCC ≥ Vdet1 or voltage detection 1
flag(3, 8)
circuit disabled
VW1C0
VW1C1
VW1F0
Sampling clock select bits
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
VW1F1
VW1C6
VW1C7
b5 b4
1
2
4
8
Voltage monitor 1 circuit mode
select bit(5)
0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode
Voltage monitor 1 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below
RO
RW
RW
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register.
2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting
1.
3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset).
6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled).
Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or
below ). (Do not set to 0.)
Figure 6.7
VW1C Register
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R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
VW2C
Bit Symbol
VW2C0
VW2C1
VW2C2
VW2C3
VW2F0
Address
0037h
Bit Name
Voltage monitor 2 interrupt/reset
enable bit(6)
VW2C7
RW
0 : Disable
1 : Enable
RW
Voltage monitor 2 digital filter
disable mode select bit(2)
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabled)
RW
Voltage change detection
flag(3, 4, 8)
0 : Not detected
1 : VCC has crossed Vdet2
RW
WDT detection flag(4, 8)
0 : Not detected
1 : Detected
RW
Sampling clock select bits
b5 b4
0 0 : fOCO-S divided by
0 1 : fOCO-S divided by
1 0 : fOCO-S divided by
1 1 : fOCO-S divided by
VW2F1
VW2C6
After Reset(8)
00h
Function
1
2
4
8
Voltage monitor 2 circuit mode
select bit(5)
0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode
Voltage monitor 2 interrupt/reset
generation condition select bit(7, 9)
0 : When VCC reaches Vdet2 or above
1 : When VCC reaches Vdet2 or below
RW
RW
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register.
2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1
bit before w riting 1.
3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled).
4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is
w ritten to it).
5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset).
6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit
enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled).
7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode).
8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset,
or voltage monitor 2 reset.
9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2
or below ). (Do not set to 0.)
Figure 6.8
VW2C Register
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R8C/2A Group, R8C/2B Group
6.1
6. Voltage Detection Circuit
VCC Input Voltage
6.1.1
Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2
Monitoring Vdet1
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed
(refer to 21. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.
6.1.3
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed
(refer to 21. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
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6.2
6. Voltage Detection Circuit
Voltage Monitor 0 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an
Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the
VW0C1 bit in the VW0C register to 1 (digital filter disabled).
Table 6.2
Step
1
2
3
4(1)
5(1)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor Reset
When Using Digital Filter
When Not Using Digital Filter
Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to
by the VW0F0 to VW0F1 bits in the VW0C 1
register
Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to
0 (digital filter enabled)
1 (digital filter disabled)
Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode)
Set the VW0C2 bit in the VW0C register to 0
Set the CM14 bit in the CM1 register to 0 −
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of
− (No wait time required)
the digital filter
Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
NOTE:
1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
VCC
Vdet0
Sampling clock of
digital filter × 4 cycles
When the VW0C1 bit is set
to 0 (digital filter enabled)
1
× 32
fOCO-S
Internal reset signal
1
× 32
fOCO-S
When the VW0C1 bit is set
to 1 (digital filter disabled)
and the VW0C7 bit is set
to 1
Internal reset signal
VW0C1 and VW0C7: Bits in VW0C register
The above applies under the following conditions.
• VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled)
• VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled)
• VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode)
When the internal reset signal is held “L”, the pins, CPU and SFR are reset.
The internal reset signal level changes from “L” to “H”, and a program is executed beginning with the address indicated by
the reset vector.
Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.9
Example of Voltage Monitor 0 Reset Operation
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R8C/2A Group, R8C/2B Group
6.3
6. Voltage Detection Circuit
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10
shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
Table 6.3
Step
1
2
3
4(2)
5(2)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
When Using Digital Filter
When Not Using Digital Filter
Voltage Monitor 1
Voltage Monitor 1
Voltage Monitor 1
Voltage Monitor 1
Interrupt
Reset
Interrupt
Reset
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
request by the VW1C7 bit in the VW1C
by the VW1F0 to VW1F1 bits in the VW1C
register
register(1)
Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1
(digital filter enabled)
(digital filter disabled)
Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in
the VW1C register to the VW1C register to the VW1C register to the VW1C register to
0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1
reset mode)
interrupt mode)
reset mode)
interrupt mode)
Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
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R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
VCC
Vdet1
2.2 V(1)
1
VW1C3 bit
0
4 cycles of sampling clock of
digital filter
4 cycles of sampling clock of
digital filter
1
VW1C2 bit
0
Set to 0 by a program
When the VW1C1 bit is set
to 0 (digital filter enabled)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
Set to 0 by a program
1
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 0
(Vdet1 or above)
VW1C2 bit
0
Set to 0 by interrupt
request
acknowledgement
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by a program
1
VW1C2 bit
0
When the VW1C1 bit is
set to 1 (digital filter
disabled) and the
VW1C7 bit is set to 1
(Vdet1 or below)
Voltage monitor 1
interrupt request
(VW1C6 = 0)
Set to 0 by interrupt
request acknowledgement
Internal reset signal
(VW1C6 = 1)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled)
NOTE:
1. If voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.10
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
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R8C/2A Group, R8C/2B Group
6.4
6. Voltage Detection Circuit
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11
shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
Table 6.4
Step
1
2
3
4
5(2)
6
7
8
9
Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
When Using Digital Filter
When Not Using Digital Filter
Voltage Monitor 2
Voltage Monitor 2
Voltage Monitor 2
Voltage Monitor 2
Interrupt
Reset
Interrupt
Reset
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
Wait for td(E-A)
Select the sampling clock of the digital filter Select the timing of the interrupt and reset
request by the VW2C7 bit in the VW2C
by the VW2F0 to VW2F1 bits in the VW2C
register
register(1)
Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1
(digital filter enabled)
(digital filter disabled)
Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in
the VW2C register to the VW2C register to the VW2C register to the VW2C register to
0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2
reset mode)
interrupt mode)
reset mode)
interrupt mode)
Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on)
Wait for 4 cycles of the sampling clock of the − (No wait time required)
digital filter
Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
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R8C/2A Group, R8C/2B Group
6. Voltage Detection Circuit
VCC
Vdet2
2.2 V(1)
1
VCA13 bit
0
4 cycles of sampling clock of
digital filter
4 cycles of sampling clock of
digital filter
1
VW2C2 bit
0
Set to 0 by a program
When the VW2C1 bit is set
to 0 (digital filter enabled)
Set to 0 by interrupt request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
Set to 0 by a program
1
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 0
(Vdet2 or above)
VW2C2 bit
0
Set to 0 by interrupt
request
acknowledgement
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by a program
1
VW2C2 bit
0
When the VW2C1 bit is
set to 1 (digital filter
disabled) and the
VW2C7 bit is set to 1
(Vdet2 or below)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Set to 0 by interrupt
request acknowledgement
Internal reset signal
(VW2C6 = 1)
VCA13: Bit in VCA1 register
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled)
NOTE:
1. When voltage monitor 0 reset is not used, set the power supply to VCC ≥ 2.2.
Figure 6.11
Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
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R8C/2A Group, R8C/2B Group
7.
7. Programmable I/O Ports
Programmable I/O Ports
There are 55 programmable Input/Output ports (I/O ports) P0 to P3, P4_3 to P4_5, P5_0 to P5_4, P6, and P8_0 to
P8_6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used.
Table 7.1 lists an Overview of Programmable I/O Ports.
Table 7.1
Overview of Programmable I/O Ports
Ports
P0 to P3, P5_0 to P5_3,
P6, P8_0 to P8_3
P4_3, P5_4
I/O
Type of Output
I/O Setting
Internal Pull-Up Resister
I/O
CMOS3 State
Set per bit
Set every 4 bits(1)
I/O
CMOS3 State
Set per bit
Set every bit(1)
P4_4, P4_5
I/O
CMOS3 State
Set per bit
P4_6, P4_7(2)
P8_4 to P8_6
I/O
I
(No output function)
None
Set every 2 bits(1)
None
CMOS3 State
Set per bit
Set every 3 bits(1)
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers
PUR0, PUR1, and PUR2.
2. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.
7.1
Functions of Programmable I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 6, 8) register controls I/O of the ports P0 to P3, P4_3 to P4_5, P5_0 to
P5_4, P6, and P8_0 to P8_6. The Pi register consists of a port latch to hold output data and a circuit to read pin
states.
Figures 7.1 to 7.10 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.12 shows the PDi (i = 0 to 6 and 8) Registers. Figure 7.13 shows the Pi (i =
0 to 6 and 8) Registers, Figure 7.14 shows the P2DRR Register, Figure 7.15 shows the PMR Register, and Figure
7.16 shows Registers PUR0, PUR1, and PUR2.
Table 7.2
Functions of Programmable I/O Ports
Operation When
Value of PDi_j Bit in PDi Register(1)
Accessing
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Pi Register
Reading
Read pin input level
Read the port latch
Write to the port latch. The value written to
Writing
Write to the port latch
the port latch is output from the pin.
i = 0 to 6, 8, j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD4_0 to PD4_2, PD4_6, and PD4_7.
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7.2
7. Programmable I/O Ports
Effect on Peripheral Functions
Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information
by Pin Number (1) and Table 1.8 Pin Name Information by Pin Number (2)).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 6, 8, j = 0 to
7).
Refer to the description of each function for information on how to set peripheral functions.
Table 7.3
Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions
(i = 0 to 6, 8, j = 0 to 7)
I/O of Peripheral Functions
PDi_j Bit Settings for Shared Pin Functions
Input
Set this bit to 0 (input mode).
Output
This bit can be set to either 0 or 1 (output regardless of the port setting)
7.3
Pins Other than Programmable I/O Ports
Figure 7.11 shows the Configuration of I/O Pins.
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R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
P0_0 to P0_4
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Analog input
P0_5
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
Analog input
P0_6 and P0_7
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Analog input
Analog output
D/A converter output enable
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.1
Configuration of Programmable I/O Ports (1)
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7. Programmable I/O Ports
P1_0 to P1_3
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
Analog input
P1_4
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Pull-up selection
P1_5 and P1_7
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
INT1 input
Digital
filter
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.2
Configuration of Programmable I/O Ports (2)
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7. Programmable I/O Ports
P1_6
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
P2
Drive capacity selection
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
Drive capacity selection
P3_0 and P3_1
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.3
Configuration of Programmable I/O Ports (3)
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7. Programmable I/O Ports
P3_2 and P3_6
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Digital
filter
Input to INT1 and INT2
P3_3, P3_4, P3_5, and P3_7
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.4
Configuration of Programmable I/O Ports (4)
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7. Programmable I/O Ports
P4_3/XCIN
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Clocked inverter(2)
(Note 3)
P4_4/XCOUT
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
P4_5
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
INT0 input
Digital
filter
NOTES:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off.
3. When CM04 = 0 the feedback resistor is disconnected.
Figure 7.5
Configuration of Programmable I/O Ports (5)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 61 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
(Note 1)
P4_6/XIN
Data bus
(Note 1)
Clocked inverter(2)
(Note 3)
(Note 1)
P4_7/XOUT
Data bus
(Note 4)
(Note 1)
P5_0
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Input to individual peripheral function
NOTES:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cut off.
3. When CM10 = 1 or CM13 = 0, the feedback resistor is disconnected.
4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up.
Figure 7.6
Configuration of Programmable I/O Ports (6)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 62 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
P5_1 to P5_4
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
P6_0
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.7
Configuration of Programmable I/O Ports (7)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 63 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
P6_1 and P6_2
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
P6_3
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
P6_4
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.8
Configuration of Programmable I/O Ports (8)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 64 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
P6_5
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
P6_6
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
INT2 input
P6_7
Digital
filter
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
INT3 input
Digital
filter
Input to individual peripheral function
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.9
Configuration of Programmable I/O Ports (9)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 65 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
P8_0 to P8_2, P8_4, and P8_5
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
P8_3
Pull-up selection
Direction
register
1
(Note 1)
Output from individual peripheral function
Data bus
Port latch
(Note 1)
Input to individual peripheral function
P8_6
Pull-up selection
Direction
register
(Note 1)
Data bus
Port latch
(Note 1)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.10
Configuration of Programmable I/O Ports (10)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 66 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
MODE
MODE signal input
(Note 1)
(Note 1)
RESET
RESET signal input
(Note 1)
NOTE:
1.
symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Figure 7.11
Configuration of I/O Pins
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 67 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
Port Pi Direction Register (i = 0 to 6, 8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD0(1)
PD1
PD2
PD3
PD4(2)
PD5(3)
PD6
PD8(4)
Bit Symbol
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Address
00E2h
00E3h
00E6h
00E7h
00EAh
00EBh
00EEh
02E4h
Bit Name
Port Pi_0 direction bit
Port Pi_1 direction bit
Port Pi_2 direction bit
Port Pi_3 direction bit
Port Pi_4 direction bit
Port Pi_5 direction bit
Port Pi_6 direction bit
Port Pi_7 direction bit
After Reset
00h
00h
00h
00h
00h
00h
00h
00h
Function
0 : Input mode
(functions as an input port)
1 : Output mode
(functions as an output port)
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. Write to the PD0 register w ith the next instruction after that used to set the PRC2 bit in the PRCR register to 1 (w rite
enabled).
2. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU.
If it is necessary to set bits PD4_0 to PD4_2, PD4_6 and PD4_7 in the PD4 register, set to 0 (input mode). When read,
the content is 0.
3. Bits PD5_5 to PD5_7 in the PD5 register are reserved bits. If it is necessary to set bits PD5_5 to PD5_7, set to 0.
4. The PD8_7 bit in the PD8 register is a reserved bit. If it is necessary to set the PD8_7 bit, set to 0.
Figure 7.12
PDi (i = 0 to 6 and 8) Registers
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 68 of 580
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
Port Pi Register (i = 0 to 6, 8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P0
P1
P2
P3
P4(1)
P5(2)
P6
P8(3)
Bit Symbol
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
Address
00E0h
00E1h
00E4h
00E5h
00E8h
00E9h
00ECh
02E6h
Bit Name
Port Pi_0 bit
Port Pi_1 bit
Port Pi_2 bit
Port Pi_3 bit
Port Pi_4 bit
Port Pi_5 bit
Port Pi_6 bit
Port Pi_7 bit
After Reset
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Function
The pin level of any I/O port w hich is set to
input mode can be read by reading the
corresponding bit in this register. The pin level
of any I/O port w hich is set to output mode
can be controlled by w riting to the
corresponding bit in this register.
0 : “L” level
1 : “H” level
NOTES:
1. Bits P4_0 to P4_2 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_2, set to 0 (“L” level). When read, the content is 0.
2. Bits P5_5 to P5_7 in the P5 register are reserved bits. If it is necessary to set bits P5_5 to P5_7, set to 0.
3. The P8_7 bit in the P8 register is a reserved bit. If it is necessary to set the P8_7 bit, set to 0.
Figure 7.13
Pi (i = 0 to 6 and 8) Registers
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 69 of 580
RW
RW
RW
RW
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
Port P2 Drive Capacity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P2DRR
Bit Symbol
P2DRR0
P2DRR1
P2DRR2
P2DRR3
P2DRR4
P2DRR5
P2DRR6
P2DRR7
Address
00F4h
Bit Name
P2_0 drive capacity
P2_1 drive capacity
P2_2 drive capacity
P2_3 drive capacity
P2_4 drive capacity
P2_5 drive capacity
P2_6 drive capacity
P2_7 drive capacity
After Reset
00h
Function
Set P2 output transistor drive capacity
0 : Low
1 : High(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTE:
1. Both “H” and “L” output are set to high drive capacity.
Figure 7.14
P2DRR Register
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
PMR
Bit Symbol
INT1SEL
Address
00F8h
Bit Name
_____
INT1 pin select bit
After Reset
00h
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
RW
INT2 pin select bit
0 : Selects P6_6
1 : Selects P3_2
RW
Reserved bits
Set to 0.
UART1 enable bit
To use the UART1, set to 1.
Reserved bits
Set to 0.
SSU / I2C bus sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
_____
INT2SEL
—
(b3-b2)
U1PINSEL
—
(b6-b5)
IICSEL
Figure 7.15
PMR Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 70 of 580
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
7. Programmable I/O Ports
Pull-Up Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Bit Symbol
PU00
PU01
PU02
PU03
PU04
PU05
PU06
PU07
Address
00FCh
Bit Name
P0_0 to P0_3 pull-up(1)
P0_4 to P0_7 pull-up(1)
P1_0 to P1_3 pull-up(1)
P1_4 to P1_7 pull-up(1)
P2_0 to P2_3 pull-up(1)
P2_4 to P2_7 pull-up(1)
P3_0 to P3_3 pll-up(1)
P3_4 to P3_7 pll-up(1)
After Reset
00h
Function
0 : Not pulled up
1 : Pulled up
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Bit Symbol
PU10
PU11
PU12
PU13
PU14
PU15
—
(b7-b6)
Address
00FDh
Bit Name
After Reset
XX000000b
Function
0 : Not pulled up
1 : Pulled up
P4_3 pull-up(1)
P4_4 and P4_5 pull-up(1)
P5_0 to P5_3 pull-up(1)
P5_4 pull-up(1)
P6_0 to P6_3 pull-up(1)
P6_4 to P6_7 pull-up(1)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
RW
RW
RW
RW
RW
RW
—
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
02FCh
PUR2
Bit Symbol
Bit Name
Reserved bits
—
(b1-b0)
PU22
PU23
—
(b4)
—
(b7-b5)
P8_0 to P8_3 pull-up(1)
P8_4 to P8_6 pull-up(1)
Reserved bit
After Reset
XXX00000b
Function
Set to 0.
0 : Not pulled up
1 : Pulled up
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
NOTE:
1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Figure 7.16
Registers PUR0, PUR1, and PUR2
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 71 of 580
RW
RW
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
7.4
7. Programmable I/O Ports
Port settings
Tables 7.4 to 7.65 list the port settings.
Table 7.4
Register
Bit
Setting
Value
Port P0_0/AN7
PD0
PD0_0
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
1
0
X
1
X
1
X
1
X
0
X
0
Function
Input port(1)
Output port
A/D converter input (AN7)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.5
Register
Bit
Setting
Value
Port P0_1/AN6
PD0
PD0_1
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
1
0
X
1
X
1
X
0
X
0
X
0
Function
Input port(1)
Output port
A/D converter input (AN6)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.6
Register
Bit
Setting
Value
Port P0_2/AN5
PD0
PD0_2
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
1
0
X
1
X
0
X
1
X
0
X
0
Function
Input port(1)
Output port
A/D converter input (AN5)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.7
Register
Bit
Setting
Value
Port P0_3/AN4
PD0
PD0_3
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
1
0
X
1
X
0
X
0
X
0
X
0
Function
Input port(1)
Output port
A/D converter input (AN4)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.8
Register
Bit
Setting
Value
Port P0_4/AN3
PD0
PD0_4
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
1
0
X
0
X
1
X
1
X
0
X
0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 72 of 580
Function
Input port(1)
Output port
A/D converter input (AN3)
R8C/2A Group, R8C/2B Group
Table 7.9
Register
Bit
Port P0_5/AN2/CLK1
PD0
ADCON0
ADCON2
PMR
U1MR
U1SR
Function
PD0_5 CH2 CH1 CH0 ADGSEL1 ADGSEL0 U1PINSEL SMD2 SMD1 SMD0 CKDIR CLK11PSEL CLK10PSEL
0
Setting
Value
7. Programmable I/O Ports
X
1
X
X
X
X
X
X
X
X
X
X
Other than 001b
X
X
X
0
X
X
X
X
X
X
X
X
X
X
1
X
X
X
Other than 001b
X
X
X
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
0
1
0
0
1
0
0
0
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
1
X
X
X
X
X
X
1
0
0
1
0
Input port(1)
Output port
A/D converter
input (AN2)
CLK1 (external
clock) input
CLK1 (internal
clock) output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.10
Register
Bit
Setting
Value
Port P0_6/AN1/DA0
PD0
PD0_6
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
DACON
DA0E
0
X
X
X
X
X
X
1
0
0
X
0
X
X
0
X
X
1
X
X
0
X
X
0
X
X
X
1
Function
Input port(1)
Output port
A/D converter input (AN1)
D/A converter output (DA0)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.11
Register
Bit
Setting
Value
Port P0_7/AN0/DA1
PD0
PD0_7
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
X
X
1
0
0
X
0
X
X
0
X
X
0
X
X
0
X
X
0
X
X
X
1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 73 of 580
DACON
DA1E
Function
Input port(1)
Output port
A/D converter input (AN0)
D/A converter output (DA1)
R8C/2A Group, R8C/2B Group
Table 7.12
Register
Bit
Setting
Value
7. Programmable I/O Ports
Port P1_0/KI0/AN8
PD1
PD1_0
KIEN
KI0EN
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
X
1
0
0
0
1
X
Function
Input port(1)
Output port
X
KI0 input
A/D converter input (AN8)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.13
Register
Bit
Setting
Value
Port P1_1/KI1/AN9
PD1
PD1_1
KIEN
KI1EN
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
X
1
0
1
0
1
X
X
Function
Input port(1)
Output port
KI1 input
A/D converter input (AN9)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.14
Register
Bit
Setting
Value
Port P1_2/KI2/AN10
PD1
PD1_2
KIEN
KI2EN
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
X
1
1
0
0
1
X
X
Function
Input port(1)
Output port
KI2 input
A/D converter input (AN10)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.15
Register
Bit
Setting
Value
Port P1_3/KI3/AN11
PD1
PD1_3
KIEN
KI3EN
CH2
ADCON0
CH1
CH0
ADCON2
ADGSEL1 ADGSEL0
0
X
X
X
X
1
X
X
X
X
X
X
0
1
X
X
X
X
X
0
X
1
1
1
0
1
X
X
Function
Input port(1)
Output port
KI3 input
A/D converter input (AN11)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.16
Register
Bit
Setting
Value
Port P1_4/TXD0
PD1
PD1_4
SMD2
U0MR
SMD1
SMD0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
0
X
Function
Input port(1)
Output port
TXD0 output(2)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the NCH bit in the U0C0 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 74 of 580
R8C/2A Group, R8C/2B Group
Table 7.17
Register
Bit
Port P1_5/RXD0/(TRAIO)/(INT1)
PD1
PD1_5
0
Setting
Value
7. Programmable I/O Ports
1
0
0
TRAIOC
TIOSEL TOPCR
0
X
X
1
X
X
0
X
X
1
X
X
X
X
0
1
X
0
1
X
X
1
0
TRAMR
TMOD2 TMOD1 TMOD0
X
X
X
X
X
X
Other than 001b
X
X
X
X
X
X
Other than 001b
Other than 001b
0
0
1
Other than 001b
INTEN
INT1EN
PMR
INT1SEL
X
X
Input port(1)
X
X
Output port
X
X
RXD0 input(1)
X
X
TRAIO input
Other than 001b
1
0
X
X
TRAIO/INT1 input
TRAIO pulse output
0
0
1
Function
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 7.18
Register
Bit
Setting
Value
Port P1_6/CLK0
PD1
PD1_6
SMD2
0
X
1
0
X
X
0
U0MR
SMD1
SMD0
Other than 001b
X
X
Other than 001b
X
X
0
1
CKDIR
X
1
X
1
0
Function
Input port(1)
Output port
CLK0 (external clock) input
CLK0 (internal clock) output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 7.19
Register
Bit
Port P1_7/TRAIO/INT1
PD1
PD1_7
0
Setting
Value
1
0
TRAIOC
TIOSEL TOPCR
1
X
X
1
X
X
1
X
X
1
X
X
0
X
0
0
X
X
0
0
TRAMR
TMOD2 TMOD1 TMOD0
X
X
X
X
X
X
Other than 001b
X
X
X
X
X
X
Other than 001b
Other than 001b
Other than 001b
0
0
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 75 of 580
1
INTEN
PMR
INT1EN INT1SEL
Function
X
X
Input port(1)
X
X
Output port
X
X
TRAIO input
1
0
X
X
TRAIO/INT1 input
TRAIO pulse output
R8C/2A Group, R8C/2B Group
Table 7.20
Port P2_0/TRDIOA0/TRDCLK
Register PD2
TRDOER1
Bit
PD2_0
EA0
Setting
Value
7. Programmable I/O Ports
CMD1
TRDFCR
CMD0 STCLK PWM3
IOA2
TRDIORA0
IOA1
IOA0
Function
0
1
X
X
X
X
X
X
X
Input port(1)
1
1
X
X
X
X
X
X
X
0
0
X
X
0
X
0
X
0
1
1
1
1
0
X
0
X
0
Output port(2)
Timer mode (input capture function)
External clock input (TRDCLK)
X
0
0
0
0
0
X
X
X
PWM3 mode waveform output(2)
X
0
0
0
0
1
0
0
0
1
1
X
Timer mode waveform output
(output compare function)(2)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR0 bit in the P2DRR register to 1.
Table 7.21
Port P2_1/TRDIOB0
Register
PD2
TRDOER1
TRDFCR
TRDPMR
TRDIORA0
Bit
PD2_1
EB0
CMD1 CMD0 PWM3
PWMB0
IOB2 IOB1 IOB0
0
1
X
X
X
X
X
X
X
Input port(1)
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform output
Setting
Value
Function
X
0
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform output
X
0
0
0
0
X
X
X
X
PWM3 mode waveform output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
0
0
1
0
1
X
Timer mode waveform output (output compare
function)(2)
X
0
0
0
1
0
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR1 bit in the P2DRR register to 1.
Table 7.22
Port P2_2/TRDIOC0
Register
PD2
TRDOER1
Bit
PD2_2
EC0
Setting
Value
TRDFCR
CMD1
CMD0 PWM3
TRDPMR
TRDIORC0
PWMC0
IOC2 IOC1 IOC0
Function
Input port(1)
0
1
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
X
0
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform
output(2)
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform
output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
0
0
1
0
1
X
Timer mode waveform output (output
compare function)(2)
X
0
0
0
1
0
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR2 bit in the P2DRR register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 76 of 580
R8C/2A Group, R8C/2B Group
Table 7.23
7. Programmable I/O Ports
Port P2_3/TRDIOD0
Register
PD2
TRDOER1
Bit
PD2_3
ED0
CMD1
0
1
X
X
X
X
X
X
X
Input port(1)
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform
output(2)
Setting
Value
TRDFCR
CMD0 PWM3
TRDPMR
TRDIORC0
PWMD0
IOD2 IOD1 IOD0
Function
X
0
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform
output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
0
0
1
0
1
X
Timer mode waveform output (output
compare function)(2)
X
0
0
0
1
0
X: 0 or 1
NOTES:
1. Pulled up by setting the PU04 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR3 bit in the P2DRR register to 1.
Table 7.24
Port P2_4/TRDIOA1
Register
PD2
TRDOER1
Bit
PD2_4
EA1
Setting
Value
TRDFCR
CMD1
TRDIORA1
CMD0 PWM3 IOA2
Function
IOA1 IOA0
Input port(1)
0
1
X
X
X
X
X
X
1
1
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
1
X
X
Timer mode (input capture function)
X
0
1
0
1
1
X
X
X
X
Complementary PWM mode waveform output(2)
X
0
0
1
X
X
X
X
Reset synchronous PWM mode waveform output(2)
0
0
1
0
1
X
Timer mode waveform output
(output compare function)(2)
X
0
0
0
1
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR4 bit in the P2DRR register to 1.
Table 7.25
Port P2_5/TRDIOB1
Register
PD2
TRDOER1
Bit
PD2_5
EB1
CMD1
0
1
X
X
X
X
X
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
X
0
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform
output(2)
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform
output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
X
0
0
0
1
0
Timer mode waveform output (output
compare function)(2)
Setting
Value
TRDFCR
CMD0 PWM3
TRDPMR
TRDIORA1
PWMB1
IOB2 IOB1 IOB0
X
X
0
0
1
0
1
X
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR5 bit in the P2DRR register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 77 of 580
Function
Input port(1)
R8C/2A Group, R8C/2B Group
Table 7.26
7. Programmable I/O Ports
Port P2_6/TRDIOC1
Register
PD2
TRDOER1
Bit
PD2_6
EC1
CMD1
0
1
X
X
X
X
X
X
X
Input port(1)
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform
output(2)
Setting
Value
TRDFCR
CMD0 PWM3
TRDPMR
TRDIORC1
PWMC1
IOC2 IOC1 IOC0
Function
X
0
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform
output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
0
0
1
0
1
X
Timer mode waveform output (output
compare function)(2)
X
0
0
0
1
0
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR6 bit in the P2DRR register to 1.
Table 7.27
Port P2_7/TRDIOD1
Register
PD2
TRDOER1
Bit
PD2_7
ED1
CMD1
0
1
X
X
X
X
X
X
X
1
1
X
X
X
X
X
X
X
Output port(2)
0
X
0
0
1
0
1
X
X
Timer mode (input capture function)
X
0
1
0
1
1
X
X
X
X
X
Complementary PWM mode waveform
output(2)
X
0
0
1
X
X
X
X
X
Reset synchronous PWM mode waveform
output(2)
X
0
0
0
1
1
X
X
X
PWM mode waveform output(2)
X
0
0
0
1
0
Timer mode waveform output
(output compare function)(2)
Setting
Value
TRDFCR
CMD0 PWM3
TRDPMR
TRDIORC1
PWMD1
IOD2 IOD1 IOD0
0
0
1
0
1
X
X: 0 or 1
NOTES:
1. Pulled up by setting the PU05 bit in the PUR0 register to 1.
2. Output drive capacity high by setting the P2DRR7 bit in the P2DRR register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 78 of 580
Function
Input port(1)
R8C/2A Group, R8C/2B Group
Table 7.28
Register
Bit
7. Programmable I/O Ports
Port P3_0/TRAO
PD3
PD3_0
TRAIOC
TOENA
0
0
1
X
0
1
Setting
Value
Function
Input port(1)
Output port
TRAO output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 7.29
Register
Bit
Setting
Value
Port P3_1/TRBO
PD3
PD3_1
TMOD1
TRBMR
TMOD0
TRBIOC
TOCNT
0
0
0
X
1
X
X
0
0
X
1
0
01b
Other than 00b
Function
Input port(1)
Output port
TRBO output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 7.30
Register
Bit
Setting
Value
Port P3_2/(INT2)
PD3
PD3_2
INTEN
INT2EN
PMR
INT2SEL
0
X
X
1
X
X
Input port(1)
Output port
0
1
1
INT2 input
Function
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 7.31
Port P3_3/SSI
Register
PD3
Bit
PD3_3
0
Setting
Value
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
SSI output control
SSI input control
0
0
X
X
X
0
X
0
X
1
1
PMR
IICSEL
0
Function
Input port(1)
0
X
1
1
0
1
0
SSI input
0
0
SSI output(2)
Output port(2)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 79 of 580
R8C/2A Group, R8C/2B Group
Table 7.32
Register
Bit
Setting
Value
7. Programmable I/O Ports
Port P3_4/SDA/SCS
PD3
PD3_4
0
0
1
1
SSMR2
CSS1
CSS0
0
0
0
0
0
0
0
0
X
X
0
1
1
1
X
0
1
X
PMR
IICSEL
0
X
0
X
ICCR1
ICE
X
0
X
0
0
X
SCS input
0
X
SCS output(2)
Function
Input port(1)
Output port(2)
X
1
1
SDA input/output
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.33
Port P3_5/SCL/SSCK
Register
PD3
Bit
PD3_5
0
0
1
1
X
Setting
Value
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
SSCK output control
SSCK input control
0
0
0
0
0
0
0
0
0
1
PMR
ICCR1
IICSEL
0
X
0
X
0
ICE
X
0
X
0
0
X
1
0
0
0
X
1
0
1
1
Function
Input port(1)
Output port(2)
SSCK input
SSCK output(2)
SCL input/output
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open-drain output by setting the SCKOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.34
Register
Bit
Port P3_6/(INT1)
PD3
PD3_6
INTEN
INT1EN
PMR
INT1SEL
0
X
X
1
X
X
Input port(1)
Output port
0
1
1
INT1 input
Setting
Value
Function
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Table 7.35
Port P3_7/SSO
Register
PD3
Bit
PD3_7
0
Setting
Value
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
SSO output control
SSO input control
0
0
X
X
SSMR2
PMR
SOOS
IICSEL
0
1
X
X
X
0
X
0
1
0
X
1
0
0
0
0
1
0
0
X
1
0
1
0
1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 80 of 580
0
Function
Input port(1)
Output port
SSO input
SSO output (CMOS output)
SSO output (N-channel open-drain
output)
R8C/2A Group, R8C/2B Group
Table 7.36
VREF
Register
Bit
ADCON1
VCUT
0
1
Setting
Value
Table 7.37
7. Programmable I/O Ports
Function
Not the pin function
VREF input
Port P4_3/XCIN
Register
PD4
CM0
Bit
PD4_3
CM04
CM10
CM12
0
0
X
X
OFF
OFF
1
0
X
X
OFF
OFF
X
1
0
0
ON
ON
X
1
0
1
ON
OFF
X
1
1
X
1
0
0
1
0
1
OFF
OFF
ON
ON
ON
OFF
ON
OFF
Setting
Value
CM1
Circuit specifications
Oscillation Feedback
buffer
resistor
Function
Input port(1)
Output port
XCIN-XCOUT oscillation (on-chip feedback resistor
enabled)
XCIN-XCOUT oscillation (on-chip feedback resistor
disabled)
XCIN-XCOUT oscillation stop
External XCIN input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU10 bit in the PUR1 register to 1.
Table 7.38
Port P4_4/XCOUT
Register
PD4
CM0
Bit
PD4_4
CM04
CM10
CM12
0
0
X
X
OFF
OFF
1
0
X
X
OFF
OFF
X
1
0
0
ON
ON
X
1
0
1
ON
OFF
X
1
1
X
1
0
0
1
0
1
OFF
OFF
ON
ON
ON
OFF
ON
OFF
Setting
Value
CM1
Circuit specifications
Oscillation Feedback
buffer
resistor
Function
Input port(1)
Output port
XCIN-XCOUT oscillation (on-chip feedback resistor
enabled)
XCIN-XCOUT oscillation (on-chip feedback resistor
disabled)
XCIN-XCOUT oscillation stop
External XCOUT output (inverted output of XCIN)(2)
X: 0 or 1
NOTES:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
2. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as
the CMOS level signal directly.
Table 7.39
Port P4_5/INT0
Register
Bit
PD4
PD4_5
INTEN
INT0EN
Setting
Value
0
X
1
X
0
1
Function
Input port(1)
Output port
INT0 input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 81 of 580
R8C/2A Group, R8C/2B Group
Table 7.40
7. Programmable I/O Ports
Port P4_6/XIN
Register
CM1
CM0
Bit
CM13
CM10
CM05
Setting
Value
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Circuit specifications
Oscillation
Feedback
buffer
resistor
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
Function
Input port
XIN-XOUT oscillation
External XIN input
XIN-XOUT oscillation stop
XIN-XOUT oscillation stop
X: 0 or 1
Table 7.41
Port P4_7/XOUT
Register
CM1
CM0
Bit
CM13
CM10
CM05
Setting
Value
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
X: 0 or 1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 82 of 580
Circuit specifications
Oscillation
Feedback
buffer
resistor
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
Function
Input port
XIN-XOUT oscillation
XOUT is “H” pull-up
XIN-XOUT oscillation stop
XIN-XOUT oscillation stop
R8C/2A Group, R8C/2B Group
Table 7.42
Register
Bit
7. Programmable I/O Ports
Port P5_0/TRCCLK
PD5
PD5_0
Setting
Value
TRCCR1
TCK1
TCK2
0
Other than 101b
1
0
Other than 101b
0
1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
Table 7.43
Register
Bit
Function
TCK0
Input port(1)
Output port
TRCCLK input
1
Port P5_1/TRCIOA/TRCTRG
PD5
PD5_1
Timer RC Setting
−
0
Other than TRCIOA usage conditions
1
X
0
Setting
Value
Function
Refer to Table 7.44 TRCIOA Pin Setting
Input port(1)
Output port
TRCIOA output
TRCIOA input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
Table 7.44
Register
Bit
Setting
value
TRCIOA Pin Setting
TRCOER
EA
TRCMR
PWM2
0
1
0
1
0
1
IOA2
0
0
TRCIOR0
IOA1
0
1
IOA0
1
X
1
1
X
X
0
X
X
X
TRCCR2
TCEG1
TCEG2
X
X
X
X
X
X
X
X
0
1
1
X
Other than above
Function
Timer waveform output
(output compare function)
Timer mode (input capture function)
PWM2 mode TRCTRG input
Other than TRCIOA usage conditions
X: 0 or 1
Table 7.45
Register
Bit
Port P5_2/TRCIOB
PD5
PD5_2
Timer RC Setting
−
0
Setting
Value
Function
Other than TRCIOB usage conditions
1
X
0
Refer to Table 7.46 TRCIOB Pin Setting
Input port(1)
Output port
TRCIOB output
TRCIOB input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
Table 7.46
Register
Bit
Setting
value
TRCIOB Pin Setting
TRCOER
EB
0
0
TRCMR
PWM2
PWMB
0
X
1
1
0
1
0
0
1
1
0
IOB2
X
X
0
0
TRCIOR0
IOB1
X
X
0
1
IOB0
X
X
1
X
1
X
X
Other than above
X: 0 or 1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 83 of 580
Function
PWM2 mode waveform output
PWM mode waveform output
Timer waveform output (output compare
function)
Timer mode (input capture function)
Other than TRCIOB usage conditions
R8C/2A Group, R8C/2B Group
Table 7.47
Register
Bit
7. Programmable I/O Ports
Port P5_3/TRCIOC
PD5
PD5_3
Timer RC Setting
−
0
Other than TRCIOC usage conditions
1
X
0
Setting
Value
Function
Refer to Table 7.48 TRCIOC Pin Setting
Input port(1)
Output port
TRCIOC output
TRCIOC input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
Table 7.48
Register
Bit
Setting
value
TRCIOC Pin Setting
TRCOER
EC
0
TRCMR
PWM2
PWMC
1
1
0
1
0
0
1
1
0
IOC2
X
0
0
TRCIOR1
IOC1
X
0
1
IOC0
X
1
X
1
X
X
Other than above
Function
PWM mode waveform output
Timer waveform output (output compare function)
Timer mode (input capture function)
Other than TRCIOC usage conditions
X: 0 or 1
Table 7.49
Register
Bit
Port P5_4/TRCIOD
PD5
PD5_4
Timer RC Setting
−
0
Other than TRCIOD usage conditions
1
X
0
Setting
Value
Function
Refer to Table 7.50 TRCIOD Pin Setting
Input port(1)
Output port
TRCIOD output
TRCIOD input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU13 bit in the PUR1 register to 1.
Table 7.50
Register
Bit
Setting
value
TRCIOD Pin Setting
TRCOER
EC
0
TRCMR
PWM2
PWMD
1
1
0
1
0
0
1
1
0
IOD2
X
0
0
TRCIOR1
IOD1
X
0
1
IOD0
X
1
X
1
X
X
Other than above
X: 0 or 1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 84 of 580
Function
PWM mode waveform output
Timer waveform output (output compare function)
Timer mode (input capture function)
Other than TRCIOD usage conditions
R8C/2A Group, R8C/2B Group
Table 7.51
Register
Bit
7. Programmable I/O Ports
Port P6_0/TREO
PD6
PD6_0
TRECR1
TOENA
0
0
1
X
0
1
Setting
Value
Function
Input port(1)
Output port
TREO output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.52
Port P6_1
Register
Bit
PD6
PD6_1
Setting
Value
0
Function
Input port(1)
Output port
1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.53
Port P6_2
Register
Bit
PD6
PD6_2
Setting
Value
0
Function
Input port(1)
Output port
1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.54
Register
Bit
Port P6_3/TXD2
PD6
PD6_3
SMD2
0
X
0
X
0
1
1
1
0
1
1
1
0
1
Setting
Value
X
X
U2MR
SMD1
0
X
0
X
0
0
0
1
0
0
0
1
SMD0
0
X
0
X
1
0
1
0
1
0
1
0
U2C0
NCH
Function
X
Input port(1)
X
Output port
0
TXD2 output (CMOS output)
1
TXD2 output (N-channel open-drain
output)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.55
Port P6_4/RXD2
Register
Bit
Setting
Value
PD6
PD6_4
0
1
Function
Input port(1)
Output port
0
RXD2 input(1)
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 85 of 580
R8C/2A Group, R8C/2B Group
Table 7.56
Register
Bit
Setting
Value
7. Programmable I/O Ports
Port P6_5/(CLK1)/CLK2
PD6
PMR
PD6_5 U1PINSEL
X
0
0
X
X
1
0
X
0
1
X
1
0
X
X
X
U1MR
SMD2 SMD1 SMD0
Other than 001b
X
X
X
X
X
X
Other than 001b
X
X
X
X
X
X
X
X
X
0
0
1
X
X
X
0
0
1
U1SR
CKDIR CLK11PSEL CLK10PSEL
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
X
X
1
1
0
0
1
0
X
0
Function
Input port(1)
Output port
CLK1 (external clock) input
CLK1 (internal clock) output
CLK2 (external clock) input
CLK2 (internal clock) output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.57
Register
Bit
Port P6_6/INT2/TXD1
PD6
PD6_6
0
1
PMR
U1PINSEL
X
0
X
0
SMD2
0
X
0
X
U1MR
SMD1
0
X
0
X
SMD0
0
X
0
X
X
X
X
X
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
Setting
Value
X
1
X
1
U1C0
NCH
INTEN
INT2EN
PMR
INT2SEL
X
X
X
Input port(1)
X
X
X
Output port
X
1
0
INT2 input
0
X
X
TXD1 output (CMOS output)
1
X
X
TXD1 output (N-channel opendrain)
Function
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.58
Register
Bit
Setting
Value
Port P6_7/INT3/RXD1
PD6
PD6_7
PMR
U1PINSEL
INTEN
INT3EN
0
X
X
1
X
X
0
X
1
INT3 input
0
1
X
RXD1 input(1)
X: 0 or 1
NOTE:
1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 86 of 580
Function
Input port(1)
Output port
R8C/2A Group, R8C/2B Group
Table 7.59
7. Programmable I/O Ports
Port P8_0/TRFO00
Register
Bit
PD8
PD8_0
TRFOUT
TRFOUT0
P8
P8_0
0
0
X
Setting
Value
1
X
X
0
1
1
X
0
1
Function
Input port(1)
Output port
TRFO00 output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
Table 7.60
Register
Bit
Setting
Value
Port P8_1/TRFO01
PD8
PD8_1
TRFOUT
TRFOUT1
P8
P8_1
0
0
X
1
X
X
0
1
1
X
0
1
Function
Input port(1)
Output port
TRFO01 output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
Table 7.61
Port P8_2/TRFO02
Register
Bit
PD8
PD8_2
TRFOUT
TRFOUT2
P8
P8_2
0
0
X
Setting
Value
1
X
X
0
1
1
X
0
1
Function
Input port(1)
Output port
TRFO02 output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
Table 7.62
Register
Bit
Setting
Value
Port P8_3/TRFO10/TRFI
PD8
PD8_3
TRFOUT
TRFOUT3
P8
P8_3
0
0
X
1
X
X
0
0
1
1
0
X
0
1
X
Function
Input port(1)
Output port
TRFO02 output
TRFI input
X: 0 or 1
NOTE:
1. Pulled up by setting the PU22 bit in the PUR2 register to 1.
Table 7.63
Port P8_4/TRFO11
Register
Bit
PD8
PD8_4
TRFOUT
TRFOUT4
P8
P8_4
0
0
X
Setting
Value
1
X
X
0
1
1
X
0
1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 87 of 580
Function
Input port(1)
Output port
TRFO11output
R8C/2A Group, R8C/2B Group
Table 7.64
7. Programmable I/O Ports
Port P8_5/TRFO12
Register
Bit
PD8
PD8_5
TRFOUT
TRFOUT5
P8
P8_5
0
0
X
Setting
Value
1
X
X
0
1
1
X
0
1
Function
Input port(1)
Output port
TRFO12output
X: 0 or 1
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
Table 7.65
Port P8_6
Register
Bit
PD8
PD8_6
Setting
Value
0
Function
Input port(1)
Output port
1
NOTE:
1. Pulled up by setting the PU23 bit in the PUR2 register to 1.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 88 of 580
R8C/2A Group, R8C/2B Group
7.5
7. Programmable I/O Ports
Unassigned Pin Handling
Table 7.66 lists Unassigned Pin Handling.
Table 7.66
Unassigned Pin Handling
Pin Name
Connection
Ports P0 to P3, P4_3 to P4_5,
• After setting to input mode, connect each pin to VSS via a resistor
P5_0 to P5_4, P6, P8_0 to P8_6 (pull-down) or connect each pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1,2)
Ports P4_6, P4_7
Connect to VCC via a pull-up resistor(2)
VREF
Connect to VCC
RESET (3)
Connect to VCC via a pull-up resistor(2)
NOTES:
1. If these ports are set to output mode and left open, they remain in input mode until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports remain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
MCU
Port P0 to P3, (Input mode )
:
P4_3 to P4_5,
:
P5_0 to P5_4, P6,
P8_0 to P8_6 (Input mode)
(Output mode)
Port P4_6, P4_7
RESET(1)
VREF
NOTE:
1. When the power-on reset function is in use.
Figure 7.17
Unassigned Pin Handling
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 89 of 580
:
:
Open
R8C/2A Group, R8C/2B Group
8.
8. Processor Mode
Processor Mode
8.1
Processor Modes
Single-chip mode can be selected as the processor mode.
Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Table 8.1
Features of Processor Mode
Processor Mode
Single-chip mode
Accessible Areas
Pins Assignable as I/O Port Pins
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
Address
PM0
0004h
Bit Symbol
Bit Name
—
Reserved bits
(b2-b0)
PM03
—
(b7-b4)
Softw are reset bit
After Reset
00h
Function
Set to 0.
RW
RW
The MCU is reset w hen this bit is set to 1.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
—
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 8.1
PM0 Register
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
PM1
0005h
Bit Symbol
Bit Name
—
Reserved bits
(b1-b0)
PM12
—
(b6-b3)
—
(b7)
WDT interrupt/reset sw itch bit
After Reset
00h
Function
Set to 0.
0 : Watchdog timer interrupt
1 : Watchdog timer reset(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Reserved bit
Set to 0.
NOTES:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
2. The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Figure 8.2
PM1 Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 90 of 580
RW
RW
RW
—
RW
R8C/2A Group, R8C/2B Group
9.
9. Bus
Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/2A Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/2B Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations and Table 9.4 lists Access Units and Bus Operations of SFR (address
0200h to 02FFh).
Table 9.1
Bus Cycles by Access Space of the R8C/2A Group
Access Area
SFR (address 0000h to 01FFh)
SFR (address 0200h to 02FFh)
ROM/RAM
Table 9.2
Bus Cycle
2 cycles of CPU clock
3 cycles of CPU clock
1 cycle of CPU clock
Bus Cycles by Access Space of the R8C/2B Group
Access Area
SFR (address 0000h to 01FFh)/Data flash
SFR (address 0200h to 02FFh)
Program ROM/RAM
Table 9.3
Bus Cycle
2 cycles of CPU clock
3 cycles of CPU clock
1 cycle of CPU clock
Access Units and Bus Operations
Area
Even address
Byte access
SFR (address 0000h to 01FFh), data flash
CPU clock
CPU
clock
Address
Even
Data
Odd address
Byte access
Odd
Address
Data
CPU
clock
Data
Even
Even + 1
Data
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Data
Odd
Data
Address
Data
Even
Data
Even + 1
Data
CPU
clock
CPU
clock
Data
Data
CPU
clock
Data
Address
Data
Even
CPU
clock
CPU
clock
Address
Address
Odd address
Word access
Address
Data
Data
Even address
Word access
ROM (program ROM), RAM
Odd
Data
Page 91 of 580
Odd + 1
Data
Address
Data
Odd
Data
Odd + 1
Data
R8C/2A Group, R8C/2B Group
Table 9.4
9. Bus
Access Units and Bus Operations of SFR (address 0200h to 02FFh)
Area
Even address
Byte access
SFR (address 0200h to 02FFh)
CPU clock
Address
Even
Data
Odd address
Byte access
Data
CPU clock
Address
Odd
Data
Even address
Word access
Data
CPU clock
Address
Even
Data
Odd address
Word access
Even + 1
Data
Data
CPU clock
Address
Odd
Odd + 1
Data
Data
Data
However, only following SFRs are connected with the 16-bit bus:
Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Timer RD: registers TRDi (i = 0,1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, data flash, even address
byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 92 of 580
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
10. Clock Generation Circuit
The clock generation circuit has:
• XIN clock oscillation circuit
• XCIN clock oscillation circuit
• Low-speed on-chip oscillator
• High-speed on-chip oscillator
Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figure 10.2
shows a Peripheral Function Clock. Figures 10.3 to 10.9 show clock associated registers. Figure 10.10 shows a
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
Table 10.1
Specifications of Clock Generation Circuit
Item
Applications
XIN Clock
Oscillation Circuit
XCIN Clock Oscillation
Circuit
• CPU clock source • CPU clock source
• Peripheral function • Timer RA and timer RE
clock source
clock source
32.768 kHz
On-Chip Oscillator
High-Speed On-Chip
Low-Speed On-Chip
Oscillator
Oscillator
• CPU clock source
• CPU clock source
• Peripheral function
• Peripheral function
clock source
clock source
• CPU and peripheral
• CPU and peripheral
function clock
function clock
sources when XIN
sources when XIN
clock stops oscillating clock stops oscillating
Approx. 125 kHz
Approx. 40 MHz(4)
Clock frequency
0 to 20 MHz
Connectable
oscillator
Oscillator
connect pins
Oscillation stop,
restart function
Oscillator status
after reset
Others
• Ceramic resonator • Crystal oscillator
• Crystal oscillator
−
−
XIN, XOUT(1)
XCIN, XCOUT(2)
−(1)
−(1)
Usable
Usable
Usable
Usable
Stop
Stop
Stop
Oscillate
−
−
• Externally generated
Externally
generated clock can clock can be input
• On-chip feedback
be input(3)
resistor Rf (connected/
not connected,
selectable)
NOTES:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit is not used.
2. These pins can be used as P4_3 and P4_4 when using the XIN clock oscillation circuit and on-chip oscillator
clock for a CPU clock while the XCIN clock oscillation circuit is not used.
3. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XINXOUT pin) when an external clock is input.
4. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 93 of 580
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Clock prescaler
fC4
fC
1/4
fC32
1/8
FRA1 register
Frequency adjustable
FRA00
XCIN
High-speed
on-chip oscillator
XCOUT
fOCO40M
FRA2 register
Divider
fOCO-F
FRA01 = 1
Divider
(1/128)
fOCO
On-chip oscillator
clock
FRA01 = 0
fOCO128
Peripheral
function
clock
fOCO
CM04
fOCO-F
Low-speed
on-chip oscillator
CM14
Power-on
reset circuit
fOCO-S
Voltage
detection
circuit
S Q
CM10 = 1 (stop mode)
fOCO-S
b
f1
R
RESET
c
Power-on reset
Software reset
Interrupt request
Oscillation
stop
detection
S Q
R
WAIT instruction
f2
d
f4
e
XIN clock
OCD2 = 1
f8
g
f32
CM13
XIN
a
Divider
CPU clock
fC
OCD2 = 0
XOUT
h CM07 = 0
CM07 = 1
CM13
CM05
System clock
CM02
1/2
a
g
e
d
c
b
1/2
1/2
1/2
1/2
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to
CM16 = 10b
h
CM06 = 0
CM17 to CM16 = 01b
CM02, CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
FRA00, FRA01: Bits in FRA0 register
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
Forcible discharge when OCD0 = 0
XIN clock
Pulse generation
circuit for clock
edge detection and
charge, discharge
control circuit
Charge,
discharge circuit
OCD1
Oscillation stop detection
interrupt generation
circuit detection
Watchdog timer
interrupt
Voltage monitor 1
interrupt
Voltage monitor 2
interrupt
OCD2 bit switch signal
CM14 bit switch signal
Figure 10.1
Clock Generation Circuit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 94 of 580
Oscillation stop detection,
Watchdog timer,
Voltage monitor 1 interrupt,
Voltage monitor 2 interrupt
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
fC4
fC32
fOCO40M
fOCO128
fOCO
fOCO-F
Watchdog
timer
fOCO-S
INT0
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
f1
f2
f4
f8
f32
CPU
CPU clock
Figure 10.2
Peripheral Function Clock
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 95 of 580
Timer RF
A/D converter
UART0 UART1
UART2
SSU /
I2C bus
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
0006h
CM0
Bit Symbol
Bit Name
—
Reserved bits
(b1-b0)
After Reset
01101000b
Function
Set to 0.
RW
RW
WAIT peripheral function clock
stop bit
0 : Peripheral function clock does not stop
in w ait mode
1 : Peripheral function clock stops in w ait
mode
RW
XCIN-XCOUT drive capacity
select bit(9)
0 : Low
1 : High
RW
Port, XCIN-XCOUT sw itch bit
0 : I/O port P4_3, P4_4
1 : XCIN-XCOUT pin(7)
RW
CM05
XIN clock (XIN-XOUT)
stop bit(2, 4)
0 : XIN clock oscillates
1 : XIN clock stops (3)
RW
CM06
System clock division select bit
0(5)
0 : CM16, CM17 enabled
1 : Divide-by-8 mode
RW
CPU clock select bit
0 : System clock
1 : XCIN clock
RW
CM02
CM03
(6)
CM04
(8)
CM07
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register.
2. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is
selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the
follow ing order:
(a) Set bits OCD1 to OCD0 in the OCD register to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
3. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged.
4. When the CM05 bit is set to 1 (XIN clock stopped) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7), P4_6
and P4_7 can be used as input ports.
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
The CM04 bit can be set to 1 by a program but cannot be set to 0.
To use the XCIN clock, set the CM04 bit to 1. Also, set ports P4_3 and P4_4 as input ports w ithout pull-up.
Set the CM07 bit to 1 from 0 (XCIN clock) after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allow ing XCIN clock
oscillation to stabilize.
9. The MCU enters stop mode, the CM03 bit is set to 1 (high). Rew rite the CM03 bit w hile the XCIN clock oscillation
stabilizes.
5.
6.
7.
8.
Figure 10.3
CM0 Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 96 of 580
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Bit Symbol
CM10
Address
0007h
Bit Name
All clock stop control bit(4, 7, 8)
After Reset
00100000b
Function
0 : Clock operates
1 : Stops all clocks (stop mode)
RW
RW
CM11
XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled
select bit
1 : On-chip feedback resistor disabled
RW
CM12
XCIN-XCOUT on-chip feedback
resistor select bit
0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled
RW
Port XIN-XOUT sw itch bit(7, 9)
0 : Input ports P4_6, P4_7
1 : XIN-XOUT pin
RW
Low -speed on-chip oscillation stop
bit(5, 6, 8)
0 : Low -speed on-chip oscillator on
1 : Low -speed on-chip oscillator off
RW
XIN-XOUT drive capacity select bit(2)
0 : Low
1 : High
RW
System clock division select bits 1(3)
b7 b6
CM13
CM14
CM15
CM16
CM17
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register.
2. When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
3. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled.
4. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled.
5. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). It remains unchanged even if 1 is w ritten to it.
6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14
bit to 0 (low -speed on-chip oscillator on).
7. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.
When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode.
8. In count source protect mode (Refer to 13.2 Count Source Protection Mode Enabled), the value remains
unchanged even if bits CM10 and CM14 are set.
9. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
Figure 10.4
CM1 Register
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R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
OCD
Bit Symbol
OCD0
OCD1
OCD2
OCD3
—
(b7-b4)
Address
After Reset
000Ch
00000100b
Bit Name
Function
Oscillation stop detection enable 0 : Oscillation stop detection function
bit(7)
disabled(2)
1 : Oscillation stop detection function
enabled
RW
RW
Oscillation stop detection
interrupt enable bit
0 : Disabled(2)
1 : Enabled
RW
System clock select bit(4)
0 : Selects XIN clock(7)
1 : Selects on-chip oscillator clock(3)
RW
Clock monitor bit(5, 6)
0 : XIN clock oscillates
1 : XIN clock stops
RO
Reserved bits
Set to 0.
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register.
2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains
unchanged even w hen set to 0 (XIN clock selected).
5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).
6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
7. Refer to Figure 10.17 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN
Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Figure 10.5
OCD Register
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R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0
Symbol
FRA0
Bit Symbol
FRA00
FRA01
—
(b7-b2)
Address
0023h
Bit Name
High-speed on-chip oscillator
enable bit
After Reset
00h
Function
0 : High-speed on-chip oscillator off
1 : High-speed on-chip oscillator on
High-speed on-chip oscillator
select bit(2)
0 : Selects low -speed on-chip oscillator
1 : Selects high-speed on-chip oscillator
Reserved bits
Set to 0.
RW
RW
(3)
RW
RW
NOTES:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register.
2. Change the FRA01 bit under the follow ing conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
• Bits FRA22 to FRA20 in the FRA2 register:
All divide ratio mode settings are supported w hen VCC = 3.0 V to 5.5 V 000b to 111b
Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V
010b to 111b (divide by 4 or more)
Divide ratio of 8 or more w hen VCC = 2.2 V to 5.5 V
110b to 111b (divide by 8 or more)
3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time.
Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
High-Speed On-Chip Oscillator Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA1
Address
0024h
After Reset
When Shipping
Function
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping)
Setting the FRA1 register to a low er value results in a higher frequency.
Setting the FRA1 register to a higher value results in a low er frequency.(2)
RW
RW
NOTE:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register.
2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
Figure 10.6
Registers FRA0 and FRA1
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10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
FRA2
Bit Symbol
FRA20
Address
0025h
Bit Name
High-speed on-chip oscillator
frequency sw itching bits
b2 b1 b0
0 0 0: Divide-by-2 mode
0 0 1: Divide-by-3 mode
0 1 0: Divide-by-4 mode
0 1 1: Divide-by-5 mode
1 0 0: Divide-by-6 mode
1 0 1: Divide-by-7 mode
1 1 0: Divide-by-8 mode
1 1 1: Divide-by-9 mode
FRA21
FRA22
—
(b7-b3)
After Reset
00h
Function
Selects the dividing ratio for the highspeed on-chip oscillator clock.
Reserved bits
Set to 0.
RW
RW
RW
RW
RW
NOTE:
1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.
High-Speed On-Chip Oscillator Control Register 6
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA6
Address
002Bh
After Reset
When Shipping
Function
Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction
to match the voltage conditions can be achieved by transferring this value to the FRA1
register.
RW
RO
High-Speed On-Chip Oscillator Control Register 7
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FRA7
Address
002Ch
After Reset
When Shipping
Function
36.864 MHz frequency correction data is stored.
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz
by transferring this value to the FRA1 register.
Figure 10.7
Registers FRA2, FRA6 and FRA7
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RW
RO
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Symbol
Address
0028h
CPSRF
Bit Symbol
Bit Name
—
Reserved bits
(b6-b0)
After Reset
00h
Function
Set to 0.
Clock prescaler reset flag
(1)
CPSR
Setting this bit to 1 initializes the clock
prescaler. (When read, the content is 0)
RW
RW
RW
NOTE:
1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
Figure 10.8
CPSRF Register
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
VCA2
Bit Symbol
VCA20
—
(b4-b1)
Address
0032h
Bit Name
Internal pow er low
consumption enable bit(6)
After Reset(5)
The LVD0ON bit in the OFS register is
set to 1 and hardw are reset
: 00h
Pow er-on reset, voltage monitor 0 reset
or LVD0ON bit in the OFS register is
set to 0, and hardw are reset
: 00100000b
Function
0 : Disables low consumption
1 : Enables low consumption
RW
RW
Reserved bits
Set to 0.
VCA25
Voltage detection 0 enable
bit(2)
0 : Voltage detection 0 circuit disabled
1 : Voltage detection 0 circuit enabled
RW
VCA26
Voltage detection 1 enable
bit(3)
0 : Voltage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled
RW
VCA27
Voltage detection 2 enable
bit(4)
0 : Voltage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled
RW
RW
NOTES:
1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
2. To use the voltage monitor 0 reset, set the VCA25 bit to 1.
After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting
operation.
5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure
10.10 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 10.9
VCA2 Register
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R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Exit wait mode by interrupt
Handling procedure of internal power
low consumption enabled by VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (4)
Enter wait mode(4)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (7) in the interrupt
routine.
Interrupt handling
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 10.10
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
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R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
The clocks generated by the clock generation circuits are described below.
10.1
XIN Clock
This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN
pin.
Figure 10.11 shows Examples of XIN Clock Connection Circuit.
In reset and after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after
setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin).
To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after
the XIN clock is oscillating stably.
The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the
OCD2 bit is set to 1 (select on-chip oscillator clock).
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If
necessary, use an external circuit to stop the clock.
In stop mode, all clocks including the XIN clock stop. Refer to 10.5 Power Control for details.
MCU
(on-chip feedback resistor)
MCU
(on-chip feedback resistor)
XIN
XIN
XOUT
Rf(1)
CIN
XOUT
Open
Rd(1)
COUT
Externally derived clock
VCC
VSS
Ceramic resonator external circuit
External clock input circuit
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the
oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so
after oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator
manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a
feedback resistor between XIN and XOUT following the instructions.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the
CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and
connect the feedback resistor to the chip externally.
Figure 10.11
Examples of XIN Clock Connection Circuit
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R8C/2A Group, R8C/2B Group
10.2
10. Clock Generation Circuit
On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1
Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
10.2.2
High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fOCO-F, and fOCO40M.
To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO,
and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows:
• All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V 000b to 111b
• Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V
010b to 111b (divide by 4 or more)
• Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V
110b to 111b (divide by 8 or more)
After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by registers FRA1 and FRA2.
Furthermore, frequency correction data corresponding to the supply voltage ranges VCC = 2.2 V to 5.5 V is
stored in FRA6 register. To use separate correction values to match this voltage ranges, transfer them from the
FRA6 register to the FRA1 register.
The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the highspeed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register
before use.
Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make
adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the
high-speed on-chip oscillator clock will be 40 MHz or less.
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R8C/2A Group, R8C/2B Group
10.3
10. Clock Generation Circuit
XCIN Clock
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU
clock, timer RA, and timer RE. The XCIN clock oscillation circuit is configured by connecting a resonator between
the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the
chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the
XCIN pin.
Figure 10.12 shows Examples of XCIN Clock Connection Circuits.
During and after reset, the XCIN clock stops.
The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin).
To use the XCIN clock for the CPU clock source, set the CM07 bit in the CM0 register to 1 (XCIN clock) after the
XCIN clock is oscillating stably. To input an external clock to the XCIN pin, set the CM04 bit in the CM0 register
to 1 (XCIN-XCOUT pin) and leave the XCOUT pin open.
This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12
bit in the CM1 register.
In stop mode, all clocks including the XCIN clock stop. Refer to 10.5 Power Control for details.
MCU
(on-chip feedback resistor)
XCIN
MCU
(on-chip feedback resistor)
XCIN
XCOUT
XCOUT
Open
Rf(1)
CIN
Rd(1)
COUT
Externally derived clock
VCC
VSS
External crystal oscillator circuit
External clock input circuit
NOTE:
1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and
the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between
XCIN and XCOUT following the instructions.
Figure 10.12
Examples of XCIN Clock Connection Circuits
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R8C/2A Group, R8C/2B Group
10.4
10. Clock Generation Circuit
CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 10.1 Clock Generation Circuit.
10.4.1
System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the
on-chip oscillator clock can be selected.
10.4.2
CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
When the CM07 bit in the CM0 register is set to 0 (system clock), the system clock can be divided by 1 (no
division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to
CM17 in the CM1 register to select the value of the division.
When the CM07 bit in the CM0 register is set to 1 (XCIN clock), the XCIN clock is used for the CPU clock.
Use the XCIN clock while the XCIN clock oscillation stabilizes.
After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
10.4.3
Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers
RA, RB, RC, RD, and RE, the serial interface and the A/D converter. The f1, f8, and f32 clock are used for
timer RF.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.4.4
fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clocks fOCO does not stop.
10.4.5
fOCO40M
fOCO40M is used as the count source for timer RC and timer RD. fOCO40M is generated by the high-speed
on-chip oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.4.6
fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does not stop.
10.4.7
fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed onchip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer,
fOCO-S does not stop.
10.4.8
fOCO128
fOCO128 is generated by fOCO divided by 128.
The clock fOCO128 is used for capture signal of timer RD (channel 0).
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R8C/2A Group, R8C/2B Group
10.4.9
fC4 and fC32
The clock fC4 and fC32 are used for timer RA and timer RE.
Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
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10. Clock Generation Circuit
R8C/2A Group, R8C/2B Group
10.5
10. Clock Generation Circuit
Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
10.5.1
Standard Operating Mode
Standard operating mode is further separated into four modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation is stabilized before exiting.
Table 10.2
Settings and Modes of Clock Associated Bits
OCD
Register
Modes
Low-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
CM0 Register
FRA0 Register
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
0
0
0
0
0
CM17,
CM16
00b
01b
10b
−
11b
−
−
−
−
1
−
−
1
−
−
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
1
1
1
1
1
1
1
1
1
1
00b
01b
10b
−
11b
00b
01b
10b
−
11b
−
−
−
−
−
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
−
−
−
−
−
OCD2
High-speed
clock mode
CM1 Register
−: can be 0 or 1, no change in outcome
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CM14
CM13
CM07
CM06
CM05
CM04 FRA01 FRA00
−
−
−
−
−
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
R8C/2A Group, R8C/2B Group
10.5.1.1
10. Clock Generation Circuit
High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (highspeed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can
be used for the watchdog timer and voltage detection circuit.
10.5.1.2
Low-Speed Clock Mode
The XCIN clock divided by 1 (no division) provides the CPU clock.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
When the FRA00 bit is set to 1, fOCO40M can be used as timer RC and timer RD. When the CM14 bit is set to
0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit.
To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal
power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.5.1.3
High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as
timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used
for the watchdog timer and voltage detection circuit.
10.5.1.4
Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as
timer RC and timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used
as the watchdog timer and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumption enabled) enables lower consumption current in wait mode.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
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REJ09B0324-0200
Page 109 of 580
R8C/2A Group, R8C/2B Group
10.5.2
10. Clock Generation Circuit
Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, and on-chip oscillator
clock do not stop and the peripheral functions using these clocks continue operating.
10.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop
in wait mode. This reduces power consumption.
10.5.2.2
Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.5.2.3
Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
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R8C/2A Group, R8C/2B Group
10.5.2.4
10. Clock Generation Circuit
Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function interrupt.
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions.
Table 10.3
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt
Serial interface interrupt
CM02 = 0
CM02 = 1
Usable when operating with internal Usable when operating with external
or external clock
clock
Clock synchronous serial I/O Usable in all modes
(Do not use)
with chip select interrupt / I2C
bus interface interrupt
Key input interrupt
Usable
Usable
A/D conversion interrupt
Usable in one-shot mode
(Do not use)
Timer RA interrupt
Usable in all modes
Can be used if there is no filter in
event counter mode.
Usable by selecting fOCO or fC32
as count source.
Timer RB interrupt
Usable in all modes
(Do not use)
Timer RC interrupt
Usable in all modes
(Do not use)
Timer RD interrupt
Usable in all modes
Usable by selecting fOCO40M as
count source
Timer RE interrupt
Usable in all modes
Usable when operating in real time
clock mode
Timer RF interrupt
Usable in all modes
(Do not use)
Usable
INT interrupt
Usable (INT0 to INT3 can be used if
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
Oscillation stop detection
interrupt
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REJ09B0324-0200
Usable
Usable
Usable
Page 111 of 580
there is no filter.)
Usable
Usable
(Do not use)
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Figure 10.13 shows the Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register
and the CM07 bit in the CM0 register, as described in Figure 10.13.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
FMR0 Register
CM0 Register
FMSTP Bit
CM07 Bit
Time until Flash Memory
is Activated (T1)
Time until CPU Clock
is Supplied (T2)
Time for Interrupt
Sequence (T3)
0
(system clock)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of CPU clock
× 6 cycles
Period of CPU clock
× 20 cycles
1
(XCIN clock)
Period of XCIN clock
× 12 cycles + 30 µs (max.)
Same as above
Same as above
0
(system clock)
Period of system clock
× 12 cycles
Same as above
Same as above
1
(XCIN clock)
Period of XCIN clock
× 12 cycles
Same as above
Same as above
0
(flash memory
operates)
1
(flash memory
stops)
Wait mode
T2
T3
Flash memory
activation sequence
CPU clock restart sequence
Interrupt sequence
Time from Wait Mode to Interrupt Routine Execution
Rev.2.00 Nov 26, 2007
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Following total
time is the time
from wait mode
until an interrupt
routine is
executed.
T1
Interrupt request generated
Figure 10.13
Remarks
Page 112 of 580
R8C/2A Group, R8C/2B Group
10.5.2.5
10. Clock Generation Circuit
Reducing Internal Power Consumption
Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator
mode. Figure 10.14 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.14 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Exit wait mode by interrupt
Handling procedure of internal power
low consumption enabled by VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or low-speed
on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (4)
Enter wait mode(4)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
Step (5)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Step (6)
Start XIN clock or high-speed on-chip
oscillator clock
Step (7)
(Wait until XIN clock oscillation stabilizes)
Step (8)
Enter high-speed clock mode or
high-speed on-chip oscillator mode
If it is necessary to start
the high-speed clock or
the high-speed on-chip
oscillator in the interrupt
routine, execute steps (5)
to (7) in the interrupt
routine.
Interrupt handling
Step (1)
Enter low-speed clock mode or
low-speed on-chip oscillator mode
Step (2)
Stop XIN clock and high-speed on-chip
oscillator clock
Step (3)
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
If the high-speed clock or
high-speed on-chip
oscillator is started in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt routine.
Interrupt handling completed
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine.
2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.7.2 Wait Mode.
VCA20: Bit in VCA2 register
Figure 10.14
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
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REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
10.5.3
10. Clock Generation Circuit
Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals continue operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
Table 10.4
Interrupts to Exit Stop Mode and Usage Conditions
Interrupt
Key input interrupt
Usage Conditions
−
INT0 to INT3 interrupt
Timer RA interrupt
Serial interface interrupt
Voltage monitor 1 interrupt
Voltage monitor 2 interrupt
10.5.3.1
Can be used if there is no filter
Can be used if there is no filter when external pulse is counted in event
counter mode
When external clock is selected
Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set
to 1)
Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set
to 1)
Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is
set to 1 (XIN clock oscillator circuit drive capacity high).
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.5.3.2
Pin Status in Stop Mode
The status before wait mode was entered is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.
Rev.2.00 Nov 26, 2007
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Page 114 of 580
R8C/2A Group, R8C/2B Group
10.5.3.3
10. Clock Generation Circuit
Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.15 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used
for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
request is generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMR0 Register
CM0 Register
FMSTP Bit
CM07 Bit
0
(flash memory
operates)
0 (system clock)
1
(flash memory stops)
Stop
mode
1 (XCIN clock)
0 (system clock)
1 (XCIN clock)
Time until Flash Memory
is Activated (T2)
Time until CPU Clock
is Supplied (T3)
Period of system clock
× 12 cycles + 30 µs (max.)
Period of XCIN clock
× 12 cycles + 30 µs (max.)
Period of system clock
× 12 cycles
Period of XCIN clock
× 12 cycles
Period of CPU clock
× 6 cycles
Same as above
Same as above
Same as above
Time for Interrupt
Sequence (T4)
Period of CPU clock Following total
× 20 cycles
time of T0 to
T4 is the time
Same as above
from stop
mode until an
Same as above
interrupt
handling is
Same as above
executed.
T0
T1
T2
T3
T4
Internal
power
stability time
Oscillation time of
CPU clock source
used immediately
before stop mode
Flash memory
activation sequence
CPU clock restart
sequence
Interrupt sequence
150 µs
Interrupt (max.)
request
generated
Figure 10.15
Time from Stop Mode to Interrupt Routine Execution
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REJ09B0324-0200
Page 115 of 580
Remarks
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Figure 10.16 shows the State Transitions in Power Control Mode.
State Transitions in Power Control Mode
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
CM04 = 1
CM07 = 1
FRA00 = 1
FRA01 = 1
CM04 = 1
CM07 = 1
High-speed clock mode
Low-speed clock mode
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
CM04 = 1
CM07 = 1
OCD2 = 1
FRA00 = 1
FRA01 = 1
CM05 = 0
CM13 = 1
OCD2 = 0
CM05 = 0
CM07 = 0
CM13 = 1
OCD2 = 0
CM14 = 0
FRA01 = 0
CM04 = 1
CM07 = 1
High-speed on-chip oscillator mode
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
Interrupt
WAIT instruction
CM10 = 1
Interrupt
Wait mode
Stop mode
CPU operation stops
All oscillators stop
CM04, CM05, CM07: Bits in CM0 register
CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 register
Figure 10.16
CM07 = 0
CM14 = 0
OCD2 = 1
FRA01 = 0
State Transitions in Power Control Mode
Rev.2.00 Nov 26, 2007
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Page 116 of 580
CM07 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
R8C/2A Group, R8C/2B Group
10.6
10. Clock Generation Circuit
Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop
detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the
following state if the XIN clock stops.
• OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
• OCD3 bit in OCD register = 1 (XIN clock stops)
• CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
• Oscillation stop detection interrupt request is generated.
Table 10.5
Specifications of Oscillation Stop Detection Function
Item
Oscillation stop detection clock and
frequency bandwidth
Enabled condition for oscillation stop
detection function
Operation at oscillation stop detection
10.6.1
Specification
f(XIN) ≥ 2 MHz
Set bits OCD1 to OCD0 to 11b
Oscillation stop detection interrupt is generated
How to Use Oscillation Stop Detection Function
• The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
•
•
•
•
•
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt
and watchdog timer interrupt, the interrupt source needs to be determined.
Table 10.6 lists Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.18 shows an Example of Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2
Interrupt.
When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU
clock and peripheral functions by a program.
Figure 10.17 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does not stop in wait mode).
Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop
mode is selected or the CM05 bit is changed).
This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1
to OCD0 to 00b.
To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip
oscillator selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
Rev.2.00 Nov 26, 2007
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Page 117 of 580
R8C/2A Group, R8C/2B Group
Table 10.6
10. Clock Generation Circuit
Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source
Bit Showing Interrupt Cause
Oscillation stop detection
(a) OCD3 bit in OCD register = 1
((a) or (b))
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer
VW2C3 bit in VW2C register = 1
Voltage monitor 1
VW1C2 bit in VW1C register = 1
Voltage monitor 2
VW2C2 bit in VW2C register = 1
Switch to XIN clock
NO
Multiple confirmations
that OCD3 bit is set to 0 (XIN
clock oscillates) ?
YES
Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0
(select XIN clock)
End
OCD3 to OCD0: Bits in OCD register
Figure 10.17
Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 118 of 580
R8C/2A Group, R8C/2B Group
10. Clock Generation Circuit
Interrupt sources judgement
OCD3 = 1 ?
(XIN clock stopped)
NO
YES
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock selected
as system clock) ?
NO
YES
VW2C3 = 1 ?
(Watchdog timer
underflow)
NO
YES
VW2C2 = 1 ?
(passing Vdet2)
NO
YES
Set OCD1 bit to 0 (oscillation stop
detection interrupt disabled). (1)
To oscillation stop detection
interrupt routine
To watchdog timer
interrupt routine
To voltage monitor 2
interrupt routine
To voltage monitor 1
interrupt routine
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C2, VW2C3: Bits in VW2C register
Figure 10.18
Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
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REJ09B0324-0200
Page 119 of 580
R8C/2A Group, R8C/2B Group
10.7
10. Clock Generation Circuit
Notes on Clock Generation Circuit
10.7.1
Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001 :
NOP
NOP
NOP
NOP
10.7.2
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
1,FMR0
FSET
I
WAIT
NOP
NOP
NOP
NOP
10.7.3
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
10.7.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
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R8C/2A Group, R8C/2B Group
11. Protection
11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, and VW2C
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
PRCR
Bit Symbol
Address
000Ah
Bit Name
Protect bit 0
PRC0
Protect bit 1
PRC1
Protect bit 2
PRC2
Protect bit 3
PRC3
After Reset
00h
Function
Writing to registers CM0, CM1, OCD, FRA0, FRA1,
and FRA2 is enabled.
0 : Disables w riting
1 : Enables w riting
RW
RW
Writing to registers PM0 and PM1 is enabled.
0 : Disables w riting
1 : Enables w riting
RW
Writing to the PD0 register is enabled.
0 : Disables w riting
1 : Enables w riting(1)
RW
Writing to registers VCA2, VW0C, VW1C, and
VW2C is enabled.
0 : Disables w riting
1 : Enables w riting
RW
—
(b5-b4)
Reserved bits
Set to 0.
—
(b7-b6)
Reserved bits
When read, the content is 0.
RW
RO
NOTE:
1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not
set to 0, set them to 0 by a program.
Figure 11.1
PRCR Register
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12. Interrupts
12. Interrupts
12.1
Interrupt Overview
12.1.1
Types of Interrupts
Figure 12.1 shows the types of Interrupts.
Software
(non-maskable interrupts)
Interrupts
Special
(non-maskable interrupts)
Hardware
Peripheral functions(1)
(maskable interrupts)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Single step(2)
Address break(2)
Address match
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. Do not use this interrupt. This is for use with development tools only.
Figure 12.1
Interrupts
• Maskable Interrupts:
• Non-Maskable Interrupts:
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
The interrupt enable flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
Page 122 of 580
R8C/2A Group, R8C/2B Group
12.1.2
12. Interrupts
Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
12.1.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
12.1.2.2
Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
12.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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R8C/2A Group, R8C/2B Group
12.1.3
12. Interrupts
Special Interrupts
Special interrupts are non-maskable.
12.1.3.1
Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the
oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3
Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4
Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5
Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by development tools only.
12.1.3.6
Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to
1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match
Interrupt.
12.1.4
Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to the descriptions of individual peripheral functions.
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12.1.5
12. Interrupts
Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low address
Mid address
Vector address (H)
Figure 12.2
12.1.5.1
0000
High address
0000
0000
Interrupt Vector
Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory.
Table 12.1
Fixed Vector Tables
Interrupt Source
Undefined instruction
Overflow
BRK instruction
Address match
Single step(1)
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1,
Voltage monitor 2
Address break(1)
(Reserved)
Reset
Vector Addresses
Remarks
Reference
Address (L) to (H)
0FFDCh to 0FFDFh Interrupt on UND
R8C/Tiny Series Software
instruction
Manual
0FFE0h to 0FFE3h Interrupt on INTO
instruction
0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
0FFE8h to 0FFEBh
12.4 Address Match
Interrupt
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
5. Resets
NOTES:
1. Do not use these interrupts. They are for use by development tools only.
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12.1.5.2
12. Interrupts
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 12.2 lists the Relocatable Vector Tables.
Table 12.2
Relocatable Vector Tables
Vector Addresses(1)
Address (L) to Address (H)
Interrupt Source
BRK instruction(3)
(Reserved)
(Reserved)
Timer RC
Timer RD
(channel 0)
Timer RD
(channel 1)
Timer RE
UART2 transmit
UART2 receive
Key input
(Reserved)
Clock synchronous
serial I/O with chip
select / I2C bus
interface(2)
Compare 1
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
INT2
Timer RA
(Reserved)
Timer RB
INT1
INT3
Timer RF
Compare 0
INT0
A/D
Capture
Software interrupt(3)
+0 to +3 (0000h to 0003h)
Software
Interrupt Control
Interrupt
Reference
Register
Number
0
−
R8C/Tiny Series Software
Manual
1 to 2
−
+28 to +31 (001Ch to 001Fh)
+32 to +35 (0020h to 0023h)
3 to 6
7
8
−
TRCIC
TRD0IC
+36 to +39 (0024h to 0027h)
9
TRD1IC
+40 to +43 (0028h to 002Bh)
+44 to +47 (002Ch to 002Fh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+60 to +63 (003Ch to 003Fh)
10
11
12
13
14
15
TREIC
S2TIC
S2RIC
KUPIC
−
SSUIC/IICIC
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
+84 to +87 (0054h to 0057h)
16
17
18
19
20
21
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
+88 to +91 (0058h to 005Bh)
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
22
23
24
25
TRAIC
−
TRBIC
INT1IC
+104 to +107 (0068h to 006Bh)
26
INT3IC
+108 to +111 (006Ch to 006Fh)
+112 to +115 (0070h to 0073h)
+116 to +119 (0074h to 0077h)
27
28
29
TRFIC
CMP0IC
INT0IC
+120 to +123 (0078h to 007Bh)
30
+124 to +127 (007Ch to 007Fh)
31
+128 to +131 (0080h to 0083h) to 32 to 63
+252 to +255 (00FCh to 00FFh)
NOTES:
1. These addresses are relative to those in the INTB register.
2. The IICSEL bit in the PMR register switches functions.
3. The I flag does not disable these interrupts.
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ADIC
CAPIC
−
−
14.3 Timer RC
14.4 Timer RD
14.5 Timer RE
15. Serial Interface
12.3 Key Input Interrupt
−
16.2 Clock Synchronous
Serial I/O with Chip
Select (SSU),
16.3 I2C bus Interface
14.6 Timer RF
15. Serial Interface
12.2 INT Interrupt
14.1 Timer RA
−
14.2 Timer RB
12.2 INT Interrupt
14.6 Timer RF
12.2 INT Interrupt
18. A/D Converter
14.6 Timer RF
R8C/Tiny Series Software
Manual
R8C/2A Group, R8C/2B Group
12.1.6
12. Interrupts
Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, TRD0IC, TRD1IC,
SSUIC, and IICIC and Figure 12.5 shows the INTiIC Register.
Interrupt Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREIC
S2TIC
S2RIC
KUPIC
CMP1IC
S0TIC
S0RIC
S1TIC
S1RIC
TRAIC
TRBIC
TRFIC
CMP0IC
ADIC
CAPIC
Bit Symbol
Address
004Ah
004Bh
004Ch
004Dh
0050h
0051h
0052h
0053h
0054h
0056h
0058h
005Bh
005Ch
005Eh
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
005Fh
XXXXX000b
Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
IR
—
(b7-b4)
Interrupt request bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
RW
RW
RW(1)
—
NOTES:
1. Only 0 can be w ritten to the IR bit. Do not w rite 1.
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents .
Figure 12.3
Interrupt Control Register
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12. Interrupts
Interrupt Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCIC
TRD0IC
TRD1IC
SSUIC/IICIC(2)
Bit Symbol
Address
0047h
0048h
0049h
After Reset
XXXXX000b
XXXXX000b
XXXXX000b
004Fh
XXXXX000b
Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
IR
—
(b7-b4)
Interrupt request bit
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
RW
RW
RO
—
NOTES:
1. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
2. The IICSEL bit in the PMR register sw itches functions.
Figure 12.4
Registers TRCIC, TRD0IC, TRD1IC, SSUIC, and IICIC
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12. Interrupts
INTi Interrupt Control Register (i=0 to 3)(2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INT2IC
INT1IC
INT3IC
Address
0055h
0059h
005Ah
After Reset
XX00X000b
XX00X000b
XX00X000b
INT0IC
005Dh
XX00X000b
Bit Symbol
Bit Name
Interrupt priority level select bits
ILVL0
ILVL1
ILVL2
IR
POL
—
(b5)
—
(b7-b6)
Function
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
RW
RW
Interrupt request bit
0 : Requests no interrupt
1 : Requests interrupt
RW(1)
Polarity sw itch bit(4)
0 : Selects falling edge
1 : Selects rising edge(3)
RW
Reserved bit
Set to 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
RW
—
NOTES:
1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.)
2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt
Sources.
Figure 12.5
INTiIC Register
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R8C/2A Group, R8C/2B Group
12.1.6.1
12. Interrupts
I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2
IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not requested).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt and the I2C bus Interface Interrupt are different. Refer to 12.5 Timer RC Interrupt, Timer RD
Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt
(Interrupts with Multiple Interrupt Request Sources).
12.1.6.3
Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
• I flag = 1
• IR bit = 1
• Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3
ILVL2 to ILVL0 Bits
000b
001b
010b
011b
100b
101b
110b
111b
Settings of Interrupt Priority
Levels
Interrupt Priority Level
Priority Order
−
Level 0 (interrupt disabled)
Level 1
Low
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
High
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Table 12.4
IPL
000b
001b
010b
011b
100b
101b
110b
111b
Interrupt Priority Levels Enabled by
IPL
Enabled Interrupt Priority Levels
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
All maskable interrupts are disabled
R8C/2A Group, R8C/2B Group
12.1.6.4
12. Interrupts
Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).(2)
(2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
(4) The CPU’s internal temporary register(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CPU Clock
Address Bus
Data Bus
Address
0000h
Undefined
Interrupt
information
RD
Undefined
SP-2 SP-1
SP-4
SP-2
SP-1
SP-4
contents contents contents
SP-3
SP-3
contents
VEC
VEC
contents
VEC+1
VEC+1
contents
VEC+2
PC
VEC+2
contents
Undefined
WR
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
Figure 12.6
Time Required for Executing Interrupt Sequence
NOTES:
1. This register cannot be accessed by the user.
2. Refer to 12.5 Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip
Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request
Sources) for the IR bit operations of the timer RC Interrupt, timer RD Interrupt, Clock Synchronous
Serial I/O with Chip Select Interrupt, and the I2C bus Interface Interrupt.
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R8C/2A Group, R8C/2B Group
12.1.6.5
12. Interrupts
Interrupt Response Time
Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt
request generation and the execution of the first instruction in the interrupt routine. The interrupt response time
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Interrupt request is generated. Interrupt request is acknowledged.
Time
Instruction
(a)
Instruction in
interrupt routine
Interrupt sequence
20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a
register is set as the divisor).
(b) 21 cycles for address match and single-step interrupts.
Figure 12.7
12.1.6.6
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in
the IPL.
Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5
IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source
Watchdog timer, oscillation stop detection, voltage monitor 1,
voltage monitor 2, Address break
Software, address match, single-step
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Value Set in IPL
7
Not changed
R8C/2A Group, R8C/2B Group
12.1.6.7
12. Interrupts
Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-order bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Stack
Address
Stack
Address
MSB
LSB
MSB
LSB
m−4
m−4
PCL
m−3
m−3
PCM
m−2
m−2
FLGL
m−1
m−1
m
Previous stack contents
m+1
Previous stack contents
[SP]
SP value before
interrupt is generated
m
m+1
Stack state before interrupt request
is acknowledged
FLGH
[SP]
New SP value
PCH
Previous stack contents
Previous stack contents
PCH
PCM
PCL
FLGH
FLGL
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
Stack state after interrupt request
is acknowledged
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.8
Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Stack
Address
Sequence in which
order registers are
saved
[SP]−5
[SP]−4
PCL
(3)
[SP]−3
PCM
(4)
[SP]−2
FLGL
(1)
Saved, 8 bits at a time
[SP]−1
FLGH
PCH
(2)
[SP]
Completed saving
registers in four
operations.
PCH
PCM
PCL
FLGH
FLGL
NOTE:
1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
Figure 12.9
Register Saving Operation
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Page 133 of 580
: 4 high-order bits of PC
: 8 middle-order bits of PC
: 8 low-order bits of PC
: 4 high-order bits of FLG
: 8 low-order bits of FLG
R8C/2A Group, R8C/2B Group
12.1.6.8
12. Interrupts
Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the interrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 12.10 shows the Priority Levels of Hardware Interrupts.
The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the
instruction is executed.
Reset
High
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Peripheral function
Single step
Address match
Figure 12.10
Priority Levels of Hardware Interrupts
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Low
R8C/2A Group, R8C/2B Group
12. Interrupts
12.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11.
Priority level of interrupt
Level 0 (default value)
Highest
A/D conversion
Compare 0
INT3
Timer RB
Timer RA
Capture
INT0
Timer RF
INT1
Timer RC
UART1 receive
UART0 receive
Priority of peripheral function interrupts
(if priority levels are same)
Compare 1
UART2 receive
Timer RE
Timer RD0
INT2
UART1 transmit
UART0 transmit
SSU / I2C bus(1)
Key input
UART2 transmit
Timer RD1
IPL
Lowest
Interrupt request level
judgment output signal
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
NOTE:
1. The IICSEL bit in the PMR register switches functions.
Figure 12.11
Interrupt Priority Level Judgement Circuit
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Interrupt request
acknowledged
R8C/2A Group, R8C/2B Group
12.2
12. Interrupts
INT Interrupt
12.2.1
INTi Interrupt (i = 0 to 3)
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register. The INT1 input and the INT2 input can select the input pin.
Inputs can be passed through a digital filter with three different sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RC and timer RD, and the external trigger
input of timer RB.
Figure 12.12 shows the PMR Register, Figure 12.13 shows the INTEN Register, Figure 12.14 shows the INTF
Register, and Figure 12.15 shows the TRAIOC Register
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
PMR
Bit Symbol
INT1SEL
Address
00F8h
Bit Name
_____
INT1 pin select bit
After Reset
00h
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
RW
INT2 pin select bit
0 : Selects P6_6
1 : Selects P3_2
RW
Reserved bits
Set to 0.
UART1 enable bit
To use the UART1, set to 1.
Reserved bits
Set to 0.
SSU / I2C bus sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
_____
INT2SEL
—
(b3-b2)
U1PINSEL
—
(b6-b5)
IICSEL
Figure 12.12
PMR Register
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RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
12. Interrupts
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INTEN
Bit Symbol
INT0EN
Address
00F9h
Bit Name
_____
INT0 input enable bit
_____
INT0PL
INT0 input polarity select bit(1,2)
_____
INT1EN
INT1 input enable bit
_____
INT1PL
INT1 input polarity select bit(1,2)
_____
INT2EN
INT2 input enable bit
_____
INT2PL
INT2 input polarity select bit(1,2)
_____
INT3EN
INT3 input enable bit
_____
INT3PL
INT3 input polarity select bit(1,2)
After Reset
00h
Function
RW
0 : Disable
1 : Enable
RW
0 : One edge
1 : Both edges
RW
0 : Disable
1 : Enable
RW
0 : One edge
1 : Both edges
RW
0 : Disable
1 : Enable
RW
0 : One edge
1 : Both edges
RW
0 : Disable
1 : Enable
RW
0 : One edge
1 : Both edges
RW
NOTES:
1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4
Changing Interrupt Sources.
Figure 12.13
INTEN Register
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R8C/2A Group, R8C/2B Group
12. Interrupts
_____
INT Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INTF
Bit Symbol
Address
00FAh
Bit Name
_____
INT0F0
INT0 input filter select bits
INT0F1
_____
INT1F0
INT1 input filter select bits
INT1F1
_____
INT2F0
INT2 input filter select bits
INT2F1
_____
INT3F0
INT3 input filter select bits
INT3F1
Figure 12.14
After Reset
00h
Function
RW
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
b3 b2
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
b7 b6
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
RW
RW
INTF Register
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TRAIO output control bit
TIPF0
TIPF1
—
(b7-b6)
Figure 12.15
INT1/TRAIO select bit
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RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Page 138 of 580
RW
_____
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select bits Function varies depending on operating mode.
TRAIOC Register
RW
RW
TRAO output enable bit
_____
TIOSEL
After Reset
00h
Function
Function varies depending on operating mode.
RW
RW
—
R8C/2A Group, R8C/2B Group
12.2.2
12. Interrupts
INTi Input Filter (i = 0 to 3)
The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register.
The INTi level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR
bit in the INTiIC register is set to 1 (interrupt requested).
Figure 12.16 shows the Configuration of INTi Input Filter. Figure 12.17 shows an Operating Example of INTi
Input Filter.
INTiF1 to INTiF0
f1
f8
f32
INTi
Port direction
register(1)
= 01b
= 10b
Sampling clock
= 11b
INTiEN
Digital filter
(input level
matches 3x)
Other than
INTiF1 to INTiF0
= 00b
= 00b
INTi interrupt
INTiPL = 0
Both edges
detection
INTiPL = 1
circuit
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0 to 3
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin
Port P1_7 direction register when using the P1_7 pin
Port P3_6 direction register when using the P3_6 pin
INT2: Port P6_6 direction register when using the P6_6 pin
Port P3_2 direction register when using the P3_2 pin
INT3: Port P6_7 direction register
Figure 12.16
Configuration of INTi Input Filter
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 by a program
This is an operation example when bits INTiF1 to INTiF0 in the
INTiF register are set to 01b, 10b, or 11b (digital filter enabled).
i = 0 to 3
Figure 12.17
Operating Example of INTi Input Filter
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R8C/2A Group, R8C/2B Group
12.3
12. Interrupts
Key Input Interrupt
A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can
be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether or not the pins are used as KIi input. The KIiPL
bit in the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 12.18 shows a Block Diagram of Key Input Interrupt.
PU02 bit in PUR0 register
Pull-up
transistor
PD1_3 bit in PD1 register
KUPIC register
KI3EN bit
PD1_3 bit
KI3PL = 0
KI3
KI3PL = 1
Pull-up
transistor
KI2EN bit
PD1_2 bit
KI2PL = 0
Interrupt control
circuit
KI2
KI2PL = 1
Pull-up
transistor
Key input interrupt
request
KI1EN bit
PD1_1 bit
KI1PL = 0
KI1
KI1PL = 1
Pull-up
transistor
KI0EN bit
PD1_0 bit
KI0PL = 0
KI0
KI0PL = 1
Figure 12.18
Block Diagram of Key Input Interrupt
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KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register
R8C/2A Group, R8C/2B Group
12. Interrupts
Key Input Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIEN
Bit Symbol
KI0EN
KI0PL
KI1EN
KI1PL
KI2EN
KI2PL
KI3EN
KI3PL
Address
00FBh
Bit Name
KI0 input enable bit
After Reset
00h
Function
RW
KI0 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI1 input enable bit
0 : Disable
1 : Enable
RW
KI1 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI2 input enable bit
0 : Disable
1 : Enable
RW
KI2 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
KI3 input enable bit
0 : Disable
1 : Enable
RW
KI3 input polarity select bit
0 : Falling edge
1 : Rising edge
RW
NOTE:
1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten.
Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.19
KIEN Register
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RW
0 : Disable
1 : Enable
Page 141 of 580
R8C/2A Group, R8C/2B Group
12.4
12. Interrupts
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
• Change the content of the stack and use the REIT instruction.
• Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged.
Then use a jump instruction.
Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged.
Figure 12.20 shows Registers AIER and RMAD0 to RMAD1.
Table 12.6
Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2)
ADD.B:S
#IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest
STNZ
#IMM8,dest STZX
#IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest PUSHM src
POPM
dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (however, dest = A0 or A1)
• Instructions other than the above
PC Value Saved(1)
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
NOTES:
1. Refer to the 12.1.6.7 Saving a Register for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 12.7
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
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R8C/2A Group, R8C/2B Group
12. Interrupts
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Bit Symbol
AIER0
AIER1
—
(b7-b2)
Address
0013h
Bit Name
Address match interrupt 0 enable bit 0 : Disable
1 : Enable
After Reset
00h
Function
RW
RW
Address match interrupt 1 enable bit 0 : Disable
1 : Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Address Match Interrupt Register i(i = 0 or 1)
(b23)
b7
(b19)
b3
(b16) (b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
0012h-0010h
0016h-0014h
Function
Address setting register for address match interrupt
—
Nothing is assigned. If necessary, set to 0.
(b7-b4)
When read, the content is 0.
Figure 12.20
Registers AIER and RMAD0 to RMAD1
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After Reset
000000h
000000h
Setting Range
RW
00000h to FFFFFh
RW
—
R8C/2A Group, R8C/2B Group
12.5
12. Interrupts
Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with
Chip Select Interrupts, and I 2 C bus Interface Interrupt (Interrupts with
Multiple Interrupt Request Sources)
The timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial
I/O with chip select interrupt, and I2C bus interface interrupt each have multiple interrupt request sources. An
interrupt request is generated by the logical OR of several interrupt request factors and is reflected in the IR bit in
the corresponding interrupt control register. Therefore, each of these peripheral functions has its own interrupt
request source status register (status register) and interrupt request source enable register (enable register) to
control the generation of interrupt requests (change the IR bit in the interrupt control register). Table 12.8 lists the
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select
Interrupt, and I2C bus Interface Interrupt and Figure 12.21 shows a Block Diagram of Timer RD Interrupt.
Table 12.8
Registers Associated with Timer RC Interrupt, Timer RD Interrupt, Clock
Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt
Peripheral Function
Name
Timer RC
Timer RD Channel 0
Channel 1
Clock synchronous serial
I/O with chip select
Status Register of
Interrupt Request Source
TRCSR
TRDSR0
TRDSR1
SSSR
Enable Register of
Interrupt Request Source
TRCIER
TRDIER0
TRDIER1
SSER
Interrupt Control
Register
TRCIC
TRD0IC
TRD1IC
SSUIC
I2C bus interface
ICSR
ICIER
IICIC
Channel i
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 12.21
Block Diagram of Timer RD Interrupt
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Page 144 of 580
Timer RD (channel i)
interrupt request
(IR bit in TRDiIC register)
R8C/2A Group, R8C/2B Group
12. Interrupts
As with other maskable interrupts, the timer RC interrupt, timer RD (channel 0) interrupt, timer RD (channel 1)
interrupt, clock synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt are controlled by
the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is
generated by a combination of multiple interrupt request sources, the following differences from other maskable
interrupts apply:
• When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable
interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested).
• When either bits in the status register or bits in the enable register corresponding to bits in the status register, or
both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not
acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set
to 0 even if 0 is written to the IR bit.
• Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the
status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the
status register to 0.
• When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is
set to 1, the IR bit remains 1.
• When multiple bits in the enable register are set to 1, determine by the status register which request source
causes an interrupt.
Refer to chapters of the individual peripheral functions (14.3 Timer RC, 14.4 Timer RD, 16.2 Clock
Synchronous Serial I/O with Chip Select (SSU) and 16.3 I2C bus Interface) for the status register and enable
register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
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R8C/2A Group, R8C/2B Group
12.6
12. Interrupts
Notes on Interrupts
12.6.1
Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
12.6.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
12.6.3
External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 21.22 (VCC = 5V), Table 21.29 (VCC = 3V), Table 21.36 (VCC = 2.2V) External
Interrupt INTi (i = 0, 2, 3) Input and Table 21.19 (VCC = 5V), Table 21.26 (VCC = 3V), Table 21.33 (VCC
= 2.2V) TRAIO Input, INT1 Input.
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R8C/2A Group, R8C/2B Group
12.6.4
12. Interrupts
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 12.22 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 12.22
Example of Procedure for Changing Interrupt Sources
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Page 147 of 580
R8C/2A Group, R8C/2B Group
12.6.5
12. Interrupts
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1:
Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
POPC
FLG
; Enable interrupts
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R8C/2A Group, R8C/2B Group
13. Watchdog Timer
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists information on the Watchdog Timer Specifications.
Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows the Registers WDTR, WDTS, and
WDC. Figure 13.3 shows the Registers CSPR and OFS.
Table 13.1
Watchdog Timer Specifications
Item
Count source
Count Source Protection
Mode Disabled
CPU clock
Count operation
Count start condition
Count Source Protection
Mode Enabled
Low-speed on-chip oscillator
clock
Decrement
Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Count stop condition
Stop mode, wait mode
None
Reset condition of watchdog
• Reset
• Write 00h to the WDTR register before writing FFh
timer
• Underflow
Operation at the time of underflow Watchdog timer interrupt or
Watchdog timer reset
watchdog timer reset
Select functions
• Division ratio of prescaler
Selected by the WDC7 bit in the WDC register
• Count source protection mode
Whether count source protection mode is enabled or disabled after a
reset can be selected by the CSPROINI bit in the OFS register (flash
memory). If count source protection mode is disabled after a reset, it
can be enabled or disabled by the CSPRO bit in the CSPR register
(program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
13. Watchdog Timer
Prescaler
1/16
1/128
CPU clock
1/2
CM07 = 0,
WDC7 = 0
CSPRO = 0
CM07 = 0,
WDC7 = 1
PM12 = 0
Watchdog timer
interrupt request
Watchdog timer
CM07 = 1
fOCO-S
CSPRO = 1
Write to WDTR register
Set to
7FFFh(1)
PM12 = 1
Watchdog
timer reset
Internal reset signal
(“L” active)
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
CM07: Bit in CM0 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
Figure 13.1
Block Diagram of Watchdog Timer
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
13. Watchdog Timer
Watchdog Timer Reset Register
b7
b0
Symbol
WDTR
Address
000Dh
After Reset
Undefined
Function
When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1)
The default value of the w atchdog timer is 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)
RW
WO
NOTES:
1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten.
2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled),
0FFFh is set in the w atchdog timer.
Watchdog Timer Start Register
b7
b0
Symbol
WDTS
Address
000Eh
After Reset
Undefined
Function
The w atchdog timer starts counting after a w rite instruction to this register.
RW
WO
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
Address
000Fh
WDC
Bit Symbol
Bit Name
—
High-order bits of w atchdog timer
(b4-b0)
—
(b5)
Reserved bit
Set to 0. When read, the content is undefined.
—
(b6)
Reserved bit
Set to 0.
Prescaler select bit
0 : Divide-by-16
1 : Divide-by-128
WDC7
Figure 13.2
Registers WDTR, WDTS, and WDC
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REJ09B0324-0200
After Reset
00X11111b
Function
Page 151 of 580
RW
RO
RW
RW
RW
R8C/2A Group, R8C/2B Group
13. Watchdog Timer
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0 0 0
Symbol
Address
001Ch
CSPR
Bit Symbol
Bit Name
Reserved bits
—
(b6-b0)
CSPRO
After Reset(1)
00h
Function
Set to 0.
Count source protection mode 0 : Count source protection mode disabled
select bit(2)
1 : Count source protection mode enabled
RW
RW
RW
NOTES:
1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b.
2. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
—
(b6)
CSPROINI
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
Reserved bit
Set to 1.
Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 13.3
Registers CSPR and OFS
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R8C/2A Group, R8C/2B Group
13.1
13. Watchdog Timer
Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
Table 13.2
Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item
Specification
Count source
Count operation
Period
CPU clock
Decrement
Reset condition of watchdog
timer
Count start condition
Count stop condition
Operation at time of underflow
Division ratio of prescaler (n) × count value of watchdog timer (32768)(1)
CPU clock
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divided by 16, the period is approximately 32.8 ms
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
The WDTON bit(2) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
• The watchdog timer and prescaler start counting automatically after a
reset
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.6 Watchdog Timer Reset)
NOTES:
1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is
reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the
prescaler.
2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
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R8C/2A Group, R8C/2B Group
13.2
13. Watchdog Timer
Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
Table 13.3
Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item
Count source
Count operation
Period
Reset condition of watchdog
timer
Count start condition
Count stop condition
Operation at time of underflow
Registers, bits
Specification
Low-speed on-chip oscillator clock
Decrement
Count value of watchdog timer (4096)
Low-speed on-chip oscillator clock
Example: Period is approximately 32.8 ms when the low-speed onchip oscillator clock frequency is 125 kHz
• Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
None (The count does not stop in wait mode after the count starts.
The MCU does not enter stop mode.)
Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.)
• When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)(2), the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low-speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions apply in count source protection mode
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
NOTES:
1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI
bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with
a flash programmer.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
14. Timers
The MCU has two 8-bit timers with 8-bit prescalers, three 16-bit timers, and a timer with a 4-bit counter and an 8-bit
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The three 16-bit timers is timer RC, timer RD, and timer RF, and have input
capture and output compare functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function.
All the timers operate independently.
Tables 14.1 and 14.2 list Functional Comparison of Timers.
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R8C/2A Group, R8C/2B Group
Table 14.1
14. Timers
Functional Comparison of Timers (1)
Item
Configuration
Timer RA
8-bit timer
with 8-bit
prescaler
(with reload
register)
Decrement
Timer RB
Timer RC
8-bit timer with 16-bit timer (with
8-bit prescaler input capture and
(with reload
output compare)
register)
Timer RD
16-bit timer × 2
(with input capture
and output
compare)
Timer RE
4-bit counter
8-bit counter
Decrement
Increment
Increment
Count sources
•
•
•
•
•
•
•
•
•
Function Count of the
internal count
source
Count of the
external count
source
External pulse
width/period
measurement
Timer mode
• f1
• f2
• f4
• f8
• f32
• fOCO40M
• TRCCLK
Timer mode
(output compare
function)
Timer mode
(output compare
function)
Timer mode (input
capture function; 4
pins)
Increment/
Decrement
• f1
• f2
• f4
• f8
• f32
• fOCO40M
• TRDIOA0
Timer mode
(output compare
function)
Timer mode
(output compare
function)
Timer mode (input
compare function;
2 channels × 4
pins)
Count
PWM output
f1
f2
f8
fOCO
fC32
f1
f2
f8
Timer RA
underflow
Timer mode
Event counter —
mode
Pulse width
measurement
mode, pulse
period
measurement
mode
Pulse output
mode(1),
Event counter
mode(1)
One-shot
waveform
output
—
Three-phase
waveforms
output
—
Timer
Timer mode
(only fC32
count)
—
Programmable
waveform
generation
mode
Timer mode
(output compare
function; 2 channels
× 4 pins)(1),
PWM mode
(2 channels × 3 pins),
PWM3 mode
(2 channels × 2 pins)
Programmable PWM mode (3 pins) PWM mode
(2 channels × 3 pins)
one-shot
generation
mode,
Programmable
wait one-shot
generation
mode
—
—
Reset
synchronous PWM
mode (2 channels
× 3 pins, Sawtooth
wave modulation),
Complementary
PWM mode
(2 channels × 3 pins,
triangular wave
modulation, dead
time)
—
—
—
Timer mode
(output compare
function; 4 pins)(1),
PWM mode (3 pins),
PWM2 mode (1 pin)
•
•
•
•
f4
f8
f32
fC4
—
—
Timer RF
16-bit timer
(with input
capture and
output
compare)
Increment
• f1
• f8
• f32
Output
compare
mode
—
—
Input capture
mode
Output
compare
mode(1)
Output
compare
mode
—
—
—
—
Real-time
clock mode
—
NOTE:
1. Rectangular waves are output in these modes. Since the waves are inverted at each overflow, the “H” and “L” level widths of
the pulses are the same.
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R8C/2A Group, R8C/2B Group
Table 14.2
14. Timers
Functional Comparison of Timers (2)
Item
Input pin
Timer RA
TRAIO
Timer RB
Timer RC
INT0
INT0, TRCCLK,
TRCTRG,
TRCIOA,
TRCIOB,
TRCIOC,
TRCIOD
Output pin
TRAO
TRAIO
TRBO
TRCIOA,
TRCIOB,
TRCIOC,
TRCIOD
Related interrupt
Timer RA
interrupt,
INT1 interrupt
Timer RB
interrupt,
INT0 interrupt
Compare match/
input capture A
to D interrupt,
Overflow
interrupt,
INT0 interrupt
Timer stop
Provided
Provided
Provided
NOTE:
1. The underflow interrupt can be set to channel 1.
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REJ09B0324-0200
Page 157 of 580
Timer RD
INT0, TRDCLK,
TRDIOA0,
TRDIOA1,
TRDIOB0,
TRDIOB1,
TRDIOC0,
TRDIOC1,
TRDIOD0,
TRDIOD1
TRDIOA0,
TRDIOA1,
TRDIOB0,
TRDIOB1,
TRDIOC0,
TRDIOC1,
TRDIOD0,
TRDIOD1
Compare match/
input capture A0 to
D0 interrupt,
Compare match/
input capture A1 to
D1 interrupt,
Overflow interrupt,
Underflow
interrupt(1),
INT0 interrupt
Provided
Timer RE
—
Timer RF
TRFI
TREO
TRFO00 to
TRFO02,
TRFO10 to
TRFO12
Timer RE
interrupt
Timer RF
interrupt,
Compare 0
interrupt,
Compare 1
interrupt,
Provided
Provided
R8C/2A Group, R8C/2B Group
14.1
14. Timers
Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.3 to 14.7
the Specifications of Each Mode).
The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with Timer
RA.
Timer RA has the following five operating modes:
• Timer mode:
The timer counts the internal count source.
• Pulse output mode:
The timer counts the internal count source and outputs pulses of which
polarity inverted by underflow of the timer.
• Event counter mode:
The timer counts external pulses.
• Pulse width measurement mode:
The timer measures the pulse width of an external pulse.
• Pulse period measurement mode:
The timer measures the pulse period of an external pulse.
Data bus
TCK2 to TCK0 bit
f1
f8
fOCO
f2
fC32
= 000b
= 001b
= 010b
= 011b
= 100b
TCKCUT bit
TMOD2 to TMOD0
= other than 010b
TIPF1 to TIPF0 bits
TMOD2 to TMOD0
= 010b
= 01b
f1
= 10b
f8
= 11b
f32
TIPF1 to TIPF0 bits
TIOSEL = 0 = other than
Digital
000b
INT1/TRAIO (P1_7) pin
filter
INT1/TRAIO (P1_5) pin
TIOSEL = 1
Reload
register
Reload
register
TCSTF bit
Counter
Counter
TRA register
(timer)
TRAPRE register
(prescaler)
Underflow signal
Timer RA interrupt
TMOD2 to TMOD0
= 011b or 100b
Polarity
switching
Count control
circle
= 00b
TMOD2 to TMOD0 = 001b
TEDGSEL = 1
TOPCR bit
Q
TOENA bit
Q
TEDGSEL = 0
Measurement completion
signal
Toggle flip-flop CK
CLR
Write to TRAMR register
Write 1 to TSTOP bit
TRAO pin
TCSTF, TSTOP: Bits in TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
Figure 14.1
Block Diagram of Timer RA
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REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RA Control Register(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRACR
Bit Symbol
TSTART
TCSTF
TSTOP
—
(b3)
TEDGF
TUNDF
—
(b7-b6)
Address
0100h
Bit Name
Timer RA count start bit(1)
After Reset
00h
Function
RW
0 : Count stops
1 : Count starts
RW
Timer RA count status flag(1)
0 : Count stops
1 : During count
RO
Timer RA count forcible stop
bit(2)
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Active edge judgment
flag(3, 5)
0 : Active edge not received
1 : Active edge received
(end of measurement period)
RW
Timer RA underflow flag(3, 5)
0 : No underflow
1 : Underflow
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Refer to 14.1.6 Notes on Tim er RA.
2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after
a reset.
3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains
unchanged w hen 1 is w ritten.
4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them.
5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
Function varies depending on operating mode.
TRAIO output control bit
TRAO output enable bit
RW
RW
RW
RW
_____
TIOSEL
TIPF0
TIPF1
—
(b7-b6)
Figure 14.2
INT1/TRAIO select bit
TRAIO input filter select bits
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Registers TRACR and TRAIOC
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 159 of 580
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RA Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRAMR
Bit Symbol
TMOD0
Address
0102h
Bit Name
Timer RA operating mode
select bits
TMOD1
TMOD2
After Reset
00h
Function
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse w idth measurement mode
1 0 0 : Pulse period measurement mode
101:
1 1 0 : Do not set.
111:
—
(b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TCK0
Timer RA count source
select bits
TCK1
TCK2
TCKCUT
Timer RA count source
cutoff bit
RW
b2 b1 b0
RW
RW
RW
—
b6 b5 b4
0 0 0 : f1
0 0 1 : f8
0 1 0 : fOCO
0 1 1 : f2
1 0 0 : fC32
101:
1 1 0 : Do not set.
111:
RW
RW
RW
0 : Provides count source
1 : Cuts off count source
RW
NOTE:
1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
Timer RA Prescaler Register
b7
b0
Symbol
TRAPRE
Mode
Timer mode
Pulse output mode
Event counter mode
Pulse w idth
measurement mode
Counts
Counts
Counts
Counts
Address
0103h
Function
an internal count source
an internal count source
an external count source
internal count source
Pulse period
measurement mode
After Reset
FFh(1)
Setting Range
00h to FFh
00h to FFh
00h to FFh
RW
RW
RW
RW
00h to FFh
RW
00h to FFh
RW
After Reset
FFh(1)
Setting Range
RW
00h to FFh
RW
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Timer RA Register
b7
b0
Symbol
TRA
Mode
All modes
Address
0104h
Function
Counts on underflow of timer RA prescaler
register
NOTE:
1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
Figure 14.3
Registers TRAMR, TRAPRE, and TRA
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R8C/2A Group, R8C/2B Group
14.1.1
14. Timers
Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 14.3 Timer Mode
Specifications).
Figure 14.4 shows TRAIOC Register in Timer Mode.
Table 14.3
Timer Mode Specifications
Item
Count sources
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
INT1/TRAIO pin
function
TRAO pin function
Read from timer
Write to timer
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
When timer RA underflows [timer RA interrupt].
Programmable I/O port, or INT1 interrupt input
Programmable I/O port
The count value can be read by reading registers TRA and TRAPRE.
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TRAIO output control bit
TIPF0
TIPF1
—
(b7-b6)
Figure 14.4
INT1/TRAIO select bit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Page 161 of 580
RW
_____
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select bits Set to 0 in timer mode.
TRAIOC Register in Timer Mode
RW
RW
TRAO output enable bit
_____
TIOSEL
After Reset
00h
Function
Set to 0 in timer mode.
RW
RW
—
R8C/2A Group, R8C/2B Group
14.1.1.1
14. Timers
Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
Count source
After writing, the reload register is
written to at the first count source.
Reloads register of
timer RA prescaler
Previous value
New value (01h)
Reload at
second count
source
Counter of
timer RA prescaler
06h
05h
04h
01h
00h
Reload at
underflow
01h
00h
01h
00h
01h
00h
After writing, the reload register is
written to at the first underflow.
Reloads register of
timer RA
Previous value
New value (25h)
Reload at the second underflow
Counter of timer RA
IR bit in TRAIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow is
generated by a new value.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
Figure 14.5
Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
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R8C/2A Group, R8C/2B Group
14.1.2
14. Timers
Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 14.4 Pulse Output Mode
Specifications).
Figure 14.6 shows TRAIOC Register in Pulse Output Mode.
Table 14.4
Pulse Output Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
When timer RA underflows [timer RA interrupt].
generation timing
Pulse output, programmable output port, or INT1 interrupt(1)
INT1/TRAIO pin
function
Programmable I/O port or inverted output of TRAIO(1)
TRAO pin function
The count value can be read by reading registers TRA and TRAPRE.
Read from timer
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control
during Count Operation).
Select functions
• TRAIO output polarity switch function
The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse
output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO pin
(selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register.
• INT1/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
RW
TRAIO output control bit
0 : TRAIO output
1 : Port P1_7 or P1_5
RW
TRAO output enable bit
0 : Port P3_0
1 : TRAO output (inverted TRAIO output from P3_0)
RW
_____
TIOSEL
TIPF0
TIPF1
—
(b7-b6)
Figure 14.6
INT1/TRAIO select bit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
_____
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select bits Set to 0 in pulse output mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Output Mode
Page 164 of 580
RW
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14.1.3
14. Timers
Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.5 Event
Counter Mode Specifications).
Figure 14.7 shows TRAIOC Register in Event Counter Mode.
Table 14.5
Event Counter Mode Specifications
Item
Count source
Count operations
Specification
External signal which is input to TRAIO pin (active edge selectable by a program)
• Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio
1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
• When timer RA underflows [timer RA interrupt].
generation timing
Count source input (INT1 interrupt input)
INT1/TRAIO pin
function
Programmable I/O port or pulse output(1)
TRAO pin function
Read from timer
The count value can be read by reading registers TRA and TRAPRE.
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write Control
during Count Operation).
Select functions
• NT1 input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register)(1).
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter
and select the sampling frequency.
NOTE:
1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR
register is written to.
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TEDGSEL
TOPCR
TOENA
TIPF0
TRAO output enable bit
0 : Port P3_0
1 : TRAO output
RW
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
RW
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Event Counter Mode
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RW
_____
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.7
RW
Set to 0 in event counter mode.
TIPF1
—
(b7-b6)
RW
TRAIO output control bit
_____
TIOSEL
After Reset
00h
Function
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
1 : Starts counting at falling edge of the TRAIO
input or TRAIO starts output at “H”
RW
—
R8C/2A Group, R8C/2B Group
14.1.4
14. Timers
Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.6 Pulse Width Measurement Mode Specifications).
Figure 14.8 shows TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an Operating
Example of Pulse Width Measurement Mode.
Table 14.6
Pulse Width Measurement Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• Continuously counts the selected signal only when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Count start condition
1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions
• 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
• When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
generation timing
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
The count value can be read by reading registers TRA and TRAPRE.
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions
• Measurement level select
• The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
TEDGSEL
TOPCR
TOENA
Address
0101h
Bit Name
TRAIO polarity sw itch bit
After Reset
00h
Function
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
TRAIO output control bit
Set to 0 in pulse w idth measurement mode.
TRAO output enable bit
_____
TIOSEL
TIPF0
—
(b7-b6)
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Width Measurement Mode
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RW
RW
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.8
RW
_____
INT1/TRAIO select bit
TIPF1
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
FFFFh
Count start
Underflow
Content of counter (hex)
n
Count stop
Count stop
Count start
Count start
0000h
Period
Set to 1 by program
TSTART bit in
TRACR register
1
Measured pulse
(TRAIO pin input)
1
0
0
Set to 0 when interrupt request is acknowledged, or set by program
IR bit in TRAIC
register
1
0
Set to 0 by program
TEDGF bit in
TRACR register
1
0
Set to 0 by program
TUNDF bit in
TRACR register
1
0
The above applies under the following conditions.
• “H” level width of measured pulse is measured. (TEDGSEL = 1)
• TRAPRE = FFh
Figure 14.9
Operating Example of Pulse Width Measurement Mode
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R8C/2A Group, R8C/2B Group
14.1.5
14. Timers
Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.7 Pulse Period Measurement Mode Specifications).
Figure 14.10 the shows TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an
Operating Example of Pulse Period Measurement Mode.
Table 14.7
Pulse Period Measurement Mode Specifications
Item
Count sources
Count operations
Count start condition
Count stop conditions
Interrupt request
generation timing
Specification
f1, f2, f8, fOCO, fC32
• Decrement
• After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
1 (count starts) is written to the TSTART bit in the TRACR register.
• 0 (count stops) is written to TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
• When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
Programmable I/O port
TRAO pin function
Read from timer
The count value can be read by reading registers TRA and TRAPRE.
Write to timer
• When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions
• Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measurement period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
NOTE:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “L” width than the timer RA prescaler period. If a pulse with a shorter period is input to
the TRAIO pin, the input may be ignored.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRAIOC
Bit Symbol
Address
0101h
Bit Name
TRAIO polarity sw itch bit
TEDGSEL
TOPCR
TOENA
TRAIO output control bit
TIPF0
0 : INT1/TRAIO pin (P1_7)
_____
1 : INT1/TRAIO pin (P1_5)
TRAIO input filter select
bits (1)
b5 b4
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRAIOC Register in Pulse Period Measurement Mode
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Page 171 of 580
RW
RW
RW
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.10
RW
_____
INT1/TRAIO select bit
TIPF1
—
(b7-b6)
Set to 0 in pulse period measurement mode.
TRAO output enable bit
_____
TIOSEL
After Reset
00h
Function
0 : Measures measurement pulse from one
rising edge to next rising edge
1 : Measures measurement pulse from one
falling edge to next falling edge
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Underflow signal of
timer RA prescaler
Set to 1 by program
TSTART bit in
TRACR register
1
0
Starts counting
Measurement pulse
(TRAIO pin input)
1
0
TRA reloads
Contents of TRA
TRA reloads
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
01h 00h 0Fh 0Eh
Underflow
Retained
Contents of read-out
buffer(1)
0Fh
Retained
0Dh
0Eh
0Bh 0Ah
09h
0Dh
01h 00h 0Fh 0Eh
TRA read(3)
TEDGF bit in
TRACR register
1
(Note 2)
(Note 2)
0
Set to 0 by program
TUNDF bit in
TRACR register
(Note 4)
(Note 6)
1
0
Set to 0 by program
IR bit in TRAIC
register
(Note 5)
1
0
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
NOTES:
1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the second time.
3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 14.11
Operating Example of Pulse Period Measurement Mode
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R8C/2A Group, R8C/2B Group
14.1.6
14. Timers
Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.2
14. Timers
Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.8 to 14.11 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 and 14.15 show the registers associated with
timer RB.
Timer RB has four operation modes listed as follows:
• Timer mode:
• Programmable waveform generation mode:
• Programmable one-shot generation mode:
• Programmable wait one-shot generation mode:
The timer counts an internal count source (peripheral
function clock or timer RA underflows).
The timer outputs pulses of a given width successively.
The timer outputs a one-shot pulse.
The timer outputs a delayed one-shot pulse.
Data bus
TCK1 to TCK0 bits
f1
f8
Timer RA underflow
f2
= 00b
Reload
register
TRBSC
register
Reload
register
TRBPR
register
Reload
register
TCKCUT bit
= 01b
Counter
= 10b
= 11b
TRBPRE register
(prescaler)
Counter (timer RB)
(Timer)
Timer RB interrupt
TMOD1 to TMOD0 bits
= 10b or 11b
TCSTF bit
TOSSTF bit
Digital filter
INT0 pin
Input polarity
selected to be one
edge or both edges
INT0PL bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
INT0EN bit
Polarity
select
INOSEG bit
TRBO pin
P3_1 bit in P3 register
TCSTF: Bit in TRBCR register
TOSSTF: Bit in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
Figure 14.12
Block Diagram of Timer RB
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 174 of 580
INOSTG bit
TOPL = 1
TOCNT = 0
TOCNT = 1
INT0 interrupt
TOPL = 0
Q
Toggle flip-flop CK
Q
CLR
TCSTF bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
R8C/2A Group, R8C/2B Group
14. Timers
Timer RB Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBCR
Bit Symbol
TSTART
Address
0108h
Bit Name
Timer RB count start bit(1)
After Reset
00h
Function
0 : Count stops
1 : Count starts
RW
RW
TCSTF
Timer RB count status flag(1) 0 : Count stops
1 : During count(3)
RO
TSTOP
Timer RB count forcible stop When this bit is set to 1, the count is forcibly
bit(1, 2)
stopped. When read, its content is 0.
RW
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Refer to 14.2.5 Notes on Tim er RB.
2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable oneshot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has
been acknow ledged.
Timer RB One-Shot Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBOCR
Bit Symbol
TOSST
Address
0109h
Bit Name
Timer RB one-shot start bit
After Reset
00h
Function
When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
Timer RB one-shot stop bit
When this bit is set to 1, counting of one-shot
pulses (including programmable w ait one-shot
pulses) stops. When read, its content is 0.
RW
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
RO
TOSSP
TOSSTF
Timer RB one-shot status
flag(1)
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
NOTES:
1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0.
2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable w ait one-shot generation mode).
Figure 14.13
Registers TRBCR and TRBOCR
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—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Address
After Reset
010Ah
00h
Bit Name
Function
Timer RB output level select Function varies depending on operating mode.
bit
Timer RB output sw itch bit
RW
RW
RW
One-shot trigger control bit
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Timer RB Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRBMR
Bit Symbol
TMOD0
Address
010Bh
Bit Name
Timer RB operating mode
select bits (1)
TMOD1
—
(b2)
TWRC
TCK0
TCKCUT
RW
b1 b0
0 0 : Timer mode
0 1 : Programmable w aveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable w ait one-shot generation mode
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB w rite control bit(2)
0 : Write to reload register and counter
1 : Write to reload register only
Timer RB count source
select bits (1)
b5 b4
TCK1
—
(b6)
After Reset
00h
Function
0 0 : f1
0 1 : f8
1 0 : Timer RA underflow
1 1 : f2
RW
RW
—
RW
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Timer RB count source
cutoff bit(1)
RW
0 : Provides count source
1 : Cuts off count source
NOTES:
1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR
register set to 0 (count stops).
2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable
one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
Figure 14.14
Registers TRBIOC and TRBMR
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14. Timers
Timer RB Prescaler Register(1)
b7
b0
Symbol
TRBPRE
Mode
Address
010Ch
Function
Counts an internal count source or timer RA
underflow s
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
Counts an internal count source or timer RA
underflow s
00h to FFh
Programmable one-shot
generation mode
Counts an internal count source or timer RA
underflow s
00h to FFh
Programmable w ait one-shot Counts an internal count source or timer RA
generation mode
underflow s
00h to FFh
Timer mode
RW
RW
RW
RW
RW
NOTE:
1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Timer RB Secondary Register(3, 4)
b7
b0
Symbol
TRBSC
Mode
Timer mode
Address
010Dh
Function
Disabled
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
Counts timer RB prescaler underflow s (1)
00h to FFh
Programmable one-shot
generation mode
Disabled
00h to FFh
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode
(one-shot w idth is counted)
00h to FFh
RW
—
WO(2)
—
WO(2)
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted.
3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
4. To w rite to the TRBSC register, perform the follow ing steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
Timer RB Primary Register(2)
b7
b0
Symbol
TRBPR
Mode
Timer mode
Address
010Eh
Function
Counts timer RB prescaler underflow s
After Reset
FFh
Setting Range
00h to FFh
Programmable w aveform
generation mode
Counts timer RB prescaler underflow s (1)
00h to FFh
Programmable one-shot
generation mode
Counts timer RB prescaler underflow s
(one-shot w idth is counted)
00h to FFh
Programmable w ait one-shot Counts timer RB prescaler underflow s
generation mode
(w ait period w idth is counted)
00h to FFh
NOTES:
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Figure 14.15
Registers TRBPRE, TRBSC, and TRBPR
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RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
14.2.1
14. Timers
Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
14.8 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 14.16 shows TRBIOC Register in Timer Mode.
Table 14.8
Timer Mode Specifications
Item
Count sources
Count operations
Divide ratio
Count start condition
Count stop conditions
Interrupt request
generation timing
TRBO pin function
INT0 pin function
Read from timer
Write to timer
Specification
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB underflows, the contents of timer RB primary
reload register is reloaded).
1/(n+1)(m+1)
n: setting value in TRBPRE register, m: setting value in TRBPR register
1 (count starts) is written to the TSTART bit in the TRBCR register.
• 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
When timer RB underflows [timer RB interrupt].
Programmable I/O port
Programmable I/O port or INT0 interrupt input
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 14.2.1.1 Timer Write Control during Count Operation.)
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Figure 14.16
Address
After Reset
010Ah
00h
Bit Name
Function
Timer RB output level select Set to 0 in timer mode.
bit
Timer RB output sw itch bit
One-shot trigger control bit
RW
RW
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
TRBIOC Register in Timer Mode
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14.2.1.1
14. Timers
Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload register.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten during Count Operation.
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14. Timers
When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
Counter of
timer RB prescaler
06h
05h
New value (01h)
04h
Reload with
the second
count source
Reload on
underflow
01h
01h
00h
00h
01h
00h
01h
00h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on the second
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
25h
24h
0
The IR bit remains unchanged until underflow
is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to
the TRBPR register by a program.
Count source
After writing, the reload register is
written with the first count source.
Reloads register of
timer RB prescaler
Previous value
New value (01h)
Reload on
underflow
Counter of
timer RB prescaler
06h
05h
04h
03h
02h
01h
00h
01h
00h
01h
00h
01h
00h
01h
After writing, the reload register is
written on the first underflow.
Reloads register of
timer RB
Previous value
New value (25h)
Reload on
underflow
Counter of timer RB
IR bit in TRBIC
register
03h
02h
01h
00h
25h
0
Only the prescaler values are updated,
extending the duration until timer RB underflow.
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 14.17
Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
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14.2.2
14. Timers
Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table
14.9 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting
value in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 14.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an
Operating Example of Timer RB in Programmable Waveform Generation Mode.
Table 14.9
Programmable Waveform Generation Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement
• When the timer underflows, it reloads the contents of the primary reload and
secondary reload registers alternately before the count continues.
Width and period of
Primary period: (n+1)(m+1)/fi
output waveform
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register.
Interrupt request
In half a cycle of the count source, after timer RB underflows during the
generation timing
secondary period (at the same time as the TRBO output change) [timer RB
interrupt]
TRBO pin function
Programmable output port or pulse output
INT0 pin function
Programmable I/O port or INT0 interrupt input
Read from timer
The count value can be read out by reading registers TRBPR and TRBPRE(1).
Write to timer
• When registers TRBPRE, TRBSC, and TRBPR are written while the count is
stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(2)
Select functions
• Output level select function
The TOPL bit in the TRBIOC register selects the output level during primary and
secondary periods.
• TRBO pin output switch function
Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the
TRBIOC register.(3)
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in the waveform output beginning with the following primary period after
writing to the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
• When count starts.
• When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following
primary period.
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14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
INOSTG
Figure 14.18
Address
010Ah
Bit Name
Timer RB output level select 0 : Outputs
bit
Outputs
Outputs
1 : Outputs
Outputs
Outputs
After Reset
00h
Function
“H” for primary period
“L” for secondary period
“L” w hen the timer is stopped
“L” for primary period
“H” for secondary period
“H” w hen the timer is stopped
RW
RW
Timer RB output sw itch bit
0 : Outputs timer RB w aveform
1 : Outputs value in P3_1 port latch
RW
One-shot trigger control bit
Set to 0 in programmable w aveform generation
mode.
RW
INOSEG
One-shot trigger polarity
select bit
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
TRBIOC Register in Programmable Waveform Generation Mode
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Count source
Timer RB prescaler
underflow signal
Timer RB secondary reloads
01h
Counter of timer RB
IR bit in TRBIC
register
00h
02h
01h
Timer RB primary reloads
00h
01h
00h
02h
Set to 0 when interrupt
request is acknowledged,
or set by program.
1
0
Set to 0 by program
TOPL bit in TRBIO
register
1
0
Waveform
output starts
TRBO pin output
Waveform output inverted
Waveform output starts
1
0
Initial output is the same level
as during secondary period.
Primary period
Secondary period
Primary period
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 14.19
Operating Example of Timer RB in Programmable Waveform Generation Mode
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14.2.3
14. Timers
Programmable One-shot Generation Mode
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an
external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable One-Shot Generation
Mode Specifications). When a trigger is generated, the timer starts operating from the point only once for a
given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode.
Figure 14.20 shows TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows an
Operating Example of Programmable One-Shot Generation Mode.
Table 14.10
Programmable One-Shot Generation Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
(n+1)(m+1)/fi
output time
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count stops).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly stops).
Interrupt request
In half a cycle of the count source, after the timer underflows (at the same time as
generation timing
the TRBO output ends) [timer RB interrupt]
TRBP pin function
Pulse output
INT0 pin functions
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer
The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer
• When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload)(1).
Select functions
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
Address
010Ah
Bit Name
Timer RB Output Level
Select Bit
Timer RB Output Sw itch Bit
0 : Outputs
Outputs
1 : Outputs
Outputs
After Reset
00h
Function
one-shot pulse “H”
“L” w hen the timer is stopped
one-shot pulse “L”
“H” w hen the timer is stopped
Set to 0 in programmable one-shot generation
mode.
INOSTG
One-Shot Trigger Control
Bit(1)
INOSEG
One-Shot Trigger Polarity
Select Bit(1)
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, its content is 0.
0 : INT0 pin one-shot trigger disabled
_____
1 : INT0 pin one-shot trigger enabled
0 : Falling edge trigger
1 : Rising edge trigger
TRBIOC Register in Programmable One-Shot Generation Mode
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RW
_____
NOTE:
1. Refer to 14.2.3.1 One -Shot Trigge r Se lection.
Figure 14.20
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR
register
TOSSTF bit in TRBOCR
register
1
0
1
Set to 0 when
counting ends
Set to 1 by setting 1 to
TOSST bit in TRBOCR
register
Set to 1 by INT0 pin
input trigger
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
Counter of timer RB
01h
Timer RB primary reloads
00h
Count starts
01h
Timer RB primary reloads
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Waveform output starts
TRBIO pin output
Waveform output ends
Waveform output starts
1
0
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.21
Operating Example of Programmable One-Shot Generation Mode
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Waveform output ends
R8C/2A Group, R8C/2B Group
14.2.3.1
14. Timers
One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
• 1 is written to the TOSST bit in the TRBOCR register by a program.
• Trigger input from the INT0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following settings:
• Set the PD4_5 bit in the PD4 register to 0 (input port).
• Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
• Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
• Set the INT0EN bit in the INTEN register to 0 (enabled).
• After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
• Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
• If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
• If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
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14.2.4
14. Timers
Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 14.11 Programmable Wait One-Shot
Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only
once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length
of time equal to the setting value in the TRBPR register.
Figure 14.22 shows TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23 shows
an Operating Example of Programmable Wait One-Shot Generation Mode.
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Table 14.11
14. Timers
Programmable Wait One-Shot Generation Mode Specifications
Item
Count sources
Count operations
Specification
f1, f2, f8, timer RA underflow
• Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the
contents of timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the
contents of timer RB primary before the count completes and the TOSSTF
bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
Wait time
(n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register(2)
One-shot pulse output time (n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
Count start conditions
• The TSTART bit in the TRBCR register is set to 1 (count starts) and the
next trigger is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTART bit in the TRBCR register is set to 0 (count starts).
• When the TSTOP bit in the TRBCR register is set to 1 (count forcibly
stops).
Interrupt request
In half a cycle of the count source after timer RB underflows during
generation timing
secondary period (complete at the same time as waveform output from the
TRBO pin) [timer RB interrupt].
TRBO pin function
Pulse output
INT0 pin functions
Read from timer
Write to timer
Select functions
• When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot
trigger disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot
trigger enabled): external trigger (INT0 interrupt input)
The count value can be read out by reading registers TRBPR and TRBPRE.
• When registers TRBPRE, TRBSC, and TRBPR are written while the count
stops, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(1)
• Output level select function
The TOPL bit in the TRBIOC register selects the output level of the oneshot pulse waveform.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and
TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
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14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRBIOC
Bit Symbol
TOPL
TOCNT
Address
After Reset
010Ah
00h
Bit Name
Function
Timer RB output level select 0: Outputs one-shot pulse “H”.
bit
Outputs “L” w hen the timer stops or during
w ait.
1: Outputs one-shot pulse “L”.
Outputs “H” w hen the timer stops or during
w ait.
Timer RB output sw itch bit
Set to 0 in programmable w ait one-shot generation
mode.
RW
RW
RW
_____
INOSTG
INOSEG
—
(b7-b4)
One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled
_____
1 : INT0 pin one-shot trigger enabled
0 : Falling edge trigger
One-shot trigger polarity
1 : Rising edge trigger
select bit(1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTE:
1. Refer to 14.2.3.1 One-Shot Trigger Selection.
Figure 14.22
TRBIOC Register in Programmable Wait One-Shot Generation Mode
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RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR
register
1
0
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
TOSSTF bit in TRBOCR
register
Set to 0 when
counting ends
1
0
INT0 pin input
Count source
Timer RB prescaler
underflow signal
Count starts
Counter of timer RB
01h
Timer RB secondary reloads
00h
04h
Timer RB primary reloads
03h
02h
01h
00h
01h
Set to 0 when interrupt request is
acknowledged, or set by program.
IR bit in TRBIC
register
1
0
Set to 0 by program
TOPL bit in
TRBIOC register
1
0
Wait starts
TRBIO pin output
Waveform output starts
Waveform output ends
1
0
Wait
(primary period)
One-shot pulse
(secondary period)
The above applies under the following conditions.
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
Figure 14.23
Operating Example of Programmable Wait One-Shot Generation Mode
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R8C/2A Group, R8C/2B Group
14.2.5
14. Timers
Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
14.2.5.1
Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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R8C/2A Group, R8C/2B Group
14.2.5.2
14. Timers
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.24 and 14.25.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
IR bit in
TRBIC register
Primary period
(a)
Interrupt request is
acknowledged
Secondary period
Ensure sufficient time
(b)
Interrupt request
is generated
Instruction in
Interrupt
sequence interrupt routine
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 14.24
Workaround Example (a) When Timer RB interrupt is Used
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R8C/2A Group, R8C/2B Group
14. Timers
• Workaround example (b):
As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
Primary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
is detected at the end of the
secondary period.
Figure 14.25
Upon detecting (i), set the secondary and
then the primary register immediately.
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
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R8C/2A Group, R8C/2B Group
14.2.5.4
14. Timers
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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R8C/2A Group, R8C/2B Group
14.3
14. Timers
Timer RC
14.3.1
Overview
Timer RC is a 16-bit timer with four I/O pins.
Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.12 lists the Timer RC Operation Clock.
Table 14.12
Timer RC Operation Clock
Condition
Timer RC Operation Clock
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in f1
TRCCR1 register are set to a value from 000b to 101b)
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set fOCO40M
to 110b)
Table 14.13 lists the Timer RC I/O Pins, and Figure 14.26 shows a Timer RC Block Diagram.
Timer RC has three modes.
• Timer mode
- Input capture function
The counter value is captured to a register, using an external signal as the trigger.
- Output compare function Matches between the counter and register values are detected. (Pin output state
changes when a match is detected.)
The following two modes use the output compare function.
• PWM mode
Pulses of a given width are output continuously.
• PWM2 mode
A one-shot waveform or PWM waveform is output following the trigger after
the wait time has elapsed.
Input capture function, output compare function, and PWM mode settings may be specified independently for
each pin.
In PWM2 mode waveforms are output based on a combination of the counter or the register.
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14. Timers
f1, f2, f4, f8, f32,
fOCO40M
TRCMR register
TRCCR1 register
TRCIER register
INT0
Count source
select circuit
TRCSR register
TRCIOR0 register
TRCIOA/TRCTRG
TRCIOR1 register
Data bus
TRCCLK
Timer RC control circuit
TRC register
TRCGRA register
TRCIOB
TRCIOC
TRCIOD
TRCGRB register
TRCGRC register
TRCGRD register
TRCCR2 register
TRCDF register
Timer RC interrupt
request
TRCOER register
Figure 14.26
Table 14.13
Timer RC Block Diagram
Timer RC I/O Pins
Pin Name
TRCIOA(P5_1)
TRCIOB(P5_2)
TRCIOC(P5_3)
TRCIOD(P5_4)
TRCCLK(P5_0)
TRCTRG(P5_1)
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I/O
I/O
Function
Function differs according to the mode. Refer to descriptions of
individual modes for details
Input
Input
External clock input
PWM2 mode external trigger input
Page 196 of 580
R8C/2A Group, R8C/2B Group
14.3.2
14. Timers
Registers Associated with Timer RC
Table 14.14 lists the Registers Associated with Timer RC. Figures 14.27 to 14.37 show details of the registers
associated with timer RC.
Table 14.14
Registers Associated with Timer RC
0008h
MSTCR
Mode
Timer
Input
Output
PWM
Capture Compare
Function Function
Valid
Valid
Valid
0120h
TRCMR
Valid
Valid
Valid
Valid
0121h
TRCCR1
Valid
Valid
Valid
Valid
0122h
TRCIER
Valid
Valid
Valid
Valid
0123h
TRCSR
Valid
Valid
Valid
Valid
0124h
TRCIOR0 Valid
Valid
−
−
0125h
TRCIOR1
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
TRC
Valid
Valid
Valid
Valid
TRCGRA
Valid
Valid
Valid
Valid
TRCCR2
−
−
−
Valid
0131h
TRCDF
Valid
−
−
Valid
0132h
TRCOER
−
Valid
Valid
Valid
Address
Symbol
PWM2
Valid
TRCGRB
Related Information
Module operation enable register
Figure 14.27 MSTCR Register
Timer RC mode register
Figure 14.28 TRCMR Register
Timer RC control register 1
Figure 14.29 TRCCR1 Register
Figure 14.50 TRCCR1 Register for Output
Compare Function
Figure 14.53 TRCCR1 Register in PWM Mode
Figure 14.57 TRCCR1 Register in PWM2 Mode
Timer RC interrupt enable register
Figure 14.30 TRCIER Register
Timer RC status register
Figure 14.31 TRCSR Register
Timer RC I/O control register 0, timer RC I/O
control register 1
Figure 14.37 Registers TRCIOR0 and TRCIOR1
Figure 14.44 TRCIOR0 Register for Input
Capture Function
Figure 14.45 TRCIOR1 Register for Input
Capture Function
Figure 14.48 TRCIOR0 Register for Output
Compare Function
Figure 14.49 TRCIOR1 Register for Output
Compare Function
Timer RC counter
Figure 14.32 TRC Register
Timer RC general registers A, B, C, and D
Figure 14.33 Registers TRCGRA, TRCGRB,
TRCGRC, and TRCGRD
TRCGRC
TRCGRD
− : Invalid
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Timer RC control register 2
Figure 14.34 TRCCR2 Register
Timer RC digital filter function select register
Figure 14.35 TRCDF Register
Timer RC output master enable register
Figure 14.36 TRCOER Register
R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.27
MSTCR Register
Timer RC Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCMR
Bit Symbol
Address
0120h
Bit Name
PWM mode of TRCIOB select bit(2)
After Reset
01001000b
Function
RW
PWM mode of TRCIOC select bit(2)
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRCIOD select bit(2)
0 : Timer mode
1 : PWM mode
RW
PWM2 mode select bit
0 : PWM 2 mode
1 : Timer mode or PWM mode
RW
BFC
TRCGRC register function select
bit(3)
0 : General register
1 : Buffer register of TRCGRA register
RW
BFD
TRCGRD register function select
bit
0 : General register
1 : Buffer register of TRCGRB register
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
PWMB
PWMC
PWMD
PWM2
TSTART
TRC count start bit
0 : Count stops
1 : Count starts
NOTES:
1. For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode .
2. These bits are enabled w hen the PWM2 bit is set to 1 (timer mode or PWM mode).
3. Set the BFC bit to 0 (general register) in PWM2 mode.
Figure 14.28
TRCMR Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
0 : Timer mode
1 : PWM mode
Page 198 of 580
—
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Function varies according to the
operating mode (function).(2)
TRCIOB output level select bit
RW
RW
(1)
TOB
RW
TRCIOC output level select bit
(1)
TOC
RW
TRCIOD output level select bit
(1)
TOD
Count source select bits
(1)
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
TCK1
TCK2
TRC counter clear select bit(2, 3)
CCLR
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. Bits CCLR, TOA, TOB, TOC and TOD are disabled for the input capture function of the timer mode.
3. The TRC counter performs free-running operation for the input capture function of the timer mode independent of the
CCLR bit setting.
Figure 14.29
TRCCR1 Register
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCIER
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
—
(b6-b4)
Address
0122h
Bit Name
Input capture / compare match
interrupt enable bit A
After Reset
01110000b
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture / compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture / compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture / compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Overflow interrupt enable bit
OVIE
Figure 14.30
TRCIER Register
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0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
RW
—
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCSR
Bit Symbol
IMFA
Address
0123h
Bit Name
Input capture / compare match flag
A
After Reset
01110000b
Function
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
Refer to the table below .
Input capture / compare match flag
B
IMFC
Input capture / compare match flag
C
RW
IMFD
Input capture / compare match flag
D
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
Overflow flag
OVF
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
Refer to the table below .
NOTE:
1. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
IMFA
IMFB
IMFC
IMFD
OVF
Timer Mode
PWM Mode
PWM2 Mode
Input capture Function
Output Compare
Function
TRCIOA pin input edge(1)
When the values of the registers TRC and TRCGRA match.
TRCIOB pin input edge(1)
When the values of the registers TRC and TRCGRB match.
TRCIOC pin input edge(1)
When the values of the registers TRC and TRCGRC
match.(2)
TRCIOD pin input edge(1)
When the values of the registers TRC and TRCGRD
match.(2)
When the TRC register overflow s.
NOTES:
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA
and TRCGRB).
Figure 14.31
TRCSR Register
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REJ09B0324-0200
RW
IMFB
—
(b6-b4)
Bit Symbol
RW
Page 201 of 580
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Counter(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRC
Address
0127h-0126h
Function
After Reset
0000h
Setting Range
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRCSR register is set to 1.
RW
0000h to FFFFh
RW
NOTE:
1. Access the TRC register in 16-bit units. Do not access it in 8-bit units.
Figure 14.32
TRC Register
Timer RC General Register A, B, C and D(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRCGRA
TRCGRB
TRCGRC
TRCGRD
Address
0129h-0128h
012Bh-012Ah
012Dh-012Ch
012Fh-012Eh
Function
Function varies according to the operating mode.
NOTE:
1. Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.
Figure 14.33
Registers TRCGRA, TRCGRB, TRCGRC, and TRCGRD
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Page 202 of 580
After Reset
FFFFh
FFFFh
FFFFh
FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRCCR2
0130h
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b4-b0)
When read, the content is 1.
CSEL
After Reset
00011111b
Function
TRC count operation select
bit(1, 2)
0 : Count continues at compare match w ith
the TRCGRA register
1 : Count stops at compare match w ith
the TRCGRA register
TRCTRG input edge select bits (3)
b7 b6
TCEG0
TCEG1
0 0 : Disable the trigger input from the
TRCTRG pin
0 1 : Rising edge selected
1 0 : Falling edge selected
1 1 : Both edges selected
RW
—
RW
RW
RW
NOTES:
1. For notes on PWM2 mode, refer to 14.3.9.5 TRCM R Re giste r in PWM 2 M ode .
2. In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting).
3. In timer mode and PWM mode these bits are disabled.
Figure 14.34
TRCCR2 Register
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14. Timers
Timer RC Digital Filter Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCDF
Bit Symbol
DFA
Address
0131h
Bit Name
TRCIOA pin digital filter function
select bit(1)
After Reset
00h
Function
0 : Function is not used
1 : Function is used
RW
RW
DFB
TRCIOB pin digital filter function
select bit(1)
RW
DFC
TRCIOC pin digital filter function
select bit(1)
RW
DFD
TRCIOD pin digital filter function
select bit(1)
RW
DFTRG
TRCTRG pin digital filter function
select bit(2)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
—
(b5)
DFCK0
Clock select bits for digital filter
function(1, 2)
DFCK1
b7 b6
0
0
1
1
0 : f32
1 : f8
0 : f1
1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRCCR1 register)
RW
RW
NOTES:
1. These bits are enabled for the input capture function.
2. These bits are enabled w hen in PWM2 mode and bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or
11b (TRCTRG trigger input enabled).
Figure 14.35
TRCDF Register
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14. Timers
Timer RC Output Master Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCOER
Bit Symbol
Address
0132h
Bit Name
TRCIOA output disable bit(1)
EA
TRCIOB output disable bit(1)
EB
TRCIOC output disable bit(1)
EC
TRCIOD output disable bit(1)
ED
—
(b6-b4)
PTO
After Reset
01111111b
Function
RW
0 : Enable output
1 : Disable output (The TRCIOB pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRCIOC pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRCIOD pin is
used as a programmable I/O port.)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
_____
INT0 of pulse output forced
cutoff signal input enabled
bit
0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(Bits EA, EB, EC, and ED are set to 1
(disable output) w hen “L” is applied to the
_____
INT0 pin)
NOTE:
1. These bits are disabled for input pins set to the input capture function.
Figure 14.36
TRCOER Register
Rev.2.00 Nov 26, 2007
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RW
0 : Enable output
1 : Disable output (The TRCIOA pin is
used as a programmable I/O port.)
—
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC I/O Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRCIOR0
0124h
Bit Symbol
Bit Name
IOA0
TRCGRA control bits
IOA1
TRCGRA mode select bit(2)
IOA2
IOA3
IOB0
IOB1
IOB2
—
(b7)
After Reset
10001000b
Function
Function varies according to the operating mode
(function).
RW
RW
RW
0 : Output compare function
1 : Input capture function
RW
TRCGRA input capture input
sw itch bit(4)
0 : fOCO128 signal
1 : TRCIOA pin input
RW
TRCGRB control bits
Function varies according to the operating mode
(function).
RW
RW
TRCGRB mode select bit(3)
0 : Output compare function
1 : Input capture function
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. The TRCIOR0 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Timer RC I/O Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRCIOR1
0125h
Bit Symbol
Bit Name
IOC0
TRCGRC control bits
IOC1
TRCGRC mode select bit(2)
IOC2
After Reset
10001000b
Function
Function varies according to the operating mode
(function).
0 : Output compare function
1 : Input capture function
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
IOD0
IOD1
TRCGRD control bits
Function varies according to the operating mode
(function).
RW
RW
TRCGRD mode select bit(3)
0 : Output compare function
1 : Input capture function
RW
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. The TRCIOR1 register is enabled in timer mode. It is disabled in modes PWM and PWM2.
2. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
3. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Registers TRCIOR0 and TRCIOR1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
—
(b3)
IOD2
Figure 14.37
RW
RW
RW
Page 206 of 580
—
—
R8C/2A Group, R8C/2B Group
14.3.3
14. Timers
Common Items for Multiple Modes
14.3.3.1
Count Source
The method of selecting the count source is common to all modes.
Table 14.15 lists the Count Source Selection, and Figure 14.38 shows a Count Source Block Diagram.
Table 14.15
Count Source Selection
Count Source
f1, f2, f4, f8, f32
fOCO40M
Selection Method
Count source selected using bits TCK2 to TCK0 in TRCCR1 register
FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits
TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)
External signal input Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge
to TRCCLK pin
of external clock) and PD5_0 bit in PD5 register is set to 0 (input mode)
TCK2 to TCK0
f1
= 000b
= 001b
f2
= 010b
f4
Count source
= 011b
f8
TRC register
= 100b
f32
= 101b
TRCCLK
= 110b
fOCO40M
TCK2 to TCK0: Bits in TRCCR1 register
Figure 14.38
Count Source Block Diagram
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC
operation clock (see Table 14.12 Timer RC Operation Clock).
To select fOCO40M as the count source, set the FRA00 bit in the FRA0 register set to 1 (high-speed on-chip
oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M).
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R8C/2A Group, R8C/2B Group
14.3.3.2
14. Timers
Buffer Operation
Bits BFC and BFD in the TRCMR register are used to select the TRCGRC or TRCGRD register as the buffer
register for the TRCGRA or TRCGRB register.
• Buffer register for TRCGRA register: TRCGRC register
• Buffer register for TRCGRB register: TRCGRD register
Buffer operation differs depending on the mode.
Table 14.16 lists the Buffer Operation in Each Mode, Figure 14.39 shows the Buffer Operation for Input
Capture Function, and Figure 14.40 shows the Buffer Operation for Output Compare Function.
Table 14.16
Buffer Operation in Each Mode
Function, Mode
Input capture function
Transfer Timing
Input capture signal input
Transfer Destination Register
Contents of TRCGRA (TRCGRB)
register are transferred to buffer
register
Contents of buffer register are
transferred to TRCGRA (TRCGRB)
register
Contents of buffer register (TRCGRD)
are transferred to TRCGRB register
Output compare function Compare match between TRC
register and TRCGRA (TRCGRB)
PWM mode
register
PWM2 mode
• Compare match between TRC
register and TRCGRA register
• TRCTRG pin trigger input
TRCIOA input
(input capture signal)
TRCGRC
register
TRCGRA
register
TRC
TRCIOA input
TRC register
n
n-1
n+1
Transfer
TRCGRA register
m
n
Transfer
TRCGRC register
(buffer)
m
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).
Figure 14.39
Buffer Operation for Input Capture Function
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R8C/2A Group, R8C/2B Group
14. Timers
Compare match signal
TRCGRC
register
TRC register
TRCGRA register
TRCGRA
register
Comparator
m
m-1
TRC
m+1
m
n
Transfer
TRCGRC register
(buffer)
n
TRCIOA output
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
Figure 14.40
Buffer Operation for Output Compare Function
Make the following settings in timer mode.
• To use the TRCGRC register as the buffer register for the TRCGRA register:
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
• To use the TRCGRD register as the buffer register for the TRCGRB register:
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
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R8C/2A Group, R8C/2B Group
14.3.3.3
14. Timers
Digital Filter
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.
Figure 14.41 shows a Block Diagram of Digital Filter.
TCK2 to TCK0
f1
f2
f4
f8
f32
TRCCLK
DFCK1 to DFCK0
= 000b
= 00b
f32
= 001b
= 01b
f8
= 010b
= 10b
f1
= 011b
= 11b
Count source
= 100b
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
(or TCEG1 to TCEG0)
= 101b
= 110b
fOCO40M
Sampling clock
DFj (or DFTRG)
C
TRCIOj input signal
(or TRCTRG input
signal)
D
C
Q
Latch
C
D
Q
Latch
D
1
C
Q
Latch
D
Q
Latch
Match detect
circuit
Edge detect
circuit
0
Timer RC operation clock
f1 or fOCO40M
C
D
Q
Latch
Clock cycle selected by
TCK2 to TCK0
(or DFCK1 to DFCK0)
Sampling clock
TRCIOj input signal
(or TRCTRG input signal)
Three matches occur and a
signal change is confirmed.
Input signal after passing
through digital filter
Maximum signal transmission
delay is five sampling clock
pulses.
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
j = A, B, C, or D
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DFCK0 to DFCK1, DFj: Bits in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0: Bits in TRCCR2 register
Figure 14.41
Block Diagram of Digital Filter
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R8C/2A Group, R8C/2B Group
14.3.3.4
14. Timers
Forced Cutoff of Pulse Output
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj output pin functions as the programmable I/O port). When one or two
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 14.12 Timer RC
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.
Make the following settings to use this function.
• Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H”
output). (Refer to 7. Programmable I/O Ports.)
• Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Select the INT0 digital filter by means of bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and
a change in the INT0 pin input (refer to 12.6 Notes on Interrupts).
For details on interrupts, refer to 12. Interrupts.
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R8C/2A Group, R8C/2B Group
14. Timers
EA bit
write value
INT0 input
EA bit
D Q
S
Timer RC
output data
TRCIOA
Port P1_1
output data
PTO bit
EB bit
write value
EB bit
D Q
S
Port P1_1
input data
Timer RC
output data
TRCIOB
Port P1_2
output data
Port P1_2
input data
EC bit
write value
EC bit
D Q
S
Timer RC
output data
TRCIOC
Port P3_4
output data
ED bit
write value
ED bit
D Q
S
Port P3_4
input data
Timer RC
output data
Port P3_5
output data
Port P3_5
input data
EA, EB, EC, ED, PTO: Bits in TRCOER register
Figure 14.42
Forced Cutoff of Pulse Output
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Page 212 of 580
TRCIOD
R8C/2A Group, R8C/2B Group
14.3.4
14. Timers
Timer Mode (Input Capture Function)
This function measures the width or period of an external signal. An external signal input to the TRCIOj (j = A,
B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj
register (input capture). The input capture function, or any other mode or function, can be selected for each
individual pin.
The TRCGRA register can also select fOCO128 signal as input-capture trigger input.
Table 14.17 lists the Specifications of Input Capture Function, Figure 14.43 shows a Block Diagram of Input
Capture Function, Figures 14.44 and 14.45 show registers associated with the input capture function, Table
14.18 lists the Functions of TRCGRj Register when Using Input Capture Function, and Figure 14.46 shows an
Operating Example of Input Capture Function.
Table 14.17
Specifications of Input Capture Function
Item
Count source
Count operation
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
1/fk × 65,536 fk: Count source frequency
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The TRC register retains a value before count stops.
• Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows.
Programmable I/O port or input capture input (selectable individually by
pin)
Programmable I/O port or INT0 interrupt input
The count value can be read by reading TRC register.
The TRC register can be written to.
• Input capture input pin select
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selected
Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRCGRA register.
j = A, B, C, or D
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
Divided
by 128
fOCO
14. Timers
fOCO128
IOA3 = 0
Input capture signal(3)
TRCIOA
IOA3 = 1
(Note 1)
TRCGRA
register
TRC register
TRCGRC
register
TRCIOC
Input capture signal
Input capture signal
TRCIOB
(Note 2)
TRCGRB
register
TRCGRD
register
TRCIOD
Input capture signal
IOA3: Bit in TRCIOR0 register
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.
Figure 14.43
Block Diagram of Input Capture Function
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REJ09B0324-0200
Page 214 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC I/O Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TRCIOR0
Bit Symbol
Address
0124h
Bit Name
TRCGRA control bits
IOA0
IOA1
IOA2
IOA3
0 0 : Input capture to the TRCGRA register
at the rising edge
0 1 : Input capture to the TRCGRA register
at the falling edge
1 0 : Input capture to the TRCGRA register
at both edges
1 1 : Do not set.
TRCGRA input capture input
sw itch bit(3)
0 : fOCO128 signal
1 : TRCIOA pin input
RW
TRCGRB control bits
b5 b4
TRCGRB mode select bit(2)
0 0 : Input capture to the TRCGRB register
at the rising edge
0 1 : Input capture to the TRCGRB register
at the falling edge
1 0 : Input capture to the TRCGRB register
at both edges
1 1 : Do not set.
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
3. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
TRCIOR0 Register for Input Capture Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
RW
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
Figure 14.44
RW
Set to 1 (input capture) in the input capture
function.
IOB1
—
(b7)
RW
b1 b0
TRCGRA mode select bit(1)
IOB0
IOB2
After Reset
10001000b
Function
Page 215 of 580
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC I/O Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TRCIOR1
Bit Symbol
Address
0125h
Bit Name
TRCGRC control bits
After Reset
10001000b
Function
0 0 : Input capture to the TRCGRC register
at the rising edge
0 1 : Input capture to the TRCGRC register
at the falling edge
1 0 : Input capture to the TRCGRC register
at both edges
1 1 : Do not set.
IOC0
IOC1
IOC2
—
(b3)
TRCGRC mode select bit(1)
RW
RW
RW
—
b5 b4
0 0 : Input capture to the TRCGRD register
at the rising edge
0 1 : Input capture to the TRCGRD register
at the falling edge
1 0 : Input capture to the TRCGRD register
at both edges
1 1 : Do not set.
IOD0
IOD1
—
(b7)
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRCGRD control bits
IOD2
RW
b1 b0
TRCGRD mode select bit(2)
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
RW
—
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Figure 14.45
Table 14.18
TRCIOR1 Register for Input Capture Function
Functions of TRCGRj Register when Using Input Capture Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
−
BFC = 0
BFD = 0
BFC = 1
BFD = 1
Input Capture
Input Pin
General register. Can be used to read the TRC register value TRCIOA
at input capture.
TRCIOB
General register. Can be used to read the TRC register value TRCIOC
at input capture.
TRCIOD
Buffer registers. Can be used to hold transferred value from TRCIOA
the general register. (Refer to 14.3.3.2 Buffer Operation.)
TRCIOB
Register Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
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R8C/2A Group, R8C/2B Group
14. Timers
TRCCLK input
count source
TRC register
count value
FFFFh
0006h
0003h
0000h
TSTART bit in
TRCMR register
1
0
65536
TRCIOA input
TRCGRA register
0006h
Transfer
TRCGRC register
0003h
Transfer
0006h
IMFA bit in
TRCSR register
1
OVF bit in
TRCSR register
1
0
Set to 0 by a program
0
The above applies under the following conditions:
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA register are set to 101b (input capture at the falling edge of the TRCIOA input).
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
Figure 14.46
Operating Example of Input Capture Function
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R8C/2A Group, R8C/2B Group
14.3.5
14. Timers
Timer Mode (Output Compare Function)
This function detects when the contents of the TRC register (counter) and the TRCGRj register (j = A, B, C, or
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The
output compare function, or other mode or function, can be selected for each individual pin.
Table 14.19 lists the Specifications of Output Compare Function, Figure 14.47 shows a Block Diagram of
Output Compare Function, Figures 14.48 to 14.50 show registers associated with the output compare function,
Table 14.20 lists the Functions of TRCGRj Register when Using Output Compare Function, and Figure 14.51
shows an Operating Example of Output Compare Function.
Table 14.19
Specifications of Output Compare Function
Item
Count source
Count operation
Count period
Waveform output timing
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
• The CCLR bit in the TRCCR1 register is set to 0 (free running
operation): 1/fk × 65,536
fk: Count source frequency
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to
0000h at TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
Compare match
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops,
the TRC register retains a value before count stops.
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port or output compare output (selectable individually
by pin)
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer
Write to timer
Select functions
The count value can be read by reading the TRC register.
The TRC register can be written to.
• Output compare output pin selected
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level select
“L” output, “H” output, or toggle output
• Initial output level select
Sets output level for period from count start to compare match
• Timing for clearing the TRC register to 0000h
Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
of Pulse Output.)
• Can be used as an internal timer by disabling timer RC output
j = A, B, C, or D
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
TRC
TRCIOA
TRCIOC
TRCIOB
TRCIOD
Figure 14.47
Output
control
Output
control
Output
control
Output
control
Compare match signal
TRCGRA
Comparator
TRCGRC
Comparator
TRCGRB
Comparator
TRCGRD
Compare match signal
Compare match signal
Compare match signal
Block Diagram of Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Comparator
Page 219 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC I/O Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
TRCIOR0
Bit Symbol
Address
0124h
Bit Name
TRCGRA control bits
IOA0
IOA1
IOA2
IOA3
—
(b7)
0 0 : Disable pin output by compare
match (TRCIOA pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRA register
1 0 : “H” output by compare match in
the TRCGRA register
1 1 : Toggle output by compare match
in the TRCGRA register
Set to 0 (output compare) in the output compare
function.
TRCGRA input capture input
sw itch bit
Set to 1.
TRCGRB control bits
b5 b4
IOB1
TRCGRB mode select bit(2)
0 0 : Disable pin output by compare
match (TRCIOB pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRB register
1 0 : “H” output by compare match in
the TRCGRB register
1 1 : Toggle output by compare match
in the TRCGRB register
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Figure 14.48
TRCIOR0 Register for Output Compare Function
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Page 220 of 580
RW
b1 b0
TRCGRA mode select bit(1)
IOB0
IOB2
After Reset
10001000b
Function
RW
RW
RW
RW
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC I/O Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
TRCIOR1
Bit Symbol
Address
0125h
Bit Name
TRCGRC control bits
IOC0
IOC1
IOC2
—
(b3)
TRCGRC mode select bit(1)
IOD0
IOD1
—
(b7)
TRCGRD mode select bit(2)
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRC register
1 0 : “H” output by compare match in
the TRCGRC register
1 1 : Toggle output by compare match
in the TRCGRC register
Set to 0 (output compare) in the output compare
function.
0 0 : Disable pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRD register
1 0 : “H” output by compare match in
the TRCGRD register
1 1 : Toggle output by compare match
in the TRCGRD register
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
TRCIOR1 Register for Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 221 of 580
RW
RW
RW
—
b5 b4
NOTES:
1. When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
Figure 14.49
RW
b1 b0
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRCGRD control bits
IOD2
After Reset
10001000b
Function
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
TOB
TOC
TOD
Address
0121h
Bit Name
TRCIOA output level select bit(1, 2)
After Reset
00h
Function
0 : Initial output “L”
1 : Initial output “H”
RW
RW
TRCIOB output level select bit(1, 2)
RW
TRCIOC output level select bit(1, 2)
RW
TRCIOD output level select bit(1, 2)
Count source select bits (1)
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
TCK1
TCK2
TRC counter clear select bit
CCLR
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Tables 7.43 to 7.50), the initial output level is output w hen the
TRCCR1 register is set.
Figure 14.50
Table 14.20
TRCCR1 Register for Output Compare Function
Functions of TRCGRj Register when Using Output Compare Function
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
TRCGRD
Setting
Register Function
−
General register. Write a compare value to one of these
registers.
BFC = 0
BFD = 0
BFC = 1
BFD = 1
General register. Write a compare value to one of these
registers.
Buffer register. Write the next compare value to one of
these registers. (Refer to 14.3.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
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Output Compare
Output Pin
TRCIOA
TRCIOB
TRCIOC
TRCIOD
TRCIOA
TRCIOB
R8C/2A Group, R8C/2B Group
14. Timers
Count source
TRC register value
m
n
p
Count
restarts
Count
stops
TSTART bit in
TRCMR register
1
0
m+1
m+1
Output level held
TRCIOA output
Output inverted at
compare match
Initial output “L”
IMFA bit in
TRCSR register
1
0
Set to 0 by a program
Output level held
n+1
TRCIOB output
“H” output at
compare match
Initial output “L”
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
P+1
Output level held
“L” output at compare match
TRCIOC output
Initial output “H”
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA and TOB are set to 0 (“L” initial output until compare match) and the TOC bit is set to 1 (“H” initial output until
compare match).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 011b (TRCIOA output inverted at TRCGRA compare match).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC output at TRCGRC compare match).
Figure 14.51
Operating Example of Output Compare Function
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R8C/2A Group, R8C/2B Group
14.3.6
14. Timers
PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA
register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer
mode.)
Table 14.21 lists the Specifications of PWM Mode, Figure 14.52 shows a Block Diagram of PWM Mode,
Figure 14.53 shows the register associated with the PWM mode, Table 14.22 lists the Functions of TRCGRj
Register in PWM Mode, and Figures 14.54 and 14.55 show Operating Examples of PWM Mode.
Table 14.21
Specifications of PWM Mode
Item
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Increment
PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count source
Count operation
PWM waveform
m+1
n+1
Count start condition
Count stop condition
Interrupt request generation
timing
TRCIOA pin function
TRCIOB, TRCIOC, and
TRCIOD pin functions
INT0 pin function
Read from timer
Write to timer
Select functions
(“L” is active level)
1 (count starts) is written to the TSTART bit in the TRCMR register.
0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
• Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
Programmable I/O port
Programmable I/O port or PWM output (selectable individually by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• One to three pins selectable as PWM output pins per channel
One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable by individual pin
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced
Cutoff of Pulse Output.)
j = A, B, C, or D
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
m-n
Page 224 of 580
R8C/2A Group, R8C/2B Group
14. Timers
TRC
Compare match signal
Comparator
TRCIOB
TRCGRA
Compare match signal
(Note 1)
TRCIOC
Output
control
TRCIOD
Comparator
TRCGRB
Comparator
TRCGRC
Compare match signal
(Note 2)
Compare match signal
Comparator
TRCGRD
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
Figure 14.52
Block Diagram of PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 225 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Disabled in PWM mode
TRCIOB output level select bit(1, 2)
0 : Active level “H”
(Initial output “L”
“H” output by compare match in
the TRCGRj register
“L” output by compare match in
the TRCGRA register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in
the TRCGRj register
“H” output by compare match in
the TRCGRA register
TOB
TRCIOC output level select bit(1, 2)
TOC
TRCIOD output level select bit(1, 2)
TOD
Count source select bits (1)
TCK1
TCK2
TRC counter clear select bit
CCLR
RW
RW
RW
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
RW
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
j = B, C or D
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Tables 7.45 to 7.50), the initial output level is output w hen the
TRCCR1 register is set.
Figure 14.53
Table 14.22
TRCCR1 Register in PWM Mode
Functions of TRCGRj Register in PWM Mode
Register
TRCGRA
TRCGRB
TRCGRC
TRCGRD
TRCGRC
Setting
−
−
BFC = 0
BFD = 0
BFC = 1
TRCGRD
BFD = 1
Register Function
General register. Set the PWM period.
General register. Set the PWM output change point.
General register. Set the PWM output change point.
Buffer register. Set the next PWM period. (Refer to 14.3.3.2
Buffer Operation.)
Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.)
PWM Output Pin
−
TRCIOB
TRCIOC
TRCIOD
−
TRCIOB
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
TRC register value
m
n
p
q
m+1
n+1
Active level is “H”
TRCIOB output
m-n
Inactive level is “L”
p+1
m-p
“L” initial output until
compare match
TRCIOC output
q+1
m-q
Active level is “L”
TRCIOD output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
IMFD bit in
TRCSR register
1
“H” initial output until
compare match
0
Set to 0 by a program
Set to 0 by a program
0
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”).
Figure 14.54
Operating Example of PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 227 of 580
R8C/2A Group, R8C/2B Group
14. Timers
TRC register value
p
m
q
n
0000h
TSTART bit in
TRCMR register
1
TRCIOB output does not switch to “L” because
no compare match with the TRCGRB register
has occurred
0
Duty 0%
TRCIOB output
TRCGRB register
n
q
p (p>m)
Rewritten by a program
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
0
Set to 0 by a program
Set to 0 by a program
0
TRC register value
m
p
n
0000h
TSTART bit in
TRCMR register
1
If compare matches occur simultaneously with registers TRCGRA and
TRCGRB, the compare match with the TRCGRB register has priority.
TRCIOB output switches to “L”. (In other words, no change).
0
Duty 100%
TRCIOB output
TRCIOB output switches to “L” at compare match with the
TRCGRB register. (In other words, no change).
n
TRCGRB register
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
m
p
Rewritten by
a program
0
Set to 0 by a program
Set to 0 by a program
0
m: TRCGRA register setting value
The above applies under the following conditions:
• The EB bit in the TRCOER register is set to 0 (output from TRCIOB enabled).
• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).
Figure 14.55
Operating Example of PWM Mode (Duty 0% and Duty 100%)
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.3.7
14. Timers
PWM2 Mode
This mode outputs a single PWM waveform. After a given wait duration has elapsed following the trigger, the
pin output switches to active level. Then, after a given duration, the output switches back to inactive level.
Furthermore, the counter stops at the same time the output returns to inactive level, making it possible to use
PWM2 mode to output a programmable wait one-shot waveform.
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with
it.
Figure 14.56 shows a Block Diagram of PWM2 Mode, Table 14.23 lists the Specifications of PWM2 Mode,
Figure 14.57 shows the register associated with PWM2 mode, Table 14.24 lists the Functions of TRCGRj
Register in PWM2 Mode, and Figures 14.58 to 14.60 show Operating Examples of PWM2 Mode.
Trigger signal
Compare match signal
TRCTRG
TRCIOB
Input
control
Count clear signal
TRC
(Note 1)
Comparator
TRCGRA
Comparator
TRCGRB
Comparator
TRCGRC
TRCGRD
register
Output
control
NOTE:
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB register).
Figure 14.56
Block Diagram of PWM2 Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 229 of 580
R8C/2A Group, R8C/2B Group
Table 14.23
14. Timers
Specifications of PWM2 Mode
Item
Count source
Count operation
PWM waveform
Specification
f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRCTRG input
m+1
n+1
n+1
p+1
p+1
TRCIOB output
n-p
n-p
(TRCTRG: Rising edge, active level is “H”)
Count start conditions
Count stop conditions
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
PWM output
TRCIOC and TRCIOD pin Programmable I/O port
functions
INT0 pin function
Read from timer
Write to timer
Select functions
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selected
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse
Output.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
j = A, B, C, or D
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RC Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRCCR1
Bit Symbol
TOA
Address
0121h
Bit Name
TRCIOA output level select bit(1)
After Reset
00h
Function
Disabled in the PWM2 mode
TRCIOB output level select bit(1, 2)
0 : Active level “H”
(Initial output “L”
“H” output by compare match in the
TRCGRC register
“L” output by compare match in the
TRCGRB register
1 : Active level “L”
(Initial output “H”
“L” output by compare match in the
TRCGRC register
“H” output by compare match in the
TRCGRB register
TOB
TOC
TOD
TRCIOC output level select bit(1)
Disabled in the PWM2 mode
TRCIOD output level select bit(1)
Count source select bits (1)
TCK1
TCK2
TRC counter clear select bit
CCLR
RW
RW
RW
RW
b6 b5 b4
0
0
0
0
1
1
1
1
TCK0
RW
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRCCLK input rising edge
0 : fOCO40M
1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match in the
TRCGRA register
RW
RW
RW
RW
NOTES:
1. Set to these bits w hen the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for w aveform output (refer to Tables 7.45 and 7.46), the initial output level is output w hen
the TRCCR1 register is set.
Figure 14.57
Table 14.24
TRCCR1 Register in PWM2 Mode
Functions of TRCGRj Register in PWM2 Mode
Register
TRCGRA
TRCGRB
TRCGRC
Setting
−
−
BFC = 0
TRCGRD
TRCGRD
BFD = 0
BFD = 1
Register Function
PWM2 Output Pin
General register. Set the PWM period.
TRCIOB pin
General register. Set the PWM output change point.
General register. Set the PWM output change point (wait time
after trigger).
(Not used in PWM2 mode)
−
Buffer register. Set the next PWM output change point. (Refer to TRCIOB pin
14.3.3.2 Buffer Operation.)
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. Do not set the TRCGRB and TRCGRC registers to the same value.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
TRC register value
FFFFh
TRC register cleared
at TRCGRA register
compare match
m
n
Previous value held if the
TSTART bit is set to 0
Set to 0000h
by a program
p
0000h
TSTART bit in
TRCMR register
Count stops
because the
CSEL bit is
set to 1
1
0
Set to 1 by
a program
CSEL bit in
TRCCR2 register
TSTART bit
is set to 0
1
0
m+1
n+1
p+1
“H” output at TRCGRC
register compare match
p+1
Return to initial output
if the TSTART bit is
set to 0
“L” initial output
TRCIOB output
“L” output at TRCGRB
register compare match
No change
No change
“H” output at TRCGRC register
compare match
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
0
Set to 0 by a program
0
Set to 0 by a program
Set to 0 by a program
0
TRCGRB register
n
Transfer
TRCGRD register
n
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 14.58
Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
TRC register value
TRC register cleared
at TRCGRA register
compare match
FFFFh
m
TRC register (counter)
cleared at TRCTRG pin
trigger input
Previous value
held if the
TSTART bit is
set to 0
n
Set to 0000h
by a program
p
0000h
TRCTRG input
Count starts at
TRCTRG pin
trigger input
Count starts
TSTART bit
is set to 1
TSTART bit in
TRCMR register
1
CSEL bit in
TRCCR2 register
1
Count stops
because the
CSEL bit is
set to 1
Changed by a program
The TSTART
bit is set to 0
0
Set to 1 by
a program
0
m+1
n+1
n+1
p+1
p+1
“H” output at
TRCGRC register
compare match
“L” output at
TRCGRB register
compare match
“L” initial output
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
TRCGRB register
p+1
Inactive level so
TRCTRG input is
enabled
Return to initial value if the
TSTART bit is set to 0
Active level so TRCTRG
input is disabled
0
Set to 0 by
a program
0
Set to 0 by
a program
Set to 0 by
a program
Set to 0 by
a program
0
n
n
Transfer
TRCGRD register
n
n
Transfer
n
Transfer from buffer register to general register
Transfer
Transfer
Next data
Transfer from buffer register to general register
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare match with the
TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
Figure 14.59
Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
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14. Timers
• TRCGRB register setting value greater than TRCGRA
register setting value
TRC register value
• TRCGRC register setting value greater than TRCGRA
register setting value
TRC register value
n
p
m
m
n
p
0000h
0000h
TSTART bit in
TRCMR register
1
TSTART bit in
TRCMR register
0
n+1
m+1
m+1
TRCIOB output
“H” output at TRCGRC register
compare match
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
0
p+1
No compare match with
TRCGRB register, so
“H” output continues
IMFA bit in
TRCSR register
1
“L” initial
output
0
0
1
Set to 0 by a
program
0
No compare match
with TRCGRC register,
so “L” output continues
TRCIOB output
IMFA bit in
TRCSR register
1
IMFB bit in
TRCSR register
1
IMFC bit in
TRCSR register
1
“L” output at
TRCGRB register
compare match
with no change.
“L” initial
output
0
0
0
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disabled).
Figure 14.60
Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
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14.3.8
14. Timers
Timer RC Interrupt
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single
TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 14.25 lists the Registers Associated with Timer RC Interrupt, and Figure 14.61 is a Timer RC Interrupt
Block Diagram.
Table 14.25
Registers Associated with Timer RC Interrupt
Timer RC Status Register
TRCSR
Timer RC Interrupt Enable Register
TRCIER
IMFA bit
IMIEA bit
Timer RC Interrupt Control Register
TRCIC
Timer RC interrupt request
(IR bit in TRCIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
Figure 14.61
Timer RC Interrupt Block Diagram
Like other maskable interrupts, the timer RC interrupt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.
• The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to
1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
• The IR bit is set to 0 (no interrupt request) when the bit in the TRCSR register or the corresponding bit in
the TRCIER register is set to 0, or both are set to 0. In other words, the interrupt request is not maintained
if the IR bit is once set to 1 but the interrupt is not acknowledged.
• If after the IR bit is set to 1 another interrupt source is triggered, the IR bit remains set to 1 and does not
change.
• If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
interrupt request.
• The bits in the TRCSR register are not automatically set to 0 when an interrupt is acknowledged. Set them
to 0 within the interrupt routine. Refer to Figure 14.31 TRCSR Register, for the procedure for setting
these bits to 0.
Refer to Figure 14.30 TRCIER Register, for details of the TRCIER register.
Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
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14.3.9
14. Timers
Notes on Timer RC
14.3.9.1
TRC Register
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.W
#XXXXh, TRC
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.W
TRC,DATA
;Read
14.3.9.2
TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.B
#XXh, TRCSR
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.B
TRCSR,DATA
;Read
14.3.9.3
Count Source Switching
• Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
14.3.9.4
Input Capture Function
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
(refer to Table 14.12 Timer RC Operation Clock).
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
14.3.9.5
TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
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14.4
14. Timers
Timer RD
Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins.
The operation clock of timer RD is f1 or fOCO40M. Table 14.26 lists the Timer RD Operation Clocks.
Table 14.26
Timer RD Operation Clocks
Condition
Operation Clock of Timer RD
The count source is f1, f2, f4, f8, f32, or TRDCLK input
f1
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to a value from 000b
to 101b).
The count source is fOCO40M
(bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b).
fOCO40M
Figure 14.62 shows a Block Diagram of Timer RD. Timer RD has 5 modes:
• Timer mode
- Input capture function
Transfer the counter value to a register with an external signal as the
trigger
- Output compare function
Detect register value matches with a counter
(Pin output can be changed at detection)
The following 4 modes use the output compare function.
• PWM mode
Output pulse of any width continuously
• Reset synchronous PWM mode
Output three-phase waveforms (6) without sawtooth wave modulation
and dead time
• Complementary PWM mode
Output three-phase waveforms (6) with triangular wave modulation and
dead time
• PWM3 mode
Output PWM waveforms (2) with a fixed period
In the input capture function, output compare function, and PWM mode, channels 0 and 1 have the equivalent
functions, and functions or modes can be selected individually for each pin. Also, a combination of these functions
and modes can be used in 1 channel.
In reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, a waveform is output with a
combination of counters and registers in channels 0 and 1.
Tables 14.27 to 14.35 list the Pin Functions of timer RD.
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Table 14.27
Pin Functions TRDIOA0/TRDCLK(P2_0)
Register TRDOER1
Bit
EA0
Setting
value
14. Timers
TRDFCR
TRDIORA0
Function
PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0
0
0
0
00b
X
XXXb
0
1
0
00b
1
001b, 01Xb
1
0
00b
X
1XXb
Timer mode trigger input (input capture function)(1)
1
1
XXb
X
000b
External clock input (TRDCLK)(1)
X
Other than above
PWM3 mode waveform output
Timer mode waveform output (output compare
function)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_0 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function) and external clock
input (TRDCLK).
Table 14.28
Pin Functions TRDIOB0(P2_1)
Register TRDOER1
Bit
EB0
Setting
value
TRDFCR
TRDPMR
TRDIORA0
PWM3 CMD1, CMD0
PWMB0
IOB2_IOB0
1Xb
X
XXXb
Complementary PWM mode waveform output
Function
0
X
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
0
00b
X
XXXb
PWM3 mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_1 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.29
Pin Functions TRDIOC0(P2_2)
Register
TRDOER1
TRDFCR
TRDPMR
TRDIORC0
Bit
EC0
PWM3 CMD1, CMD0
PWMC0
IOC2_IOC0
1Xb
X
XXXb
Setting
value
Function
0
X
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Complementary PWM mode waveform output
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_2 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
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R8C/2A Group, R8C/2B Group
Table 14.30
14. Timers
Pin Functions TRDIOD0(P2_3)
Register
TRDOER1
TRDFCR
TRDPMR
TRDIORC0
Bit
ED0
PWM3 CMD1, CMD0
PWMD0
IOD2_IOD0
1Xb
X
XXXb
Setting
value
Function
0
X
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Complementary PWM mode waveform output
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_3 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.31
Pin Functions TRDIOA1(P2_4)
Register
TRDOER1
TRDFCR
TRDIORA1
Bit
EA1
PWM3 CMD1, CMD0
IOA2_IOA0
Setting
value
Function
0
X
1Xb
XXXb
Complementary PWM mode waveform output
0
X
01b
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
001b, 01Xb
X
1
00b
1XXb
Other than above
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_4 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.32
Pin Functions TRDIOB1(P2_5)
Register
TRDOER1
TRDFCR
TRDPMR
TRDIORA1
Bit
EB1
PWM3 CMD1, CMD0
PWMB1
IOB2_IOB0
1Xb
X
XXXb
Setting
value
Function
Complementary PWM mode waveform output
0
X
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_5 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
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R8C/2A Group, R8C/2B Group
Table 14.33
14. Timers
Pin Functions TRDIOC1(P2_6)
Register
TRDOER1
TRDFCR
TRDPMR
TRDIORC1
Bit
EC1
PWM3 CMD1, CMD0
PWMC1
IOC2_IOC0
1Xb
X
XXXb
Setting
value
Function
0
X
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Complementary PWM mode waveform output
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_6 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.34
Pin Functions TRDIOD1(P2_7)
Register
TRDOER1
TRDFCR
TRDPMR
TRDIORC1
Bit
ED1
PWM3 CMD1, CMD0
PWMD1
IOD2_IOD0
Setting
value
Function
0
X
1Xb
X
XXXb
Complementary PWM mode waveform output
0
X
01b
X
XXXb
Reset synchronous PWM mode waveform output
0
1
00b
1
XXXb
PWM mode waveform output
0
1
00b
0
001b, 01Xb
X
1
00b
0
1XXb
Other than above
Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
I/O port
X: can be 0 or 1, no change in outcome
NOTE:
1. Set the PD2_7 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.35
Pin Functions INT0(P4_5)
Register
TRDOER2
Bit
PTO
Setting
value
1
INTEN
PD4
INT0PL
INT0EN
PD4_5
0
1
0
Other than above
X: can be 0 or 1, no change in outcome
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Function
Pulse output forced cutoff signal input
I/O port or INT0 interrupt input
R8C/2A Group, R8C/2B Group
14. Timers
f1, f2, f4, f8, f32,
fOCO40M
Channel i
TRDi register
TRDGRAi register
TRDGRBi register
TRDGRCi register
INT0
Count source
select circuit
TRDGRDi register
TRDDFi register
Data bus
TRDCRi register
TRDIOB0
Timer RD control
circuit
TRDIOC0
TRDIOD0
TRDIORAi register
TRDIOA1
TRDIORCi register
TRDIOB1
TRDSRi register
TRDIOC1
TRDIERi register
TRDIOD1
TRDPOCRi register
TRDSTR register
TRDMR register
TRDPMR register
TRDFCR register
TRDOER1 register
TRDOER2 register
TRDOCR register
i = 0 or 1
Figure 14.62
TRDIOA0/TRDCLK
Block Diagram of Timer RD
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Channel 0 interrupt
request
Channel 1 interrupt
request
A/D trigger
R8C/2A Group, R8C/2B Group
14.4.1
14. Timers
Count Sources
The count source selection method is the same in all modes. However, in PWM3 mode, the external clock
cannot be selected.
Table 14.36
Count Source Selection
Count Source
Selection
f1, f2, f4, f8, f32
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
fOCO40M(1)
The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
External signal input
to TRDCLK pin
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
i = 0 or 1
NOTE:
1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.
TCK2 to TCK0
f1
= 000b
= 001b
f2
= 010b
f4
Count source
= 011b
f8
TRDi register
= 100b
f32
= 110b
fOCO40M
STCLK = 1
TRDCLK/
TRDIOA0
CKEG1 to CKEG0
Valid edge
selected
= 101b
STCLK = 0
TRDIOA0 I/O or programmable I/O port
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
Figure 14.63
Block Diagram of Count Source
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 14.26 Timer RD Operation Clocks).
When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed onchip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).
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14.4.2
14. Timers
Buffer Operation
The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the
TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi
in the TRDMR register.
• TRDGRAi buffer register: TRDGRCi register
• TRDGRBi buffer register: TRDGRDi register
Buffer operation depends on the mode. Table 14.37 lists the Buffer Operation in Each Mode.
Table 14.37
Buffer Operation in Each Mode
Function and Mode
Transfer Timing
Transfer Register
Input capture function
Input capture signal input
Transfer content in TRDGRAi
(TRDGRBi) register to buffer register
Output compare function
Compare match with TRDi register
and TRDGRAi (TRDGRBi) register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
Reset synchronous PWM Compare match withTRD0 register
mode
and TRDGRA0 register
Transfer content in buffer register to
TRDGRAi (TRDGRBi) register
PWM mode
Complementary PWM
mode
• Compare match with TRD0 register Transfer content in buffer register to
and TRDGRA0 register
registers TRDGRB0, TRDGRA1, and
• TRD1 register underflow
TRDGRB1
PWM3 mode
Compare match with TRD0 register
and TRDGRA0 register
Transfer content in buffer register to
registers TRDGRA0, TRDGRB0,
TRDGRA1, and TRDGRB1
i = 0 or 1
TRDIOAi input
(input capture signal)
TRDGRCi register
(buffer)
TRDGRAi
register
TRDi
TRDIOAi input
TRDi register
n
n-1
n+1
Transfer
TRDGRAi register
m
n
Transfer
TRDGRCi register
(buffer)
m
i = 0 or 1
The above applies under the following conditions:
• The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
Figure 14.64
Buffer Operation in Input Capture Function
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14. Timers
Compare match signal
TRDGRCi register
(buffer)
TRDi register
TRDGRAi
register
m
m-1
TRDGRAi register
Comparator
TRDi
m+1
m
n
Transfer
TRDGRCi register
(buffer)
n
TRDIOAi output
i = 0 or 1
The above applies under the following conditions:
• BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of
the TRDGRAi register).
• Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b (“L” output by the compare match).
Figure 14.65
Buffer Operation in Output Compare Function
Perform the following for the timer mode (input capture and output compare functions).
When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register
• Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register).
• Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register.
When using the TRDGRDi register as the buffer register of the TRDGRBi register
• Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register).
• Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using
registers TRDGRCi and TRDGRDi as the buffer register in the input capture function.
When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, reset
synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi
register are set to 1 by a compare match with the TRDi register.
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R8C/2A Group, R8C/2B Group
14.4.3
14. Timers
Synchronous Operation
The TRD1 register is synchronized with the TRD0 register.
• Synchronous preset
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both
the TRD0 and TRD1 registers after writing to the TRDi register.
• Synchronous clear
When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register
are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register
is set to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi
register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0
register is set to 0000h.
TRDIOA0 input
Set to 0000h by input capture
Value in
TRD0 register
n
n writing
n is set
Value in
TRD1 register
n is set
n
Set to 0000h with TRD0 register
The above applies under the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with
the TRD0 register).
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b.
(Input capture at the rising edge of the TRDIOA0 input)
The PWM 3 bit in the TRDFCR register is set to 1.
Figure 14.66
Synchronous Operation
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14.4.4
14. Timers
Pulse Output Forced Cutoff
In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and
PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable
I/O port by the INT0 pin input, and pulse output can be cut off.
The pins used for output in these functions or modes can function as the output pin of timer RD when the
applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the
TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1
register are set to 1 (disable timer RD output, the TRDIOji output pin is used as the programmable I/O port)
after “L” is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after “L” is
applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 14.26
Timer RD Operation Clocks).
Set as below when using this function:
• Set the pin status (high impedance, “L” or “H” output) to pulse output forced cutoff by registers P2 and
PD2.
• Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0).
According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in
the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.
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14. Timers
EA0 bit
writing value
INT0 input
EA0 bit
D Q
S
Timer RD
output data
TRDIOA0
Port P2_0
output data
PTO bit
EB0 bit
writing value
EB0 bit
D Q
S
Port P2_0
input data
Timer RD
output data
TRDIOB0
Port P2_1
output data
Port P2_1
input data
EC0 bit
writing value
EC0 bit
D Q
S
Timer RD
output data
TRDIOC0
Port P2_2
output data
ED0 bit writing
value
ED0 bit
D Q
S
Port P2_2
input data
Timer RD
output data
TRDIOD0
Port P2_3
output data
Port P2_3
input data
EA1 bit writing
value
EA1 bit
D Q
S
Timer RD
output data
TRDIOA1
Port P2_4
output data
Port P2_4
input data
EB1 bit writing
value
EB1 bit
D Q
S
Timer RD
output data
TRDIOB1
Port P2_5
output data
EC1 bit
writing value
EC1 bit
D Q
S
Port P2_5
input data
Timer RD
output data
TRDIOC1
Port P2_6
output data
ED1 bit
writing value
ED1 bit
D Q
S
Port P2_6
input data
Timer RD
output data
Port P2_7
output data
Port P2_7
input data
PTO: Bit in TRDOER2 register
EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register
Figure 14.67
Pulse Output Forced Cutoff
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TRDIOD1
R8C/2A Group, R8C/2B Group
14.4.5
14. Timers
Input Capture Function
The input capture function measures the external signal width and period. The content of the TRDi register
(counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D)
pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and
TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual
pin.
The TRDGRA0 register can also select fOCO128 signal as input-capture trigger input.
Figure 14.68 shows a Block Diagram of Input Capture Function, Table 14.38 lists the Input Capture Function
Specifications. Figures 14.69 to 14.80 show the Registers Associated with Input Capture Function, and Figure
14.81 shows an Operating Example of Input Capture Function.
Input capture signal
TRDIOAi(3)
(Note 1)
TRDGRAi
register
TRDi register
TRDGRCi
register
TRDIOCi
Input capture signal
Input capture signal
TRDIOBi
(Note 2)
TRDGRBi
register
fOCO
TRDIOA0
TRDGRDi
register
TRDIODi
Input capture signal
Divided
by 128
fOCO128
IOA3 = 0
Input capture
signal
IOA3 = 1
NOTE 3: The trigger input of the TRDGRA0 register
can select the TRDIOA0 pin input or
fOCO128 signal.
i = 0 or 1
NOTE 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the
TRDGRAi register).
NOTE 2: When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the
TRDGRBi register).
Figure 14.68
Block Diagram of Input Capture Function
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Table 14.38
14. Timers
Input Capture Function Specifications
Item
Specification
Count sources
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations
Increment
Count period
When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b
(free-running operation).
1/fk × 65536 fk: Frequency of count source
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop condition
0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
Interrupt request generation
timing
• Input capture (valid edge of TRDIOji input or fOCO128 signal edge)
• TRDi register overflows
TRDIOA0 pin function
Programmable I/O port, input-capture input, or TRDCLK (external clock)
input
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
Programmable I/O port, or input-capture input (selectable by pin)
INT0 pin function
Programmable I/O port or INT0 interrupt input
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
• When the SYNC bit in the TRDMR register is set to 0 (channels 0 and
1 operate independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and
1 operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to
the TRDi register.
Select functions
• Input-capture input pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or
TRDIODi.
• Input-capture input valid edge selected
The rising edge, falling edge, or both the rising and falling edges
• The timing when the TRDi register is set to 0000h
At overflow or input capture
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Digital filter
The TRDIOji input is sampled, and when the sampled input level match
as 3 times, the level is determined.
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRDGRA0 register.
i = 0 or 1, j = either A, B, C, or D
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R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b2-b0)
When read, the content is 0.
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.69
MSTCR Register
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14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
Symbol
TRDSTR
Bit Symbol
TSTART0
TSTART1
CSEL0
CSEL1
—
(b7-b4)
Address
0137h
Bit Name
TRD0 count start flag
After Reset
11111100b
Function
RW
0 : Count stops
1 : Count starts
RW
TRD1 count start flag
0 : Count stops
1 : Count starts
RW
TRD0 count operation select bit
Set to 1 in the input capture function.
TRD1 count operation select bit
Set to 1 in the input capture function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
—
NOTE:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDMR
Bit Symbol
Address
0138h
Bit Name
Timer RD synchronous bit
SYNC
—
(b3-b1)
Figure 14.70
After Reset
00001110b
Function
0 : Registers TRD0 and TRD1
operate independently
1 : Registers TRD0 and TRD1
operate synchronously
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
BFC0
TRDGRC0 register function select 0 : General register
bit
1 : Buffer register of TRDGRA0 register
RW
BFD0
TRDGRD0 register function select 0 : General register
bit
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function select 0 : General register
bit
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function select 0 : General register
bit
1 : Buffer register of TRDGRB1 register
RW
Registers TRDSTR and TRDMR in Input Capture Function
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REJ09B0324-0200
RW
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14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0 0 0
Symbol
TRDPMR
Bit Symbol
PWMB0
PWMC0
PWMD0
—
(b3)
PWMB1
PWMC1
PWMD1
—
(b7)
Figure 14.71
Address
0139h
Bit Name
PWM mode of TRDIOB0 select bit
After Reset
10001000b
Function
Set to 0 (timer mode) in the input capture
function.
RW
PWM mode of TRDIOC0 select bit
Set to 0 (timer mode) in the input capture
function.
RW
PWM mode of TRDIOD0 select bit
Set to 0 (timer mode) in the input capture
function.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
PWM mode of TRDIOB1 select bit
Set to 0 (timer mode) in the input capture
function.
RW
PWM mode of TRDIOC1 select bit
Set to 0 (timer mode) in the input capture
function.
RW
PWM mode of TRDIOD1 select bit
Set to 0 (timer mode) in the input capture
function.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDPMR Register in Input Capture Function
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RW
Page 252 of 580
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14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits (1)
After Reset
10000000b
Function
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in the input capture function.
CMD1
RW
OLS0
RW
OLS1
Counter-phase output level select bit This bit is disabled in the input capture
(in reset synchronous PWM mode or function.
complementary PWM mode)
RW
ADTRG
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in the input capture
function.
RW
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in the input capture
function.
RW
External clock input select bit
0 : External clock input disabled
1 : External clock input enabled
RW
PWM3 mode select bit
Set this bit to 1 (other than PWM3 mode) in
the input capture function.
RW
(2)
PWM3
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
TRDFCR Register in Input Capture Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Normal-phase output level select bit This bit is disabled in the input capture
(in reset synchronous PWM mode or function.
complementary PWM mode)
STCLK
Figure 14.72
RW
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14. Timers
Timer RD Digital Filter Function Select Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDDF0
TRDDF1
Bit Symbol
Address
013Eh
013Fh
Bit Name
TRDIOA pin digital filter function
select bit
Function
0 : Function is not used
1 : Function is used
DFB
TRDIOB pin digital filter function
select bit
0 : Function is not used
1 : Function is used
RW
DFC
TRDIOC pin digital filter function
select bit
0 : Function is not used
1 : Function is used
RW
DFD
TRDIOD pin digital filter function
select bit
0 : Function is not used
1 : Function is used
RW
DFA
—
(b5-b4)
DFCK0
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock select bits for digital filter
function
DFCK1
Figure 14.73
After Reset
00h
00h
Page 254 of 580
RW
—
b7 b6
0
0
1
1
0 : f32
1 : f8
0 : f1
1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRDCRi register)
Registers TRDDF0 to TRDDF1 in Input Capture Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDCR0
TRDCR1
Bit Symbol
Address
0140h
0150h
Bit Name
Count source select bits
After Reset
00h
00h
Function
0
0
0
0
1
1
1
1
TCK0
TCK1
TCK2
External clock edge select bits (2)
CKEG0
CKEG1
TRDi counter clear select bits
CCLR0
CCLR1
CCLR2
RW
b2 b1 b0
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRDCLK input(1)
0 : fOCO40M
1 : Do not set.
RW
RW
RW
b4 b3
0
0
1
1
0 : Count at the rising edge
1 : Count at the falling edge
0 : Count at both edges
1 : Do not set.
RW
RW
b7 b6 b5
0 0 0 : Disable clear (free-running
operation)
0 0 1 : Clear by input capture in the
TRDGRAi register
0 1 0 : Clear by input capture in the
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other
channel counter)(3)
1 0 0 : Do not set.
1 0 1 : Clear by input capture in the
TRDGRCi register
1 1 0 : Clear by input capture in the
TRDGRDi register
1 1 1 : Do not set.
RW
RW
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
synchronously).
Figure 14.74
Registers TRDCR0 to TRDCR1 in Input Capture Function
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14. Timers
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol
TRDIORA0
TRDIORA1
Bit Symbol
Address
0141h
0151h
Bit Name
TRDGRA control bits
IOA0
IOA1
IOA2
IOA3
RW
0 0 : Input capture to the TRDGRAi register
at the rising edge
0 1 : Input capture to the TRDGRAi register
at the falling edge
1 0 : Input capture to the TRDGRAi register
at both edges
1 1 : Do not set.
RW
RW
Set to 1 (input capture) in the input capture
function.
RW
Input capture input sw itch
bit(3, 4)
0 : fOCO128 Signal
1 : TRDIOA0 pin input
RW
TRDGRB control bits
b5 b4
IOB1
—
(b7)
Function
b1 b0
TRDGRA mode select bit(1)
IOB0
IOB2
After Reset
10001000b
10001000b
TRDGRB mode select bit(2)
0 0 : Input capture to the TRDGRBi register
at the rising edge
0 1 : Input capture to the TRDGRBi register
at the falling edge
1 0 : Input capture to the TRDGRBi register
at both edges
1 1 : Do not set.
Set to 1 (input capture) in the input capture
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
RW
—
NOTES:
1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1.
4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Figure 14.75
Registers TRDIORA0 to TRDIORA1 in Input Capture Function
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14. Timers
Timer RD I/O Control Register Ci (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
1 1
1 1
Symbol
TRDIORC0
TRDIORC1
Bit Symbol
Address
0142h
0152h
Bit Name
TRDGRC control bits
IOC0
IOC1
IOC2
IOC3
RW
0 0 : Input capture to the TRDGRCi register
at the rising edge
0 1 : Input capture to the TRDGRCi register
at the falling edge
1 0 : Input capture to the TRDGRCi register
at both edges
1 1 : Do not set.
RW
RW
Set to 1 (input capture) in the input capture
function.
RW
TRDGRC register function
select bit
Set to 1 (general register or buffer register) in
the input capture function.
RW
TRDGRD control bits
b5 b4
IOD1
IOD3
Function
b1 b0
TRDGRC mode select bit(1)
IOD0
IOD2
After Reset
10001000b
10001000b
0 0 : Input capture to the TRDGRDi register
at the rising edge
0 1 : Input capture to the TRDGRDi register
at the falling edge
1 0 : Input capture to the TRDGRDi register
at both edges
1 1 : Do not set.
RW
RW
TRDGRD mode select bit(2)
Set to 1 (input capture) in the input capture
function.
RW
TRDGRD register function
select bit
Set to 1 (general register or buffer register) in
the input capture function.
RW
NOTES:
1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
Figure 14.76
Registers TRDIORC0 to TRDIORC1 in Input Capture Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 257 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
Address
0143h
0153h
Bit Name
Input capture/compare match
flag A
IMFA
After Reset
11100000b
11000000b
Function
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
TRDSR0 register:
fOCO128 signal edge w hen the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128 signal)
TRDIOA0 pin input edge w hen the IOA3 bit in the
TRDIORA0 register is set to 1 (TRDIOA0 input)(3)
RW
RW
TRDSR1 register:
Input edge of TRDIOA1 pin(3)
IMFB
IMFC
IMFD
Input capture/compare match
flag B
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIOBi pin(3)
RW
Input capture/compare match
flag C
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIOCi pin(4)
RW
Input capture/compare match
flag D
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
Input edge of TRDIODi pin(4)
RW
Overflow flag
[Source for setting this bit to 0]
Write 0 after read(2)
[Source for setting this bit to 1]
When the TRDi register overflow s
RW
OVF
UDF
—
(b7-b6)
Underflow flag(1)
This bit is disabled in the input capture function.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even
if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
3. Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.
4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register
Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
Figure 14.77
Registers TRDSR0 to TRDSR1 in Input Capture Function
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Page 258 of 580
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
After Reset
11100000b
11100000b
Bit Name
Input capture/compare match
interrupt enable bit A
Function
0 : Disable interrupt (IMIA) by the IMFA bit
1 : Enable interrupt (IMIA) by the IMFA bit
IMIEB
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the IMFB bit
1 : Enable interrupt (IMIB) by the IMFB bit
RW
IMIEC
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the IMFC bit
1 : Enable interrupt (IMIC) by the IMFC bit
RW
IMIED
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the IMFD bit
1 : Enable interrupt (IMID) by the IMFD bit
RW
OVIE
Overflow /underflow interrupt
enable bit
0 : Disable interrupt (OVI) by the OVF bit
1 : Enable interrupt (OVI) by the OVF bit
RW
IMIEA
—
(b7-b5)
Figure 14.78
Address
0144h
0154h
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
—
Registers TRDIER0 to TRDIER1 in Input Capture Function
Timer RD Counter i (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD0
TRD1
Address
0147h-0146h
0157h-0156h
Function
Count the count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
NOTE:
1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.79
Registers TRD0 to TRD1 in Input Capture Function
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REJ09B0324-0200
Page 259 of 580
After Reset
0000h
0000h
Setting Range
0000h to FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
Refer to Table 14.39 TRDGRji Register Functions in Input Capture Function
RW
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.80
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Input Capture Function
The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR,
TRDPOCR0, and TRDPOCR1.
Table 14.39
TRDGRji Register Functions in Input Capture Function
Register
TRDGRAi
Setting
−
TRDGRBi
TRDGRCi
BFCi = 0
TRDGRDi
BFDi = 0
TRDGRCi
BFCi = 1
TRDGRDi
BFDi = 1
Register Function
General register
The value in the TRDi register can be read at input
capture.
General register
The value in the TRDi register can be read at input
capture.
Buffer register
The value in the TRDi register can be read at input
capture. (Refer to 14.4.2 Buffer Operation)
Input-Capture Input Pin
TRDIOAi
TRDIOBi
TRDIOCi
TRDIODi
TRDIOAi
TRDIOBi
i = 0 or 1, j = either A, B, C, or D
BFCi, BFDi: Bits in TRDMR register
Set the pulse width of the input capture signal applied to the TRDIOji pin to 3 cycles or more of the timer RD
operation clock (refer to Table 14.26 Timer RD Operation Clocks) for no digital filter (the DFj bit in the
TRDDFi register set to 0).
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R8C/2A Group, R8C/2B Group
14. Timers
TRDCLK input
count source
Count value
in TRDi register
FFFFh
0009h
0006h
0000h
TSTARTi bit in
TRDSTR register
1
0
65536
TRDIOAi input
TRDGRAi register
0006h
Transfer
TRDGRCi register
0009h
Transfer
0006h
IMFA bit in
TRDSRi register
1
OVF bit in
TRDSRi register
1
0
Set to 0 by a program
0
i = 0 or 1
The above applies under the following conditions:
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (the TRDi register set to 0000h by TRDGRAi register input capture).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input for the count source).
Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge for the count source).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input).
The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register).
Figure 14.81
Operating Example of Input Capture Function
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R8C/2A Group, R8C/2B Group
14.4.5.1
14. Timers
Digital Filter
The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is determined.
Select the digital filter function and sampling clock by the TRDDFi register.
TCK2 to TCK0
fOCO40M
TRDCLK
f32
f8
f4
f2
DFCK1 to DFCK0
= 110b
= 00b
f32
= 101b
= 01b
f8
= 100b
= 10b
f1
= 011b
= 11b
Count source
= 010b
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
= 001b
= 000b
f1
Sampling clock
DFj
C
TRDIOji input signal
D
C
Q
D
Latch
C
Q
D
Latch
1
C
Q
Latch
D
Q
Latch
Match
detection
circuit
Edge detection
circuit
0
Timer RD operation clock
f1, fOCO40M)
C
D
Q
Latch
Clock period selected by
bits TCK2 to TCK0 or
bits DFCK1 to DFCK0
Sampling clock
TRDIOji input signal
Recognition of the
signal change with
3-time match
Input signal through
digital filtering
Signal transmission delayed
up to 5-sampling clock
Transmission cannot be
performed without 3-time match
because the input signal is
assumed to be noise.
i = 0 or 1, j = either A, B, C, or D
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
Figure 14.82
Block Diagram of Digital Filter
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R8C/2A Group, R8C/2B Group
14.4.6
14. Timers
Output Compare Function
This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D)
register and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is output
from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji
register, the output compare function, or any other mode or function, can be selected for each individual pin.
Figure 14.83 shows a Block Diagram of Output Compare Function, Table 14.40 lists the Output Compare
Function Specifications. Figures 14.84 to 14.96 list the registers associated with output compare function, and
Figure 14.97 shows an Operating Example of Output Compare Function.
Channel 0
TRD0
Compare match signal
Output
control
TRDIOA0
IOC3 = 0 in
TRDIORC0 register
Comparator
TRDGRA0
Comparator
TRDGRC0
Comparator
TRDGRB0
Comparator
TRDGRD0
Compare match signal
Output
control
TRDIOC0
Output
control
TRDIOB0
IOC3 = 1
Compare match signal
IOD3 = 0 in
TRDIORD0 register
Compare match signal
Output
control
TRDIOD0
IOD3 = 1
Channel 1
TRD1
Compare match signal
Output
control
TRDIOA1
IOC3 = 0 in
TRDIORC1 register
Comparator
TRDGRA1
Comparator
TRDGRC1
Comparator
TRDGRB1
Comparator
TRDGRD1
Compare match signal
Output
control
TRDIOC1
IOC3 = 1
Compare match signal
Output
control
TRDIOB1
IOD3 = 0 in
TRDIORD1 register
Compare match signal
Output
control
TRDIOD1
Figure 14.83
IOD3 = 1
Block Diagram of Output Compare Function
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R8C/2A Group, R8C/2B Group
Table 14.40
14. Timers
Output Compare Function Specifications
Item
Specification
Count sources
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Count operations
Increment
Count period
• When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running
operation)
1/fk × 65536 fk: Frequency of count source
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi
register to 0000h at the compare match in the TRDGRji register).
Frequency of count source x (n+1)
n: Setting value in the TRDGRji register
Waveform output timing
Compare match
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
compare match in the TRDGRAi register.
The output compare output pin holds level after output change by the compare
match.
Interrupt request generation
timing
• Compare match (content of the TRDi register matches content of the TRDGRji
register.)
• TRDi register overflows
TRDIOA0 pin function
Programmable I/O port, output-compare output, or TRDCLK (external clock) input
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
Programmable I/O port or output-compare output (Selectable by pin)
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
• When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate
independently).
Data can be written to the TRDi register.
• When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate
synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Select functions
• Output-compare output pin selected
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
• Output level at the compare match selected
“L” output, “H” output, or output level inversed
• Initial output level selected
Set the level at period from the count start to the compare match.
• Timing to set the TRDi register to 0000h
Overflow or compare match in the TRDGRAi register
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Output pin in registers TRDGRCi and TRDGRDi changed
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output Forced
Cutoff.)
• Timer RD can be used as the internal timer without output.
i = 0 or 1, j = either A, B, C, or D
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R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b2-b0)
When read, the content is 0.
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.84
MSTCR Register
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSTR
Bit Symbol
TSTART0
TSTART1
CSEL0
CSEL1
—
(b7-b4)
Address
0137h
Bit Name
TRD0 count start flag(4)
After Reset
11111100b
Function
RW
0 : Count stops (2)
1 : Count starts
RW
TRD1 count start flag(5)
0 : Count stops (3)
1 : Count starts
RW
TRD0 count operation
select bit
0 : Count stops at the compare match w ith the
TRDGRA0 register
1 : Count continues after the compare match
w ith the TRDGRA0 register
RW
TRD1 count operation
select bit
0 : Count stops at the compare match w ith the
TRDGRA1 register
1 : Count continues after the compare match
w ith the TRDGRA1 register
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
2. When the CSEL0 bit is
3. When the CSEL1 bit is
4. When the CSEL0 bit is
stops).
5. When the CSEL1 bit is
stops).
set to 1, w rite 0 to the TSTART0 bit.
set to 1, w rite 0 to the TSTART1 bit.
set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDMR
Bit Symbol
Address
0138h
Bit Name
Timer RD synchronous bit
SYNC
—
(b3-b1)
After Reset
00001110b
Function
0 : Registers TRD0 and TRD1
operate independently
1 : Registers TRD0 and TRD1
operate synchronously
—
BFC0
TRDGRC0 register function select 0 : General register
1 : Buffer register of TRDGRA0 register
bit(1)
RW
BFD0
TRDGRD0 register function select 0 : General register
bit(1)
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function select 0 : General register
bit(1)
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function select 0 : General register
bit(1)
1 : Buffer register of TRDGRB1 register
RW
Registers TRDSTR and TRDMR in Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTE:
1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1)
register, set the BFji bit in the TRDMR register to 0.
Figure 14.85
RW
Page 266 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
0 0 0
Symbol
TRDPMR
Bit Symbol
PWMB0
PWMC0
PWMD0
—
(b3)
PWMB1
PWMC1
PWMD1
—
(b7)
Figure 14.86
Address
0139h
Bit Name
PWM mode of TRDIOB0 select bit
After Reset
10001000b
Function
Set to 0 (timer mode) in the output
compare function.
RW
PWM mode of TRDIOC0 select bit
Set to 0 (timer mode) in the output
compare function.
RW
PWM mode of TRDIOD0 select bit
Set to 0 (timer mode) in the output
compare function.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
PWM mode of TRDIOB1 select bit
Set to 0 (timer mode) in the output
compare function.
RW
PWM mode of TRDIOC1 select bit
Set to 0 (timer mode) in the output
compare function.
RW
PWM mode of TRDIOD1 select bit
Set to 0 (timer mode) in the output
compare function.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
TRDPMR Register in Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Page 267 of 580
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits (1)
CMD1
After Reset
10000000b
Function
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in the output compare
function.
RW
OLS0
RW
OLS1
Counter-phase output level select bit This bit is disabled in the output compare
(in reset synchronous PWM mode or function.
complementary PWM mode)
RW
ADTRG
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in the output compare
function.
RW
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in the output compare
function.
RW
External clock input select bit
0 : External clock input disabled
1 : External clock input enabled
RW
PWM3 mode select bit(2)
Set this bit to 1 (other than PWM3 mode) in
the output compare function.
RW
PWM3
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
TRDFCR Register in Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Normal-phase output level select bit This bit is disabled in the output compare
(in reset synchronous PWM mode or function.
complementary PWM mode)
STCLK
Figure 14.87
RW
Page 268 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDOER1
Bit Symbol
Address
013Bh
Bit Name
TRDIOA0 output disable bit
EA0
TRDIOB0 output disable bit
EB0
TRDIOC0 output disable bit
EC0
TRDIOD0 output disable bit
ED0
TRDIOA1 output disable bit
EA1
TRDIOB1 output disable bit
EB1
TRDIOC1 output disable bit
EC1
TRDIOD1 output disable bit
ED1
After Reset
FFh
Function
0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
RW
RW
0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
013Ch
TRDOER2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b6-b0)
When read, the content is 1.
_____
PTO
INT0 of pulse output forced
cutoff signal input enabled
bit(1)
After Reset
01111111b
Function
0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
Figure 14.88
Registers TRDOER1 to TRDOER2 in Output Compare Function
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REJ09B0324-0200
Page 269 of 580
RW
—
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Control Register(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
TRDOCR
Bit Symbol
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
Address
013Dh
Bit Name
TRDIOA0 output level select bit
After Reset
00h
Function
0 : Initial output “L”
1 : Initial output “H”
RW
TRDIOB0 output level select bit
0 : Initial output “L”
1 : Initial output “H”
RW
TRDIOC0 initial output level select bit
0 : “L”
1 : “H”
RW
TRDIOD0 initial output level select bit
TRDIOA1 initial output level select bit
TRDIOB1 initial output level select bit
TRDIOC1 initial output level select bit
TRDIOD1 initial output level select bit
RW
RW
RW
RW
RW
RW
NOTES:
1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stopped).
2. If the pin function is set for w aveform output (refer to Tables 14.27 to 14.34), the initial output level is output w hen
the TRDOCR register is set.
Figure 14.89
TRDOCR Register in Output Compare Function
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REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDCR0
TRDCR1
Bit Symbol
Address
0140h
0150h
Bit Name
Count source select bits
Function
TCK1
TCK2
External clock edge select
bits (2)
CKEG1
TRDi counter clear select
bits
CCLR0
CCLR1
CCLR2
RW
b2 b1 b0
0
0
0
0
1
1
1
1
TCK0
CKEG0
After Reset
00h
00h
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRDCLK input(1)
0 : fOCO40M
1 : Do not set.
RW
RW
RW
b4 b3
0
0
1
1
0 : Count at the rising edge
1 : Count at the falling edge
0 : Count at both edges
1 : Do not set.
RW
RW
b7 b6 b5
0 0 0 : Disable clear (free-running operation)
0 0 1 : Clear by compare match w ith the
TRDGRAi register
0 1 0 : Clear by compare match w ith the
TRDGRBi register
0 1 1 : Synchronous clear (clear
simultaneously w ith other channel
counter)(3)
1 0 0 : Do not set.
1 0 1 : Clear by compare match w ith the
TRDGRCi register
1 1 0 : Clear by compare match w ith the
TRDGRDi register
1 1 1 : Do not set.
RW
RW
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate
synchronously).
Figure 14.90
Registers TRDCR0 to TRDCR1 in Output Compare Function
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
TRDIORA0
TRDIORA1
Bit Symbol
Address
0141h
0151h
Bit Name
TRDGRA control bits
IOA0
IOA1
After Reset
10001000b
10001000b
Function
RW
b1 b0
0 0 : Disable pin output by the compare match
(TRDIOAi pin functions as programmable
I/O port)
0 1 : “L” output at compare match w ith
the TRDGRAi register
1 0 : “H” output at compare match w ith
the TRDGRAi register
1 1 : Toggle output by compare match
w ith the TRDGRAi register
RW
RW
IOA2
TRDGRA mode select bit(1) Set to 0 (output compare) in the output compare
function.
RW
IOA3
Input capture input sw itch
bit
Set to 1.
RW
TRDGRB control bits
b5 b4
IOB0
IOB1
IOB2
—
(b7)
TRDGRB mode select bit(2)
0 0 : Disable pin output by the compare match
(TRDIOBi pin functions as programmable
I/O port)
0 1 : “L” output at compare match
w ith the TRDGRBi register
1 0 : “H” output at compare match
w ith the TRDGRBi
1 1 : Toggle output by compare match
w ith the TRDGRBi register
Set to 0 (output compare) in the output compare
function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
RW
—
NOTES:
1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
Figure 14.91
Registers TRDIORA0 to TRDIORA1 in Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD I/O Control Register Ci (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
TRDIORC0
TRDIORC1
Bit Symbol
Address
0142h
0152h
Bit Name
TRDGRC control bits
IOC0
IOC1
IOC2
Function
RW
b1 b0
0 0 : Disable pin output by compare match
0 1 : “L” output at compare match w ith
the TRDGRCi register
1 0 : “H” output at compare match w ith
the TRDGRCi register
1 1 : Toggle output by compare match
w ith the TRDGRCi register
RW
RW
TRDGRC mode select bit(1)
Set to 0 (output compare) in the output compare
function.
RW
TRDGRC register function
select bit
0 : TRDIOA output register
(Refer to 14.4.6.1 Changing Output Pins in
Registers TRDGRCi (i = 0 or 1) and
TRDGRDi.)
1 : General register or buffer register
RW
IOC3
TRDGRD control bits
IOD0
IOD1
IOD2
After Reset
10001000b
10001000b
b5 b4
0 0 : Disable pin output by compare match
0 1 : “L” output at compare match w ith
the TRDGRDi register
1 0 : “H” output at compare match w ith
the TRDGRDi register
1 1 : Toggle output by compare match
w ith the TRDGRDi register
RW
RW
TRDGRD mode select bit(2)
Set to 0 (output compare) in the output compare
function.
RW
TRDGRD register function
select bit
0 : TRDIOB output register
(Refer to 14.4.6.1 Changing Output Pins in
Registers TRDGRCi (i = 0 or 1) and
TRDGRDi.)
1 : General register or buffer register
RW
IOD3
NOTES:
1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in
the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi
register.
2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in
the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi
register.
Figure 14.92
Registers TRDIORC0 to TRDIORC1 in Output Compare Function
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14. Timers
Timer RD Status Register i (i=0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
IMFA
Address
0143h
0153h
After Reset
11100000b
11000000b
Bit Name
Function
Input capture/compare match [Source for setting this bit to 0]
flag A
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
IMFB
RW
IMFC
Input capture/compare match [Source for setting this bit to 0]
flag C
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register (3).
RW
IMFD
Input capture/compare match [Source for setting this bit to 0]
flag D
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register (3).
RW
OVF
UDF
—
(b7-b6)
Underflow flag(1)
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
This bit is disabled in the output compare function.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Registers TRDSR0 to TRDSR1 in Output Compare Function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Input capture/compare match [Source for setting this bit to 0]
flag B
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
Overflow flag
Figure 14.93
RW
Page 274 of 580
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
—
(b7-b5)
Figure 14.94
Address
0144h
0154h
After Reset
11100000b
11100000b
Bit Name
Input capture/compare match
interrupt enable bit A
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
Registers TRDIER0 to TRDIER1 in Output Compare Function
Rev.2.00 Nov 26, 2007
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RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Counter i (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
0147h-0146h
0157h-0156h
TRD0
TRD1
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
After Reset
0000h
0000h
Setting Range
0000h to FFFFh
RW
RW
NOTE:
1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.95
Registers TRD0 to TRD1 in Output Compare Function
Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
Refer to Table 14.41 TRDGRji Register Function in Output Com pare Function
RW
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.96
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Output Compare Function
The following registers are disabled in the output compare function: TRDDF0, TRDDF1, TRDPOCR0, and
TRDPOCR1.
Table 14.41
Register
TRDGRAi
TRDGRBi
TRDGRCi
TRDGRDi
TRDGRCi
TRDGRDi
TRDGRCi
TRDGRDi
TRDGRji Register Function in Output Compare Function
Setting
BFji
IOj3
−
−
0
1
1
1
0
0
Output-Compare
Output Pin
General register. Write the compare value.
TRDIOAi
TRDIOBi
General register. Write the compare value.
TRDIOCi
TRDIODi
Buffer register. Write the next compare value
TRDIOAi
(Refer to 14.4.2 Buffer Operation.)
TRDIOBi
TRDIOAi output control (Refer to 14.4.6.1 Changing TRDIOAi
Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDIOBi
TRDGRDi.)
Register Function
i = 0 or 1, j = either A, B, C, or D
BFji: Bit in TRDMR register
IOj3: Bit in TRDIORCi register
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
Value in TRDi register
m
n
p
Count
restarts
Count
stops
TSTARTi bit in
TRDSTR register
1
0
m+1
m+1
Output level
held
TRDIOAi output
Output inverted by compare match
Initial output “L”
IMFA bit in
TRDSRi register
1
0
Set to 0 by a program
n+1
TRDIOBi output
“H” output by compare match
n+1
Initial output “L”
IMFB bit in
TRDSRi register
Output level
held
1
0
Set to 0 by a program
P+1
“L” output by compare match
TRDIOCi output
Output level
held
Initial output “H”
IMFC bit in
TRDSRi register
1
0
Set to 0 by a program
i = 0 or 1
M: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output “L” to compare match), the TOCi bit is set to 1 (initial output “H” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi “H” output at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi “L” output at TRDGRCi register compare match).
The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output).
Figure 14.97
Operating Example of Output Compare Function
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REJ09B0324-0200
Page 277 of 580
R8C/2A Group, R8C/2B Group
14.4.6.1
14. Timers
Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi
The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be
used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows:
• TRDIOAi output is controlled by the values in registers TRDGRAi and TRDGRCi.
• TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRDi.
Change output pins in registers TRDGRCi and TRDGRDi as follows:
• Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register.
• Set the BFji bit in the TRDMR register to 0 (general register).
• Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers
TRDGRDi and TRDGRBi.
Figure 14.99 shows an Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi
Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
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R8C/2A Group, R8C/2B Group
14. Timers
Channel 0
TRD0
Compare match signal
Output
control
TRDIOA0
IOC3 = 0 in
TRDIORC0 register
Comparator
TRDGRA0
Comparator
TRDGRC0
Comparator
TRDGRB0
Comparator
TRDGRD0
Compare match signal
Output
control
TRDIOC0
IOC3 = 1
Compare match signal
Output
control
TRDIOB0
IOD3 = 0 in
TRDIORD0 register
Compare match signal
Output
control
TRDIOD0
IOD3 = 1
Channel 1
TRD1
Compare match signal
Output
control
TRDIOA1
IOC3 = 0 in
TRDIORC1 register
Comparator
TRDGRA1
Comparator
TRDGRC1
Comparator
TRDGRB1
Comparator
TRDGRD1
Compare match signal
Output
control
TRDIOC1
IOC3 = 1
Compare match signal
Output
control
TRDIOB1
IOD3 = 0 in
TRDIORD1 register
Compare match signal
Output
control
TRDIOD1
Figure 14.98
IOD3 = 1
Changing Output Pins in Registers TRDGRCi and TRDGRDi
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
Value in TRDi register
FFFFh
m
n
p
q
0000h
m+1
n+1
m-n
p+1
q+1
p-q
Initial output “L”
TRDIOAi output
Output inverted by compare match
IMFA bit in
TRDSRi register
1
0
Set to 0 by a program
IMFC bit in
TRDSRi register
Set to 0 by a program
1
0
Initial output “L”
TRDIOBi output
Output inverted by compare match
IMFB bit in
TRDSRi register
1
IMFD bit in
TRDSRi register
1
0
Set to 0 by a program
Set to 0 by a program
0
m: Value set in TRDGRAi register
n: Value set in TRDGRCi register
p: Value set in TRDGRBi register
q: Value set in TRDGRDi register
i = 0 or 1
The above applies under the following conditions:
The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match).
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register).
Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs).
Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register).
Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output “L” to compare match).
Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match).
Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match).
Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match).
Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).
Figure 14.99
Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi
Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.4.7
14. Timers
PWM Mode
In PWM mode, a PWM waveform is output. Up to 3 PWM waveforms with the same period can be output by 1
channel. Also, up to 6 PWM waveforms with the same period can be output by synchronizing channels 0 and 1.
Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji
register, the PWM mode, or any other mode or function, can be selected for each individual pin. (However,
since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used
for other modes.)
Figure 14.100 shows a Block Diagram of PWM Mode, and Table 14.42 lists the PWM Mode Specifications.
Figures 14.101 to 14.111 show the registers associated with PWM mode, and Figures 14.112 and 14.113 show
the Operations of PWM Mode.
TRDi
Compare match signal
Comparator
TRDIOBi
TRDIOCi
TRDGRAi
Compare match signal
Output
control
TRDIODi
(Note 1)
Comparator
TRDGRBi
Comparator
TRDGRCi
Compare match signal
Compare match signal
(Note 2)
Comparator
TRDGRDi
i = 0 or 1
NOTES:
1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the
buffer register of the TRDGRAi register).
2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the
buffer register of the TRDGRBi register).
Figure 14.100 Block Diagram of PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
Table 14.42
14. Timers
PWM Mode Specifications
Item
Specification
Count sources
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
Count operations
Increment
PWM waveform
PWM period: 1/fk x (m+1)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
fk: Frequency of count source
m: Value set in the TRDGRAi (i = 0 or 1) register
n: Value set in the TRDGRji (j = B, C, or D) register
m+1
n+1
m-n
(When “L” is selected as the active level)
Count start condition
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
• When the CSELi bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRAi register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation
timing
• Compare match (The content of the TRDi register matches content of
the TRDGRji register.)
• TRDi register overflows
TRDIOA0 pin function
Programmable I/O port or TRDCLK (external clock) input
TRDIOA1 pin function
Programmable I/O port
TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or pulse output (selectable by pin)
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer
The count value can be read by reading the TRDi register.
Write to timer
The value can be written to the TRDi register.
Select functions
• 1 to 3 PWM output pins selected per 1 channel
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
• The active level selected by pin.
• Initial output level selected by pin.
• Synchronous operation (Refer to 14.4.3 Synchronous Operation.)
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output
Forced Cutoff.)
i = 0 or 1
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R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.101 MSTCR Register
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSTR
Bit Symbol
TSTART0
TSTART1
Address
0137h
Bit Name
TRD0 count start flag(4)
TRD1 count start flag(5)
After Reset
11111100b
Function
RW
0 : Count stops (2)
1 : Count starts
RW
0 : Count stops (3)
1 : Count starts
RW
CSEL0
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
RW
CSEL1
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDMR
Bit Symbol
Address
0138h
Bit Name
Timer RD synchronous bit
SYNC
After Reset
00001110b
Function
0 : Registers TRD0 and TRD1 operate
independently
1 : Registers TRD0 and TRD1 operate
synchronously
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
BFC0
TRDGRC0 register function
select bit
0 : General register
1 : Buffer register of TRDGRA0 register
RW
BFD0
TRDGRD0 register function
select bit
0 : General register
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function
select bit
0 : General register
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function
select bit
0 : General register
1 : Buffer register of TRDGRB1 register
RW
—
(b3-b1)
Figure 14.102 Registers TRDSTR and TRDMR in PWM Mode
Rev.2.00 Nov 26, 2007
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RW
Page 284 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDPMR
Bit Symbol
PWMB0
PWMC0
PWMD0
—
(b3)
PWMB1
PWMC1
PWMD1
—
(b7)
Address
0139h
Bit Name
PWM mode of TRDIOB0 select bit
RW
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRDIOC0 select bit
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRDIOD0 select bit
0 : Timer mode
1 : PWM mode
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
PWM mode of TRDIOB1 select bit
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRDIOC1 select bit
0 : Timer mode
1 : PWM mode
RW
PWM mode of TRDIOD1 select bit
0 : Timer mode
1 : PWM mode
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Figure 14.103 TRDPMR Register in PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
After Reset
10001000b
Function
Page 285 of 580
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits (1)
After Reset
10000000b
Function
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM mode.
CMD1
RW
RW
OLS0
Normal-phase output level select Bit This bit is disabled in PWM mode.
(in reset synchronous PWM mode or
complementary PWM mode)
RW
OLS1
Counter-phase output level select bit This bit is disabled in PWM mode.
(in reset synchronous PWM mode or
complementary PWM mode)
RW
ADTRG
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in PWM mode.
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in PWM mode.
External clock input select bit
0 : External clock input disabled
1 : External clock input enabled
RW
PWM3 mode select bit(2)
Set this bit to 1 (other than PWM3 mode) in
PWM mode.
RW
STCLK
PWM3
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.104 TRDFCR Register in PWM Mode
Rev.2.00 Nov 26, 2007
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RW
Page 286 of 580
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDOER1
Bit Symbol
Address
013Bh
Bit Name
TRDIOA0 output disable bit
EA0
TRDIOB0 output disable bit
EB0
TRDIOC0 output disable bit
EC0
TRDIOD0 output disable bit
ED0
TRDIOA1 output disable bit
EA1
TRDIOB1 output disable bit
EB1
TRDIOC1 output disable bit
EC1
TRDIOD1 output disable bit
ED1
After Reset
FFh
Function
0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
RW
RW
0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
013Ch
TRDOER2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b6-b0)
When read, the content is 1.
After Reset
01111111b
Function
RW
—
_____
PTO
INT0 of pulse output forced
0 : Pulse output forced cutoff input disabled
cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
Figure 14.105 Registers TRDOER1 to TRDOER2 in PWM Mode
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RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
TRDOCR
Bit Symbol
TOA0
TOB0
TOC0
TOD0
TOA1
TOB1
TOC1
TOD1
Address
013Dh
Bit Name
TRDIOA0 output level select bit
After Reset
00h
Function
Set this bit to 0 (enable output) in
PWM mode.
RW
TRDIOB0 output level select bit(2)
TRDIOC0 initial output level select bit(2)
TRDIOD0 initial output level select bit(2)
TRDIOA1 initial output level select bit
0 : Initial output is inactive
level
1 : Initial output is active level
RW
RW
RW
Set this bit to 0 (enable output) in
PWM mode.
RW
TRDIOB1 initial output level select bit(2)
TRDIOC1 initial output level select bit(2)
TRDIOD1 initial output level select bit(2)
0 : Inactive level
1 : Active level
RW
RW
RW
RW
NOTES:
1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count
stops).
2. If the pin function is set for w aveform output (refer to Tables 14.28 to 14.30 and Tables 14.32 to 14.34), the initial
output level is output w hen the TRDOCR register is set.
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
TRDCR0
TRDCR1
Bit Symbol
Address
0140h
0150h
Bit Name
Count source select bits
Function
TCK1
TCK2
External clock edge select bits (2)
CKEG0
CKEG1
TRDi counter clear select bits
RW
b2 b1 b0
0
0
0
0
1
1
1
1
TCK0
CCLR0
CCLR1
CCLR2
After Reset
00h
00h
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRDCLK input(1)
0 : fOCO40M
1 : Do not set.
RW
RW
RW
b4 b3
0
0
1
1
0 : Count at the rising edge
1 : Count at the falling edge
0 : Count at both edges
1 : Do not set.
RW
RW
Set to 001b (the TRDi register cleared at
RW
compare match w ith TRDGRAi register) in PWM RW
mode.
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
Figure 14.106 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Status Register i (i=0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
IMFA
Address
0143h
0153h
After Reset
11100000b
11000000b
Bit Name
Function
Input capture/compare match [Source for setting this bit to 0]
flag A
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
RW
IMFB
Input capture/compare match [Source for setting this bit to 0]
flag B
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
RW
IMFC
Input capture/compare match [Source for setting this bit to 0]
flag C
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register (3).
RW
IMFD
Input capture/compare match [Source for setting this bit to 0]
flag D
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register (3).
RW
Overflow flag
OVF
UDF
—
(b7-b6)
Underflow flag(1)
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
This bit is disabled in PWM mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.107 Registers TRDSR0 to TRDSR1 in PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Page 289 of 580
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
—
(b7-b5)
Address
0144h
0154h
After Reset
11100000b
11100000b
Bit Name
Input capture/compare match
interrupt enable bit A
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
Figure 14.108 Registers TRDIER0 to TRDIER1 in PWM Mode
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RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD PWM Mode Output Level Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDPOCR0
TRDPOCR1
Bit Symbol
POLB
POLC
POLD
—
(b7-b3)
Address
0145h
0155h
After Reset
11111000b
11111000b
Bit Name
PWM mode output level control bit
B
Function
0 : “L” active TRDIOBi output level is
selected
1 : “H” active TRDIOBi output level is
selected
PWM mode output level control bit
C
0 : “L” active TRDIOCi output level is
selected
1 : “H” active TRDIOCi output level is
selected
RW
PWM mode output level control bit
D
0 : “L” active TRDIODi output level is
selected
1 : “H” active TRDIODi output level is
selected
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
RW
—
Figure 14.109 Registers TRDPOCR0 to TRDPOCR1 in PWM Mode
Timer RD Counter i (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD0
TRD1
Address
0147h-0146h
0157h-0156h
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
NOTE:
1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.110 Registers TRD0 to TRD1 in PWM Mode
Rev.2.00 Nov 26, 2007
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Page 291 of 580
After Reset
0000h
0000h
Setting Range
0000h to FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
Refer to Table 14.43 TRDGRji Register Functions in PWM Mode.
RW
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.111 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM Mode
The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0,
TRDIORA1, and TRDIORC1.
Table 14.43
TRDGRji Register Functions in PWM Mode
Register
Setting
Register Function
PWM Output Pin
TRDGRAi
−
General register. Set the PWM period
TRDGRBi
−
General register. Set the changing point of PWM output TRDIOBi
TRDGRCi
BFCi = 0
General register. Set the changing point of PWM output TRDIOCi
TRDGRDi
BFDi = 0
TRDIODi
TRDGRCi
BFCi = 1
Buffer register. Set the next PWM period
(Refer to 14.4.2 Buffer Operation.)
TRDGRDi
BFDi = 1
Buffer register. Set the changing point of the next PWM TRDIOBi
output
(Refer to 14.4.2 Buffer Operation.)
i = 0 or 1
BFCi, BFDi: Bits in TRDMR register
Rev.2.00 Nov 26, 2007
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−
−
R8C/2A Group, R8C/2B Group
14. Timers
Count source
Value in TRDi register
m
n
p
q
m+1
n+1
m-n
Active level “H”
Initial output “L”
to compare match
TRDIOBi output
Inactive level “L”
p+1
TRDIOCi output
Initial output “H”
to compare match
m-p
Inactive level “H”
q+1
m-q
Active level “L”
TRDIODi output
Initial output “L”
to compare match
IMFA bit in
TRDSRi register
1
IMFB bit in
TRDSRi register
1
IMFC bit in
TRDSRi register
1
IMFD bit in
TRDSRi register
1
0
Set to 0 by a program
Set to 0 by a program
0
0
Set to 0 by a program
Set to 0 by a program
0
m: Value set in TRDGRAi register
n: Value set in TRDGRBi register
p: Value set in TRDGRCi register
q: Value set in TRDGRDi register
i = 0 or 1
The above applies under the following conditions:
Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers).
Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (enable TRDIOBi, TRDIOCi and TRDIODi pin outputs).
Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level).
The POLB bit in the TRDPOCRi register is set to 1 (active level “H”), bits POLC and POLD are set to 0 (active level “L”).
Figure 14.112 Operating Example of PWM Mode
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Value in TRDi register
p
m
q
n
0000h
TSTARTi bit in
TRDSTR register
1
Since no compare match in the TRDGRBi register is
generated, “L” is not applied to the TRDIOBi output
0
TRDIOBi output
Duty 0%
n
TRDGRBi register
p (p>m)
q
Rewrite by a program
IMFA bit in
TRDSRi register
1
IMFB bit in
TRDSRi register
1
0
Set to 0 by a program
Set to 0 by a program
0
Value in TRDi register
m
p
n
0000h
TSTARTi bit in
TRDSTR register
1
When compare matches with registers TRDGRAi and TRDGRBi are generated
simultaneously, the compare match with the TRDGRBi register has priority.
“L” is applied to the TRDIOBi output without any change.
0
Duty 100%
TRDIOBi output
“L” is applied to TRDIOBi output at compare match
with the TRDGRBi register with no change.
TRDGRBi register
n
m
p
Rewrite by a program
IMFA bit in
TRDSRi register
1
IMFB bit in
TRDSRi register
1
0
Set to 0 by a program
Set to 0 by a program
0
i = 0 or 1
m: Value set in TRDGRAi register
The above applies under the following conditions:
The EBi bit in the TRDOER1 register is set to 0 (enable TRDIOBi output).
The POLB bit in the TRDPOCRi register is set to 0 (active level “L”).
Figure 14.113 Operating Example of PWM Mode (Duty 0%, Duty 100%)
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.4.8
14. Timers
Reset Synchronous PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, sawtooth wave modulation, and no dead time).
Figure 14.114 shows a Block Diagram of Reset Synchronous PWM Mode, and Table 14.44 lists the Reset
Synchronous PWM Mode Specifications. Figures 14.115 to 14.123 show the registers associated with reset
synchronous PWM mode and Figure 14.124 shows an Operating Example of Reset Synchronous PWM Mode.
Refer to Figure 14.113 Operating Example of PWM Mode (Duty 0%, Duty 100%) for an operating
example of PWM Mode with duty 0% and duty 100%.
Buffer(1)
TRDGRC0
register
Waveform control
TRDGRA0
register
Period
TRDIOC0
Normal-phase
TRDGRD0
register
TRDGRB0
register
PWM1
TRDIOB0
Counter-phase
Normal-phase
TRDGRC1
register
TRDGRA1
register
PWM2
Counter-phase
TRDGRB1
register
PWM3
TRDIOA1
TRDIOC1
Normal-phase
TRDGRD1
register
TRDIOD0
Counter-phase
TRDIOB1
TRDIOD1
NOTE:
1.When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).
Figure 14.114 Block Diagram of Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 295 of 580
R8C/2A Group, R8C/2B Group
Table 14.44
14. Timers
Reset Synchronous PWM Mode Specifications
Item
Specification
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
The TRD0 register is incremented (the TRD1 register is not used).
PWM period
: 1/fk × (m+1)
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output),
Value set in the TRDGRA1 register (PWM2 output),
Value set in the TRDGRB1 register (PWM3 output)
Count sources
Count operations
PWM waveform
m+1
Normal-phase
m-n
Counter-phase
n+1
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Select functions
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at the compare match in the TRDGRA0 register.
The PWM output pin holds level after output change at compare
match.
• Compare match (the content of the TRD0 register matches content
of registers TRDGRj0, TRDGRA1, and TRDGRB1).
• The TRD0 register overflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every PWM period
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• The active level of normal-phase and counter-phase and initial
output level selected individually.
• Buffer operation (Refer to 14.4.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse
Output Forced Cutoff.)
j = either A, B, C, or D
Rev.2.00 Nov 26, 2007
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(When “L” is selected as the active level)
Page 296 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.115 MSTCR Register
Rev.2.00 Nov 26, 2007
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Page 297 of 580
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSTR
Bit Symbol
TSTART0
TSTART1
Address
0137h
Bit Name
TRD0 count start flag(4)
TRD1 count start flag(5)
After Reset
11111100b
Function
RW
0 : Count stops (2)
1 : Count starts
RW
0 : Count stops (3)
1 : Count starts
RW
CSEL0
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
RW
CSEL1
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRDMR
Bit Symbol
Address
0138h
Bit Name
Timer RD synchronous bit
SYNC
—
(b3-b1)
After Reset
00001110b
Function
Set this bit to 0 (registers TRD0 and TRD1
operate independently) in reset synchronous
PWM mode.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
BFC0
TRDGRC0 register function select 0 : General register
bit
1 : Buffer register of TRDGRA0 register
RW
BFD0
TRDGRD0 register function select 0 : General register
bit
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function select 0 : General register
bit
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function select 0 : General register
bit
1 : Buffer register of TRDGRB1 register
RW
Figure 14.116 Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Page 298 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits (1, 2)
After Reset
10000000b
Function
Set to 01b (reset synchronous PWM
mode) in reset synchronous PWM mode.
CMD1
OLS0
OLS1
RW
RW
Normal-phase output level select bit 0 : Initial output “H”
(in reset synchronous PWM mode or
Active level “L”
complementary PWM mode)
1 : Initial output “L”
Active level “H”
Counter-phase output level select bit 0 : Initial output “H”
(in reset synchronous PWM mode or
Active level “L”
complementary PWM mode)
1 : Initial output “L”
Active level “H”
RW
RW
ADTRG
A/D trigger enable bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mode.
RW
ADEG
A/D trigger edge select bit
(in complementary PWM mode)
This bit is disabled in reset synchronous
PWM mode.
RW
External clock input select bit
0 : External clock input disabled
1 : External clock input enabled
RW
PWM3 mode select bit(3)
This bit is disabled in reset synchronous
PWM mode.
RW
STCLK
PWM3
NOTES:
1. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or
complementary PWM mode in spite of the setting of the TRDPMR register.
2. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.117 TRDFCR Register in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Page 299 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
TRDOER1
Bit Symbol
Address
013Bh
Bit Name
TRDIOA0 output disable bit
EA0
TRDIOB0 output disable bit
EB0
TRDIOC0 output disable bit
EC0
TRDIOD0 output disable bit
ED0
TRDIOA1 output disable bit
EA1
TRDIOB1 output disable bit
EB1
TRDIOC1 output disable bit
EC1
TRDIOD1 output disable bit
ED1
After Reset
FFh
Function
Set this bit to 1 (the TRDIOA0 pin is
used as a programmable I/O port) in reset
synchronous PWM mode.
RW
RW
0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
013Ch
TRDOER2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b6-b0)
When read, the content is 1.
After Reset
01111111b
Function
RW
—
_____
PTO
INT0 of pulse output forced
0 : Pulse output forced cutoff input disabled
cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
Figure 14.118 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 300 of 580
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Control Register 0(3)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
TRDCR0
Bit Symbol
Address
0140h
Bit Name
Count source select bits
TCK1
TCK2
External clock edge select bits (2)
CKEG0
CKEG1
TRD0 counter clear select bits
RW
b2 b1b0
0
0
0
0
1
1
1
1
TCK0
CCLR0
CCLR1
CCLR2
After Reset
00h
Function
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRDCLK input(1)
0 : fOCO40M
1 : Do not set.
RW
RW
RW
b4 b3
0
0
1
1
0 : Count at the rising edge
1 : Count at the falling edge
0 : Count at both edges
1 : Do not set.
Set to 001b (TRD0 register cleared at compare
match w ith TRDGRA0 register) in reset
synchronous PWM mode.
RW
RW
RW
RW
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
3. The TRDCR1 register is not used in reset synchronous PWM mode.
Figure 14.119 TRDCR0 Register in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
IMFA
Address
0143h
0153h
After Reset
11100000b
11000000b
Bit Name
Function
Input capture/compare match [Source for setting this bit to 0]
flag A
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRAi register.
RW
IMFB
Input capture/compare match [Source for setting this bit to 0]
flag B
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRBi register.
RW
IMFC
Input capture/compare match [Source for setting this bit to 0]
flag C
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRCi register (3).
RW
IMFD
Input capture/compare match [Source for setting this bit to 0]
flag D
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register matches w ith
the value in the TRDGRDi register (3).
RW
Overflow flag
OVF
UDF
—
(b7-b6)
Underflow flag(1)
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
This bit is disabled in reset synchronous PWM
mode.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.120 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
Page 302 of 580
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
—
(b7-b5)
Address
0144h
0154h
After Reset
11100000b
11100000b
Bit Name
Input capture/compare match
interrupt enable bit A
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
RW
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
RW
Figure 14.121 Registers TRDIER0 to TRDIER1 in Reset Synchronous PWM Mode
Timer RD Counter 0(1, 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD0
Address
0147h-0146h
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
NOTES:
1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
2. The TRD1 register is not used in reset synchronous PWM mode.
Figure 14.122 TRD0 Registrar in Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 303 of 580
After Reset
0000h
Setting Range
0000h to FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
RW
Refer to Table 14.45 TRDGRji Register Functions in Reset Synchronous PWM Mode.
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.123 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Reset Synchronous PWM Mode
The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Table 14.45
TRDGRji Register Functions in Reset Synchronous PWM Mode
Register
Setting
Register Function
PWM Output Pin
TRDGRA0
−
General register. Set the PWM period.
(Output inverted every PWM
period and TRDIOC0 pin)
TRDGRB0
−
General register. Set the changing point of
PWM1 output.
TRDIOB0
TRDIOD0
TRDGRC0
BFC0 = 0
−
TRDGRD0
BFD0 = 0
(These registers are not used in reset
synchronous PWM mode.)
TRDGRA1
−
General register. Set the changing point of
PWM2 output.
TRDIOA1
TRDIOC1
TRDGRB1
−
General register. Set the changing point of
PWM3 output.
TRDIOB1
TRDIOD1
TRDGRC1
BFC1 = 0
−
TRDGRD1
BFD1 = 0
(These points are not used in reset
synchronous PWM mode.)
TRDGRC0
BFC0 = 1
Buffer register. Set the next PWM period.
(Refer to 14.4.2 Buffer Operation.)
(Output inversed every PWM
period and TRDIOC0 pin)
TRDGRD0
BFD0 = 1
Buffer register. Set the changing point of
the next PWM1 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOB0
TRDIOD0
TRDGRC1
BFC1 = 1
Buffer register. Set the changing point of
the next PWM2 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOA1
TRDIOC1
TRDGRD1
BFD1 = 1
Buffer register. Set the changing point of
the next PWM3 output.
(Refer to 14.4.2 Buffer Operation.)
TRDIOB1
TRDIOD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14. Timers
Count source
Value in TRD0 register
m
n
p
q
0000h
TSTARTi bit in
TRDSTR register
1
0
m+1
m-n
TRDIOB0 output
n+1
TRDIOD0 output
m-p
TRDIOA1 output
p+1
TRDIOC1 output
m-q
TRDIOB1 output
Initial output “H”
q+1
Active level “L”
TRDIOD1 output
Active level “L”
TRDIOC0 output
Initial output “H”
IMFA bit in
TRDSR0 register
1
IMFB bit in
TRDSR0 register
1
IMFA bit in
TRDSR1 register
1
IMFB bit in
TRDSR1 register
1
0
Set to 0 by a program
Set to 0 by a program
0
0
Set to 0 by a program
Set to 0 by a program
0
Transfer from the buffer register to the
general register during buffer operation
Transfer from the buffer register to the
general register during buffer operation
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRDGRA1 register
q: Value set in TRDGRB1 register
i = 0 or 1
The above applies under the following conditions:
Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level “H”, active level “L”).
Figure 14.124 Operating Example of Reset Synchronous PWM Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
14.4.9
14. Timers
Complementary PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period
(three-phase, triangular wave modulation, and with dead time).
Figure 14.125 shows a Block Diagram of Complementary PWM Mode, and Table 14.46 lists the
Complementary PWM Mode Specifications. Figures 14.126 to 14.135 show the Registers Associated with
Complementary PWM Mode, Figure 14.136 shows Output Model of Complementary PWM Mode and Figure
14.137 shows Operating Example of Complementary PWM Mode.
Buffer
Waveform control
TRDGRA0
register
Period
TRDGRB0
register
PWM1
TRDIOC0
Normal-phase
TRDGRD0
register
TRDGRC1
register
Counter-phase
Normal-phase
TRDGRA1
register
PWM2
Counter-phase
Normal-phase
TRDGRD1
register
TRDGRB1
register
PWM3
Figure 14.125 Block Diagram of Complementary PWM Mode
Rev.2.00 Nov 26, 2007
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Page 306 of 580
Counter-phase
TRDIOB0
TRDIOD0
TRDIOA1
TRDIOC1
TRDIOB1
TRDIOD1
R8C/2A Group, R8C/2B Group
Table 14.46
14. Timers
Complementary PWM Mode Specifications
Item
Count sources
Specification
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Increment or decrement
Registers TRD0 and TRD1 are decremented with the compare match in registers
TRD0 and TRDGRA0 during increment operation. The TRD1 register value is
changed from 0000h to FFFFh during decrement operation, and registers TRD0 and
TRD1 are incremented.
Count operations
PWM operations
PWM period: 1/fk × (m+2-p) × 2(1)
Dead time: p
Active level width of normal-phase: 1/fk × (m-n-p+1) × 2
Active level width of counter-phase: 1/fk × (n+1-p) × 2
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
p: Value set in the TRD0 register
m+2-p
n+1
Normal-phase
Counter-phase
n+1-p
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Select functions
m-p-n+1
(When “L” is selected as the active level)
1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
(The PWM output pin holds output level before the count stops.)
• Compare match (The content of the TRDi register matches content of the TRDGRji
register.)
• The TRD1 register underflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every 1/2 period of PWM
Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse Output Forced
Cutoff.)
• The active level of normal-phase and counter-phase and initial output level
selected individually
• Transfer timing from the buffer register selected
• A/D trigger generated
i = 0 or 1, j = either A, B, C, or D
NOTE:
1. After a count starts, the PWM period is fixed.
Rev.2.00 Nov 26, 2007
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p
Page 307 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.126 MSTCR Register
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSTR
Bit Symbol
TSTART0
TSTART1
Address
0137h
Bit Name
TRD0 count start flag(4)
TRD1 count start flag(5)
After Reset
11111100b
Function
RW
0 : Count stops (3)
1 : Count starts
RW
CSEL0
TRD0 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
RW
CSEL1
TRD1 count operation select bit 0 : Count stops at the compare match w ith
the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
NOTES:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Figure 14.127 TRDSTR Register in Complementary PWM Mode
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RW
0 : Count stops (2)
1 : Count starts
Page 309 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
TRDMR
Bit Symbol
Address
0138h
Bit Name
Timer RD synchronous bit
SYNC
—
(b3-b1)
After Reset
00001110b
Function
Set this bit to 0 (registers TRD0 and TRD1
operate independently) in complementary
PWM mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
—
BFC0
TRDGRC0 register function select bit Set this bit to 0 (general register) in
complementary PWM mode.
RW
BFD0
TRDGRD0 register function select bit 0 : General register
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function select bit 0 : General register
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function select bit 0 : General register
1 : Buffer register of TRDGRB1 register
RW
Figure 14.128 TRDMR Register in Complementary PWM Mode
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RW
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14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDFCR
Bit Symbol
Address
013Ah
Bit Name
Combination mode select bits (1,2)
CMD0
CMD1
OLS0
OLS1
ADTRG
PWM3
RW
b1 b0
1 0 : Complementary PWM mode
(transfer from the
buffer register to the general
register at the underflow in
the TRD1 register)
1 1 : Complementary PWM mode
(transfer from the
buffer register to the general
register at the compare match w ith
registers TRD0 and TRDGRA0.)
Other than above : Do not set.
Normal-phase output level select bit 0 : Initial output “H”
(in reset synchronous PWM mode or
Active level “L”
complementary PWM mode)
1 : Initial output “L”
Active level “H”
Counter-phase output level select bit 0 : Initial output “H”
(in reset synchronous PWM mode or
Active level “L”
complementary PWM mode)
1 : Initial output “L”
Active level “H”
RW
RW
RW
RW
A/D trigger enable bit
(in complementary PWM mode)
0 : Disable A/D trigger
1 : Enable A/D trigger (3)
A/D trigger edge select bit
(in complementary PWM mode)
0 : A/D trigger is generated at
compare match betw een registers
TRD0 and TRDGRA0
1 : A/D trigger is generated at underflow
in the TRD1 register
RW
External clock input select bit
0 : External clock input disabled
1 : External clock input enabled
RW
PWM3 mode select bit(4)
This bit is disabled in complementary PWM
mode.
RW
ADEG
STCLK
After Reset
10000000b
Function
RW
NOTES:
1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of
the TRDPMR register.
2. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
3. Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD).
4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.129 TRDFCR Register in Complementary PWM Mode
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14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
TRDOER1
Bit Symbol
Address
013Bh
Bit Name
TRDIOA0 output disable bit
EA0
TRDIOB0 output disable bit
EB0
TRDIOC0 output disable bit
EC0
TRDIOD0 output disable bit
ED0
TRDIOA1 output disable bit
EA1
TRDIOB1 output disable bit
EB1
TRDIOC1 output disable bit
EC1
TRDIOD1 output disable bit
ED1
After Reset
FFh
Function
Set this bit to 1 (the TRDIOA0 pin is
used as a programmable I/O port) in
complementary PWM mode.
RW
RW
0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD0 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOA1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOB1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOC1 pin is
used as a programmable I/O port.)
RW
0 : Enable output
1 : Disable output (The TRDIOD1 pin is
used as a programmable I/O port.)
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
013Ch
TRDOER2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b6-b0)
When read, the content is 1.
After Reset
01111111b
Function
RW
—
_____
PTO
INT0 of pulse output forced
0 : Pulse output forced cutoff input disabled
cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
Figure 14.130 Registers TRDOER1 to TRDOER2 in Complementary PWM Mode
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RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
TRDCR0
TRDCR1
Bit Symbol
Address
0140h
0150h
Bit Name
Count source select bits (2)
Function
TCK1
TCK2
External clock edge select bits (2,3)
CKEG0
CKEG1
TRDi counter clear select bits
RW
b2 b1 b0
0
0
0
0
1
1
1
1
TCK0
CCLR0
After Reset
00h
00h
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : TRDCLK input(1)
0 : fOCO40M
1 : Do not set.
RW
RW
RW
b4 b3
0
0
1
1
0 : Count at the rising edge
1 : Count at the falling edge
0 : Count at both edges
1 : Do not set.
Set to 000b (disable clearing (free-running
operation)) in complementary PWM mode.
RW
RW
RW
CCLR1
RW
CCLR2
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values.
3. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
Figure 14.131 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode
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14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
Address
0143h
0153h
Bit Name
Input capture/compare match flag A
IMFA
Input capture/compare match flag B
IMFB
Input capture/compare match flag C
IMFC
Input capture/compare match flag D
IMFD
Overflow flag
OVF
Underflow flag(1)
UDF
—
(b7-b6)
After Reset
11100000b
11000000b
Function
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRAi
register.
RW
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRCi
register (3).
RW
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRDi
register (3).
RW
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the TRD1 register underflow s.
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.132 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode
Page 314 of 580
RW
[Source for setting this bit to 0]
Write 0 after read(2).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRBi
register.
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
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—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
—
(b7-b5)
Address
0144h
0154h
After Reset
11100000b
11100000b
Bit Name
Input capture/compare match
interrupt enable bit A
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit
OVF and UDF bits
1 : Enable interrupt (OVI) by the
OVF and UDF bits
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
Figure 14.133 Registers TRDIER0 to TRDIER1 in Complementary PWM Mode
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RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Counter 0(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD0
Address
0147h-0146h
Function
Set the dead time.
Count a count source. Count operation is incremented or decremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
After Reset
0000h
Setting Range
0000h to FFFFh
RW
RW
NOTE:
1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
Timer RD Counter 1(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD1
Address
0157h-0156h
Function
Select 0000h.
Count a count source. Count operation is incremented or decremented.
When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1.
After Reset
0000h
Setting Range
0000h to FFFFh
RW
RW
NOTE:
1. Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
Figure 14.134 Registers TRD0 to TRD1 in Complementary PWM Mode
Timer RD General Registers Ai, Bi, C1, and Di (i = 0 or 1)(1, 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRDGRA0
TRDGRB0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
Address
0149h-0148h
014Bh-014Ah
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
After Reset
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
Refer to Table 14.47 TRDGRji Register Functions in Com plem entary PWM Mode .
RW
RW
NOTES:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
2. The TRDGRC0 register is not used in complementary PWM mode.
Figure 14.135 Registers TRDGRAi, TRDGRBi, TRDGRC1, and TRDGRDi in Complementary PWM Mode
The following registers are disabled in the complementary PWM mode: TRDPMR, TRDOCR, TRDDF0,
TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
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Table 14.47
14. Timers
TRDGRji Register Functions in Complementary PWM Mode
Register
Setting
Register Function
PWM Output Pin
TRDGRA0
−
General register. Set the PWM period at initialization.
(Output inverted every half
Setting range: Setting value or above in TRD0 register
period of TRDIOC0 pin)
FFFFh - TRD0 register setting value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDGRB0
−
General register. Set the changing point of PWM1 output at
TRDIOB0
initialization.
TRDIOD0
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDGRA1
−
General register. Set the changing point of PWM2 output at
TRDIOA1
initialization.
TRDIOC1
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDGRB1
−
General register. Set the changing point of PWM3 output at
TRDIOB1
initialization.
TRDIOD1
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Do not write to this register when the TSTART0 and TSTART1
bits in the TRDSTR register are set to 1 (count starts).
TRDGRC0
−
This register is not used in complementary PWM mode.
−
TRDGRD0
BFD0 = 1
Buffer register. Set the changing point of next PWM1 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRB0 register
for initialization.
TRDIOB0
TRDIOD0
TRDGRC1
BFC1 = 1
Buffer register. Set the changing point of next PWM2 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRA1 register
for initialization.
TRDIOA1
TRDIOC1
TRDGRD1
BFD1 = 1
Buffer register. Set the changing point of next PWM3 output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Setting value or above in TRD0 register
TRDGRA0 register - TRD0 register setting
value or below
Set this register to the same value as the TRDGRB1 register
for initialization.
TRDIOB1
TRDIOD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count
operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1
to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
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14. Timers
Value in TRDi register
Value in TRD0 register
Value in TRDGRA0
register
Value in TRD1 register
Value in TRDGRB0
register
Value in TRDGRA1
register
Value in TRDGRB1
register
0000h
TRDIOB0 output
TRDIOD0 output
TRDIOA1 output
TRDIOC1 output
TRDIOB1 output
TRDIOD1 output
TRDIOC0 output
i = 0 or 1
Figure 14.136 Output Model of Complementary PWM Mode
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14. Timers
Count source
Value in TRDi register
m+1
m
Value in TRD0 register
n
Value in TRD1 register
p
0000h
Set to
FFFFh
Bits TSTART0 and TSTART1
in TRDSTR register
1
0
TRDIOB0 output
Initial output “H”
Active level “L”
TRDIOD0 output
TRDIOC0 output
Initial output “H”
m+2-p
m-p-n+1
n+1
n+1-p
p
p
(m-p-n+1) × 2
Width of normalphase active level
UDF bit in
TRDSR1 register
1
IMFA bit in
TRDSR0 register
1
Dead
time
n+1-p
(n+1-p) × 2
Width of counter-phase active level
0
Set to 0 by a program
0
TRDGRB0 register
n
n
Transfer (when bits CMD1 to CMD0 are set to 11b)
TRDGRD0 register
Transfer (when bits CMD1 to CMD0
are set to 10b)
n
Following data
Modify with a program
IMFB bit in
TRDSR0 register
1
Set to 0 by a program
Set to 0 by a program
0
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
The above applies under the following conditions:
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level “H”, active level “L” for normal-phase and counter-phase)
Figure 14.137 Operating Example of Complementary PWM Mode
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14.4.9.1
14. Timers
Transfer Timing from Buffer Register
• Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or
TRDGRB1 register.
When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the
TRD1 register underflows.
When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers
TRD0 and TRDGRA0.
14.4.9.2
A/D Trigger Generation
Compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion
start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register.
Also, set the ADCAP bit in the ADCON0 register to 1 (starts by timer RD).
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14. Timers
14.4.10 PWM3 Mode
In this mode, 2 PWM waveforms are output with the same period.
Figure 14.138 shows a Block Diagram of PWM3 Mode, and Table 14.48 lists the PWM3 Mode Specifications.
Figures 14.139 to 14.149 show the registers associated with PWM3 mode, and Figure 14.150 shows an Operating
Example of PWM3 Mode.
Buffer
Compare match signal
TRD0
TRDIOA0
Output
control
Comparator
TRDGRA0
TRDGRC0
Comparator
TRDGRA1
TRDGRC1
Comparator
TRDGRB0
TRDGRD0
Comparator
TRDGRB1
TRDGRD1
Compare match signal
Compare match signal
TRDIOB0
Output
control
Compare match signal
Figure 14.138 Block Diagram of PWM3 Mode
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Table 14.48
14. Timers
PWM3 Mode Specifications
Item
Specification
Count sources
f1, f2, f4, f8, f32, fOCO40M
Count operations
The TRD0 register is incremented (the TRD1 is not used).
PWM waveform
PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
m+1
n+1
p+1
q+1
TRDIOA0 output
m-n
TRDIOB0 output
p-q
(When “H” is selected as the active level)
Count start condition
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
Count stop conditions
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
stops at compare match with the TRDGRA0 register.
The PWM output pin holds level after output change by compare
match.
Interrupt request generation
timing
• Compare match (The content of the TRDi register matches content
of the TRDGRji register.)
• The TRD0 register overflows
TRDIOA0, TRDIOB0 pin
functions
PWM output
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 pin functions
Programmable I/O port
INT0 pin function
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
Read from timer
The count value can be read by reading the TRD0 register.
Write to timer
The value can be written to the TRD0 register.
Select functions
• Pulse output forced cutoff signal input (Refer to 14.4.4 Pulse
Output Forced Cutoff.)
• Buffer Operation (Refer to 14.4.2 Buffer Operation.)
• Active level selectable by pin
i = 0 or 1, j = either A, B, C, or D
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14. Timers
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTTRD
MSTTRC
—
(b7-b6)
RW
—
SSU, I C bus operation enable bit
0: Disable
1: Enable
RW
Timer RD operation enable bit
0: Disable
1: Enable
RW
Timer RC operation enable bit
0: Disable
1: Enable
RW
2
MSTIIC
After Reset
00h
Function
(1)
(2)
(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 14.139 MSTCR Register
Rev.2.00 Nov 26, 2007
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—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSTR
Bit Symbol
Address
0137h
Bit Name
TRD0 count start flag(4)
After Reset
11111100b
Function
RW
TRD1 count start flag(5)
0 : Count stops (3)
1 : Count starts
RW
TRD0 count operation select bit
CSEL0
0 : Count stops at the compare match
w ith the TRDGRA0 register
1 : Count continues after the compare
match w ith the TRDGRA0 register
RW
CSEL1
TRD1 count operation select bit
0 : Count stops at the compare match
[this bit is not used in PWM3 mode]
w ith the TRDGRA1 register
1 : Count continues after the compare
match w ith the TRDGRA1 register
RW
—
(b7-b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
TSTART0
TSTART1
NOTES:
1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.4.12.1
TRDSTR Register of Notes on Tim er RD.
2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit.
3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit.
4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
stops).
5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
stops).
Figure 14.140 TRDSTR Register in PWM3 Mode
Rev.2.00 Nov 26, 2007
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RW
0 : Count stops (2)
1 : Count starts
Page 324 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDMR
Bit Symbol
SYNC
Address
0138h
Bit Name
Timer RD synchronous bit
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
BFC0
TRDGRC0 register function select 0 : General register
bit
1 : Buffer register of TRDGRA0 register
RW
BFD0
TRDGRD0 register function select 0 : General register
bit
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function select 0 : General register
bit
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function select 0 : General register
bit
1 : Buffer register of TRDGRB1 register
RW
—
(b3-b1)
Figure 14.141 TRDMR Register in PWM3 Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
After Reset
00001110b
Function
Set this bit to 0 (TRD0 and TRD1 operate
independently) in PWM3 mode.
Page 325 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode select bits (1)
After Reset
10000000b
Function
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM3 mode.
CMD1
RW
RW
This bit is disabled in PWM3 mode.
OLS0
Normal-phase output level select bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
This bit is disabled in PWM3 mode.
OLS1
Counter-phase output level select bit
(enabled in reset synchronous PWM
mode or complementary PWM mode)
RW
RW
ADTRG
A/D trigger enable bit
This bit is disabled in PWM3 mode.
(enabled in complementary PWM mode)
RW
ADEG
A/D trigger edge select bit
This bit is disabled in PWM3 mode.
(enabled in complementary PWM mode)
RW
STCLK
PWM3
External clock input select bit
Set this bit to 0 (external clock input
disabled) in PWM3 mode.
RW
PWM3 mode select bit(2)
Set this bit to 0 (PWM3 mode) in PWM3
mode.
RW
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.142 TRDFCR Register in PWM3 Mode
Rev.2.00 Nov 26, 2007
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RW
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1 1
Symbol
TRDOER1
Bit Symbol
Address
013Bh
Bit Name
TRDIOA0 output disable bit
EA0
TRDIOB0 output disable bit
EB0
EC0
ED0
EA1
EB1
EC1
ED1
TRDIOC0 output disable bit
TRDIOD0 output disable bit
TRDIOA1 output disable bit
TRDIOB1 output disable bit
TRDIOC1 output disable bit
TRDIOD1 output disable bit
After Reset
FFh
Function
0 : Enable output
1 : Disable output (The TRDIOA0 pin is
used as a programmable I/O port.)
0 : Enable output
1 : Disable output (The TRDIOB0 pin is
used as a programmable I/O port.)
Set these bits to 1 (programmable I/O port)
in PWM3 mode.
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
013Ch
TRDOER2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b6-b0)
When read, the content is 1.
_____
PTO
INT0 of pulse output forced
cutoff signal input enabled
bit(1)
0 : Pulse output forced cutoff input disabled
1 : Pulse output forced cutoff input enabled
(All bits in the TRDOER1 register
are set to 1 (disable output) w hen “L” is
_____
applied to the INT0 pin.)
NOTE:
1. Refer to 14.4.4 Pulse Output Forced Cutoff.
Figure 14.143 Registers TRDOER1 to TRDOER2 in PWM3 Mode
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Page 327 of 580
After Reset
01111111b
Function
RW
—
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Output Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDOCR
Bit Symbol
Address
013Dh
Bit Name
TRDIOA0 output level select
bit(2)
TOA0
TRDIOB0 output level select
bit(2)
TOB0
After Reset
00h
Function
0 : Active level “H”,
initial output “L”,
output “H” at compare match w ith the
TRDGRA1register,
output “L” at compare match w ith the
TRDGRA0 register
1 : Active level “L”,
initial output “H”,
output “L” at compare match w ith the
TRDGRA1register,
output “H” at compare match w ith the
TRDGRA0 register
0 : Active level “H”,
initial output “L”,
output “H” at compare match w ith the
TRDGRB1register,
output “L” at compare match w ith the
TRDGRB0 register
1 : Active level “L”,
initial output “H”,
output “L” at compare match w ith the
TRDGRB1register,
output “H” at compare match w ith the
TRDGRB0 register
These bits are disabled in PWM3 mode.
RW
RW
RW
TOC0
TRDIOC0 initial output level
select bit
TOD0
TRDIOD0 initial output level
select bit
RW
TOA1
TRDIOA1 initial output level
select bit
RW
TOB1
TRDIOB1 initial output level
select bit
RW
TOC1
TRDIOC1 initial output level
select bit
RW
TOD1
TRDIOD1 initial output level
select bit
RW
RW
NOTES:
1. Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count
stops).
2. If the pin function is set for w aveform output (refer to Tables 14.27 and 14.28), the initial output level is output w hen
the TRDOCR register is set.
Figure 14.144 TRDOCR Register in PWM3 Mode
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14. Timers
Timer RD Control Register 0(2)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
TRDCR0
Bit Symbol
Address
0140h
Bit Name
Count source select bits
TCK1
TCK2
0
0
1
1
0
0
1
1
0 : f1
1 : f2
0 : f4
1 : f8
0 : f32
1 : Do not set.
0 : fOCO40M
1 : Do not set.
External clock edge select bits (1) These bits are disabled in PWM3 mode.
TRD0 counter clear select bits
RW
b2 b1b0
0
0
0
0
1
1
1
1
TCK0
CKEG0
CKEG1
CCLR0
CCLR1
CCLR2
After Reset
00h
Function
Set to 001b (the TRD0 register cleared at
compare match w ith TRDGRA0 register) in
PWM3 mode.
RW
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
2. The TRDCR1 register is not used in PWM3 mode.
Figure 14.145 TRDCR0 Register in PWM3 Mode
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14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDSR0
TRDSR1
Bit Symbol
Address
0143h
0153h
Bit Name
Input capture/compare match flag A
IMFA
Input capture/compare match flag B
IMFB
Input capture/compare match flag C
IMFC
Input capture/compare match flag D
IMFD
Overflow flag
OVF
UDF
—
(b7-b6)
Underflow flag(1)
After Reset
11100000b
11000000b
Function
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRAi
register.
RW
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRCi
register (2).
RW
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRDi
register (2).
RW
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the TRDi register overflow s.
RW
This bit is disabled in PWM3 mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.146 Registers TRDSR0 to TRDSR1 in PWM3 Mode
Page 330 of 580
RW
[Source for setting this bit to 0]
Write 0 after read(1).
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRBi
register.
NOTES:
1. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains
1 even if it is set to 1 from 0 after reading, and w riting 0).
• This bit remains unchanged if 1 is w ritten to it.
Rev.2.00 Nov 26, 2007
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RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRDIER0
TRDIER1
Bit Symbol
IMIEA
IMIEB
IMIEC
IMIED
OVIE
—
(b7-b5)
Address
0144h
0154h
Bit Name
Input capture/compare match
interrupt enable bit A
After Reset
11100000b
11100000b
Function
0 : Disable interrupt (IMIA) by the
IMFA bit
1 : Enable interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
RW
Input capture/compare match
interrupt enable bit C
0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
RW
Input capture/compare match
interrupt enable bit D
0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
RW
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the
bit
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
RW
RW
Figure 14.147 Registers TRDIER0 to TRDIER1 in PWM3 Mode
Timer RD Counter 0(1, 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRD0
Address
0147h-0146h
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
NOTES:
1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
2. The TRD1 register is not used in PWM3 mode.
Figure 14.148 TRD0 Register in PWM3 Mode
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After Reset
0000h
Setting Range
0000h to FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
Address
After Reset
0149h-0148h
014Bh-014Ah
014Dh-014Ch
014Fh-014Eh
0159h-0158h
015Bh-015Ah
015Dh-015Ch
015Fh-015Eh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
Function
Refer to Table 14.49 TRDGRji Register Functions in PWM3 m ode.
RW
RW
NOTE:
1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.149 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM3 Mode
The following registers are disabled in the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1,
TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
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R8C/2A Group, R8C/2B Group
Table 14.49
Register
14. Timers
TRDGRji Register Functions in PWM3 Mode
Setting
Register Function
TRDGRA0 −
General register. Set the PWM period.
Setting range: Value set in TRDGRA1 register or above
TRDGRA1
General register. Set the changing point (the active level
timing) of PWM output.
Setting range: Value set in TRDGRA0 register or below
TRDGRB0
General register. Set the changing point (the timing that
returns to initial output level) of PWM output.
Setting range: Value set in TRDGRB1 register or above
Value set in TRDGRA0 register or below
TRDGRB1
General register. Set the changing point (active level timing) of
PWM output.
Setting range: Value set in TRDGRB0 register or below
TRDGRC0 BFC0 = 0 (These registers is not used in PWM3 mode.)
PWM Output Pin
TRDIOA0
TRDIOB0
−
TRDGRC1 BFC1 = 0
TRDGRD0 BFD0 = 0
TRDGRD1 BFD1 = 0
TRDGRC0 BFC0 = 1 Buffer register. Set the next PWM period.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRC1 register or above
TRDIOA0
TRDGRC1 BFC1 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRC0 register or below
TRDGRD0 BFD0 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRD1 register or above,
setting value or below in TRDGRC0 register.
TRDIOB0
TRDGRD1 BFD1 = 1 Buffer register. Set the changing point of next PWM output.
(Refer to 14.4.2 Buffer Operation.)
Setting range: Value set in TRDGRD0 register or below
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as
buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the
TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1
may be set to 1 (buffer register).
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14. Timers
Count source
Value in TRD0 register
FFFFh
m
n
p
q
0000h
TSTART0 bit in
TRDSTR register
1
0
Count stop
CSEL0 bit in
TRDSTR register
Set to 0 by a program
1
0
m+1
n+1
m-n
p+1
q+1
p-q
Output “H” at compare
match with the
TRDGRA1 register
TRDIOA0 output
Output “L” at compare match
with the TRDGRA0 register
Initial output “L”
TRDIOB0 output
IMFA bit in
TRDSR0 register
1
0
Set to 0 by a program
IMFB bit in
TRDSR0 register
Set to 0 by a program
1
0
Set to 0 by a program
TRDGRA0 register
Set to 0 by a program
m
m
Transfer
TRDGRC0 register
m
Transfer
Following data
Transfer from buffer register to
general register
j = either A or B
Transfer from buffer register to
general register
m: Value set in TRDGRA0 register
n: Value set in TRDGRA1 register
p: Value set in TRDGRB0 register
q: Value set in TRDGRB1 register
The above applies under the following conditions:
• Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level “L”, output “H” by compare match with the
TRDGRj1 register, output “L” at compare match with the TRDGRj0 register).
• The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
Figure 14.150 Operating Example of PWM3 Mode
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14. Timers
14.4.11 Timer RD Interrupt
Timer RD generates the timer RD interrupt request based on 6 sources for each channel. The timer RD interrupt
has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each channel. Table 14.50 lists the
Registers Associated with Timer RD Interrupt, and Figure 14.151 shows a Block Diagram of Timer RD
Interrupt.
Table 14.50
Registers Associated with Timer RD Interrupt
Timer RD
Status Register
Timer RD
Interrupt Enable Register
Timer RD
Interrupt Control Register
Channel 0
TRDSR0
TRDIER0
TRD0IC
Channel 1
TRDSR1
TRDIER1
TRD1IC
Channel i
IMFA bit
IMIEA bit
Timer RD interrupt request
(IR bit in TRDiIC register)
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
UDF bit
OVF bit
OVIE bit
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 14.151 Block Diagram of Timer RD Interrupt
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a
combination of multiple interrupt request sources, the following differences from other maskable interrupts
apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable
interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the
TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore,
even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
maintained.
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is
determined by the TRDSRi register.
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set
each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions
of the registers used in the different modes (Figures 14.77, 14.93, 14.107, 14.120, 14.132, and 14.146).
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Refer to Registers TRDSR0 to TRDSR1 in each mode (Figures 14.77, 14.93, 14.107, 14.120, 14.132, and
14.146) for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (Figures 14.78,
14.94, 14.108, 14.121, 14.133, and 14.147) for the TRDIERi register.
Refer to 12.1.6 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector
Tables for the interrupt vectors.
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14. Timers
14.4.12 Notes on Timer RD
14.4.12.1 TRDSTR Register
• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
• Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
• To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be
stopped.
• Table 14.51 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji
(j = A, B, C, or D) pin with the timer RD output.
Table 14.51
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Count Stop
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count
stops.
When the CSELi bit is set to 0, the count stops at compare match of
registers TRDi and TRDGRAi.
TRDIOji Pin Output when Count Stops
Hold the output level immediately before the
count stops.
Hold the output level after output changes by
compare match.
14.4.12.2 TRDi Register (i = 0 or 1)
• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.W
#XXXXh, TRD0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.W
TRD0,DATA
;Reading
14.4.12.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.B
#XXh, TRDSR0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.B
TRDSR0,DATA
;Reading
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R8C/2A Group, R8C/2B Group
14. Timers
14.4.12.4 Count Source Switch
• Switch the count source after the count stops.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi register.
• When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO40M.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi register.
(3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
14.4.12.5 Input Capture Function
• Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.26 Timer RD Operation Clocks).
• The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
14.4.12.6 Reset Synchronous PWM Mode
• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
14.4.12.7 Complementary PWM Mode
• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
• Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
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14. Timers
• If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Count value in TRD0
register
Setting value in
TRDGRA0
register m
m+1
Set to 0 by a program
IMFA bit in
TRDSR0 register
No change
1
0
Transferred from
buffer register
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Figure 14.152 Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
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14. Timers
• The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
Count value in TRD0
register
1
0
FFFFh
Set to 0 by a program
UDF bit in
TRDSR0 register
1
OVF bit in
TRDSR0 register
1
0
No change
0
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 10b
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
Figure 14.153 Operation when TRD1 Register Underflows in Complementary PWM Mode
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14. Timers
• Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
n3
m+1
Count value in TRD0
register
n2
n1
Count value in TRD1
register
0000h
TRDGRD0 register
n2
Transfer
TRDGRB0 register
n1
Transfer with timing set by
bits CMD1 to CMD0
n2
n3
Transfer
Transfer
n2
n1
n3
Transfer at
underflow of TRD1
register because of
n3 > m
Transfer
n2
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
n1
Transfer with timing set by
bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Figure 14.154 Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
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14. Timers
When the value in the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the
timing selected by bits CMD1 to CMD0.
m+1
Count value in TRD0 register
n2
n1
Count value in TRD1 register
0000h
0000h
n1
TRDGRD0 register
Transfer
Transfer
TRDGRB0 register
n2
n1
n1
Transfer with timing
set by bits CMD1 to
CMD0
Transfer
0000h
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to
0000h.
Transfer
n1
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h ≤ n1 < m
Transfer with timing
set by bits CMD1 to
CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Figure 14.155 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
Mode
14.4.12.8 Count Source fOCO40M
• The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
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R8C/2A Group, R8C/2B Group
14.5
14. Timers
Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes:
• Real-time clock mode
Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of
the week.
• Output compare mode
Count a count source and detect compare matches.
The count source for timer RE is the operating clock that regulates the timing of timer operations.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.5.1
14. Timers
Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit
counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 14.156
shows a Block Diagram of Real-Time Clock Mode and Table 14.52 lists the Real-Time Clock Mode
Specifications. Figures 14.157 to 14.161 and 14.163 to 14.164 show the Registers Associated with Real-Time
Clock Mode. Table 14.53 lists the Interrupt Sources, Figure 14.162 shows the Definition of Time
Representation and Figure 14.165 shows the Operating Example in Real-Time Clock Mode.
1/2
fC4
(1/16)
(1/256)
4-bit counter
8-bit counter
(1s)
Overflow
Data bus
Overflow
TRESEC
register
Overflow
TREMIN
register
Overflow
TREHR
register
H12_H24
bit
TREWK
register
000
PM
bit
WKIE
DYIE
Timing
control
HRIE
INT
bit
MNIE
SEIE
BSY
bit
H12_H24, PM, INT: Bits in TRECR1 register
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.156 Block Diagram of Real-Time Clock Mode
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Timer RE
interrupt
R8C/2A Group, R8C/2B Group
Table 14.52
14. Timers
Real-Time Clock Mode Specifications
Item
Count source
Count operation
Count start condition
Count stop condition
Interrupt request generation
timing
TREO pin function
Read from timer
Write to timer
Select function
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Specification
fC4
Increment
1 (count starts) is written to TSTART bit in TRECR1 register
0 (count stops) is written to TSTART bit in TRECR1 register
Select any one of the following:
• Update second data
• Update minute data
• Update hour data
• Update day of week data
• When day of week data is set to 000b (Sunday)
Programmable I/O ports or output of f2, f4, or f8
When reading TRESEC, TREMIN, TREHR, or TREWK register, the count
value can be read. The values read from registers TRESEC, TREMIN,
and TREHR are represented by the BCD code.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), the value can be written to registers TRESEC, TREMIN, TREHR,
and TREWK. The values written to registers TRESEC, TREMIN, and
TREHR are represented by the BCD codes.
• 12-hour mode/24-hour mode switch function
Page 345 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Second Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
After Reset
00h
Bit Symbol
Bit Name
Function
SC00
SC01
SC02
SC03
SC10
SC11
SC12
Setting
Range
1st digit of second count bits
Count 0 to 9 every second. When the 0 to 9
digit moves up, 1 is added to the 2nd (BCD
digit of second.
code)
2nd digit of second count bits
When counting 0 to 5, 60 seconds
are counted.
Timer RE busy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
0 to 5
(BCD
code)
RW
RW
RW
RW
RW
RW
RW
RW
RO
Figure 14.157 TRESEC Register in Real-Time Clock Mode
Timer RE Minute Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
After Reset
00h
Bit Symbol
Bit Name
Function
MN00
MN01
MN02
MN03
MN10
MN11
MN12
1st digit of minute count bits
Count 0 to 9 every minute. When the 0 to 9
digit moves up, 1 is added to the 2nd (BCD
code)
digit of minute.
2nd digit of minute count bits
When counting 0 to 5, 60 minutes are 0 to 5
counted.
(BCD
code)
Timer RE busy flag
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
BSY
Figure 14.158 TREMIN Register in Real-Time Clock Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Setting
Range
Page 346 of 580
RW
RW
RW
RW
RW
RW
RW
RW
RO
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Hour Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREHR
Address
011Ah
After Reset
00h
Bit Symbol
Bit Name
Function
HR00
HR01
HR02
HR03
HR10
1st digit of hour count bits
Count 0 to 9 every hour. When the
0 to 9
digit moves up, 1 is added to the 2nd (BCD
digit of hour.
code)
2nd digit of hour count bits
Count 0 to 1 w hen the H12_H24 bit is 0 to 2
set to 0 (12-hour mode).
(BCD
Count 0 to 2 w hen the H12_H24 bit is code)
set to 1 (24-hour mode).
HR11
—
(b6)
Setting
Range
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
BSY
RW
RW
RW
RW
RW
RW
RW
—
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
RO
Figure 14.159 TREHR Register in Real-Time Clock Mode
Timer RE Day of Week Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREWK
Bit Symbol
Address
011Bh
Bit Name
Day of w eek count bits
WK0
WK1
WK2
—
(b6-b3)
After Reset
00h
Function
0 0 0 : Sunday
0 0 1 : Monday
0 1 0 : Tuesday
0 1 1 : Wednesday
1 0 0 : Thursday
1 0 1 : Friday
1 1 0 : Saturday
1 1 1 : Do not set.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE busy flag
BSY
This bit is set to 1 w hile registers TRESEC,
TREMIN, TREHR, and TREWK are updated.
Figure 14.160 TREWK Register in Real-Time Clock Mode
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REJ09B0324-0200
Page 347 of 580
RW
b2 b1 b0
RW
RW
RW
—
RO
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
011Ch
TRECR1
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b0)
When read, the content is 0.
TCSTF
TOENA
INT
—
0 : Count stopped
1 : Counting
RO
TREO pin output enable bit
0 : Disable clock output
1 : Enable clock output
RW
Interrupt request timing bit
Set to 1 in real-time clock mode.
Timer RE reset bit
When setting this bit to 0, after setting it to 1, the
follow ings w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and TSTART
in the TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
RW
When the H12_H24 bit is set to 0
(12-hour mode)(1)
0 : a.m.
1 : p.m.
When the H12_H24 bit is set to 1 (24-hour
mode), its value is undefined.
RW
Operating mode select bit
0 : 12-hour mode
1 : 24-hour mode
RW
Timer RE count start bit
0 : Count stops
1 : Count starts
RW
A.m./p.m. bit
PM
TSTART
RW
Timer RE count status flag
TRERST
H12_H24
After Reset
00h
Function
RW
NOTE:
1. This bit is automatically modified w hile timer RE counts.
Figure 14.161 TRECR1 Register in Real-Time Clock Mode
Noon
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H12_H24 bit = 0
(12-hour mode)
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
0 (a.m.)
Contents of PM bit
1 (p.m.)
000 (Sunday)
Contents in TREWK register
Date changes
Contents of
TREHR Register
H12_H24 bit = 1
(24-hour mode)
18
19
20
21
22
23
0
1
2
3
⋅⋅⋅
H12_H24 bit = 0
(12-hour mode)
6
7
8
9
10
11
0
1
2
3
⋅⋅⋅
Contents of PM bit
Contents in TREWK register
1 (p.m.)
0 (a.m.)
⋅⋅⋅
000 (Sunday)
001 (Monday)
⋅⋅⋅
PM bit and H12_H24 bits: Bits in TRECR1 register
The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 14.162 Definition of Time Representation
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R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECR2
Bit Symbol
SEIE
MNIE
HRIE
DYIE
WKIE
COMIE
—
(b7-b6)
Address
011Dh
Bit Name
Periodic interrupt triggered every
second enable bit(1)
After Reset
00h
Function
0 : Disable periodic interrupt triggered
every second
1 : Enable periodic interrupt triggered
every second
Periodic interrupt triggered every
minute enable bit(1)
0 : Disable periodic interrupt triggered
every minute
1 : Enable periodic interrupt triggered
every minute
RW
Periodic interrupt triggered every
hour enable bit(1)
0 : Disable periodic interrupt triggered
every hour
1 : Enable periodic interrupt triggered
every hour
RW
Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered
every day
enable bit(1)
1 : Enable periodic interrupt triggered
every day
RW
Periodic interrupt triggered every
w eek enable bit(1)
0 : Disable periodic interrupt triggered
every w eek
1 : Enable periodic interrupt triggered
every w eek
RW
Compare match interrupt enable bit
Set to 0 in real-time clock mode.
RW
RW
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTE:
1. Do not set multiple enable bits to 1 (enable interrupt).
Figure 14.163 TRECR2 Register in Real-Time Clock Mode
Table 14.53
Interrupt Sources
Factor
Periodic interrupt
triggered every week
Periodic interrupt
triggered every day
Periodic interrupt
triggered every hour
Periodic interrupt
triggered every minute
Periodic interrupt
triggered every second
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Interrupt Source
Value in TREWK register is set to 000b (Sunday)
(1-week period)
TREWK register is updated (1-day period)
Interrupt Enable Bit
WKIE
DYIE
TREHR register is updated (1-hour period)
HRIE
TREMIN register is updated (1-minute period)
MNIE
TRESEC register is updated (1-second period)
SEIE
Page 349 of 580
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14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
1 0 0 0
Symbol
TRECSR
Bit Symbol
RCS0
Address
011Eh
Bit Name
Count source select bits
After Reset
00001000b
Function
Set to 00b in real-time clock mode.
RCS1
RCS2
RCS3
—
(b4)
4-bit counter select bit
Set to 0 in real-time clock mode.
Real-time clock mode select bit
Set to 1 in real-time clock mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock output select bits (1)
RCS6
0 0 : f2
0 1 : f4
1 0 : f8
1 1 : Do not set.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 14.164 TRECSR Register in Real-Time Clock Mode
Page 350 of 580
RW
RW
—
b6 b5
NOTE:
1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
RW
RCS5
—
(b7)
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
1s
Approx.
62.5 ms
Approx.
62.5 ms
BSY bit
Bits SC12 to SC00 in
TRESEC register
58
59
Bits MN12 to MN00 in
TREMIN register
03
Bits HR11 to HR00 in
TREHR register
(Not changed)
PM bit in
TRECR1 register
IR bit in TREIC register
(when SEIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every second))
IR bit in TREIC register
(when MNIE bit in TRECR2 register is set
to 1 (enable periodic interrupt triggered
every minute))
(Not changed)
0
(Not changed)
1
0
1
0
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.165 Operating Example in Real-Time Clock Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
04
1
Bits WK2 to WK0 in
TREWK register
Page 351 of 580
00
Set to 0 by acknowledgement
of interrupt request
or a program
R8C/2A Group, R8C/2B Group
14.5.2
14. Timers
Output Compare Mode
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and
compare value match is detected with the 8-bit counter. Figure 14.166 shows a Block Diagram of Output
Compare Mode and Table 14.54 lists the Output Compare Mode Specifications. Figures 14.167 to 14.171 show
the registers associated with output compare mode, and Figure 14.172 shows the Operating Example in Output
Compare Mode.
f4
f8
RCS6 to RCS5
= 00b
f2
= 01b
RCS1 to RCS0
= 00b
= 01b
f32
fC4
= 10b
1/2
4-bit
counter
= 10b
RCS2 = 1
T Q
8-bit
counter
= 11b
TREMIN
Data bus
Figure 14.166 Block Diagram of Output Compare Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 352 of 580
= 11b
Reset
Comparison
circuit
TRESEC
TREO pin
R
RCS2 = 0
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TOENA bit
Match
signal
TRERST bit
COMIE bit
Timer RE interrupt
R8C/2A Group, R8C/2B Group
Table 14.54
14. Timers
Output Compare Mode Specifications
Item
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request generation
timing
TREO pin function
Read from timer
Write to timer
Select functions
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Specification
f4, f8, f32, fC4
• Increment
• When the 8-bit counter content matches with the TREMIN register
content, the value returns to 00h and count continues.
The count value is held while count stops.
• When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• When RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
1 (count starts) is written to the TSTART bit in the TRECR1 register
0 (count stops) is written to the TSTART bit in the TRECR1 register
When the 8-bit counter content matches with the TREMIN register content
Select any one of the following:
• Programmable I/O ports
• Output f2, f4, or f8
• Compare output
When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
• Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value,
TREO output polarity is reversed. The TREO pin outputs “L” after reset
is deasserted and the timer RE is reset by the TRERST bit in the
TRECR1 register. Output level is held by setting the TSTART bit to 0
(count stops).
Page 353 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Counter Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRESEC
Address
0118h
Function
After Reset
00h
RW
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The TRESEC register is set to 00h at the compare match.
RO
Figure 14.167 TRESEC Register in Output Compare Mode
Timer RE Compare Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TREMIN
Address
0119h
Function
8-bit compare data is stored.
Figure 14.168 TREMIN Register in Output Compare Mode
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After Reset
00h
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
Address
011Ch
TRECR1
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b0)
TCSTF
TOENA
INT
TSTART
RW
—
Timer RE count status flag
0 : Count stopped
1 : Counting
RO
TREO pin output enable bit
0 : Disable clock output
1 : Enable clock output
RW
Interrupt request timing bit
Set to 0 in output compare mode.
Timer RE reset bit
When setting this bit to 0, after setting it to 1, the
follow ing w ill occur.
• Registers TRESEC, TREMIN, TREHR, TREWK,
and TRECR2 are set to 00h.
• Bits TCSTF, INT, PM, H12_H24, and
TSTART in the TRECR1 register are
set to 0.
• The 8-bit counter is set to 00h and
the 4-bit counter is set to 0h.
TRERST
PM
H12_H24
After Reset
00h
Function
A.m./p.m. bit
Operating mode select bit
Timer RE count start bit
Set to 0 in output compare mode.
0 : Count stops
1 : Count starts
RW
RW
RW
RW
RW
Figure 14.169 TRECR1 Register in Output Compare Mode
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Symbol
TRECR2
Bit Symbol
SEIE
Address
011Dh
Bit Name
Periodic interrupt triggered every
second enable bit
RW
RW
MNIE
Periodic interrupt triggered every
minute enable bit
RW
HRIE
Periodic interrupt triggered every
hour enable bit
RW
DYIE
Periodic interrupt triggered every
day enable bit
RW
WKIE
Periodic interrupt triggered every
w eek enable bit
RW
COMIE
—
(b7-b6)
Compare match interrupt enable bit
0 : Disable compare match interrupt
1 : Enable compare match interrupt
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 14.170 TRECR2 Register in Output Compare Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
After Reset
00h
Function
Set to 0 in output compare mode.
Page 355 of 580
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRECSR
Bit Symbol
Address
011Eh
Bit Name
Count source select bits
RCS0
RCS1
RCS2
RCS3
—
(b4)
4-bit counter select bit
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : fC4
Real-time clock mode select bit
Set to 0 in output compare mode.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Clock output select bits
(1)
RCS6
0 0 : f2
0 1 : f4
1 0 : f8
1 1 : Compare output
NOTE:
1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
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Page 356 of 580
RW
RW
RW
RW
—
b6 b5
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Figure 14.171 TRECSR Register in Output Compare Mode
RW
b1 b0
0 : Not used
1 : Used
RCS5
—
(b7)
After Reset
00001000b
Function
RW
RW
—
R8C/2A Group, R8C/2B Group
14. Timers
8-bit counter content
(hexadecimal number)
Count starts
Matched
TREMIN register
setting value
Matched
Matched
00h
Time
Set to 1 by a program
TSTART bit in
TRECR1 register
1
0
2 cycles of maximum count source
TCSTF bit in
TRECR1 register
1
0
Set to 0 by acknowledgement of interrupt request
or a program
IR bit in
TREIC register
TREO output
1
0
1
0
Output polarity is inverted
when the compare matches
The above applies under the following conditions.
TOENA bit in TRECR1 register = 1 (enable clock output)
COMIE bit in TRECR2 register = 1 (enable compare match interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Figure 14.172 Operating Example in Output Compare Mode
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Page 357 of 580
R8C/2A Group, R8C/2B Group
14.5.3
14. Timers
Notes on Timer RE
14.5.3.1
Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
14.5.3.2
Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 14.173 shows a Setting Example in Real-Time Clock Mode.
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Page 358 of 580
R8C/2A Group, R8C/2B Group
14. Timers
TSTART in TRECR1 register = 0
TCSTF in
TRECR1 register = 0?
Stop timer RE operation
TREIC register←00h
(disable timer RE interrupt)
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2 register
Timer RE register
and control circuit reset
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Setting of TREIC register (IR bit ←0,
select interrupt priority level)
TSTART in TRECR1 register = 1
Start timer RE operation
TCSTF in
TRECR1 register = 1?
Figure 14.173 Setting Example in Real-Time Clock Mode
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REJ09B0324-0200
Page 359 of 580
R8C/2A Group, R8C/2B Group
14.5.3.3
14. Timers
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14.6
14. Timers
Timer RF
Timer RF is a 16-bit timer. The count source for timer RF is the operating clock that regulates the timing of timer
operations. Figure 14.174 shows a Block Diagram of Timer RF. Figure 14.175 shows a Block Diagram of CMP
Waveform Generation Unit. Figure 14.176 shows a Block Diagram of CMP Waveform Output Unit.
Timer RF has two modes: input capture mode and output compare mode. Figures 14.177 to 14.180 show the Timer
C-associated registers.
TRFI
TIPF1 to TIPF0
f1 = 01b
Sampling clock
f8 = 10b
=
11b
=
other
than
f32
Digital
00b
filter
= 00b
Edge
detection
Capture interrupt
Capture signal
Capture, Compare 0 register
Data bus
TRFM0 register
TCK1 to TCK0
f1 = 00b
f8 = 01b
f32 = 10b
Comparator
Timer RF
interrupt
Counter
TRF register
TSTART
Compare 0
interrupt
CCLR = 1
CCLR = 0
Timer RF counter
clear signal
Compare 1 register
Comparator
CMP
waveform
generation
unit
CMP waveform
output unit
TRFO00
CMP waveform
output unit
TRFO01
CMP waveform
output unit
TRFO02
CMP waveform
output unit
TRFO10
CMP waveform
output unit
TRFO11
CMP waveform
output unit
TRFO12
Compare 1
interrupt
TRFM1 register
TSTART, TCK0 to TCK1: Bits in TRFCR0 register
TIPF0 to TIPF1, CCLR: Bits in TRFCR1 register
Figure 14.174 Block Diagram of Timer RF
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 361 of 580
R8C/2A Group, R8C/2B Group
14. Timers
TRFC14
TRFC15
Compare 0 interrupt signal
Compare 1 interrupt signal
TRFC16
TRFC17
“H”
“L”
Inverted
TRFC17 to TRFC16
T
= 11b
D
= 10b
= 01b
Latch
CMP output
(internal signal)
Q
R
Reset
Inverted
“L”
“H”
TRFC15 to TRFC14
= 01b
= 10b
= 11b
TRFC14 to TRFC17: Bits in TRFC1 register
Figure 14.175 Block Diagram of CMP Waveform Generation Unit
TRFOUT6 = 0
CMP output
(Internal signal)
TRFOUT0 = 1
Inverted
TRFOUT6 = 1
TRFO00
TRFOUT0 = 0
P8_0 bit
This diagram is a block diagram of the TRFO00 waveform output unit.
The TRFO01 to TRFO02 and TRFO10 to TRFO12 waveform output units have the same configuration.
TRFOUT0 and TRFOUT6: Bits in TRFOUT register
P8_0: Bit in P8 register
Figure 14.176 Block Diagram of CMP Waveform Output Unit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 362 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Timer RF Register(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRF
Address
0291h-0290h
Function
After Reset
0000h
RW
Count source increment .
0000h can be read w hen the TSTART bit is set to 0 (count stops).
Count value can be read w hen the TSTART bit is set to 1 (count starts).
RO
NOTE:
1. Access the TRF register in 16-bit units.
Capture and Compare 0 Register(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRFM0
Mode
Input capture mode
Output compare mode(3)
Address
029Dh-029Ch
Function
When the active edge of the measured
pulse is input, store the value in the TRF
register
Store the value compared w ith TRF
register (counter)
After Reset
0000h(2)
Setting Range
RW
―
RO
0000h to FFFFh
RW
NOTES:
1. Access the TRFM0 register in 16-bit units.
2. When the TMOD bit in the TRFCR1 register is set to 1, the value is set to FFFFh.
3. When setting a value in the TRFM0 register, set the TMOD bit in the TRFCR1 register to 1 (output compare mode).
When the TMOD bit is set to 0 (input capture mode), no value can be w ritten.
Compare 1 Register(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TRFM1
Mode
Output compare mode
Address
029Fh-029Eh
Function
Store the value compared w ith TRF
register (counter)
NOTE:
1. Access the TRFM1 register in 16-bit units.
Figure 14.177 Registers TRF, TRFM0, and TRFM1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 363 of 580
After Reset
FFFFh
Setting Range
0000h to FFFFh
RW
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RF Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TRFCR0
Bit Symbol
TSTART
TCK0
Address
029Ah
Bit Name
Timer RF count start bit
Timer RF count source select
bits (1)
TCK1
TRFC03
Capture polarity select bits (1)
TRFC06
—
(b7)
b2 b1
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Do not set.
b4 b3
RW
RW
RW
RW
RW
RW
CMP output select bit 0 w hen
count stops
0 : TRFC06 bit disabled
Holds output level before count stops
1 : TRFC06 bit enabled
RW
CMP output select bit 1 w hen
count stops
0 : “L” output w hen count stops
1 : “H” output w hen count stops
RW
Reserved bit
Set to 0.
NOTE:
1. Rew rite this bit w hen the TSTART bit is set to 0 (count stops).
Figure 14.178 TRFCR0 Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
0 : Count stops
1 : Count starts
0 0 : Rising edge
0 1 : Falling edge
1 0 : Both edges
1 1 : Do not set.
TRFC04
TRFC05
After Reset
00h
Function
Page 364 of 580
RW
R8C/2A Group, R8C/2B Group
14. Timers
Timer RF Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRFCR1
Bit Symbol
TIPF0
Address
029Bh
Bit Name
TRFI filter select bits (1)
After Reset
00h
Function
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF1
RW
RW
RW
CCLR
TRF register count operation 0 : Free-running operation
select bit(2, 3)
1 : Set TRF register to 0000h w hen compare
1 is matched.
RW
TMOD
Timer RF operation mode
select bit(3)
0 : Input capture mode(2, 4)
1 : Output compare mode
RW
Compare 0 output select
bits (2)
b5 b4 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
TRFC14
TRFC15
TRFC16
Compare 1 output select
bits (2)
TRFC17
b7 b6 CMP output w hen compare 0 is matched
0 0 : Unchanged
0 1 : Inverted
1 0 : “L”
1 1 : “H”
RW
RW
NOTES:
1. If filter enabled, w hen the same value from the TRFI pin is sampled three times continuously, the input is determined.
2. When the TMOD bit is set to 0 (input capture mode), set bits CCLR, and TRFC14 to TRFC17 to 0.
3. When the TSTART bit in the TRFCR0 register is set to 0 (count stops), rew rite bits CCLR and TMOD.
4. When the TMOD bit is set to 0 (input capture mode), set bits ILVL2 to ILVL0 in the CMP1IC register to 000b (level 0)
and set the IR bit to 0 (no interrupt requested).
Figure 14.179 TRFCR1 Register
Timer RF Output Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRFOUT
Bit Symbol
TRFOUT0
TRFOUT1
TRFOUT2
TRFOUT3
TRFOUT4
TRFOUT5
TRFOUT6
TRFOUT7
Address
02FFh
Bit Name
TRFO00 output enable bit
TRFO01 output enable bit
TRFO02 output enable bit
TRFO10 output enable bit
TRFO11 output enable bit
TRFO12 output enable bit
TRFO00 to TRFO02 output invert
bit
TRFO10 to TRFO12 output invert
bit
Figure 14.180 TRFOUT Register
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REJ09B0324-0200
Page 365 of 580
After Reset
00h
Function
0 : Output disabled
1 : Output enabled
0 : Output not inverted
1 : Output inverted
RW
RW
RW
RW
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
14.6.1
14. Timers
Input Capture Mode
In input capture mode, the edge of the TRFI pin input signal is used as a trigger to latch the timer value and the
width or the period of external signal is measured. The TRFI input is equipped with a digital filter, and this
prevents errors caused by noise or the like from occurring. Table 14.55 shows the Input Capture Mode
Specifications. Figure 14.181 shows an Operating Example in Input Capture Mode.
Table 14.55
Input Capture Mode Specifications
Item
Count sources
Count operations
Count period
Count start condition
Count stop condition
Interrupt request
generation timing
TRFI pin function
Specification
f1, f8, f32
• Increment
• Transfer the value in the TRF register to the TRFM0 register at the valid
edge of the measured pulse.
1/fk × 65536 fk: Frequency of count source
The TSTART bit in the TRFCR0 register is set to 1 (count starts).
The TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The valid edge of TRFI input [capture interrupt]
• When timer RF overflows [timer RF interrupt]
Measured pulse input
TRFO00 to TRFO02,
Programmable I/O port
TRFO11 to TRFO12 pin
functions
Counter value reset timing In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
Read from timer
• The count value can be read out by reading the TRF register.
• The count value at the measured pulse valid edge input can be read out by
reading the TRFM0 register.
Write to timer
Write to the TRF and TRFM0 registers is disabled.
Select functions
• TRFI polarity selected
Selects the valid edge of the measured pulse.
(Bits TRFC03 to TRFC04 in the TRFCR0 register.)
• Digital filter function
The TRFI input is sampled, and when the sampled input level matches as
three times, the level is determined.
Selects the sampling clock of the digital filter.
(Bits TIPF0 to TIPF1 in the TRFCR1 register.)
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
14. Timers
Overflow
Counter contents (hex)
FFFFh
Count starts
← Measurement value 2
←
Measurement
value 3
← Measurement value1
0000h
Set to 0 by
a program
Set to 1 by a program
TSTART bit in
TRFCR0 register
1
0
Time
When the count
stops, the value
is set to 0000h.
The delay caused by digital filter and
one count source cycle delay (max.).
Measured pulse
(TRFI pin input)
1
0
TRFM0 register
Undefined
Measured
value 1
Measured value 2
Measured
value 3
Undefined
Set to 0 when interrupt request is acknowledged, or set by a program.
IR bit in
CAPIC register
1
0
Set to 0 when interrupt request is
acknowledged, or set by a program.
IR bit in
TRFIC register
1
0
Measurement value 2 measurement value 1
(10000h - measurement value 2) +
measurement value 3
The above applies under the following conditions.
Bits TRFC04 to TRFC03 in TRFCR0 register = 01b (Capture input polarity is set for falling edge.)
Figure 14.181 Operating Example in Input Capture Mode
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R8C/2A Group, R8C/2B Group
14.6.1.1
14. Timers
Digital Filter
The TRFI input is sampled, and when the sampled input level matches three times, its level is determined.
Select the digital filter function and sampling clock by the TRFCR1 register.
TIPF1 to TIPF0
f1
f8
f32
= 01b
= 10b
= 11b
TMOD
TRFC04 to TRFC03
Sampling clock
TIPF1 to TIPF0
C
TRFI input
signal
D
C
Q
Latch
D
C
Q
D
Latch
C
Q
Latch
D
Q
Latch
Match
detection
circuit
= 01b, 10b, 11b
= 00b
Count source
C
D
Q
Latch
Clock period selected by
bits TIPF1 to TIPF0
Sampling clock
TRFI input signal
Recognition of the
signal change with
three times match
Input signal
through digital
filtering
Signal transmission delayed
up to five sampling clock
Transmission cannot be performed
without three times match because the
input signal is assumed to be noise.
TRFC03 to TRFC04: Bits in TRFCR0 register
TIPF0 to TIPF1 and TMOD: Bits in TRFCR1 register
Figure 14.182 Block Diagram of Digital Filter
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 368 of 580
Edge
detection
circuit
R8C/2A Group, R8C/2B Group
14.6.2
14. Timers
Output Compare Mode
In output compare mode, when the value of the TRF register matches the value of the TRFM0 (compare 0 match)
or TRFM1 (compare 1 match) register, a user-set level is output mode from the output-compare output pin.
Table 14.56 shows the Output Compare Mode Specifications. Table 14.57 shows the Output in Output
Compare Mode (Example of TRFO00 Pin). Figure 14.183 shows an Operating Example in Output Compare
Mode. Figure 14.184 shows the Operating Example in Output Compare Mode (“L” and “H” Held Output in
Count Stops).
Table 14.56
Output Compare Mode Specifications
Item
Count sources
Count operations
PWM waveform
Specification
f1, f8, f32
Increment
PWM period: 1/fk × (n + 1)
“L” level width: 1/fk × (m + 1)
“H” level width: 1/fk × (n - m)
fk: Frequency of count source
m: Value set in the TRFM0 register
n: Value set in the TRFM1 register
m+1
n-m
n+1
It applies under the following conditions.
• CMP output “H” when compare 0 is matched
• CMP output “L” when compare 1 is matched
• CMP output not inverted
Count start condition
Count stop condition
Interrupt request
generation timing
The TSTART bit in the TRFCR0 register is set to 1 (count starts).
The TSTART bit in the TRFCR0 register is set to 0 (count stops).
• When compare 0 match is generated [compare 0 interrupt]
• When compare 1 match is generated [compare 1 interrupt]
• When time RF overflows [timer RF interrupt].
TRFO00 to TRFO12 pins
function
Counter value reset timing
Programmable I/O port or output-compare output
Read from timer
Write to timer
Select functions
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
In the following cases, the value in the TRF register is set to 0000h.
• When the TSTART bit in the TRFCR0 register is set to 0 (count stops).
• The CCLR bit in the TRFCR1 register is set to 1 (the TRF register is set to
0000h at compare 1 match) in the compare 1 matches.
• The count value can be read out by reading the TRF register.
• The value in the compare register can be read out by reading registers
TRFM0 and TRFM1.
Write to the TRF register is disabled
• Output-compare output pin selected
Either 1 pin or multiple pins among TRFO00 to TRFO02, or TRFO10 to
TRFO12 (bits TRFOUT0 to TRFOUT5 in the TRFOUT register).
• Output level at the compare match
Selects “H”, “L”, inverted, or unchanged (bits TRFC14 to TRFC17 in the
TRFCR1 register).
• Output level inverted
Selects output level inverted or not inverted (bits TRFOUT6 to TRFOUT7
in the TRFOUT register).
• Output level at the count stops
Selects “H”, “L”, or unchanged (bits TRFC05 to TRFC06 in the TRFCR0
register).
• Timing to set the TRF register to 0000h
Overflow or compare 1 match in the TRFM1 register (the CCLR bit in the
TRFCR1 register).
Page 369 of 580
R8C/2A Group, R8C/2B Group
Table 14.57
14. Timers
Output in Output Compare Mode (Example of TRFO00 Pin)
TRFO00 Output
Counting CMP output
Inverted output of
CMP output
“L” output
“H” output
Count
Holds output level
stops
before count stops
“L” output
“H” output
Bit Setting Value
TRFCR0 Register
TRFOUT Register
P8 Register
TRFC06 TRFC05 TSTART TRFOUT6 TRFOUT0
P8_0
X
X
1
0
1
1
X
X
1
1
1
1
X
X
X
X
X
0
1
1
0
0
1
X
1
1
1
0
0
1
0
1
1
1
0
0
X
X
1
1
1
1
X: 0 or 1
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 370 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Match
Counter content (hex)
Value set in
TRFM1 register
Count starts
Value set in
TRFM0 register
Match
Match
0000h
Time
Set to 1 by a program
TSTART bit in
TRFCR0 register
When the count
stops, the value
is set to 0000h.
1
0
Set to 0 when interrupt request is acknowledged,
or set by a program.
IR bit in
CMP0IC register
1
0
Set to 0 when interrupt request is
acknowledged, or set by a program.
IR bit in
CMP1IC register
TRFO00 output
TRFO10 output
1
0
1
0
1
0
The above applies under the following conditions.
TRFC05 bit in TRFCR0 register = 1, TRFC06 bit in TRFCR0 register = 0 (“L” output when count stops)
CCLR bit in TRFCR1 register = 1 (TRF register is set to 0000h at compare 1 match occurrence)
TMOD bit in TRFCR1 register = 1 (output compare mode)
Bits TRFC15 to TRFC14 in TRFCR1 register = 11b (CMP output level is set to “H” at compare 0 match)
Bits TRFC17 to TRFC16 in TRFCR1 register = 10b (CMP output level is set to “L” at compare 1 match)
TRFOUT6 bit in TRFOUT register = 0 (not inverted)
TRFOUT7 bit in TRFOUT register = 1 (inverted)
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
P8_0 bit in P8 register = 1 (“H”)
P8_3 bit in P8 register = 1 (“H”)
Figure 14.183 Operating Example in Output Compare Mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 371 of 580
R8C/2A Group, R8C/2B Group
14. Timers
Set to 1 by program
P8_0 bit in
P8 register
1
0
P8_3 bit in
P8 register
1
0
Set to 0 by program
CMP output
(internal signal)
TRFO00 output
TRFO10 output
The above applies under the following conditions.
TRFOUT0 bit in TRFOUT register = 1 (TRFO00 output enabled)
TRFOUT3 bit in TRFOUT register = 1 (TRFO10 output enabled)
TRFOUT6 bit in TRFOUT register = 0 (TRFO00 to TRFO02 output not inverted)
TRFOUT7 bit in TRFOUT register = 1 (TRFO10 to TRFO12 output inverted)
TSTART bit in TRFCR0 register = 1 (count starts)
Figure 14.184 Operating Example in Output Compare Mode (“L” and “H” Held Output in Count
Stops)
In output compare mode, the same PWM waveform is output from all of pins TRFO00 to TRFO02 and
TRFO10 to TRFO12 during count operation. Note that the output waveform can be inverted for pins TRFO00
to TRFO02 or for pins TRFO10 to TRFO12. The output can also be fixed at “L” or “H” for individual pins for
a given period.
The behavior when count operation stops can be selected from the following two options: the output level
before the count stops is maintained, or output is fixed at “L” or “H”.
The values in the compare i register can be read by reading the TRFMi (i = 0 or 1) register. Writing to the
TRFMi register causes the values to be stored in the compare i register in the following timing:
• If the TSTART bit is set to 0 (count stops)
Values are stored simultaneously with the write to the TRFMi register.
• If the TSTART bit is set to 1 (count starts) and the CCLR bit in the TRFCR1 register is set to 0 (free running)
Values are stored when the TRF register (counter) overflows.
• If the TSTART bit is set to 1 and the CCLR bit is set to 1 (TRF register set to 0000h at compare 1 match)
Values are stored when the compare 1 and TRF register (counter) values match.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 372 of 580
R8C/2A Group, R8C/2B Group
14.6.3
14. Timers
Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W
0290H,R0
; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 373 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
15. Serial Interface
The serial interface consists of three channels (UART0 to UART2). Each UARTi (i = 0 to 2) has an exclusive timer to
generate the transfer clock and operates independently.
Figure 15.1 shows a UARTi (i = 0 to 2) Block Diagram. Figure 15.2 shows a UARTi Transmit/Receive Unit. Figure
15.3 shows a Block Diagram of CLK1 and CLK2 Pin Switching Unit.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 15.4 to 15.8 show the registers associated with UARTi.
UARTj (j = 0 or 2)
TXDj
RXDj
CLK1 to CLK0 = 00b
f1
f8
f32
CKDIR = 0
Internal
= 01b
Clock
synchronous type
U0BRG register
= 10b
1/(n0+1)
External
CKDIR = 1
1/16
Reception control
circuit
UART transmission
Transmission
control circuit
Clock
synchronous type
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
switch
circuit
CLKj
1/16
UART reception
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR = 0
CKDIR = 1
TXD1EN
UART1
RXD1
TXD1
CLK1 to CLK0 = 00b
f1
f8
f32
CKDIR = 0
Internal
= 01b
1/16
U1BRG register
= 10b
1/(n0+1)
External
CKDIR = 1
1/16
UART reception
Clock
synchronous type
Reception control
circuit
UART transmission
Clock
synchronous type
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is selected)
Transmission
control circuit
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR = 0
CKDIR = 1
CLK11PSEL to CLK10PSEL
= 00b
CLK1 (P0_5)
CLK1 (P6_5)
= 01b
= 10b
CLK
polarity
switch
circuit
i = 0 to 2
CKDIR: Bit in UiMR register
CLK0 to CLK1: Bits in UiC0 register
CLK10PSEL to CLK11PSEL: Bits in U1SR register
U1PINSEL: Bit in PMR register
Figure 15.1
UARTi (i = 0 to 2) Block Diagram
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 374 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
1SP
RXDi
SP
SP
Clock
synchronous
type
PRYE = 0
Clock
PAR
disabled synchronous
type
UART (7 bits)
UART (8 bits)
UART (7 bits)
UARTi receive register
PAR
PAR
UART
enabled
PRYE = 1
2SP
UART (9 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0 UiRB register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D8
PRYE = 1
PAR
enabled
2SP
SP
SP
UART
D6
D5
D4
D3
D2
D1
TXDi
Clock
PAR
disabled synchronous
PRYE = 0 type
0
UARTi Transmit/Receive Unit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
D0 UiTB register
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
PAR
1SP
Figure 15.2
UART (9 bits)
D7
Page 375 of 580
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UART (7 bits)
UARTi transmit register
i = 0 to 2
SP: Stop bit
PAR: Parity bit
R8C/2A Group, R8C/2B Group
15. Serial Interface
Clock synchronous type
CLK10PSEL
CLK11PSEL
CLK11PSEL
CLK10PSEL
CLK11PSEL = 0
CLK polarity
switch
P0_5
CLK11PSEL = 1
CLK polarity
switch
CLK polarity
switch
CLK11PSEL = 1
CLK2
CLK11PSEL = 0
P6_5
CLK11PSEL
Clock synchronous
type (UART1)
CLK11PSEL
Clock synchronous
type (UART2)
CLK11PSEL
CLK polarity
switch
CLK polarity
switch
CLK10PSEL, CLK11PSEL: Bits in U1SR register
Figure 15.3
Block Diagram of CLK1 and CLK2 Pin Switching Unit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 376 of 580
CLK1
R8C/2A Group, R8C/2B Group
15. Serial Interface
UARTi Transmit/Receive Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0MR
U1MR
U2MR
Bit Symbol
Address
00A0h
00A8h
0160h
Bit Name
Serial I/O mode select bits
SMD0
SMD2
STPS
Internal/external clock select bit 0 : Internal clock
1 : External clock
—
(b7)
RW
RW
RW
RW
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
RW
Odd/even parity select bit
Enable w hen PRYE = 1
0 : Odd parity
1 : Even parity
RW
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
Reserved bit
Set to 0.
PRY
PRYE
RW
b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Other than above : Do not set.
SMD1
CKDIR
After Reset
00h
00h
00h
Function
RW
UARTi Bit Rate Register (i = 0 to 2)(1, 2, 3)
b7
b0
Symbol
U0BRG
U1BRG
U2BRG
Address
00A1h
00A9h
0161h
Function
Assuming the set value is n, UiBRG divides the count source by n+1
NOTES:
1. Write to this register w hile the serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to w rite to this register.
3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
Figure 15.4
Registers U0MR to U2MR and U0BRG to U2BRG
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 377 of 580
After Reset
Undefined
Undefined
Undefined
Setting Range
00h to FFh
RW
WO
R8C/2A Group, R8C/2B Group
15. Serial Interface
UARTi Transmit Buffer Register (i = 0 to 2)(1, 2)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0TB
U1TB
U2TB
Address
00A3h-00A2h
00ABh-00AAh
0163h-0162h
Function
—
(b8-b0)
Transmit data
—
(b15-b9)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
After Reset
Undefined
Undefined
Undefined
RW
WO
—
NOTES:
1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte.
2. Use the MOV instruction to w rite to this register.
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0C0
U1C0
U2C0
Bit Symbol
CLK0
CLK1
—
(b2)
TXEPT
—
(b4)
NCH
Address
00A4h
00ACh
0164h
Bit Name
BRG count source select b1 b0
0 0 : Selects f1
bits (1)
0 1 : Selects f8
1 0 : Selects f32
1 1 : Do not set.
Reserved bit
Set to 0.
Transmit register empty
flag
0 : Data in transmit register (during transmit)
1 : No data in transmit register (transmit completed)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RO
—
RW
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer
clock and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer
clock and receive data is input at falling edge
RW
Transfer format select bit 0 : LSB first
1 : MSB first
Registers U0TB to U2TB and U0C0 to U2C0
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
RW
0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open-drain output
NOTE:
1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 15.5
RW
Data output select bit
CKPOL
UFORM
After Reset
00001000b
00001000b
00001000b
Function
Page 378 of 580
RW
R8C/2A Group, R8C/2B Group
15. Serial Interface
UARTi Transmit/Receive Control Register 1 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1
U1C1
U2C1
Bit Symbol
Address
00A5h
00ADh
0165h
Bit Name
Transmit enable bit
After Reset
00000010b
00000010b
00000010b
Function
0 : Disables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Data in UiTB register
1 : No data in UiTB register
RO
Receive enable bit
0 : Disables reception
1 : Enables reception
RW
Receive complete flag(1)
0 : No data in UiRB register
1 : Data in UiRB register
RO
UiIRS
UARTi transmit interrupt cause
select bit
0 : Transmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1)
RW
UiRRM
UARTi continuous receive mode
enable bit(2)
0 : Disables continuous receive mode
1 : Enables continuous receive mode
RW
—
(b7-b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TE
TI
RE
RI
RW
RW
—
NOTES:
1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out.
2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UARTi Receive Buffer Register (i = 0 to 2)(1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
U0RB
U1RB
U2RB
Bit Symbol
—
(b7-b0)
Address
00A7h-00A6h
00AFh-00AEh
0167h-0166h
Bit Name
—
—
(b8)
—
(b11-b9)
—
RO
—
RO
Framing error flag
0 : No framing error
1 : Framing error
RO
Parity error flag
0 : No parity error
1 : Parity error
RO
Error sum flag
0 : No error
1 : Error
RO
(2)
SUM
RO
0 : No overrun error
1 : Overrun error
(2)
PER
RW
Overrun error flag
(2)
FER
Receive data (D8)
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
(2)
OER
After Reset
Undefined
Undefined
Undefined
Function
Receive data (D7 to D0)
NOTES:
1. Read out the UiRB register in 16-bit units.
2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b
(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no
error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the UiRB register is read out.
Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
Figure 15.6
Registers U0C1 to U2C1 and U0RB to U2RB
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 379 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
UART1 Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U1SR
Bit Symbol
—
(b1-b0)
Address
00F5h
Bit Name
Nothing is assigned. If necessary, set to 0 or 1.
When read, the content is undefined.
CLK1 pin select bits
CLK11PSEL
Figure 15.7
RW
—
b3 b2
0 0 : CLK1 pin is not selected.
0 1 : Selects CLK1 (P0_5)
1 0 : Selects CLK1 (P6_5)
1 1 : Do not set.
CLK10PSEL
—
(b7-b4)
After Reset
000000XXb
Function
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
—
U1SR Register
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
PMR
Bit Symbol
INT1SEL
Address
00F8h
Bit Name
_____
INT1 pin select bit
After Reset
00h
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
RW
INT2 pin select bit
0 : Selects P6_6
1 : Selects P3_2
RW
Reserved bits
Set to 0.
UART1 enable bit
To use the UART1, set to 1.
Reserved bits
Set to 0.
SSU / I2C bus sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
_____
INT2SEL
—
(b3-b2)
U1PINSEL
—
(b6-b5)
IICSEL
Figure 15.8
PMR Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 380 of 580
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
15.1
15. Serial Interface
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and
Settings in Clock Synchronous Serial I/O Mode(1).
Table 15.1
Clock Synchronous Serial I/O Mode Specifications
Item
Transfer data format
Transfer clocks
Specification
• Transfer data length: 8 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLKi pin
Transmit start conditions
• Before transmission starts, the following requirements must be met(1)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
Receive start conditions
• Before reception starts, the following requirements must be met(1)
- The RE bit in the UiC1 register is set to 1 (reception enabled)
- The TE bit in the UiC1 register is set to 1 (transmission enabled)
- The TI bit in the UiC1 register is set to 0 (data in the UiTB register)
• When transmitting, one of the following conditions can be selected
- The UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- The UiIRS bit is set to 1 (transmission completes):
When completing data transmission from UARTi transmit register.
• When receiving
When data transfer from the UARTi receive register to the UiRB register
(when reception completes).
Interrupt request
generation timing
Error detection
Select functions
• Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receives the 7th bit of the next data.
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enabled immediately by reading the UiRB register.
i = 0 to 2
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the UiC0
register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the external clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 381 of 580
R8C/2A Group, R8C/2B Group
Table 15.2
Register
UiTB
UiRB
UiBRG
UiMR
UiC0
UiC1
15. Serial Interface
Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Bit
0 to 7
0 to 7
OER
0 to 7
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
Function
Set data transmission
Data reception can be read
Overrun error flag
Set bit rate
Set to 001b
Select the internal clock or external clock
Select the count source in the UiBRG register
Transmit register empty flag
Select TXDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to 1 to enable transmission/reception
Transmit buffer empty flag
Set this bit to 1 to enable reception
Reception complete flag
Select the UARTi transmit interrupt source
Set this bit to 1 to use continuous receive mode
i = 0 to 2
NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 382 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs “H” level
between the operating mode selection of UARTi (i = 0 to 2) and transfer start. (If the NCH bit is set to 1 (N-channel
open-drain output), this pin is in a high-impedance state.)
Table 15.3
I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name
TXD0 (P1_4)
RXD0 (P1_5)
Function
Output serial data
Input serial data
CLK0 (P1_6)
Output transfer clock
Input transfer clock
TXD1 (P6_6)
Output serial data
RXD1 (P6_7)
Input serial data
CLK1 (P0_5
or P6_5)
Output transfer clock
Input transfer clock
TXD2 (P6_3)
RXD2 (P6_4)
Output serial data
Input serial data
CLK2 (P6_5)
Output transfer clock
Input transfer clock
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Selection Method
(Outputs dummy data when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CKDIR bit in U0MR register = 0
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
U1PINSEL bit in PMR register = 1
(Outputs dummy data when performing reception only)
U1PINSEL bit in PMR register = 1
PD6_7 bit in PD6 register = 0
(P6_7 can be used as an input port when performing
transmission only)
• When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
CKDIR bit in U1MR register = 0
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
CKDIR bit in U1MR register = 0
• When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
PD6_5 bit in PD6 register = 0
CKDIR bit in U1MR register = 1
(Outputs dummy data when performing reception only)
PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CKDIR bit in U2MR register = 0
CKDIR bit in U2MR register = 1
PD6_6 bit in PD6 register = 0
Page 383 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
• Example of transmit timing (when internal clock is selected)
TC
Transfer clock
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Set data in UiTB register
Transfer from UiTB register to UARTi transmit register
TCLK
Stop pulsing because the TE bit is set to 0
CLKi
D0
TXDi
TXEPT bit in
UiC0 register
1
0
IR bit in SiTIC
register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Set to 0 when interrupt request is acknowledged, or set by a program
TC=TCLK=2(n+1)/fi
fi: Frequency of UiBRG count source (f1, f8, f32)
The above applies under the following settings:
n: Setting value to UiBRG register
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
• Example of receive timing (when external clock is selected)
RE bit in UiC1
register
1
0
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Write dummy data to UiTB register
Transfer from UiTB register to UARTi transmit register
1/fEXT
CLKi
Receive data is taken in
D0
RXDi
RI bit in UiC1
register
1
0
IR bit in SiRIC
register
1
0
D1
D2
D3
D4
D5
D6
D7
D0
D1
Transfer from UARTi receive register to
UiRB register
D2
D3
D4
D5
Read out from UiRB register
Set to 0 when interrupt request is acknowledged, or set by a program
The above applies under the following settings:
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
fEXT: Frequency of external clock
i = 0 to 2
Figure 15.9
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
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REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
15.1.1
15. Serial Interface
Polarity Select Function
Figure 15.10 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 to 2) register to select
the transfer clock polarity.
• When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling
edge and input receive data at the rising edge of the transfer clock)
CLKi(1)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
• When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising
edge and input receive data at the falling edge of the transfer clock)
CLKi(2)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES:
1. When not transferring, the CLKi pin level is “H”.
2. When not transferring, the CLKi pin level is “L”.
i = 0 to 2
Figure 15.10
15.1.2
Transfer Clock Polarity
LSB First/MSB First Select Function
Figure 15.11 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 to 2) register to select the
transfer format.
• When UFORM bit in UiC0 register = 0 (LSB first)(1)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
• When UFORM bit in UiC0 register = 1 (MSB first)(1)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
NOTE:
1. The above applies when the CKPOL bit in the UiC0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
i = 0 to 2
Figure 15.11
Transfer Format
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 385 of 580
R8C/2A Group, R8C/2B Group
15.1.3
15. Serial Interface
Continuous Receive Mode
Continuous receive mode is selected by setting the UiRRM (i = 0 to 2) bit in the UiC1 register to 1 (enables
continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data
in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a
program.
Rev.2.00 Nov 26, 2007
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Page 386 of 580
R8C/2A Group, R8C/2B Group
15.2
15. Serial Interface
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format.
Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode.
Table 15.4
UART Mode Specifications
Item
Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request
generation timing
Error detection
Specification
• Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
• CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1))
fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh
• CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh
• Before transmission starts, the following are required
- TE bit in UiC1 register is set to 1 (transmission enabled)
- TI bit in UiC1 register is set to 0 (data in UiTB register)
• Before reception starts, the following are required
- RE bit in UiC1 register is set to 1 (reception enabled)
- Start bit detected
• When transmitting, one of the following conditions can be selected
- UiIRS bit is set to 0 (transmit buffer empty):
When transferring data from the UiTB register to UARTi transmit register
(when transmission starts).
- UiIRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UARTi
transmit register
• When receiving
When transferring data from the UARTi receive register to UiRB register
(when reception ends).
• Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the UiRB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, framing, or parity error is
generated.
i = 0 to 2
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR
bit in the SiRIC register remains unchanged.
Rev.2.00 Nov 26, 2007
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Page 387 of 580
R8C/2A Group, R8C/2B Group
Table 15.5
15. Serial Interface
Registers Used and Settings for UART Mode
Register
UiTB
0 to 8
Set transmit
UiRB
0 to 8
UiBRG
UiMR
OER,FER,PER,SUM
0 to 7
SMD2 to SMD0
Receive data can be read(1, 2)
Error flag
Set a bit rate
Set to 100b when transfer data is 7 bits long
Set to 101b when transfer data is 8 bits long
Set to 110b when transfer data is 9 bits long
Select the internal clock or external clock
Select the stop bit
Select whether parity is included and whether odd or even
Select the count source for the UiBRG register
Transmit register empty flag
Select TXDi pin output mode
Set to 0
LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
Set to 1 to enable transmit
Transmit buffer empty flag
Set to 1 to enable receive
Receive complete flag
Select the source of UARTi transmit interrupt
Set to 0
UiC0
UiC1
Bit
CKDIR
STPS
PRY, PRYE
CLK0, CLK1
TXEPT
NCH
CKPOL
UFORM
TE
TI
RE
RI
UiIRS
UiRRM
Function
data(1)
i = 0 to 2
NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long.
2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Rev.2.00 Nov 26, 2007
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Page 388 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 to 2) operating mode is selected, the
TXDi pin outputs “H” level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a highimpedance state) until transfer starts.)
Table 15.6
I/O Pin Functions in UART Mode
Pin name
Function
TXD0 (P1_4) Output serial data
RXD0 (P1_5) Input serial data
Selection Method
(Cannot be used as a port when performing reception only)
PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock
CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
TXD1 (P6_6) Output serial data
U1PINSEL bit in PMR register = 1
(Cannot be used as a port when performing reception only)
RXD1 (P6_7) Input serial data
U1PINSEL bit in PMR register = 1
PD6_7 bit in PD6 register = 0
(P6_7 can be used as an input port when performing
transmission only)
CLK1 (P0_5 Programmable I/O Port Bits CLK11PSEL to CLK10PSEL in U1SR register = 00b
or P6_5)
(CLK1 pin is not selected)
Input transfer clock
• When CLK1 (P0_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 01b (P0_5)
PD0_5 bit in PD0 register = 0
CKDIR bit in U1MR register = 1
• When CLK1 (P6_5)
Bits CLK11PSEL to CLK10PSEL in U1SR register = 10b (P6_5)
PD6_5 bit in PD6 register = 0
CKDIR bit in U1MR register = 1
TXD2 (P6_3) Output serial data
(Cannot be used as a port when performing reception only)
RXD2 (P6_4) Input serial data
PD6_4 bit in PD6 register = 0
(P6_4 can be used as an input port when performing
transmission only)
CLK2 (P6_5) Programmable I/O Port CKDIR bit in U2MR register = 0
Input transfer clock
CKDIR bit in U2MR register = 1
PD6_6 bit in PD6 register = 0
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 389 of 580
R8C/2A Group, R8C/2B Group
15. Serial Interface
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Write data to UiTB register
Stop pulsing
because the TE bit is set to 0
Transfer from UiTB register to UARTi transmit register
Start
bit
TXDi
ST
TXEPT bit in
UiC0 register
1
0
IR bit SiTIC
register
1
0
Parity Stop
bit
bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
Set to 0 when interrupt request is acknowledged, or set by a program
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 1 (parity enabled)
fj: Frequency of UiBRG count source (f1, f8, f32)
• STPS bit in UiMR register = 0 (1 stop bit)
fEXT: Frequency of UiBRG count source (external clock)
• UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes)
n: Setting value to UiBRG register
i = 0 to 2
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1
register
1
0
TI bit in UiC1
register
1
0
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register
Stop Stop
bit
bit
Start
bit
TXDi
ST
TXEPT bit in
UiC0 register
1
0
IR bit in SiTIC
register
1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 1 (2 stop bits)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
Figure 15.12
Transmit Timing in UART Mode
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REJ09B0324-0200
Page 390 of 580
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of UiBRG count source (f1, f8, f32)
fEXT: Frequency of UiBRG count source (external clock)
n: Setting value to UiBRG register
i = 0 to 2
D1
R8C/2A Group, R8C/2B Group
15. Serial Interface
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register
RE bit
1
0
Stop bit
Start bit
RXDi
D0
D1
D7
Determined to be “L” Receive data taken in
Transfer clock
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
RI bit
1
0
SiRIC register
IR bit
1
0
Transferred from UARTi receive
register to UiRB register
Set to 0 when interrupt request is accepted, or set by a program
The above timing diagram applies when the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
i = 0 to 2
Figure 15.13
Receive Timing Example in UART Mode
Rev.2.00 Nov 26, 2007
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Page 391 of 580
R8C/2A Group, R8C/2B Group
15.2.1
15. Serial Interface
Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 to 2) register.
UART mode
• Internal clock selected
UiBRG register setting value =
fj
Bit Rate × 16
-1
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
• External clock selected
UiBRG register setting value =
fEXT
Bit Rate × 16
-1
fEXT: Count source frequency of the UiBRG register (external clock)
i = 0 to 2
Figure 15.14
Table 15.7
Bit Rate
(bps)
1200
2400
4800
9600
14400
19200
28800
31250
38400
51200
Calculation Formula of UiBRG (i = 0 to 2) Register Setting Value
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
BRG
Count
Source
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
System Clock = 20 MHz
System Clock = 8 MHz
UiBRG
Actual Time
UiBRG
Actual
Error (%)
Error (%)
Setting Value
(bps)
Setting Value Time (bps)
129 (81h)
1201.92
0.16
51 (33h)
1201.92
0.16
64 (40h)
2403.85
0.16
25 (19h)
2403.85
0.16
32 (20h)
4734.85
-1.36
12 (0Ch)
4807.69
0.16
129 (81h)
9615.38
0.16
51 (33h)
9615.38
0.16
86 (56h)
14367.82
-0.22
34 (22h)
14285.71
-0.79
64 (40h)
19230.77
0.16
25 (19h)
19230.77
0.16
42 (2Ah)
29069.77
0.94
16 (10h)
29411.76
2.12
39 (27h)
31250.00
0.00
15 (0Fh)
31250.00
0.00
32 (20h)
37878.79
-1.36
12 (0Ch)
38461.54
0.16
23 (17h)
52083.33
1.73
9 (09h)
50000.00
-2.34
i = 0 to 2
Rev.2.00 Nov 26, 2007
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Page 392 of 580
R8C/2A Group, R8C/2B Group
15.3
15. Serial Interface
Notes on Serial Interface
• When reading data from the UiRB (i = 0 to 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W
00A6H,R0
; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B
#XXH,00A2H ; Write the low-order byte of U0TB register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 393 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
16. Clock Synchronous Serial Interface
The clock synchronous serial interface is configured as follows.
Clock synchronous serial interface
Clock synchronous serial I/O with chip select (SSU)
Clock synchronous communication mode
4-wire bus communication mode
I2C bus Interface
I2C bus interface mode
Clock synchronous serial mode
The clock synchronous serial interface uses the registers at addresses 00B8h to 00BFh. Registers, bits, symbols, and
functions vary even for the same addresses depending on the mode. Refer to the register diagrams of each function for
details.
Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the
options of the transfer clock, clock output format, and data output format.
16.1
Mode Selection
The clock synchronous serial interface has four modes.
Table 16.1lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and the
sections that follow for details of each mode.
Table 16.1
IICSEL Bit
in PMR
Register
0
0
1
1
Mode Selections
Bit 0 in 00BDh
Bit 7 in 00B8h
(SSUMS Bit in SSMR2
(ICE Bit in ICCR1
Function
Register, FS Bit in
Register)
SAR Register)
0
0
Clock synchronous
serial I/O with chip
select
0
1
1
0
1
1
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I2C bus interface
Mode
Clock synchronous
communication mode
4-wire bus communication mode
I2C bus interface mode
Clock synchronous serial mode
R8C/2A Group, R8C/2B Group
16.2
16. Clock Synchronous Serial Interface
Clock Synchronous Serial I/O with Chip Select (SSU)
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication.
Table 16.2 shows a Clock Synchronous Serial I/O with Chip Select Specifications and Figure 16.1 shows a Block
Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.10 show clock synchronous serial
I/O with chip select associated registers.
Table 16.2
Clock Synchronous Serial I/O with Chip Select Specifications
Item
Transfer data format
Specification
• Transfer data length: 8 bits
Continuous transmission and reception of serial data are supported since
both transmitter and receiver have buffer structures.
Operating modes
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
Master/slave device
Selectable
I/O pins
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip-select I/O pin
Transfer clocks
• When the MSS bit in the SSCRH register is set to 0 (operates as slave
device), external clock is selected (input from SSCK pin).
• When the MSS bit in the SSCRH register is set to 1 (operates as master
device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16,
f1/8 and f1/4, output from SSCK pin) is selected.
• Clock polarity and phase of SSCK can be selected.
Receive error detection • Overrun error
Overrun error occurs during reception and completes in error. While the
RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
when next serial data receive is completed, the ORER bit is set to 1.
Multimaster error
• Conflict error
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
detection
communication mode) and the MSS bit in the SSCRH register is set to 1
(operates as master device) and when starting a serial communication, the
CE bit in the SSSR register is set to 1 if “L” applies to the SCS pin input.
When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus
communication mode), the MSS bit in the SSCRH register is set to 0
(operates as slave device) and the SCS pin input changes state from “L” to
“H”, the CE bit in the SSSR register is set to 1.
Interrupt requests
5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full,
overrun error, and conflict error)(1).
Select functions
• Data transfer direction
Selects MSB-first or LSB-first
• SSCK clock polarity
Selects “L” or “H” level when clock stops
• SSCK clock phase
Selects edge of data change and data download
NOTE:
1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
f1
Internal clock (f1/i)
Internal clock
generation
circuit
Multiplexer
SSCK
SSMR register
SSCRL register
SSCRH register
Transmit/receive
control circuit
SCS
SSER register
SSMR2 register
SSTDR register
SSO
Data bus
SSSR register
SSTRSR register
Selector
SSI
SSRDR register
Interrupt requests
(TXI, TEI, RXI, OEI, and CEI)
i = 4, 8, 16, 32, 64, 128, or 256
Figure 16.1
Block Diagram of Clock Synchronous Serial I/O with Chip Select
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b2-b0)
When read, the content is 0.
MSTIIC
MSTTRD
MSTTRC
—
(b7-b6)
After Reset
00h
Function
RW
—
SSU, I2C bus operation enable bit
0: Disable(1)
1: Enable
RW
Timer RD operation enable bit
0: Disable(2)
1: Enable
RW
Timer RC operation enable bit
0: Disable(3)
1: Enable
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 16.2
MSTCR Register
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—
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SS Control Register H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSCRH
Bit Symbol
Address
00B8h
Bit Name
Transfer clock rate select bits (1)
CKS1
CKS2
MSS
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RW
—
Master/slave device select bit(2)
0 : Operates as slave device
1 : Operates as master device
RW
Receive single stop bit(3)
0 : Maintains receive operation after
receiving 1 byte of data
1 : Completes receive operation after
receiving 1 byte of data
RW
RSSTP
—
(b7)
RW
b2 b1 b0
0 0 0 : f1/256
0 0 1 : f1/128
0 1 0 : f1/64
0 1 1 : f1/32
1 0 0 : f1/16
1 0 1 : f1/8
1 1 0 : f1/4
1 1 1 : Do not set.
CKS0
—
(b4-b3)
After Reset
00h
Function
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. The set clock is used w hen the internal clock is selected.
2. The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device).
The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conflict error
occurs).
3. The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device).
Figure 16.3
SSCRH Register
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SS Control Register L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
00B9h
SSCRL
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b0)
When read, the content is 1.
SRES
—
(b3-b2)
SOLP
SOL
Clock synchronous
serial I/O w ith chip
select control part
reset bit
After Reset
01111101b
Function
When this bit is set to 1, the clock synchronous serial
I/O w ith chip select control block and SSTRSR register
are reset.
The values of the registers (1) in the clock synchronous
serial I/O w ith chip select register are maintained.
RW
—
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
SOL w rite protect bit(2) The output level can be changed by the SOL bit w hen
this bit is set to 0.
The SOLP bit remains unchanged even if 1 is w ritten to
it. When read, the content is 1.
RW
Serial data output value When read
setting bit
0 : The serial data output is set to “L”.
1 : The serial data output is set to “H”.
When w ritten(2,3)
0 : The data output is “L” after the serial data output.
1 : The data output is “H” after the serial data output.
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
NOTES:
1. Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
2. The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When
w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
3. Do not w rite to the SOL bit during data transfer.
Figure 16.4
SSCRL Register
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SS Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol
SSMR
Bit Symbol
Address
00BAh
Bit Name
Bits counter 2 to 0
BC0
BC1
BC2
After Reset
00011000b
Function
0 0 0 : 8 bits left
0 0 1 : 1 bit left
0 1 0 : 2 bits left
0 1 1 : 3 bits left
1 0 0 : 4 bits left
1 0 1 : 5 bits left
1 1 0 : 6 bits left
1 1 1 : 7 bits left
RO
Set to 1.
When read, the content is 1.
RW
—
(b3)
Reserved bit
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SSCK clock phase select bit(1)
MLS
RO
RO
—
0 : Change data at odd edge
(Dow nload data at even edge)
1 : Change data at even edge
(Dow nload data at odd edge)
RW
SSCK clock polarity select bit(1)
0 : “H” w hen clock stops
1 : “L” w hen clock stops
RW
MSB first/LSB first select bit
0 : Transfers data MSB first
1 : Transfers data LSB first
RW
CPHS
CPOS
RW
b2 b1 b0
NOTE:
1. Refer to 16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
and CPOS bits.
Figure 16.5
SSMR Register
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16. Clock Synchronous Serial Interface
SS Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSER
Bit Symbol
CEIE
—
(b2-b1)
Address
After Reset
00BBh
00h
Bit Name
Function
Conflict error interrupt enable bit 0 : Disables conflict error interrupt request
1 : Enables conflict error interrupt request
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Receive enable bit
0 : Disables receive
1 : Enables receive
RW
Transmit enable bit
0 : Disables transmit
1 : Enables transmit
RW
Receive interrupt enable bit
RIE
0 : Disables receive data full and overrun
error interrupt request
1 : Enables receive data full and overrun
error interrupt request
RW
TEIE
Transmit end interrupt enable bit 0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
RW
RE
TE
Transmit interrupt enable bit
TIE
Figure 16.6
SSER Register
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REJ09B0324-0200
RW
Page 400 of 580
0 : Disables transmit data empty interrupt
request
1 : Enables transmit data empty interrupt
request
RW
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SS Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSSR
Bit Symbol
CE
—
(b1)
ORER
—
(b4-b3)
RDRF
Address
00BCh
Bit Name
Conflict error flag(1)
After Reset
00h
Function
0 : No conflict errors generated
1 : Conflict errors generated(2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Overrun error flag(1)
0 : No overrun errors generated
1 : Overrun errors generated(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Receive data register full
(1,4)
Transmit end(1, 5)
TEND
Transmit data empty (1, 5, 6)
TDRE
RW
RW
—
RW
—
0 : No data in SSRDR register
1 : Data in SSRDR register
RW
0 : The TDRE bit is set to 0 w hen transmitting
the last bit of transmit data
1 : The TDRE bit is set to 1 w hen transmitting
the last bit of transmit data
RW
0 : Data is not transferred from registers SSTDR to
SSTRSR
1 : Data is transferred from registers SSTDR to
SSTRSR
RW
NOTES:
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0.
2. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set
_____
_____
to 1 if “L” is applied to the SCS pin input. Refer to 16.2.7 SCS Pin Control and Arbitration for more information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the
_____
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H” during
transfer, the CE bit is set to 1.
3. Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive
operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the
ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1.
4. The RDRF bit is set to 0 w hen reading out the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register.
6. The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled).
7. When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.7
SSSR Register
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SS Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSMR2
Bit Symbol
SSUMS
Address
After Reset
00BDh
00h
Bit Name
Function
Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode
1 : Four-w ire bus communication mode
chip select mode select bit(1)
_____
CSOS
SOOS
SCKOS
SCS pin open drain output
select bit
Serial data pin open output drain
select bit(1)
0 : CMOS output
1 : N-channel open-drain output
0 : CMOS output(5)
1 : N-channel open-drain output
SSCK pin open drain output
select bit
0 : CMOS output
1 :N-channel open-drain output
SCS pin select bits (2)
b5 b4
_____
0 0 : Functions
0 1 : Functions
1 0 : Functions
1 1 : Functions
CSS0
CSS1
SCKS
as
as
as
as
port
_____
SCS input pin
_____
SCS output pin(3)
_____
SCS output pin(3)
RW
RW
RW
RW
RW
RW
RW
SSCK pin select bit
0 : Functions as port
1 : Functions as serial clock pin
RW
Bidirectional mode enable bit(1, 4)
0 : Standard mode (communication using 2
pins of data input and data output)
1 : Bidirectional mode (communication using
1 pin of data input and data output)
RW
BIDE
NOTES:
1. Refer to 16.2.2.1 Association betw een Data I/O Pins and SS Shift Register for information on combinations of
data I/O pins.
_____
2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 w hen the SSUMS bit is set to 0
(clock synchronous communication mode).
3. This bit functions as the SCS input pin before starting transfer.
4. The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode).
5. The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0
(CMOS output).
Figure 16.8
SSMR2 Register
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16. Clock Synchronous Serial Interface
SS Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSTDR
Address
00BEh
After Reset
FFh
Function
RW
Store the transmit data.
The stored transmit data is transferred to the SSTRSR register and transmission is started
w hen it is detected that the SSTRSR register is empty.
When the next transmit data is w ritten to the SSTDR register during the data transmission from RW
the SSTRSR register, the data can be transmitted continuously.
When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in
w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
SS Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SSRDR
Address
00BFh
After Reset
FFh
Function
Store the receive data.(1)
The receive data is transferred to the SSRDR register and the receive operation is completed
w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive
operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
RW
RO
NOTE:
1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1
(overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be
discarded.
Figure 16.9
Registers SSTDR and SSRDR
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
PMR
Bit Symbol
INT1SEL
Address
00F8h
Bit Name
_____
INT1 pin select bit
After Reset
00h
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
RW
INT2 pin select bit
0 : Selects P6_6
1 : Selects P3_2
RW
Reserved bits
Set to 0.
UART1 enable bit
To use the UART1, set to 1.
Reserved bits
Set to 0.
SSU / I C bus sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
_____
INT2SEL
—
(b3-b2)
U1PINSEL
—
(b6-b5)
2
IICSEL
Figure 16.10
PMR Register
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Page 403 of 580
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
16.2.1
16. Clock Synchronous Serial Interface
Transfer Clock
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
16.2.1.1
Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 16.11 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
• SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd
edge), and CPOS bit = 0 (“H” when clock stops)
SSCK
SSO, SSI
b1
b0
b2
b3
b4
b5
b6
b7
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
SCS
• SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK
CPOS = 0
(“H” when clock stops)
SSCK
CPOS = 1
(“L” when clock stops)
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
SCS
CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register
Figure 16.11
Association between Transfer Clock Polarity, Phase, and Transfer Data
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R8C/2A Group, R8C/2B Group
16.2.2
16. Clock Synchronous Serial Interface
SS Shift Register (SSTRSR)
The SSTRSR register is a shift register for transmitting and receiving serial data.
When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the
SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR
register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the
SSTRSR register.
16.2.2.1
Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a
combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection
also changes according to the BIDE bit in the SSMR2 register.
Figure 16.12 shows the Association between Data I/O Pins and SSTRSR Register.
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 1 (operates as
master device)
• SSUMS = 0
(clock synchronous communication mode)
SSTRSR register
SSO
SSTRSR register
SSI
• SSUMS = 1 (4-wire bus communication mode),
BIDE = 0 (standard mode), and MSS = 0 (operates
as slave device)
SSTRSR register
SSO
SSI
• SSUMS = 1 (4-wire bus communication mode) and
BIDE = 1 (bidirectional mode)
SSTRSR register
SSI
Figure 16.12
Association between Data I/O Pins and SSTRSR Register
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SSO
SSO
SSI
R8C/2A Group, R8C/2B Group
16.2.3
16. Clock Synchronous Serial Interface
Interrupt Requests
Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end,
receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock
synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required.
Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests.
Table 16.3
Clock Synchronous Serial I/O with Chip Select Interrupt Requests
Interrupt Request
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
Abbreviation
TXI
TEI
RXI
OEI
CEI
Generation Condition
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
If the generation conditions in Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request
is generated. Set each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
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R8C/2A Group, R8C/2B Group
16.2.4
16. Clock Synchronous Serial Interface
Communication Modes and Pin Functions
Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication
mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register.
Table 16.4 shows the Association between Communication Modes and I/O Pins.
Table 16.4
Association between Communication Modes and I/O Pins
Communication Mode
Clock synchronous
communication mode
Bit Setting
SSUMS
BIDE
MSS
TE
0
Disabled 0
0
1
4-wire bus
communication mode
1
0
0
1
4-wire bus
1
(bidirectional)
communication mode(2)
1
0
1
RE
1
SSI
Input
1
0
0
1
1
1
0
0
1
1
1
0
Output
0
1
1
Output
Input
1
0
0
1
1
−(1)
Input
1
−(1)
Input
Input
−(1)
Input
−(1)
Pin State
SSO
−(1)
Output
Output
Page 408 of 580
Input
−(1)
Input
Output
Output
Output
Output
Input
Output
Input
−(1)
Input
Input
−(1)
Input
Output
Output
Output
−(1)
Output
Input
Output
Input
0
−(1)
Output
Input
0
1
−(1)
Input
Output
1
0
−(1)
Output
Output
NOTES:
1. This pin can be used as a programmable I/O port.
2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode.
SSUMS and BIDE: Bits in SSMR2 register
MSS: Bit in SSCRH register
TE and RE: Bits in SSER register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
SSCK
Input
R8C/2A Group, R8C/2B Group
16.2.5
16. Clock Synchronous Serial Interface
Clock Synchronous Communication Mode
16.2.5.1
Initialization in Clock Synchronous Communication Mode
Figure 16.13 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in
the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or
reception.
Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format.
Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR
register.
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 0
SSMR2 register
SSMR register
CPHS bit ← 0
CPOS bit ← 0
Set MLS bit
SSCRH register
SCKS bit ← 1
Set SOOS bit
SSMR2 register
SSCRH register
Set bits CKS0 to CKS2
Set RSSTP bit
SSSR register
SSER register
Set MSS bit
ORER bit ← 0(1)
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.13
Initialization in Clock Synchronous Communication Mode
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R8C/2A Group, R8C/2B Group
16.2.5.2
16. Clock Synchronous Serial Interface
Data Transmission
Figure 16.14 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode). During data transmission, the clock synchronous
serial I/O with chip select operates as described below.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and
data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized
with the input clock.
When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE
bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred
from registers SSTDR to SSTRSR.
After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When
the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is
transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and
transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND
bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted)
and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to
1 (transmit-end interrupt request enabled). The SSCK pin is fixed “H” after transmit-end.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
Figure 16.15 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at
odd numbers), and CPOS = 0 (“H” when clock stops)
SSCK
SSO
b0
b1
b7
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b1
b7
1 frame
TEI interrupt request
generation
0
TXI interrupt request generation
0
Processing
by program
Figure 16.14
b0
Write data to SSTDR register
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Transmission (Clock Synchronous Communication Mode)
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16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
Data
transmission
continues?
(2)
Yes
(2) Determine whether data transmission continues.
No
(3)
Read TEND bit in SSSR register
TEND = 1 ?
No
(3) When data transmission is completed, the TEND
bit is set to 1. Set the TEND bit to 0 and the TE bit
to 0 and complete transmit mode.
Yes
SSSR register
TEND bit ← 0(1)
SSER register
TE bit ← 0
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.15
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
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16.2.5.3
16. Clock Synchronous Serial Interface
Data Reception
Figure 16.16 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode).
During data reception, clock synchronous serial I/O with chip select operates as described below. When the
clock synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and
inputs data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data
synchronized with the input clock.
When clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts
receiving by performing dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is
automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm
that the ORER bit is set to 0 before restarting receive.
Figure 16.17 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode).
• SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at
even edges), and CPOS bit = 0 (“H” when clock stops)
SSCK
b7
b0
SSI
b0
b7
1
RSSTP bit in
SSCRH register
1
Processing
by program
Figure 16.16
b7
1 frame
1 frame
RDRF bit in
SSSR register
b0
0
RXI interrupt request
generation
RXI interrupt request
generation
RXI interrupt request
generation
0
Dummy read in
SSRDR register
Read data in SSRDR
register
Set RSSTP bit to 1
Read data in
SSRDR register
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data
Reception (Clock Synchronous Communication Mode)
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16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Dummy read of SSRDR register
(2)
Last data
received?
Yes
(1) After setting each register in the clock synchronous
serial I/O with chip select register, a dummy read of
the SSRDR register is performed and the receive
operation is started.
(2) Determine whether it is the last 1 byte of data to be
received. If so, set to stop after the data is received.
No
Read ORER bit in SSSR register
ORER = 1 ?
(3)
Yes
No
(3) If a receive error occurs, perform error
(6) Processing after reading the ORER bit. Then set
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
Read RDRF bit in SSSR register
(4)
No
(4) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
RDRF = 1 ?
Yes
Read receive data in SSRDR register
(5)
SSCRH register
(5)Before the last 1 byte of data is received, set the
RSSTP bit to 1 and stop after the data is
received.
RSSTP bit ← 1
Read ORER bit in SSSR register
ORER = 1 ?
(6)
Yes
No
Read RDRF in SSSR register
No
RDRF = 1 ?
(7)
Yes
SSCRH register
RSSTP bit ← 0
SSER register
RE bit ← 0
(7) Confirm that the RDRF bit is set to 1. When the
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
Overrun
error
processing
Read receive data in SSRDR register
End
Figure 16.17
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Mode)
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16.2.5.4
16. Clock Synchronous Serial Interface
Data Transmission/Reception
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is
transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 16.18 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
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16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ?
No
(1) After reading the SSSR register and confirming
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
Yes
Write transmit data to SSTDR register
(2)
Read RDRF bit in SSSR register
No
RDRF = 1 ?
(2) Confirm that the RDRF bit is set to 1. If the RDRF
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
Yes
Read receive data in SSRDR register
Data
transmission(2)
continues?
(3)
Yes
(3) Determine whether the data transmission
continues
No
(4)
Read TEND bit in SSSR register
TEND = 1 ?
(4) When the data transmission is completed, the
TEND bit in the SSSR register is set to 1.
No
Yes
(5)
(6)
SSSR register
TEND bit ← 0(1)
SSER register
RE bit ← 0
TE bit ← 0
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
receive mode.
End
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.18
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Communication Mode)
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16.2.6
16. Clock Synchronous Serial Interface
Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line,
and a chip select line is used for communication. This mode includes bidirectional mode in which the data input
line and data output line function as a single pin.
The data input line and output line change according to the settings of the MSS bit in the SSCRH register and
the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS
Shift Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in
the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and
Data.
When this MCU is set as the master device, the chip select line controls output. When clock synchronous serial
I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master
device, the chip select line controls output of the SCS pin or controls output of a general port according to the
setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets
the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b.
In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is
performed MSB-first.
16.2.6.1
Initialization in 4-Wire Bus Communication Mode
Figure 16.19 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive
operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0
(receive disabled), and initialize the clock synchronous serial I/O with chip select.
To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change.
Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR
register.
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16. Clock Synchronous Serial Interface
Start
RE bit ← 0
TE bit ← 0
SSER register
SSUMS bit ← 1
SSMR2 register
(1)
SSMR register
Set bits CPHS and CPOS
MLS bits ← 0
SSCRH register
SSMR2 register
(2)
SSCRH register
Set MSS bit
SCKS bit ← 1
Set bits SOOS, CSS0 to
CSS1, and BIDE
(2) Set the BIDE bit to 1 in bidirectional mode and
set the I/O of the SCS pin by bits CSS0 and
CSS1.
Set bits CKS0 to CKS2
Set RSSTP bit
ORER bit ← 0(1)
SSSR register
SSER register
(1) The MLS bit is set to 0 for MSB-first transfer.
The clock polarity and phase are set by bits
CPHS and CPOS.
RE bit ← 1 (receive)
TE bit ← 1 (transmit)
Set bits RIE, TEIE, and TIE
End
NOTE:
1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.19
Initialization in 4-Wire Bus Communication Mode
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16.2.6.2
16. Clock Synchronous Serial Interface
Data Transmission
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous
serial I/O with chip select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a
slave device, it outputs data in synchronization with the input clock while the SCS pin is “L”.
When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the
TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the
data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from
registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI
interrupt request is generated.
After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR
to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1,
TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set
to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests
enabled), a TEI interrupt request is generated. The SSCK pin remains “H” after transmit-end and the SCS pin is
held “H”. When transmitting continuously while the SCS pin is held “L”, write the next transmit data to the
SSTDR register before transmitting the 8th bit.
Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm
that the ORER bit is set to 0 before transmission.
In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while
the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in
high-impedance state while the SCS pin is placed in “H” input state when operating as a slave device.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.15
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
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16. Clock Synchronous Serial Interface
• CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
SSO
b6
b7
b7
b0
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request is
generated
TXI interrupt request is
generated
0
Data write to SSTDR register
Processing
by program
• CPHS bit = 1 (data change at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
b7
SSO
b6
1 frame
TDRE bit in
SSSR register
1
TEND bit in
SSSR register
1
b0
b7
b6
b0
1 frame
TEI interrupt request is
generated
0
TXI interrupt request is
generated
TXI interrupt request is
generated
0
Processing
by program
Data write to SSTDR register
CPHS, CPOS: Bits in SSMR register
Figure 16.20
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Transmission (4-Wire Bus Communication Mode)
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16.2.6.3
16. Clock Synchronous Serial Interface
Data Reception
Figure 16.21 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip
select operates as described below.
When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is
set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives “L” input.
When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a
dummy read of the SSRDR register.
After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and
receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI
interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF
bit is automatically set to 0 (no data in the SSRDR register).
Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the
receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8
bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to
0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR
register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again.
When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun
error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed.
Confirm that the ORER bit is set to 0 before restarting reception.
The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the
SSMR register. Figure 16.21 shows when bits RDRF and ORER are set to 1.
When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some
point during the frame.
The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.17
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
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16. Clock Synchronous Serial Interface
• CPHS bit = 0 (data download at even edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
SSI
b0
b7
b7
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
b7
b0
b0
1 frame
0
RXI interrupt request
is generated
0
Data read in SSRDR
register
Dummy read in
SSRDR register
Processing
by program
RXI interrupt request
is generated
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
• CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 (“H” when clock stops)
High-impedance
SCS
(output)
SSCK
b7
SSI
b0
b7
1 frame
RDRF bit in
SSSR register
1
RSSTP bit in
SSCRH register
1
Processing
by program
b0
b7
b0
1 frame
0
RXI interrupt request
is generated
RXI interrupt request
is generated
0
Dummy read in
SSRDR register
Data read in SSRDR
register
Set RSSTP
bit to 1
RXI interrupt request
is generated
Data read in SSRDR
register
CPHS and CPOS: Bit in SSMR register
Figure 16.21
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data
Reception (4-Wire Bus Communication Mode)
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16.2.7
16. Clock Synchronous Serial Interface
SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in
the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as
the master device) and check the arbitration of the SCS pin before starting serial transfer. If clock synchronous
serial I/O with chip select detects that the synchronized internal SCS signal is held “L” in this period, the CE bit
in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave
device).
Figure 16.22 shows the Arbitration Check Timing.
Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error)
before starting transmission.
SCS input
Internal SCS
(synchronization)
MSS bit in
SSCRH register
1
0
Transfer start
Data write to
SSTDR register
CE
High-impedance
SCS output
Maximum time of SCS internal
synchronization
During arbitration detection
Figure 16.22
Arbitration Check Timing
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16.2.8
16. Clock Synchronous Serial Interface
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
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16.3
16. Clock Synchronous Serial Interface
I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I2C bus.
Table 16.5 lists the I2C bus Interface Specifications, Figure 16.23 shows a Block Diagram of I2C bus interface, and
Figure 16.24 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.25 to 16.33 show
the registers associated with the I2C bus interface.
* I2C bus is a trademark of Koninklijke Philips Electronics N. V.
Table 16.5
I2C bus Interface Specifications
Item
Specification
2
Communication formats • I C bus format
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
- Start/stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
- Support for direct drive of pins SCL and SDA (N-channel open-drain output)
• Clock synchronous serial format
- Continuous transmit/receive operation (because the shift register, transmit
data register, and receive data register are independent)
I/O pins
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks
• When the MST bit in the ICCR1 register is set to 0
The external clock (input from the SCL pin)
• When the MST bit in the ICCR1 register is set to 1
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Receive error detection • Overrun error detection (clock synchronous serial format)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
Interrupt sources
• I2C bus format .................................. 6 sources(1)
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
• Clock synchronous serial format ...... 4 sources(1)
Transmit data empty, transmit ends, receive data full and overrun error
Select functions
• I2C bus format
- Selectable output level for acknowledge signal during reception
• Clock synchronous serial format
- MSB-first or LSB-first selectable as data transfer direction
NOTE:
1. All sources use one interrupt vector for I2C bus interface.
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16. Clock Synchronous Serial Interface
f1
Transfer clock
generation
circuit
SCL
Output
control
ICCR1 register
Transmit/receive
control circuit
Noise
canceller
ICCR2 register
ICMR register
ICDRT register
SAR register
Output
control
ICDRS register
Noise
canceller
Address comparison
circuit
Data bus
SDA
ICDRR register
Bus state judgment
circuit
Arbitration judgment
circuit
ICSR register
ICIER register
Interrupt generation
circuit
Interrupt request
(TXI, TEI, RXI, STPI, NAKI)
Figure 16.23
Block Diagram of I2C bus interface
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16. Clock Synchronous Serial Interface
VCC
VCC
SCL
SCL
SDA
SDA
SCL input
SCL output
SDA input
SDA output
SCL
(Master)
SCL input
SCL input
SCL output
SCL output
SDA input
SDA
SDA output
(Slave 1)
Figure 16.24
SCL
SDA
SDA input
SDA output
(Slave 2)
External Circuit Connection Example of Pins SCL and SDA
Module Operation Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0008h
MSTCR
Bit Symbol
Bit Name
Nothing is assigned. If necessary, set to 0.
—
When read, the content is 0.
(b2-b0)
MSTTRD
MSTTRC
—
(b7-b6)
RW
—
SSU, I C bus operation enable bit
0: Disable
1: Enable
RW
Timer RD operation enable bit
0: Disable
1: Enable
RW
Timer RC operation enable bit
0: Disable
1: Enable
RW
2
MSTIIC
After Reset
00h
Function
(1)
(2)
(3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
NOTES:
1. When the MSTIIC bit is set to 0 (disable), any access to the SSU or the I2C bus associated registers (addresses
00B8h to 00BFh) is disabled.
2. When the MSTTRD bit is set to 0 (disable), any access to the timer RD associated registers (addresses 0137h to
015Fh) is disabled.
3. When the MSTTRC bit is set to 0 (disable), any access to the timer RC associated registers (addresses 0120h to
0132h) is disabled.
Figure 16.25
MSTCR Register
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—
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICCR1
Bit Symbol
CKS0
CKS1
CKS2
CKS3
TRS
Address
00B8h
Bit Name
Transmit clock select bits 3 to b3 b2 b1 b0
0 0 0 0 : f1/28
0(1)
0 0 0 1 : f1/40
0 0 1 0 : f1/48
0 0 1 1 : f1/64
0 1 0 0 : f1/80
0 1 0 1 : f1/100
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
1 1 1 0 : f1/224
1 1 1 1 : f1/256
Transfer/receive select
bit(2, 3, 6)
Master/slave select bit(5, 6)
MST
Receive disable bit
RCVD
IIC bus interface enable bit
ICE
After Reset
00h
Function
RW
RW
RW
RW
RW
b5 b4
0 0 : Slave Receive Mode(4)
0 1 : Slave Transmit Mode
1 0 : Master Receive Mode
1 1 : Master Transmit Mode
RW
RW
After reading the ICDRR register w hile the TRS bit
is set to 0
0 : Maintains the next receive operation
1 : Disables the next receive operation
RW
0 : This module is halted
(Pins SCL and SDA are set to port function)
1 : This module is enabled for transfer
operations
(Pins SCL and SDA are bus drive state)
RW
NOTES:
1. Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Exam ples for the
transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode. The time is 10Tcyc
w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
2. Rew rite the TRS bit betw een transfer frames.
3. When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
4. In master mode w ith the I2C bus format, w hen arbitration is lost, bits MST and TRS are set to 0
and the IIC enters slave receive mode.
5. When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit
is set to 0 and the IIC enters slave receive mode.
6. In multimaster operation use the MOV instruction to set bits TRS and MST.
Figure 16.26
ICCR1 Register
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
00B9h
ICCR2
Bit Symbol
Bit Name
—
Nothing is assigned. If necessary, set to 0.
(b0)
When read, the content is 1.
IIC control part reset bit
IICRST
—
(b2)
SCLO
SDAOP
SDAO
SCP
After Reset
01111101b
Function
When hang-up occurs due to communication failure
during I2C bus interface operation, w rite 1, to reset the
control block of the I2C bus interface w ithout setting
ports or initializing registers.
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
RW
—
0 : SCL pin is set to “L”
1 : SCL pin is set to “H”
RO
SDAO w rite protect bit
When rew rite to SDAO bit, w rite 0 simultaneously (1).
When read, the content is 1.
RW
SDA output value control When read
bit
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w ritten(1,2)
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
(“H” output via external pull-up resistor)
RW
Start/stop condition
generation disable bit
When w riting to the to BBSY bit, w rite 0
simultaneously (3).
When read, the content is 1.
Writing 1 is invalid.
RW
Bus busy bit(4)
When read
0 : Bus is in released state
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
1 : Bus is in occupied state
(SDA signal changes from “H” to “L” w hile SCL
signal is in “H” state)
When w ritten(3)
0 : Generates stop condition
1 : Generates start condition
RW
NOTES:
1. When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
2. Do not w rite during a transfer operation.
3. This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
4. This bit is disabled w hen the clock synchronous serial format is used.
ICCR2 Register
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
—
SCL monitor flag
BBSY
Figure 16.27
RW
Page 428 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
IIC bus Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ICMR
Bit Symbol
Address
00BAh
Bit Name
Bits counter 2 to 0
After Reset
00011000b
Function
I2C bus format (remaining transfer bit count w hen
read out and data bit count of next transfer w hen
w ritten) (1,2).
RW
b2 b1 b0
0 0 0 : 9 bits (3)
0 0 1 : 2 bits
0 1 0 : 3 bits
0 1 1 : 4 bits
1 0 0 : 5 bits
1 0 1 : 6 bits
1 1 0 : 7 bits
1 1 1 : 8 bits
Clock synchronous serial format (w hen read, the
remaining transfer bit count and w hen w ritten
000b).
BC0
BC1
RW
RW
b2 b1 b0
0 0 0 : 8 bits
0 0 1 : 1 bit
0 1 0 : 2 bits
0 1 1 : 3 bits
1 0 0 : 4 bits
1 0 1 : 5 bits
1 1 0 : 6 bits
1 1 1 : 7 bits
BC2
BC w rite protect bit
BCWP
When rew riting bits BC0 to BC2, w rite 0
simultaneously (2,4).
When read, the content is 1.
—
(b4)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
(b5)
Reserved bit
Set to 0.
Wait insertion bit
(5)
WAIT
MLS
MSB-first/LSB-first select
bit
ICMR Register
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RW
—
RW
0 : No w ait
(Transfer data and acknow ledge bit
consecutively)
1 : Wait
(After the clock falls for the final
data bit, “L” period is extended for tw o
transfer clocks cycles)
RW
0 : Data transfer w ith MSB-first(6)
1 : Data transfer w ith LSB-first
RW
NOTES:
1. Rew rite betw een transfer frames. When w riting values other than 000b, w rite w hen the SCL signal is “L”.
2. When w riting to bits BC0 to BC2, w rite 0 to the BCWP bit using the MOV instruction.
3. After data including the acknow ledge bit is transferred, these bits are automatically set to 000b. When the start
condition is detected, these bits are automatically set to 000b.
4. Do not rew rite w hen the clock synchronous serial format is used.
5. The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C
bus format or w hen the clock synchronous serial format is used.
6. Set to 0 w hen the I2C bus format is used.
Figure 16.28
RW
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
IIC bus Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICIER
Bit Symbol
ACKBT
Address
00BBh
Bit Name
Transmit acknow ledge
select bit
After Reset
00h
Function
0 : 0 is transmitted as acknow ledge bit in
receive mode.
1 : 1 is transmitted as acknow ledge bit in
receive mode.
Receive acknow ledge bit
0 : Acknow ledge bit received from
receive device in transmit mode is set to 0.
1 : Acknow ledge bit received from
receive device in transmit mode is set to 1.
ACKBR
ACKE
Acknow ledge bit judgment 0 : Value of receive acknow ledge bit is ignored
select bit
and continuous transfer is performed.
1 : When receive acknow ledge bit is set to 1,
continuous transfer is halted.
RW
RW
RO
RW
Stop condition detection
interrupt enable bit
0 : Disables stop condition detection interrupt
request
1 : Enables stop condition detection interrupt
request(2)
RW
NACK receive interrupt
enable bit
0 : Disables NACK receive interrupt request and
arbitration lost/overrun error interrupt request
1 : Enables NACK receive interrupt request and
arbitration lost/overrun error interrupt request(1)
RW
Receive interrupt enable
bit
0 : Disables receive data full and overrun
error interrupt request
1 : Enables receive data full and overrun
error interrupt request(1)
RW
TEIE
Transmit end interrupt
enable bit
0 : Disables transmit end interrupt request
1 : Enables transmit end interrupt request
RW
TIE
Transmit interrupt enable
bit
0 : Disables transmit data empty interrupt request
1 : Enables transmit data empty interrupt request
RW
STIE
NAKIE
RIE
NOTES:
1. An overrun error interrupt request is generated w hen the clock synchronous format is used.
2. Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set
to 0.
Figure 16.29
ICIER Register
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16. Clock Synchronous Serial Interface
IIC bus Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICSR
Bit Symbol
ADZ
AAS
Address
00BCh
Bit Name
General call address
recognition flag(1,2)
Slave address recognition This flag is set to 1 w hen the first frame follow ing
start condition matches bits SVA0 to SVA6 in the
flag(1)
SAR register in slave receive mode. (Detect the
slave address and generate call address)
RDRF
RW
RW
RW
When the stop condition is detected after the frame
is transferred, this flag is set to 1.
RW
No acknow ledge detection When no acknow ledge is detected from the receive
flag(1,4)
device after transmission, this flag is set to 1.
RW
Receive data register
full(1,5)
When receive data is transferred from in registers
ICDRS to ICDRR , this flag is set to 1.
RW
Transmit end(1,6)
When the 9th clock cycle of the SCL signal in the I2C
bus format occurs w hile the TDRE bit is set to 1, this
flag is set to 1.
This flag is set to 1 w hen the final bit of the transmit
frame is transmitted in the clock synchronous format.
RW
In the follow ing cases, this flag is set to 1.
• Data is transferred from registers ICDRT to ICDRS
and the ICDRT register is empty
• When setting the TRS bit in the ICCR1
register to 1 (transmit mode)
• When generating the start condition
(including retransmit)
• When changing from slave receive mode to
slave transmit mode
RW
AL
NACKF
RW
When the I2C bus format is used, this flag indicates
that arbitration has been lost in master mode. In the
follow ing cases, this flag is set to 1(3).
• When the internal SDA signal and SDA pin
level do not match at the rise of the SCL signal
in master transmit mode
• When the start condition is detected and the
SDA pin is held “H” in master transmit/receive
mode
This flag indicates an overrun error w hen the clock
synchronous format is used.
In the follow ing case, this flag is set to 1.
• When the last bit of the next data item is
received w hile the RDRF bit is set to 1
Arbitration lost
flag/overrun error flag(1)
STOP
After Reset
0000X000b
Function
When the general call address is detected, this flag
is set to 1.
Stop condition detection
flag(1)
TEND
Transmit data empty (1,6)
TDRE
NOTES:
1. Each bit is set to 0 by reading 1 before w riting 0.
2. This flag is enabled in slave receive mode of the I2C bus format.
3. When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface
monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the
bus is occupied by another master.
4. The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is
set to 1, transfer is halted).
5. The RDRF bit is set to 0 w hen reading data from the ICDRR register.
6. Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register.
7. When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to
access it.
Figure 16.30
ICSR Register
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Slave Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SAR
Bit Symbol
FS
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
Address
00BDh
Bit Name
Format select bit
Slave address 6 to 0
After Reset
00h
Function
0 : I2C bus format
1 : Clock synchronous serial format
Set an address different from that of the other
slave devices w hich are connected to the I2C
bus. When the 7 high-order bits of the first frame
transmitted after the starting condition match bits
SVA0 to SVA6 in slave mode of the I2C bus
format, the MCU operates as a slave device.
RW
RW
RW
RW
RW
RW
RW
RW
RW
IIC bus Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRT
Address
00BEh
After Reset
FFh
Function
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Figure 16.31
Registers SAR and ICDRT
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REJ09B0324-0200
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RW
RW
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
IIC bus Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRR
Address
00BFh
After Reset
FFh
Function
Store receive data
When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR
register and the next receive operation is enabled.
RW
RO
IIC bus Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ICDRS
Function
This register is used to transmit and receive data.
The transmit data is transferred from registers ICRDT to the ICDRS and data is transmitted
from the SDA pin w hen transmitting.
After 1 byte of data received, data is transferred from registers ICDRS to ICDRR w hile
receiving.
Figure 16.32
RW
—
Registers ICDRR and ICDRS
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0
Symbol
PMR
Bit Symbol
INT1SEL
Address
00F8h
Bit Name
_____
INT1 pin select bit
After Reset
00h
Function
0 : Selects P1_5, P1_7
1 : Selects P3_6
RW
INT2 pin select bit
0 : Selects P6_6
1 : Selects P3_2
RW
Reserved bits
Set to 0.
UART1 enable bit
To use the UART1, set to 1.
Reserved bits
Set to 0.
SSU / I2C bus sw itch bit
0 : Selects SSU function
1 : Selects I2C bus function
_____
INT2SEL
—
(b3-b2)
U1PINSEL
—
(b6-b5)
IICSEL
Figure 16.33
PMR Register
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RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
16.3.1
16. Clock Synchronous Serial Interface
Transfer Clock
When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL
pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits
CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin.
Table 16.6 lists the Transfer Rate Examples.
Table 16.6
Transfer Rate Examples
ICCR1 Register
Transfer
Transfer Rate
CKS3 CKS2 CKS1 CKS0 Clock f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz
0
0
0
0
f1/28
179 kHz
286 kHz
357 kHz
571 kHz
714 kHz
1
f1/40
125 kHz
200 kHz
250 kHz
400 kHz
500 kHz
1
0
f1/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz
1
f1/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
1
0
0
f1/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
f1/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
1
0
f1/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
f1/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
1
0
0
0
f1/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
f1/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
0
f1/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
f1/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
1
0
0
f1/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
f1/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
1
0
f1/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
f1/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
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R8C/2A Group, R8C/2B Group
16.3.2
16. Clock Synchronous Serial Interface
Interrupt Requests
I2 C
The
bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests
when the clock synchronous serial format is used.
Table 16.7 lists the Interrupt Requests of I2C bus Interface.
Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source
bit by bit is necessary.
Table 16.7
Interrupt Requests of I2C bus Interface
Format
Interrupt Request
Transmit data empty
Transmit ends
Receive data full
Stop condition detection
NACK detection
Arbitration lost/overrun error
Generation Condition
TXI
TEI
RXI
STPI
NAKI
TIE = 1 and TDRE = 1
TEIE = 1 and TEND = 1
RIE = 1 and RDRF = 1
STIE = 1 and STOP = 1
NAKIE = 1 and AL = 1 (or
NAKIE = 1 and NACKF = 1)
I2C bus
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Clock
Synchronous
Serial
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register
When the generation conditions listed in Table 16.7 are met, an I2C bus interface interrupt request is generated.
Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, bits TDRE and
TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is
automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the
TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by
further setting the TDRE bit to 0, 1 additional byte may be transmitted.
Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
I2C bus Interface Mode
16.3.3
I2C bus Format
16.3.3.1
Setting the FS bit in the SAR register to 0 enables communication in I2C bus format.
Figure 16.34 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of
8 bits.
(1) I2C bus format
(a) I2C bus format (FS = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
Transfer bit count (n = 1 to 8)
m
Transfer frame count (m = from 1)
(b) I2C bus format (when start condition is retransmitted, FS = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
1
m1
m2
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
(2) I2C bus timing
SDA
SCL
1 to 7
S
SLA
8
R/W
9
1 to 7
A
8
DATA
9
1 to 7
A
8
DATA
9
A
Explanation of symbols
S
: Start condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
SLA : Slave address
R/W : Indicates the direction of data transmit/receive
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
R/W value is 0.
A
: Acknowledge
The receive device sets the SDA signal to “L”.
DATA : Transmit / receive data
P
: Stop condition
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
Figure 16.34
I2C bus Format and Bus Timing
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P
R8C/2A Group, R8C/2B Group
16.3.3.2
16. Clock Synchronous Serial Interface
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.35 and 16.36 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1
(transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to
CKS3 in the ICCR1 register (initial setting).
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the
ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit
and 0 to the SCP bit by the MOV instruction.
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers
ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W
are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred
from registers ICDRT to ICDRS, and the TDRE bit is set to 1 again.
(4) When transmission of 1 byte of data is completed while the TDRE bit is set to 1, the TEND bit in the
ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER
register, and confirm that the slave is selected. Write the 2nd byte of data to the ICDRT register. Since
the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The
stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV
instruction. The SCL signal is held “L” until data is available and the stop condition is generated.
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is
set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to
1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive
acknowledge bit is set to 1, transfer is halted). Then generate the stop condition before setting bits
TEND and NACKF to 0.
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
SCL
(master output)
1
2
3
4
5
6
7
8
SDA
(master output)
b7
b6
b5
b4
b3
b2
b1
b0
Slave address
9
TEND bit in
ICSR register
b6
1
0
1
0
Address + R/W
Data 1
Address + R/W
ICDRS register
(2) Instruction of
start condition
generation
Processing
by program
(3) Data write to ICDRT
register (1st byte)
Data 2
Data 1
(5) Data write to ICDRT
register (3rd byte)
(4) Data write to ICDRT
register (2nd byte)
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)
SCL
(master output)
9
SDA
(master output)
SDA
(slave output)
TDRE bit in
ICSR register
TEND bit in
ICSR register
1
2
3
4
5
6
7
8
b7
b6
b5
b4
b3
b2
b1
b0
A
9
A/A
1
0
1
0
ICDRT register
Data n
ICDRS register
Processing
by program
Figure 16.36
b7
A
ICDRT register
Figure 16.35
2
R/W
SDA
(slave output)
TDRE bit in
ICSR register
1
Data n
(3) Data write to ICDRT
register
(6) Generate stop condition and
set TEND bit to 0
(7) Set to slave receive mode
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
16.3.3.3
16. Clock Synchronous Serial Interface
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 16.37 and 16.38 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR
register to 0.
(2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive
clock is output in synchronization with the internal clock and data is received. The master device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th
clock cycle of the receive clock.
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the
RDRF bit is set to 0 simultaneously.
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set
to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit
is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables
the next receive operation) before reading the ICDRR register, stop condition generation is enabled after
the next receive operation.
(6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0
(maintain the following receive operation).
(8) Return to slave receive mode.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Master transmit mode
SCL
(master output)
Master receive mode
9
1
2
3
4
5
6
7
8
SDA
(master output)
TEND bit in
ICSR register
TRS bit in
ICCR1 register
RDRF bit in
ICSR register
A
b7
b6
b5
b4
b3
b2
b1
b7
b0
1
0
1
0
1
0
1
0
ICDRS register
Data 1
ICDRR register
Processing
by program
Figure 16.37
1
A
SDA
(slave output)
TDRE bit in
ICSR register
9
Data 1
(1) Set TEND and TRS bits to 0 before
setting TDRE bits to 0
(2) Read ICDRR register
(3) Read ICDRR register
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 440 of 580
R8C/2A Group, R8C/2B Group
SCL
(master output)
9
SDA
(master output)
A
SDA
(slave output)
RDRF bit in
ICSR register
RCVD bit in
ICCR1 register
16. Clock Synchronous Serial Interface
1
2
3
4
5
6
7
8
9
A/A
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
ICDRS register
Data n-1
Data n
Data n-1
ICDRR register
Processing
by program
(5) Set RCVD bit to 1 before
reading ICDRR register
Data n
(6) Stop condition
generation
(7) Read ICDRR register before
setting RCVD bit to 0
(8) Set to slave receive mode
Figure 16.38
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 441 of 580
R8C/2A Group, R8C/2B Group
16.3.3.4
16. Clock Synchronous Serial Interface
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive
clock and returns an acknowledge signal.
Figures 16.39 and 16.40 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode).
The transmit procedure and operation in slave transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1,
and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by
writing transmit data to the ICDRT register every time the TDRE bit is set to 1.
(3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT
register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the
TEND bit is set to 1, set the TEND bit to 0.
(4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR
register to end the process.
(5) Set the TDRE bit to 0.
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R8C/2A Group, R8C/2B Group
Slave receive mode
SCL
(master output)
16. Clock Synchronous Serial Interface
Slave transmit mode
9
1
2
3
4
5
6
7
8
1
9
SDA
(master output)
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
TEND bit in
ICSR register
TRS bit in
ICCR1 register
A
b6
b7
b5
b4
b3
b2
b1
b7
b0
1
0
1
0
1
0
ICDRT register
Data 1
ICDRS register
Data 3
Data 2
Data 1
Data 2
ICDRR register
(1) Data write to ICDRT
register (data 1)
Processing
by program
Figure 16.39
(2) Data write to ICDRT
register (data 2)
(2) Data write to ICDRT
register (data 3)
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
Rev.2.00 Nov 26, 2007
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Page 443 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Slave receive
mode
Slave transmit mode
SCL
(master output)
9
SDA
(master output)
A
1
2
3
4
5
6
7
8
9
A
SCL
(slave output)
SDA
(slave output)
TDRE bit in
ICSR register
TEND bit in
ICSR register
TRS bit in
ICCR1 register
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
1
0
ICDRT register
Data n
Data n
ICDRS register
ICDRR register
Processing
by program
Figure 16.40
(3) Set the TEND bit to 0
(4) Dummy read of ICDRR register
after setting TRS bit to 0
(5) Set TDRE bit to 0
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 444 of 580
R8C/2A Group, R8C/2B Group
16.3.3.5
16. Clock Synchronous Serial Interface
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 16.41 and 16.42 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode).
The receive procedure and operation in slave receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the
ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in
the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock
cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy read (the
read data is unnecessary because it indicates the slave address and R/W).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the
RDRF bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of
the acknowledge signal returned to the master device before reading the ICDRR register takes affect
from the following transfer frame.
(4) Reading the last byte is performed by reading the ICDRR register in like manner.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
SCL
(master output)
16. Clock Synchronous Serial Interface
9
1
SDA
(master output)
2
3
b6
b7
4
5
b4
b5
6
7
b2
b3
8
b7
b0
b1
1
9
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Processing
by program
Figure 16.41
Data 1
(2) Read ICDRR register
(2) Dummy read of ICDRR register
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1)
SCL
(master output)
1
9
SDA
(master output)
b7
2
3
b6
b5
4
5
b4
b3
6
b2
7
b1
8
9
b0
SCL
(slave output)
SDA
(slave output)
RDRF bit in
ICSR register
A
A
1
0
ICDRS register
Data 2
Data 1
ICDRR register
Processing
by program
Figure 16.42
Data 1
(3) Set ACKBT bit to 1
(3) Read ICDRR register
(4) Read ICDRR register
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
16.3.4
16. Clock Synchronous Serial Interface
Clock Synchronous Serial Mode
16.3.4.1
Clock Synchronous Serial Format
Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication.
Figure 16.43 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during transfer standby.
SCL
SDA
Figure 16.43
b0
b1
b2
b3
b4
b5
Transfer Format of Clock Synchronous Serial Format
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 447 of 580
b6
b7
R8C/2A Group, R8C/2B Group
16.3.4.2
16. Clock Synchronous Serial Interface
Transmit Operation
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the
transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when
the MST bit is set to 0.
Figure 16.44 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the
ICCR1 register to 1.
(3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by
writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous
transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When
switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SCL
1
SDA
(output)
TRS bit in
ICCR1 register
TDRE bit in
ICSR register
b0
b1
b6
8
b7
1
b0
7
b6
8
1
b7
b0
1
0
1
0
ICDRT register
Data 2
Data 1
ICDRS register
Processing
by program
7
2
Data 1
(3) Data write to
ICDRT register
Data 3
Data 3
Data 2
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(3) Data write to
ICDRT register
(2) Set TRS bit to 1
Figure 16.44
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
16.3.4.3
16. Clock Synchronous Serial Interface
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.45 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
ICCR1 register and set the MST bit (initial setting).
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
output.
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
SCL
1
SDA
(input)
MST bit in
ICCR1 register
TRS bit in
ICCR1 register
RDRF bit in
ICSR register
b0
2
b1
b7
1
b0
7
b6
8
1
b7
2
b0
0
1
0
1
0
Data 1
Data 2
Data 1
ICDRR register
Figure 16.45
b6
8
1
ICDRS register
Processing
by program
7
(2) Set MST bit to 1
(when transfer clock is output)
(3) Read ICDRR register
Data 3
Data 2
(3) Read ICDRR register
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 449 of 580
R8C/2A Group, R8C/2B Group
16.3.5
16. Clock Synchronous Serial Interface
Examples of Register Setting
Figures 16.46 to 16.49 show Examples of Register Setting When Using I2C bus interface.
Start
• Set the STOP bit in the ICSR register to 0.
• Set the IICSEL bit in the PMR register to 1.
• Set the MSTIIC bit in the MSTCR register to 1.
Initial setting
Read BBSY bit in ICCR2 register
No
(1) Judge the state of the SCL and SDA lines
(1)
BBSY = 0 ?
(2) Set to master transmit mode
(3) Generate the start condition
Yes
ICCR1 register
TRS bit ← 1
MST bit ← 1
(2)
ICCR2 register
SCP bit ← 0
BBSY bit ← 1
(3)
(4) Set the transmit data of the 1st byte
(slave address + R/W)
(5) Wait for 1 byte to be transmitted
Write transmit data to ICDRT register
(4)
(6) Judge the ACKBR bit from the specified slave device
(7) Set the transmit data after 2nd byte (except the last byte)
(8) Wait until the ICRDT register is empty
Read TEND bit in ICSR register
(9) Set the transmit data of the last byte
No
(5)
TEND = 1 ?
(10) Wait for end of transmission of the last byte
(11) Set the TEND bit to 0
Yes
Read ACKBR bit in ICIER register
(12) Set the STOP bit to 0
(13) Generate the stop condition
ACKBR = 0 ?
No
(6)
(15) Set to slave receive mode
Set the TDRE bit to 0
Yes
Transmit
mode ?
(14) Wait until the stop condition is generated
No
Master receive
mode
Yes
Write transmit data to ICDRT register
(7)
Read TDRE bit in ICSR register
No
(8)
TDRE = 1 ?
Yes
No
Last byte ?
(9)
Yes
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
(10)
TEND = 1 ?
Yes
ICSR register
TEND bit ← 0
(11)
ICSR register
STOP bit ← 0
(12)
ICCR2 register
SCP bit ← 0
BBSY bit ← 0
(13)
Read STOP bit in ICSR register
No
(14)
STOP = 1 ?
Yes
ICCR1 register
ICSR register
TRS bit ← 0
MST bit ← 0
(15)
TDRE bit ← 0
End
Figure 16.46
Example of Register Setting in Master Transmit Mode (I2C bus Interface Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 450 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Master receive mode
TEND bit ← 0
ICSR register
TRS bit ← 0
ICCR1 register
ICSR register
TDRE bit ← 0
ICIER register
ACKBT bit ← 0
Dummy read in ICDRR register
(1) Set the TEND bit to 0 and set to master receive mode.
Set the TDRE bit to 0 (1,2)
(1)
(2) Set the ACKBT bit to the transmit device (1)
(3) Dummy read the ICDRR register(1)
(2)
(3)
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable
continuous receive operation (RCVD = 1)(2)
Read RDRF bit in ICSR register
No
(4)
RDRF = 1 ?
(8) Read the receive data of (last byte - 1)
(9) Wait until the last byte is received
Yes
(10) Set the STOP bit to 0
Last receive
-1?
Yes
(5)
(12) Wait until the stop condition is generated
No
Read ICDRR register
(11) Generate the stop condition
(6)
(13) Read the receive data of the last byte
(14) Set the RCVD bit to 0
ACKBT bit ← 1
ICIER register
(7)
ICCR1 register
(15) Set to slave receive mode
RCVD bit ← 1
Read ICDRR register
(8)
Read RDRF bit in ICSR register
No
RDRF = 1 ?
(9)
Yes
STOP bit ← 0
ICSR register
SCP bit ← 0
BBSY bit ← 0
ICCR2 register
(10)
(11)
Read STOP bit in ICSR register
(12)
No
STOP = 1 ?
Yes
Read ICDRR register
(13)
ICCR1 register
RCVD bit ← 0
(14)
ICCR1 register
MST bit ← 0
(15)
End
NOTES:
1. Do not generate the interrupt while processing steps (1) to (3).
2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.47
Example of Register Setting in Master Receive Mode (I2C bus Interface Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 451 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Slave transmit mode
AAS bit ← 0
ICSR register
(1)
(1) Set the AAS bit to 0
(2) Set the transmit data (except the last byte)
Write transmit data to ICDRT register
(2)
(3) Wait until the ICRDT register is empty
(4) Set the transmit data of the last byte
Read TDRE bit in ICSR register
(5) Wait until the last byte is transmitted
No
TDRE = 1 ?
(3)
(7) Set to slave receive mode
Yes
No
(6) Set the TEND bit to 0
(8) Dummy read the ICDRR register to release the
SCL signal
Last byte ?
(4)
Yes
(9) Set the TDRE bit to 0
Write transmit data to ICDRT register
Read TEND bit in ICSR register
No
TEND = 1 ?
ICSR register
ICCR1 register
Yes
TEND bit ← 0
(6)
TRS bit ← 0
(7)
Dummy read in ICDRR register
ICSR register
(5)
TDRE bit ← 0
(8)
(9)
End
Figure 16.48
Example of Register Setting in Slave Transmit Mode (I2C bus Interface Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 452 of 580
R8C/2A Group, R8C/2B Group
16. Clock Synchronous Serial Interface
Slave receive mode
AAS bit ← 0
(1)
ICIER register ACKBT bit ← 0
(2)
ICSR register
(1) Set the AAS bit to 0 (1)
(2) Set the ACKBT bit to the transmit device
(3) Dummy read the ICDRR register
Dummy read ICDRR register
(3)
(4) Wait until 1 byte is received
(5) Judge (last receive - 1)
Read RDRF bit in ICSR register
(6) Read the receive data
No
(4)
RDRF = 1 ?
(7) Set the ACKBT bit of the last byte(1)
(8) Read the receive data of (last byte - 1)
Yes
(9) Wait until the last byte is received
Last receive
-1?
Yes
(5)
(10) Read the receive data of the last byte
No
Read ICDRR register
(6)
ACKBT bit ← 1
(7)
Read ICDRR register
(8)
ICIER register
Read RDRF bit in ICSR register
No
(9)
RDRF = 1 ?
Yes
Read ICDRR register
(10)
End
NOTE:
1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7).
Processing step (8) is dummy read of the ICDRR register.
Figure 16.49
Example of Register Setting in Slave Receive Mode (I2C bus Interface Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 453 of 580
R8C/2A Group, R8C/2B Group
16.3.6
16. Clock Synchronous Serial Interface
Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally.
Figure 16.50 shows a Block Diagram of Noise Canceller.
The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal
(or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next
circuit. When they do not match, the former value is retained.
f1 (sampling clock)
C
SCL or SDA
input signal
D
C
Q
D
Latch
Period of f1
f1 (sampling clock)
Figure 16.50
Block Diagram of Noise Canceller
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 454 of 580
Q
Latch
Match
detection
circuit
Internal SCL
or SDA signal
R8C/2A Group, R8C/2B Group
16.3.7
16. Clock Synchronous Serial Interface
Bit Synchronization Circuit
When setting the I2C bus interface to master mode, the high-level period may become shorter in the following
two cases:
• If the SCL signal is driven L level by a slave device
• If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 16.51 shows the Timing of Bit Synchronization Circuit and Table 16.8 lists the Time between Changing
SCL Signal from “L” Output to High-Impedance and Monitoring of SCL Signal.
Reference clock of
SCL monitor timing
SCL
VIH
Internal SCL
Figure 16.51
Timing of Bit Synchronization Circuit
Table 16.8
Time between Changing SCL Signal from “L” Output to High-Impedance and
Monitoring of SCL Signal
ICCR1 Register
CKS3
0
1
CKS2
0
1
0
1
1Tcyc = 1/f1(s)
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Time for Monitoring SCL
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
R8C/2A Group, R8C/2B Group
16.3.8
16. Clock Synchronous Serial Interface
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
16.3.8.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
16.3.8.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
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R8C/2A Group, R8C/2B Group
17. Hardware LIN
17. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1
Features
The hardware LIN has the features listed below.
Figure 17.1 shows a Block Diagram of Hardware LIN.
Master mode
• Generates Synch Break
• Detects bus collision
Slave mode
• Detects Synch Break
• Measures Synch Field
• Controls Synch Break and Synch Field signal inputs to UART0
• Detects bus collision
NOTE:
1.The WakeUp function is detected by INT1.
Hardware LIN
Synch Field
control
circuit
RXD0 pin
Timer RA
TIOSEL = 0
RXD data
LSTART bit
SBE bit
LINE bit
RXD0 input
control
circuit
Timer RA
underflow signal
TIOSEL = 1
Bus collision
detection
circuit
Timer RA
interrupt
Interrupt
control
circuit
BCIE, SBIE,
and SFIE bits
UART0
UART0 transfer clock
UART0 TE bit
Timer RA output pulse
MST bit
UART0 TXD data
TXD0 pin
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
Figure 17.1
Block Diagram of Hardware LIN
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R8C/2A Group, R8C/2B Group
17.2
17. Hardware LIN
Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 17.1.
Table 17.1
Pin Configuration
Name
Abbreviation
Input/Output
Receive data input
RXD0
Input
Transmit data output
TXD0
Output
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Function
Receive data input pin of the hardware LIN
Transmit data output pin of the hardware LIN
R8C/2A Group, R8C/2B Group
17.3
17. Hardware LIN
Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 17.2 and 17.3.
• LIN Control Register 2 (LINCR2)
• LIN Control Register (LINCR)
• LIN Status Register (LINST)
LIN Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
LINCR2
Bit Symbol
Address
0105h
Bit Name
Bus collision during Sync Break
transmission detection enable bit
After Reset
00h
Function
0 : Disables bus collision detection
1 : Enables bus collision detection
—
(b2-b1)
Reserved bits
Set to 0.
—
(b7-b3)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
Address
0106h
Bit Name
Synch Field measurementcompleted interrupt enable bit
RW
BCE
RW
RW
RW
LIN Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINCR
Bit Symbol
SFIE
After Reset
00h
Function
0 : Disables Synch Field measurementcompleted interrupt
1 : Enables Synch Field measurementcompleted interrupt
RW
SBIE
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt
enable bit
1 : Enables Synch Break detection interrupt
RW
BCIE
Bus collision detection interrupt
enable bit
0 : Disables bus collision detection interrupt
1 : Enables bus collision detection interrupt
RW
RXD0 input status flag
0 : RXD0 input enabled
1 : RXD0 input disabled
RO
Synch Break detection start
bit(1)
When this bit is set to 1, timer RA input is
enabled and RXD0 input is disabled.
When read, the content is 0.
RW
RXDSF
LSTART
SBE
RXD0 input unmasking timing
0 : Unmasked after Synch Break is detected
select bit (effective only in slave 1 : Unmasked after Synch Field measurement
mode)
is completed
LIN operation mode setting bit(2)
MST
LINE
LIN operation start bit
RW
0 : Slave mode
(Synch Break detection circuit actuated)
1 : Master mode
(timer RA output OR’ed w ith TXD0)
RW
0 : Causes LIN to stop
1 : Causes LIN to start operating(3)
RW
NOTES:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Exam ple of
Header Field Transm iss ion Flow chart (1) and Figure 17.9 Exam ple of Header Fie ld Re ception Flow chart
(2).)
Figure 17.2
Registers LINCR2 and LINCR
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R8C/2A Group, R8C/2B Group
17. Hardware LIN
LIN Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LINST
Bit Symbol
SFDCT
SBDCT
BCDCT
Address
0107h
Bit Name
Synch Field measurementcompleted flag
After Reset
00h
Function
1 show s Synch Field measurement completed.
Synch Break detection flag
1 show s Synch Break detected or Synch
Break generation completed.
Bus collision detection flag
1 show s Bus collision detected
SFDCT bit clear bit
When this bit is set to 1, the SFDCT bit is set to
0.
When read, the content is 0.
RW
When this bit is set to 1, the SBDCT bit is set to
0.
When read, the content is 0.
RW
When this bit is set to 1, the BCDCT bit is set to
0.
When read, the content is 0.
RW
B0CLR
SBDCT bit clear bit
B1CLR
BCDCT bit clear bit
B2CLR
—
(b7-b6)
Figure 17.3
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
LINST Register
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RW
RO
RO
RO
—
R8C/2A Group, R8C/2B Group
17.4
17. Hardware LIN
Functional Description
17.4.1
Master Mode
Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 17.5 and 17.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Synch Break
TXD0 pin
Synch Field
1
0
SBDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
(1)
(2)
(3)
The above applies under the following conditions:
LINE = 1, MST = 1, SBIE = 1
Figure 17.4
Typical Operation when Sending a Header Field
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IDENTIFIER
Page 461 of 580
(4)
(5)
R8C/2A Group, R8C/2B Group
17. Hardware LIN
Timer RA Set to timer mode
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
UART0
Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0
Set the BRG count source (f1, f8, f32)
U0C0CLK0 to 1 bit
UART0
Set the bit rate
U0BRG register
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break period.
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set bus collision detection enabled
BCE bit in LINCR2 register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
A
Figure 17.5
Example of Header Field Transmission Flowchart (1)
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During master mode, the
Synch Field measurementcompleted interrupt cannot be
used.
R8C/2A Group, R8C/2B Group
17. Hardware LIN
A
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
TCSTF = 1 ?
NO
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
SBDCT = 1 ?
NO
YES
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0 ?
NO
YES
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
UART0 Communication via UART0
U0TB register ← ID field
Figure 17.6
Timer RA generates Synch Break.
If registers TRAPRE and TRA for
timer RA do not need to be read or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
The timer RA interrupt may be used
to terminate generation of Synch
Break.
Three to five cycles of the CPU clock
are required after Synch Break
generation completes before the
SBDCT flag is set to 1.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
Transmit the ID field.
Example of Header Field Transmission Flowchart (2)
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R8C/2A Group, R8C/2B Group
17.4.2
17. Hardware LIN
Slave Mode
Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
17.8 through Figure 17.10 show an Example of Header Field Reception Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a duration equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Synch Break
RXD0 pin
1
0
RXD0 input for
UART0
1
0
RXDSF flag in the
LINCR register
1
0
SBDCT flag in the
LINST register
1
0
Synch Field
IDENTIFIER
Set by writing 1 to
the LSTART bit in
the LINCR register
Cleared to 0 when Synch
Field measurement
finishes
Set by writing 1 to
the B1CLR bit in
the LINST register
Measure this period
SFDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Cleared to 0 upon
acceptance of
interrupt request or
by a program
(1)
(2)
(3)
(4)
The above applies under the following conditions:
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 17.7
Typical Operation when Receiving a Header Field
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Set by writing 1 to the
B0CLR bit in the LINST
register
Page 464 of 580
(5)
(6)
R8C/2A Group, R8C/2B Group
17. Hardware LIN
Timer RA Set to pulse width measurement mode
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in the TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
A
Figure 17.8
Example of Header Field Reception Flowchart (1)
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Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
R8C/2A Group, R8C/2B Group
17. Hardware LIN
A
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register ← 1
Timer RA waits until the timer starts
counting.
Timer RA Read the count status flag
TCSTF flag in the TRACR register
TCSTF = 1 ?
NO
YES
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
RXDSF = 1 ?
NO
YES
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1 ?
NO
YES
B
Figure 17.9
Zero to one cycle of the timer RA count
source is required after timer RA starts
counting before the TCSTF flag is set to
1.
Hardware LIN waits until the RXD0
input for UART0 is masked.
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
Three to five cycles of the CPU clock
are required after the LSTART bit is set
to 1 before the RXDSF flag is set to 1.
After this, input to timer RA and UART0
is enabled.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
When Synch Break is detected, timer
RA is reloaded with the initially set
count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value and waits until the
next “L” level is input.
Three to five cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (unmasked after
Synch Break is detected), timer RA
can be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag is set to
0.
Example of Header Field Reception Flowchart (2)
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R8C/2A Group, R8C/2B Group
17. Hardware LIN
B
YES
Hardware LIN Read the Synch Field measurementcompleted flag
SFDCT flag in the LINST register
SFDCT = 1 ?
NO
YES
UART0 Set the UART0 communication rate
U0BRG register
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
Figure 17.10
Example of Header Field Reception Flowchart (3)
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Hardware LIN measures the Synch
Field.
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit in
the LINST register is set to 1.
Set a communication rate based on
the Synch Field measurement
result.
Communication via UART0
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
R8C/2A Group, R8C/2B Group
17.4.3
17. Hardware LIN
Bus Collision Detection Function
The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1
register = 1). To detect a bus collision during Synch Break transmission, set the BCE bit in the LINCR2 register
to 1 (bus collision detection enabled).
Figure 17.11 shows typical operation of the hardware LIN when a bus collision is detected.
TXD0 pin
1
0
RXD0 pin
1
0
Transfer clock
1
0
LINE bit in the
LINCR register
1
0
TE bit in the U0C1
register
1
0
BCDCT flag in the
LINST register
1
0
IR bit in the TRAIC
register
1
0
Set to 1 by a program
Set to 1 by a program
Figure 17.11
Set by writing 1 to
the B2CLR bit in the
LINST register
Cleared to 0 upon
acceptance of interrupt
request or by a program
Typical Operation when a Bus Collision is Detected
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R8C/2A Group, R8C/2B Group
17.4.4
17. Hardware LIN
Hardware LIN End Processing
Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart.
Use the following timing for hardware LIN end processing:
• If the hardware bus collision detection function is used
Perform hardware LIN end processing after checksum transmission completes.
• If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA
Timer RA
Set the timer to stop counting
TSTART bit in TRACR register ← 0
Read the count status flag
TCSTF flag in TRACR register
TCSTF = 0 ?
NO
YES
UART0 Complete transmission via UART0
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
Set the timer to stop counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
When the bus collision detection
function is not used, end
processing for the UART0
transmission is not required.
After clearing hardware LIN
status flag, stop the
hardware LIN operation.
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Figure 17.12
Example of Hardware LIN Communication Completion Flowchart
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R8C/2A Group, R8C/2B Group
17.5
17. Hardware LIN
Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 17.2 lists the Interrupt Requests of Hardware LIN.
Table 17.2
Interrupt Requests of Hardware LIN
Interrupt Request
Synch Break detection
Status Flag
Cause of Interrupt
SBDCT
Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period
during communication.
Synch Break generation
completed
Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field
measurement completed
SFDCT
Generated when measurement for 6 bits of the Synch Field
by timer RA is completed.
Bus collision detection
BCDCT
Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
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R8C/2A Group, R8C/2B Group
17.6
17. Hardware LIN
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
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R8C/2A Group, R8C/2B Group
18. A/D Converter
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (VREF unconnected) so that no
current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter.
Figures 18.2 and 18.4 show the A/D converter-related registers.
Table 18.1
Performance of A/D converter
Item
A/D conversion method
Performance
Successive approximation (with capacitive coupling amplifier)
0 V to AVCC
Analog input voltage(1)
4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.2 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
8 bits or 10 bits selectable
AVCC = Vref = 5 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
AVCC = Vref = 2.2 V, φAD = 5 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
Operating clock φAD(2)
Resolution
Absolute accuracy
Operating mode
Analog input pin
A/D conversion start condition
Conversion rate per pin
One-shot mode and repeat mode 0(3)
12 pins (AN0 to AN11)
• Software trigger
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
• Capture
Timer RD interrupt request is generated while the ADST bit is set to 1
• Without sample and hold function
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
NOTES:
1. The analog input voltage does not depend on use of a sample and hold function.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
When 2.2 V ≤ AVCC < 2.7 V, the frequency of φAD must be 5 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
3. In repeat mode 0, only 8-bit mode can be used.
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R8C/2A Group, R8C/2B Group
18. A/D Converter
CKS0 = 1
fOCO-F
A/D conversion rate selection
f1
CKS0 = 0
CKS1 = 1
CKS0 = 1
φAD
f2
CKS1 = 0
f4
CKS0 = 0
VCUT = 0
AVSS
VREF
Resistor ladder
VCUT = 1
Successive conversion register
Software trigger
ADCAP = 0
ADCON0
Trigger
Timer RD
interrupt request
ADCAP = 1
Vcom
AD0 register
Decoder
Comparator
VIN
Data bus
P0_7/AN0
P0_6/AN1
P0_5/AN2
P0_4/AN3
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
P1_0/AN8
P1_1/AN9
P1_2/AN10
P1_3/AN11
CH2 to
CH2 to
CH2 to
CH2 to
CH2 to
CH2 to
CH2 to
CH2 to
CH0 = 000b
CH0 = 001b
CH0 = 010b
CH0 = 011b
CH0 = 100b
CH0 = 101b
CH0 = 110b
CH0 = 111b
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
CH0 to CH2, CKS0: Bits in ADCON0 register
CKS1, VCUT: Bits in ADCON1 register
ADGSEL0: Bit in ADCON2 register
Figure 18.1
Block Diagram of A/D Converter
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ADGSEL0 = 0
ADGSEL0 = 1
R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Register 0
(b15)
b7
(b8)
b0 b7
b0
Symbol
AD0
Address
02C1h-02C0h
After Reset
Undefined
Function
When BITS bit in ADCON1 register is set to 1 When BITS bit in ADCON1 register is set to 0
(10-bit mode).
(8-bit mode).
8 low -order bits in A/D conversion result
2 high-order bits in A/D conversion result
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
A/D conversion result
When read, the content is 0.
RW
RO
RO
—
A/D Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
ADCON2
Bit Symbol
SMP
—
(b2-b1)
ADGSEL0
Address
02D4h
Bit Name
A/D conversion method select bit
After Reset
00h
Function
0 : Without sample and hold
1 : With sample and hold
Reserved bits
Set to 0.
A/D input group select bit(4)
0 : Port P0 group (AN0 to AN7)
1 : Port P1 group (AN8 to AN11)
ADGSEL1 Reserved bit
Set to 0.
—
Nothing is assigned. If necessary, set to 0.
(b7-b5)
When read, the content is 0.
NOTE:
1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.
Figure 18.2
Registers AD0 and ADCON2
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RW
RW
RW
RW
RW
—
R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
MD0
MD1
ADCAP
ADST
Address
02D6h
Bit Name
Analog input pin select bits
(Note 4)
A/D operating mode select
bit(2)
0 : One-shot mode
1 : Repeat mode 0
Reserved bit
A/D conversion automatic
start bit
Set to 0.
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Selects fOCO-F
RW
CKS0
After Reset
00h
Function
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. When changing A/D operating mode, set the analog input pin again.
3. Set øAD frequency to 10 MHz or below .
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register.
CH2 to CH0
000b
001b
010b
011b
100b
101b
110b
111b
Figure 18.3
ADGSEL0 = 0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADGSEL0 = 1
Do not set.
ADCON0 Register
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AN8
AN9
AN10
AN11
RW
RW
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0 0 0
Symbol
Address
02D7h
ADCON1
Bit Symbol
Bit Name
SCAN0
Reserved bit
Reserved bits
—
(b2-b1)
BITS
CKS1
—
(b6-b7)
Set to 0.
Set to 0.
RW
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function
RW
VREF connect bit
0 : VREF not connected
1 : VREF connected
RW
Reserved bits
Set to 0.
ADCON1 Register
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REJ09B0324-0200
RW
0 : 8-bit mode
1 : 10-bit mode
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Set the BITS bit to 0 (8-bit mode) in repeat mode 0.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
Figure 18.4
RW
RW
8/10-bit mode select bit(2)
(3)
VCUT
After Reset
00h
Function
Page 476 of 580
RW
R8C/2A Group, R8C/2B Group
18.1
18. A/D Converter
One-Shot Mode
In one-shot mode, the input voltage of one selected pin is A/D converted once.
Table 18.2 lists the One-Shot Mode Specifications. Figure 18.5 shows the ADCON0 Register in One-Shot Mode
and Figure 18.6 shows the ADCON1 Register in One-Shot Mode.
Table 18.2
One-Shot Mode Specifications
Item
Specification
Function
The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted once
Start condition
• When the ADCAP bit is set to 0 (software trigger),
set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode),
A compare match between registers TRD0 and TRDGRA0 or a TRD1
underflow is generated while the ADST bit is set to 1
Stop condition
• A/D conversion completes (when the ADCAP bit is set to 0 (software
trigger), ADST bit is set to 0)
• Set the ADST bit to 0
Interrupt request generation A/D conversion completes
timing
Input pin
Select one of AN0 to AN11
Reading of A/D conversion Read AD0 register
result
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R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
MD0
MD1
ADCAP
ADST
Address
02D6h
Bit Name
Analog input pin select bits (Note 4)
After Reset
00h
Function
A/D operating mode select 0 : One-shot mode
bit(2)
Set to 0.
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Selects fOCO-F
RW
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. After changing the A/D operating mode, select the analog input pin again.
3. Set øAD frequency to 10 MHz or below .
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register.
Figure 18.5
ADGSEL0 = 0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADGSEL0 = 1
Do not set.
AN8
AN9
AN10
AN11
ADCON0 Register in One-Shot Mode
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REJ09B0324-0200
RW
Reserved bit
A/D conversion automatic
start bit
CKS0
CH2 to CH0
000b
001b
010b
011b
100b
101b
110b
111b
RW
RW
RW
RW
Page 478 of 580
RW
RW
R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0 0 0
Symbol
Address
02D7h
ADCON1
Bit Symbol
Bit Name
Reserved bit
SCAN0
—
Reserved bits
(b2-b1)
BITS
CKS1
VCUT
—
(b6-b7)
After Reset
00h
Function
Set to 0.
Set to 0.
0 : 8-bit mode
1 : 10-bit mode
RW
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function
RW
VREF connect bit(2)
Reserved bits
1 : VREF connected
Set to 0.
ADCON1 Register in One-Shot Mode
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REJ09B0324-0200
RW
8/10-bit mode select bit
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
Figure 18.6
RW
RW
Page 479 of 580
RW
RW
R8C/2A Group, R8C/2B Group
18.2
18. A/D Converter
Repeat Mode 0
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 18.3 lists the Repeat Mode 0 Specifications. Figure 18.7 shows the ADCON0 Register in Repeat Mode 0 and
Figure 18.8 shows the ADCON1 Register in Repeat Mode 0.
Table 18.3
Repeat Mode 0 Specifications
Item
Specification
Function
The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is
A/D converted repeatedly
Start conditions
• When the ADCAP bit is set to 0 (software trigger),
set the ADST bit to 1 (A/D conversion starts)
• When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM
mode)), a compare match between registers TRD0 and TRDGRA0 or a
TRD1 underflow is generated while the ADST bit is set to 1
Stop condition
Set the ADST bit to 0
Interrupt request generation Not generated
timing
Input pin
Select one of AN0 to AN11
Reading of result of A/D
Read AD0 register
converter
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R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
ADCON0
Bit Symbol
CH0
CH1
CH2
MD0
MD1
ADCAP
ADST
Address
02D6h
Bit Name
Analog input pin select bits (Note 4)
After Reset
00h
Function
A/D operating mode select 1 : Repeat mode 0
bit(2)
Set to 0.
0 : Starts at softw are trigger (ADST bit)
1 : Starts at timer RD
(complementary PWM mode)
A/D conversion start flag
0 : Stops A/D conversion
1 : Starts A/D conversion
RW
Frequency select bit 0
[When CKS1 in ADCON1 register = 0]
0 : Selects f4
1 : Selects f2
[When CKS1 in ADCON1 register = 1]
0 : Selects f1(3)
1 : Do not set.
RW
NOTES:
1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined.
2. After changing A/D operation mode, select the analog input pin again.
3. Set øAD frequency to 10 MHz or below .
4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit in the
ADCON2 register .
Figure 18.7
ADGSEL0 = 0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADGSEL0 = 1
Do not set.
AN8
AN9
AN10
AN11
ADCON0 Register in Repeat Mode 0
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REJ09B0324-0200
RW
Reserved bit
A/D conversion automatic
start bit
CKS0
CH2 to CH0
000b
001b
010b
011b
100b
101b
110b
111b
RW
RW
RW
RW
Page 481 of 580
RW
RW
R8C/2A Group, R8C/2B Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
0 0 0 0
Symbol
Address
02D7h
ADCON1
Bit Symbol
Bit Name
Reserved bit
SCAN0
—
Reserved bits
(b2-b1)
BITS
CKS1
VCUT
—
(b6-b7)
After Reset
00h
Function
Set to 0.
Set to 0.
8/10-bit mode select bit(2)
0 : 8-bit mode
Frequency select bit 1
Refer to the description of the CKS0 bit in the
ADCON0 register function
VREF connect bit(3)
Reserved bits
1 : VREF connected
Set to 0.
NOTES:
1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined.
2. Set the BITS bit to 0 (8-bit mode) in repeat mode 0.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
Figure 18.8
ADCON1 Register in Repeat Mode 0
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RW
RW
RW
RW
RW
RW
RW
R8C/2A Group, R8C/2B Group
18.3
18. A/D Converter
Sample and Hold
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after
selecting whether the sample and hold circuit is to be used or not.
Figure 18.9 shows a Timing Diagram of A/D Conversion.
Sample and hold
disabled
Conversion time of 1st bit
Sampling time
4ø AD cycles
2nd bit
Comparison Sampling time Comparison Sampling time Comparison
2.5ø AD cycles
2.5ø AD cycles
time
time
time
* Repeat until conversion ends
Sample and hold
enabled
2nd bit
Conversion time of 1st bit
Sampling time
4ø AD cycles
Comparison
time
Comparison Comparison Comparison
time
time
time
* Repeat until conversion ends
Figure 18.9
18.4
Timing Diagram of A/D Conversion
A/D Conversion Cycles
Figure 18.10 shows the A/D Conversion Cycles.
Conversion time at the 1st bit
A/D Conversion Mode
Conversion
Time
Sampling
Time
Comparison
Time
Conversion time at the 2nd
bit and the follows
Sampling
Time
End process
Comparison
End process
Time
Without Sample & Hold
8 bits
49φAD
4φAD
2.0φAD
2.5φAD
2.5φAD
8.0φAD
Without Sample & Hold
10 bits
59φAD
4φAD
2.0φAD
2.5φAD
2.5φAD
8.0φAD
With Sample & Hold
8 bits
28φAD
4φAD
2.5φAD
0.0φAD
2.5φAD
4.0φAD
With Sample & Hold
10 bits
33φAD
4φAD
2.5φAD
0.0φAD
2.5φAD
4.0φAD
Figure 18.10
A/D Conversion Cycles
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R8C/2A Group, R8C/2B Group
18.5
18. A/D Converter
Internal Equivalent Circuit of Analog Input
Figure 18.11 shows the Internal Equivalent Circuit of Analog Input.
VCC
VCC VSS
AVCC
ON Resistor
Approx. 2kΩ Wiring Resistor
Approx. 0.2kΩ
Parasitic Diode
AN0
SW1
ON Resistor
Approx. 0.6kΩ
Analog Input
Voltage
SW2
Parasitic Diode
i Ladder-type
Switches
i = 12
AMP
VIN
Sampling
Control Signal
VSS
C = Approx.1.5pF
ON Resistor
Approx. 5kΩ
SW3
SW4
i Ladder-type
Wiring Resistors
AVSS
ON Resistor
Approx. 2kΩ Wiring Resistor
Approx. 0.2kΩ
Chopper-type
Amplifier
AN11
SW1
A/D Successive
Conversion Register
b3
b0
ADCON2 b1
register
b2
Reference
Control Signal
ADCON0
register
Vref
VREF
Resistor
ladder
Comparison
SW5
voltage
ON Resistor
Approx. 0.6kΩ
AVSS
A/D Conversion
Interrupt Request
Comparison reference voltage
(Vref) generator
Sampling Comparison
SW1 conducts only on the ports selected for analog input.
Connect to
Control signal
for SW2
Connect to
Connect to
Control signal
for SW3
SW2 and SW3 are open when A/D conversion is not in progress;
their status varies as shown by the waveforms in the diagrams on the left.
SW4 conducts only when A/D conversion is not in progress.
Connect to
SW5 conducts when compare operation is in progress.
NOTE:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
Figure 18.11
Internal Equivalent Circuit of Analog Input
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R8C/2A Group, R8C/2B Group
18.6
18. A/D Converter
Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.12 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
VC is generally
And when t = T,
1
– -------------------------C ( R0 + R )

VC = VIN  1 – e

t



X
X
VC = VIN – ---- VIN = VIN  1 – ----

Y
Y
1
– --------------------------T
C
(
R0
+ R) = X
e
---Y
1
– -------------------------T = ln X
---C ( R0 + R )
Y
Hence,
T
R0 = – ------------------- – R
X
C • ln ---Y
Figure 18.12 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN
and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample and hold. Output impedance R0
for sufficiently charging capacitor C within time T is determined as follows.
T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
3
3
0.25 × 10 – 6
- – 2.8 ×10 ≈ 1.7 ×10
R0 = – -------------------------------------------------0.1 6.0 × 10 – 12 • ln ----------1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately 1.7 kΩ. maximum.
MCU
Sensor equivalent
circuit
R0
VIN
R (2.8 kΩ)
C (6.0 pF)
VC
NOTE:
1. The capacity of the terminal is assumed to be 4.5 pF.
Figure 18.12
Analog Input Pin and External Sensor Equivalent Circuit
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REJ09B0324-0200
Page 485 of 580
R8C/2A Group, R8C/2B Group
18.7
18. A/D Converter
Notes on A/D Converter
• Write to each bit (other than ADST bit) in the ADCON0 register, each bit in the ADCON1 register, or the SMP
•
•
•
•
•
•
•
bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
After changing the A/D operating mode, select an analog input pin again.
When using the one-shot mode, ensure that A/D conversion is completed before reading the AD0 register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
When using the repeat mode 0, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
Do not select the fOCO-F for the φAD.
If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD0 register.
Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
Do not enter stop mode during A/D conversion.
Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
Rev.2.00 Nov 26, 2007
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Page 486 of 580
R8C/2A Group, R8C/2B Group
19. D/A Converter
19. D/A Converter
The D/A converters are 8-bit R-2R type units. There are two independent D/A converters.
D/A conversion is performed by writing to the DAi register (i = 0 or 1). To output the conversion result, set the DAiE
bit in the DACON register to 1 (output enabled). Before using D/A conversion, the corresponding port direction bit
must be set to 0 (input mode). Setting the DAiE bit to 1 removes the pull-up from the corresponding port.
The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register.
V = Vref × n/ 256 (n = 0 to 255)
Vref: Reference voltage
Table 19.1 lists the D/A Converter Specifications. Figure 19.1 shows the Block Diagram of D/A Converter. Figure
19.2 shows the D/A converter related registers. Figure 19.3 shows the D/A Converter Equivalent Circuit.
Table 19.1
D/A Converter Specifications
Item
D/A conversion method
Resolution
Analog output pins
Performance
R-2R method
8 bits
2 (DA0 and DA1)
Data bus
DA0 register
R-2R resistor ladder
0
1
DA0E bit
DA0
DA1 register
0
R-2R resistor ladder
1
DA1E bit
Figure 19.1
Block Diagram of D/A Converter
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 487 of 580
DA1
R8C/2A Group, R8C/2B Group
19. D/A Converter
D/Ai Register (i = 0 or 1)(1)
b7
b0
Address
00D8h
Symbol
DA0
DA1
After Reset
00h
00h
00DAh
Function
Output value of D/A conversion
Setting Range
RW
00h to FFh
RW
NOTE:
1. When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.
D/A Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
After Reset
00h
Address
00DCh
Bit Name
Bit Symbol
DA0E
DA1E
Function
RW
D/A0 output enable bit
0 : Output disabled
1 : Output enabled
RW
D/A1 output enable bit
0 : Output disabled
1 : Output enabled
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b2)
—
NOTE:
1. When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current from flow ing into the R-2R resistor ladder to reduce unnecessary current consumption.
Figure 19.2
Registers DA0 to DA1 and DACON
DAiE bit
r
0
R
R
R
R
2R
2R
2R
2R
R
R
R
2R
DAi
1
2R
MSB
DAi register
2R
2R
LSB
0
1
AVSS
VREF(2)
i = 0 to 1
NOTES:
1. The above diagram applies when the value of the DAi register is 2Ah.
2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register.
Figure 19.3
2R
D/A Converter Equivalent Circuit
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R8C/2A Group, R8C/2B Group
20. Flash Memory
20. Flash Memory
20.1
Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,
standard serial I/O, and parallel I/O.
Table 20.1 lists the Flash Memory Performance.
Table 20.1
Flash Memory Performance
Item
Flash memory operating mode
Division of erase block
Programming method
Erase method
Programming and erasure control method(3)
Rewrite control method
Number of commands
Programming and Blocks 0 to 3 (program
erasure
ROM)
endurance(1)
Blocks A and B (data
flash)(2)
ID code check function
ROM code protect
Specification
3 modes (CPU rewrite, standard serial I/O, and parallel I/O)
Refer to Figure 20.1 and Figure 20.2
Byte unit
Block erase
Program and erase control by software command
Rewrite control for blocks 0 to 3 by FMR02 bit in FMR0 register
Rewrite control for block 0 by FMR15 bit and Block 1 by FMR16 bit in
FMR1 register
5 commands
R8C/2A Group: 100 times; R8C/2B Group: 1,000 times
10,000 times
Standard serial I/O mode supported
Parallel I/O mode supported
NOTES:
1. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When
performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations
in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to
retain data on the erase count of each block and limit the number of erase operations to a certain number.
2. Blocks A and B are implemented only in the R8C/2B group.
3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Table 20.2
Flash Memory Rewrite Modes
Flash memory
Rewrite mode
Function
Standard Serial I/O
Mode
User ROM area is rewritten by executing User ROM area is
rewritten by a
software commands from the CPU.
dedicated serial
EW0 mode: Rewritable in the RAM
EW1 mode: Rewritable in flash memory programmer.
User ROM area
User ROM area
CPU Rewrite Mode
Areas which can
be rewritten
Operating mode
Single chip mode
ROM Programmer None
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Boot mode
Serial programmer
Parallel I/O Mode
User ROM area is
rewritten by a
dedicated parallel
programmer.
User ROM area
Parallel I/O mode
Parallel programmer
R8C/2A Group, R8C/2B Group
20.2
20. Flash Memory
Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash
Memory Block Diagram for R8C/2A Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2B
Group.
The user ROM area of the R8C/2B Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable. When rewriting blocks 2 and 3 in CPU rewrite mode,
FMR02 bit is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
48 Kbytes ROM product
04000h
Block 1: 32 Kbytes(1)
04000h
Block 1: 32 Kbytes(1)
Block 1: 32 Kbytes(1)
Block 0: 16 Kbytes(1)
0FFFFh
User ROM area
Program
ROM
0BFFFh
0C000h
0BFFFh
0C000h
0BFFFh
0C000h
96 Kbytes ROM product
64 Kbytes ROM product
04000h
0E000h
0FFFFh
10000h
Block 0: 32 Kbytes(1)
0FFFFh
10000h
User ROM area
13FFFh
14000h
13FFFh
Block 0: 32 Kbytes(1)
0FFFFh
8 Kbytes
Boot ROM area
(reserved area)(4)
Block 2: 32 Kbytes(2)
1BFFFh
User ROM area
128 Kbytes ROM product
04000h
Block 1: 32 Kbytes(1)
0BFFFh
0C000h
0FFFFh
10000h
Block 0: 32 Kbytes(1)
Program
ROM
13FFFh
14000h
Block 2: 32 Kbytes(2)
1BFFFh
1C000h
Block 3: 32 Kbytes(2, 3)
23FFFh
User ROM area
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled),
block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable (only for CPU rewrite mode).
3. The emulator debugger cannot be used by address 20000h to 23FFFh. Refer to 24. Notes on Emulator Debugger.
4. This area is for storing the boot program provided by Renesas Technology.
Figure 20.1
Flash Memory Block Diagram for R8C/2A Group
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R8C/2A Group, R8C/2B Group
02400h
02BFFh
20. Flash Memory
96 Kbytes ROM product
64 Kbytes ROM product
48 Kbytes ROM product
02400h
02400h
Block A: 1 Kbyte
Block A: 1 Kbyte
Block A: 1 Kbyte
Block B: 1 Kbyte
02BFFh
Block B: 1 Kbyte
04000h
04000h
Block 1: 32 Kbytes(1)
Block B: 1 Kbyte
Block 1: 32 Kbytes(1)
Block 1: 32 Kbytes(1)
User ROM area
0FFFFh
10000h
Program
ROM
0BFFFh
0C000h
Block 0: 16 Kbytes(1)
0FFFFh
Data
flash
04000h
0BFFFh
0C000h
0BFFFh
0C000h
02BFFh
Block 0: 32 Kbytes(1)
13FFFh
User ROM area
0FFFFh
10000h
Block 0: 32 Kbytes(1)
0E000h
0FFFFh
8 Kbytes
Boot ROM area
(reserved area)(4)
13FFFh
14000h
Block 2: 32 Kbytes(2)
1BFFFh
User ROM area
128 Kbytes ROM product
02400h
02BFFh
Block A: 1 Kbyte
Block B: 1 Kbyte
Data
flash
04000h
Block 1: 32 Kbytes(1)
0BFFFh
0C000h
0FFFFh
10000h
Block 0: 32 Kbytes(1)
Program
ROM
13FFFh
14000h
Block 2: 32 Kbytes(2)
1BFFFh
1C000h
Block 3: 32 Kbytes(2, 3)
23FFFh
User ROM area
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite
enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode).
2. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable (only for CPU rewrite mode).
3. The emulator debugger cannot be used by address 20000h to 23FFFh. Refer to 24. Notes on Emulator Debugger.
4. This area is for storing the boot program provided by Renesas Technology.
Figure 20.2
Flash Memory Block Diagram for R8C/2B Group
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R8C/2A Group, R8C/2B Group
20.3
20. Flash Memory
Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
20.3.1
ID Code Check Function
This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write
them to the flash memory.
Address
00FFDFh to 00FFDCh
ID1
Undefined instruction vector
00FFE3h to 00FFE0h
ID2
Overflow vector
BRK instruction vector
00FFE7h to 00FFE4h
00FFEBh to 00FFE8h
ID3
Address match vector
00FFEFh to 00FFECh
ID4
Single step vector
00FFF3h to 00FFF0h
ID5
00FFF7h to 00FFF4h
ID6
00FFFBh to 00FFF8h
ID7
00FFFFh to 00FFFCh
(Note 1)
Oscillation stop detection/watchdog
timer/voltage monitor 1 and voltage
monitor 2 vector
Address break
(Reserved)
Reset vector
4 bytes
NOTE:
1. The OFS register is assigned to 00FFFFh.
Refer to Figure 20.4 OFS Register for OFS register details.
Figure 20.3
Address for Stored ID Code
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R8C/2A Group, R8C/2B Group
20.3.2
20. Flash Memory
ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 20.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol
OFS
Bit Symbol
WDTON
—
(b1)
ROMCR
ROMCP1
—
(b4)
LVD0ON
—
(b6)
Address
0FFFFh
Bit Name
Watchdog timer start
select bit
When Shipping
FFh(3)
Function
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Reserved bit
Set to 1.
ROM code protect
disabled bit
0 : ROM code protect disabled
1 : ROMCP1 enabled
RW
ROM code protect bit
0 : ROM code protect enabled
1 : ROM code protect disabled
RW
Reserved bit
Set to 1.
Voltage detection 0
circuit start bit(2)
0 : Voltage monitor 0 reset enabled after hardw are
reset
1 : Voltage monitor 0 reset disabled after hardw are
reset
Reserved bit
Set to 1.
Count source protect
CSPROINI mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
RW
RW
RW
RW
RW
RW
RW
NOTES:
1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after hardw are reset).
3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 20.4
OFS Register
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R8C/2A Group, R8C/2B Group
20.4
20. Flash Memory
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in
CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erasesuspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module
has a program-suspend function which performs the interrupt process after the auto-program operation is
suspended. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists
the Differences between EW0 Mode and EW1 Mode.
Table 20.3
Differences between EW0 Mode and EW1 Mode
Item
Operating mode
Areas in which a rewrite
control program can be
located
Areas in which a rewrite
control program can be
executed
Areas which can be
rewritten
EW0 Mode
Single-chip mode
User ROM area
Necessary to transfer to any area other
Executing directly in user ROM or RAM
than the flash memory (e.g., RAM) before area possible
executing
User ROM area
User ROM area
However, blocks which contain a rewrite
control program are excluded(1)
None
• Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be executed
Read status register mode
Read array mode
Software command
restrictions
Modes after program or
erase
Modes after read status
register
CPU status during autowrite and auto-erase
Flash memory status
detection
Read status register mode
Do not execute this command
Operating
Conditions for transition to
erase-suspend
Conditions for transitions to
program-suspend
CPU clock
EW1 Mode
Single-chip mode
User ROM area
Hold state (I/O ports hold state before the
command is executed)
• Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in
in the FMR0 register by a program
the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set
register to 1 by a program.
to 1 and the interrupt request of the
enabled maskable interrupt is generated
Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set
register to 1 by a program.
to 1 and the interrupt request of the
enabled maskable interrupt is generated
5 MHz or below
No restriction (on clock frequency to be
used)
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting
the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the
FMR16 bit to 0 (rewrite enabled).
When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), blocks 2 and 3 are rewritable.
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R8C/2A Group, R8C/2B Group
20.4.1
20. Flash Memory
EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erasesuspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read
enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the
FMR42 bit to 0 (program restarts).
20.4.2
EW1 Mode
The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine when program and erase operations complete. Do not execute
commands that use the read status register in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is
acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt
process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts)
To enable the program-suspend function during auto-programming, execute the program command after setting
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is
acknowledged.
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and
the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0)
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0
(programming restarts).
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R8C/2A Group, R8C/2B Group
20. Flash Memory
Figure 20.5 shows the FMR0 Register, Figure 20.6 shows the FMR1 Register and Figure 20.7 shows the FMR4
Register.
20.4.2.1
FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure
(including suspend periods), or erase-suspend mode; otherwise, it is 1.
20.4.2.2
FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
20.4.2.3
FMR02 Bit
Rewriting of blocks 0 to 3 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of blocks 2 and 3 are enabled, if the FMR02 bit is set to 1 (rewrite enabled). Rewriting of blocks 0
and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite enabled).
20.4.2.4
FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
• When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
• To provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock mode (XIN clock stops).
Figure 20.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops). Handle
according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled,
the FMR0 register does not need to be set because the power for the flash memory is automatically turned off
and is turned back on again after returning from stop or wait mode.
20.4.2.5
FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program
error occurs; otherwise, it is set to 0. For details, refer to the description in 20.4.5 Full Status Check.
20.4.2.6
FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error
occurs; otherwise, it is set to 0. Refer to 20.4.5 Full Status Check for details.
20.4.2.7
FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
20.4.2.8
FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
20.4.2.9
FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
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20. Flash Memory
20.4.2.10 FMR40 Bit
The suspend function is enabled by setting the FMR40 bit to 1 (enable).
20.4.2.11 FMR41 Bit
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is
generated in EW1 mode, and then the MCU enters erase-suspend mode.
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
20.4.2.12 FMR42 Bit
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
20.4.2.13 FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit
remains set to 1 (erase execution in progress) during erase-suspend operation.
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
20.4.2.14 FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44
bit remains set to 1 (program execution in progress) during program-suspend operation.
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
20.4.2.15 FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading
enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.
20.4.2.16 FMR47 Bit
Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in
low-speed clock mode (XIN clock stops) and low-speed on-chip oscillator mode (XIN clock stops).
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R8C/2A Group, R8C/2B Group
20. Flash Memory
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
FMR0
Bit Symbol
FMR00
FMR01
FMR02
Address
01B7h
___
Bit Name
RY/BY status flag
CPU rew rite mode select bit(1)
FMSTP
FMR06
FMR07
Function
0 : Busy (w riting or erasing in progress)
1 : Ready
0 : CPU rew rite mode disabled
1 : CPU rew rite mode enabled
Blocks 0 to 3 rew rite enable bit(2, 6) 0 : Disables rew rite
1 : Enables rew rite
Flash memory stop bit(3, 5)
—
(b5-b4)
After Reset
00000001b
0 : Enables flash memory operation
1 : Stops flash memory
(enters low -pow er consumption state
and flash memory is reset)
RW
RO
RW
RW
RW
Reserved bits
Set to 0.
Program status flag(4)
0 : Completed successfully
1 : Terminated by error
RO
Erase status flag(4)
0 : Completed successfully
1 : Terminated by error
RO
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1.
Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
3. Set this bit by a program transferred to the RAM.
4. This bit is set to 0 by executing the clear status command.
5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0,
w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er
consumption state nor is it reset.
6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
Figure 20.5
FMR0 Register
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20. Flash Memory
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
0 0 0
Symbol
Address
01B5h
FMR1
Bit Symbol
Bit Name
Reserved bit
—
(b0)
FMR11
—
(b4-b2)
FMR15
FMR16
—
(b7)
After Reset
1000000Xb
Function
When read, the content is undefined.
RW
RO
EW1 mode select bit(1, 2)
0 : EW0 mode
1 : EW1 mode
Reserved bits
Set to 0.
Block 0 rew rite disable bit(2,3)
0 : Enables rew rite
1 : Disables rew rite
RW
Block 1 rew rite disable bit(2,3)
0 : Enables rew rite
1 : Disables rew rite
RW
Reserved bit
Set to 1.
RW
RW
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode
enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1.
2. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled).
3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to.
To set this bit to 0, set it to 0 immediately after setting it first to 1.
To set this bit to 1, set it to 1.
Figure 20.6
FMR1 Register
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20. Flash Memory
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR4
Bit Symbol
FMR40
FMR41
FMR42
FMR43
FMR44
—
(b5)
FMR46
FMR47
Address
01B3h
Bit Name
Erase-suspend function
enable bit(1)
After Reset
01000000b
Function
RW
0 : Disable
1 : Enable
RW
0 : Erase restart
1 : Erase-suspend request
RW
0 : Program restart
1 : Program-suspend request
RW
Erase command flag
0 : Erase not executed
1 : Erase execution in progress
RO
Program command flag
0 : Program not executed
1 : Program execution in progress
RO
Reserved bit
Set to 0.
Read status flag
0 : Disables reading
1 : Enables reading
Erase-suspend request bit
(2)
Program-suspend request bit
(3)
Low -pow er consumption read 0 : Disable
mode enable bit (1, 4, 5)
1 : Enable
RO
RO
RW
NOTES:
1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit
to 0 and setting it to 1.
2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase
operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten).
3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled
until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program.
4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode.
Figure 20.7
FMR4 Register
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20. Flash Memory
Figure 20.8 shows the Timing of Suspend Operation.
Erasure
starts
Erasure
suspends
Programming Programming Programming Programming Erasure
starts
suspends
restarts
ends
restarts
During erasure
FMR00 bit in
FMR0 register
1
FMR46 bit in
FMR4 register
1
FMR44 bit in
FMR4 register
1
FMR43 bit in
FMR4 register
1
During programming
During programming
Erasure
ends
During erasure
Remains 0 during suspend
0
0
0
0
Remains 1 during suspend
Check that the
FMR43 bit is set to 1
(during erase
execution), and that
the erase-operation
has not ended.
Check that the
FMR44 bit is set to 1
(during program
execution), and that
the program has not
ended.
Check the status,
and that the
programming ends
normally.
Check the status,
and that the
erasure ends
normally.
The above figure shows an example of the use of program-suspend during programming following erase-suspend.
NOTE:
1. If program-suspend is entered during erase-suspend, always restart programming.
Figure 20.8
Timing of Suspend Operation
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20. Flash Memory
Figure 20.9 shows How to Set and Exit EW0 Mode. Figure 20.10 shows How to Set and Exit EW1 Mode.
EW0 Mode Operating Procedure
Rewrite control program
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Set registers(1) CM0 and CM1
Execute software commands
Transfer a rewrite control program which uses CPU
rewrite mode to the RAM.
Execute the read array command(3)
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to the rewrite control program which has been
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Jump to a specified address in the flash memory
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewrite mode after executing the read array command.
Figure 20.9
How to Set and Exit EW0 Mode
EW1 Mode Operating Procedure
Program in ROM
Write 0 to the FMR01 bit before writing 1 (CPU
rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
NOTE:
1.To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
Figure 20.10
How to Set and Exit EW1 Mode
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Transfer a high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program to
the RAM.
20. Flash Memory
High-speed on-chip oscillator mode,
low-speed on-chip oscillator mode
(XIN clock stops), and low-speed
clock mode (XIN clock stops)
program
Jump to the high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and
low-speed clock mode (XIN clock stops) program
which has been transferred to the RAM.
(The subsequent processing is executed by the
program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)
Write 1 to the FMSTP bit (flash memory stops.
low power consumption mode)(1)
Switch the clock source for the CPU clock.
Turn XIN off
Process in high-speed on-chip oscillator
mode, low-speed on-chip oscillator mode
(XIN clock stops), and low-speed clock
mode (XIN clock stops)
Turn XIN clock on → wait until oscillation
stabilizes → switch the clock source for CPU
clock(2)
Write 0 to the FMSTP bit
(flash memory operation)
NOTES:
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the
FMSTP bit to 1.
2. Before switching to a different clock source for the CPU, make sure
the designated clock is stable.
3. Insert a 30 µs wait time in a program. Do not access to the flash
memory during this wait time.
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes
(30 µs)(3)
Jump to a specified address in the flash memory
Figure 20.11
Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode,
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode
(XIN Clock Stops)
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20.4.3
20. Flash Memory
Software Commands
The software commands are described below. Read or write commands and data in 8-bit units.
Table 20.4
Software Commands
First Bus Cycle
Command
Read array
Read status register
Clear status register
Program
Block erase
Mode
Write
Write
Write
Write
Write
Address
×
×
×
WA
×
Data
Mode
(D7 to D0)
FFh
70h
Read
50h
40h
Write
20h
Write
Second Bus Cycle
Address
Data
(D7 to D0)
×
SRD
WA
BA
WD
D0h
SRD: Status register data (D7 to D0)
WA: Write address (ensure the address specified in the first bus cycle is the same address as the write
address specified in the second bus cycle.)
WD: Write data (8 bits)
BA: Given block address
×: Any specified address in the user ROM area
20.4.3.1
Read Array Command
The read array command reads the flash memory.
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since the MCU remains in read array mode until another command is written, the contents of multiple
addresses can be read continuously.
In addition, the MCU enters read array mode after a reset.
20.4.3.2
Read Status Register Command
The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 20.4.4
Status Registers). When reading the status register, specify an address in the user ROM area.
Do not execute this command in EW1 mode.
The MCU remains in read status register mode until the next read array command is written.
20.4.3.3
Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the
status register are set to 0.
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20.4.3.4
20. Flash Memory
Program Command
The program command writes data to the flash memory in 1-byte units.
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the
same address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed.
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when autoprogramming completes. When suspend function enabled, the FMR44 bit is set to 1 during auto-programming
and set to 0 when auto-programming completes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been
finished (refer to 20.4.5 Full Status Check).
Do not write additions to the already programmed addresses.
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), program commands targeting blocks
0 to 3 are not acknowledged. When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1
register is set to 1 (rewriting disabled), program commands targeting block 0 are not acknowledged. When the
FMR16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged.
Figure 20.12 shows the Program Command (When Suspend Function Disabled). Figure 20.13 shows the
Program Command (When Suspend Function Enabled).
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register
mode until the next read array command is written. The status register can be read to determine the result of
auto-programming after auto-programming has completed.
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
No
Yes
Full status check
Program completed
Figure 20.12
Program Command (When Suspend Function Disabled)
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EW0 Mode
20. Flash Memory
Maskable interrupt(1)
Start
FMR40 = 1
FMR44 = 1 ?
No
Yes
Write the command code 40h
to the write address
FMR42 = 1(4)
I = 1 (enable interrupt)(3)
FMR46 = 1 ?
Write data to the write address
Yes
No
Access flash memory
Access flash memory
FMR44 = 0 ?
No
FMR42 = 0
Yes
REIT
Full status check
Program completed
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
REIT
Write the command code 40h
I = 1 (enable interrupt)
Write data to the write address
FMR42 = 0
FMR44 = 0 ?
No
Yes
Full status check
Program completed
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Figure 20.13
Program Command (When Suspend Function Enabled)
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20.4.3.5
20. Flash Memory
Block Erase
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus
cycle, an auto-erase operation (erase and verify) of the specified block starts.
The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has
completed (refer to 20.4.5 Full Status Check).
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), the block erase commands targeting
blocks 0 to 3 are not acknowledged. When the FMR02 bit is set to 1 (rewriting enabled) and the FMR15 bit in
the FMR1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not
acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase commands targeting block 1
are not acknowledged.
Do not use the block erase command during program-suspend.
Figure 20.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 20.15 shows
the Block Erase Command (When Erase-Suspend Function Enabled).
In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read
array command is written.
Start
Write the command code 20h
Write D0h to a given block
address
FMR00 = 1?
No
Yes
Full status check
Block erase completed
Figure 20.14
Block Erase Command (When Erase-Suspend Function Disabled)
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EW0 Mode
20. Flash Memory
Maskable interrupt(1)
Start
FMR40 = 1
FMR43 = 1 ?
No
Yes
Write the command code 20h
FMR41 = 1(4)
I = 1 (enable interrupt)(3)
FMR46 = 1 ?
Write D0h to any block
address
Yes
No
Access flash memory
Access flash memory
FMR00 = 1 ?
No
FMR41 = 0
Yes
Full status check
REIT
Block erase completed
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
Write the command code 20h
REIT
I = 1 (enable interrupt)
Write D0h to any block
address
FMR41 = 0
FMR00 = 1 ?
No
Yes
Full status check
Block erase completed
NOTES:
1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3. When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.
Figure 20.15
Block Erase Command (When Erase-Suspend Function Enabled)
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20.4.4
20. Flash Memory
Status Registers
The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 20.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
• When a given address in the user ROM area is read after writing the read status register command
• When a given address in the user ROM area is read after executing program or block erase command but
before executing the read array command.
20.4.4.1
Sequencer Status (Bits SR7 and FMR00)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during autoprogramming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.
20.4.4.2
Erase Status (Bits SR5 and FMR07)
Refer to 20.4.5 Full Status Check.
20.4.4.3
Program Status (Bits SR4 and FMR06)
Refer to 20.4.5 Full Status Check.
Table 20.5
Status Register Bits
Status Register
Bit
SR0 (D0)
SR1 (D1)
SR2 (D2)
SR3 (D3)
SR4 (D4)
FMR0 Register
Bit
−
−
−
−
FMR06
Reserved
Reserved
Reserved
Reserved
Program status
SR5 (D5)
FMR07
Erase status
SR6 (D6)
SR7 (D7)
−
FMR00
Reserved
Sequencer
status
Status Name
Description
0
−
−
−
−
Completed
normally
Completed
normally
−
Busy
Value After
Reset
1
−
−
−
−
Error
−
−
−
−
0
Error
0
−
Ready
−
1
D0 to D7:Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot
be accepted.
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20.4.5
20. Flash Memory
Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
Table 20.6
Errors and FMR0 Register Status
FRM0 Register (Status
Register) Status
Error
FMR07(SR5) FMR06(SR4)
1
1
Command
sequence
error
1
0
Erase error
0
1
Program error
Error Occurrence Condition
• When a command is not written correctly
• When invalid data other than that which can be written
in the second bus cycle of the block erase command is
written (i.e., other than D0h or FFh)(1)
• When the program command or block erase command
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input
• When attempting to erase the block for which rewriting
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write to a block for which rewriting
is disabled during write command input.
• When the block erase command is executed but autoerasure does not complete correctly
• When the program command is executed but not autoprogramming does not complete.
NOTE:
1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands.
At the same time, the command code written in the first bus cycle is disabled.
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20. Flash Memory
Command sequence error
Full status check
Execute the clear status register command
(set these status flags to 0)
FMR06 = 1
and
FMR07 = 1?
Yes
Command sequence error
Check if command is properly input
No
Re-execute the command
FMR07 = 1?
Yes
Erase error
No
Erase error
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
FMR06 = 1?
Yes
Program error
No
Yes
Re-execute block erase command
No
Program error
Execute the clear status register
command
(set these status flags to 0)
Full status check completed
Specify the other address besides the
write address where the error occurs for
the program address(1)
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Figure 20.16
Re-execute program command
Full Status Check and Handling Procedure for Individual Errors
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Block targeting for erasure
cannot be used
R8C/2A Group, R8C/2B Group
20.5
20. Flash Memory
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of Standard serial I/O modes:
• Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
• Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.
Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.
Contact the manufacturer of your serial programmer for details. Refer to the user’s manual of your serial
programmer for instructions on how to use it.
Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 20.8 lists the Pin Functions
(Flash Memory Standard Serial I/O Mode 3), and Figure 20.17 shows Pin Connections for Standard Serial I/O
Mode 3.
After processing the pins shown in Table 20.8 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
20.5.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match (refer to 20.3 Functions to Prevent Rewriting of Flash Memory).
Table 20.7
Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin
VCC,VSS
Name
Power input
VREF
Reference voltage input I
RESET
P4_6/XIN
P4_7/XOUT
P4_3/XCIN
P4_4/XCOUT
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_5
P5_0 to P5_4
P6_0 to P6_5
P8_0 to P8_6
P6_6
P6_7
MODE
Reset input
I
P4_6 input/clock input
P4_7 input/clock output
P4_3 input/clock input
P4_4 input/clock output
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
Input port P5
Input port P6
Input port P8
TXD output
RXD input
MODE
I
I/O
I
I/O
I
I
I
I
I
I
I
I
O
I
I
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I/O
Description
Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
Reference voltage input pin to A/D converter and D/A
converter.
Reset input pin.
Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins.
Connect crystal oscillator between pins XCIN and
XCOUT.
Input “H” or “L” level signal or leave the pin open.
Serial data output pin.
Serial data input pin.
Input “L” level signal.
R8C/2A Group, R8C/2B Group
Table 20.8
20. Flash Memory
Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin
VCC,VSS
Name
Power input
I/O
VREF
Reference voltage input
I
RESET
P4_6/XIN
Reset input
I
P4_6 input/clock input
I
P4_7/XOUT
P4_7 input/clock output
P4_3/XCIN
P4_3 input/clock input
P4_4/XCOUT
P4_4 input/clock output
Connect crystal oscillator between pins XCIN and
XCOUT when connecting external oscillator. Apply “H”
I/O and “L” or leave the pin open when using as a port.
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_5
P5_0 to P5_4
P6_0 to P6_7
P8_0 to P8_6
MODE
Input port P0
Input port P1
Input port P2
Input port P3
Input port P4
Input port P5
Input port P6
Input port P8
MODE
I
Input “H” or “L” level signal or leave the pin open.
I
I
I
I
I
I
I
I/O Serial data I/O pin. Connect to the flash programmer.
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REJ09B0324-0200
Page 513 of 580
Description
Apply the voltage guaranteed for programming and
erasure to the VCC pin and 0 V to the VSS pin.
Reference voltage input pin to A/D converter and D/A
converter.
Reset input pin.
Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins when connecting
I/O external oscillator. Apply “H” and “L” or leave the pin
open when using as input port.
I
33
34
35
36
37
38
39
40
41
42
43
44
45
46
20. Flash Memory
47
48
R8C/2A Group, R8C/2B Group
49
32
50
31
51
30
52
29
53
28
54
27
55
26
R8C/2A Group,
R8C/2B Group
56
57
58
25
24
23
59
22
60
21
16
15
14
13
12
11
10
9
8
7
6
17
5
18
64
4
63
3
19
2
20
62
1
61
VSS
MODE
VCC
Connect oscillator circuit(1)
Mode setting
Signal
Value
MODE
Voltage from programmer
RESET
VSS → VCC
Figure 20.17
Package: PLQP0064KB-A
PLQP0064GA-A
NOTE:
1. It is not necessary to connect an oscillating circuit
when operating with the on-chip oscillator clock.
Pin Connections for Standard Serial I/O Mode 3
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 514 of 580
R8C/2A Group, R8C/2B Group
20.5.1.1
20. Flash Memory
Example of Circuit Application in Standard Serial I/O Mode
Figure 20.18 shows an example of Pin Processing in Standard Serial I/O Mode 2 and Figure 20.19 shows an
example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the
programmer, refer to the manual of your serial programmer for details.
MCU
Data Output
TXD
Data Input
RXD
MODE
NOTES:
1. In this example, modes are switched between single-chip mode and
standard serial I/O mode by controlling the MODE input with a switch.
2. Connecting the oscillation is necessary. Set the main clock frequency 1
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example
with M16C Flash Starter (M3A-0806).
Figure 20.18
Pin Processing in Standard Serial I/O Mode 2
MCU
MODE I/O
MODE
Reset input
RESET
User reset signal
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit.
Figure 20.19
Pin Processing in Standard Serial I/O Mode 3
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 515 of 580
R8C/2A Group, R8C/2B Group
20.6
20. Flash Memory
Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figures 20.1 and 20.2 can be rewritten in parallel I/O mode.
20.6.1
ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to the 20.3
Functions to Prevent Rewriting of Flash Memory.)
Rev.2.00 Nov 26, 2007
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Page 516 of 580
R8C/2A Group, R8C/2B Group
20.7
20. Flash Memory
Notes on Flash Memory
20.7.1
CPU Rewrite Mode
20.7.1.1
Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
20.7.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
20.7.1.3
Interrupts
Table 20.9 lists the EW0 Mode Interrupts and Table 20.10 lists the EW1 Mode Interrupts.
Table 20.9
Mode
EW0 Mode Interrupts
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Any interrupt can be used Once an interrupt request is acknowledged,
by allocating a vector in auto-programming or auto-erasure is
forcibly stopped immediately and the flash
RAM
memory is reset. Interrupt handling starts
after the fixed period and the flash memory
restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it completes
normally.
Since the watchdog timer does not stop
during the command operation, interrupt
requests may be generated. Reset the
watchdog timer regularly.
When Maskable
Interrupt Request is
Acknowledged
Status
EW0 During auto-erasure
Auto-programming
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.00 Nov 26, 2007
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Page 517 of 580
R8C/2A Group, R8C/2B Group
Table 20.10
Mode
20. Flash Memory
EW1 Mode Interrupts
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Auto-erasure is suspended after Once an interrupt request is
acknowledged, auto-programming or
td(SR-SUS) and interrupt
auto-erasure is forcibly stopped
handling is executed. Autoimmediately and the flash memory is
erasure can be restarted by
reset. Interrupt handling starts after the
setting the FMR41 bit in the
FMR4 register to 0 (erase restart) fixed period and the flash memory
restarts. Since the block during autoafter interrupt handling
erasure or the address during autocompletes.
Auto-erasure has priority and the programming is forcibly stopped, the
normal value may not be read. Execute
interrupt request
auto-erasure again and ensure it
acknowledgement is put on
completes normally.
standby. Interrupt handling is
Since the watchdog timer does not stop
executed after auto-erasure
during the command operation,
completes.
Auto-programming is suspended interrupt requests may be generated.
Reset the watchdog timer regularly
after td(SR-SUS) and interrupt
using the erase-suspend function.
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
When Maskable Interrupt
Request is Acknowledged
Status
EW1 During auto-erasure
(erase-suspend
function enabled)
During auto-erasure
(erase-suspend
function disabled)
During autoprogramming
(program suspend
function enabled)
During autoprogramming
(program suspend
function disabled)
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
20.7.1.4
20. Flash Memory
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
20.7.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
20.7.1.6
Program
Do not write additions to the already programmed address.
20.7.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
20.7.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
21. Electrical Characteristics
The electrical characteristics of N version (Topr = –20°C to 85°C) and D version (Topr = –40°C to 85°C) are
listed below.
Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr =
–20°C to 105°C).
Table 21.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
-0.3 to 6.5
V
Input voltage
-0.3 to VCC + 0.3
V
VO
Output voltage
-0.3 to VCC + 0.3
V
Pd
Power dissipation
700
mW
Topr
Operating ambient temperature
-20 to 85 (N version) /
-40 to 85 (D version)
°C
Tstg
Storage temperature
-65 to 150
°C
VCC/AVCC
Supply voltage
VI
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 520 of 580
Condition
Topr = 25°C
R8C/2A Group, R8C/2B Group
Table 21.2
21. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC
Supply voltage
2.2
−
5.5
V
VSS/AVSS
Supply voltage
−
0
−
V
VIH
Input “H” voltage
0.8 VCC
−
VCC
V
VIL
Input “L” voltage
0
−
0.2 VCC
V
IOH(sum)
Peak sum output
“H” current
Sum of all pins IOH(peak)
−
−
−240
mA
IOH(sum)
Average sum
output “H” current
Sum of all pins IOH(avg)
−
−
−120
mA
IOH(peak)
Peak output “H”
current
IOH(avg)
Average output
“H” current
Except P2_0 to P2_7
−
−
-10
mA
P2_0 to P2_7
−
−
-40
mA
Except P2_0 to P2_7
−
−
-5
mA
P2_0 to P2_7
−
−
-20
mA
IOL(sum)
Peak sum output
“L” current
Sum of all pins IOL(peak)
−
−
240
mA
IOL(sum)
Average sum
output “L” current
Sum of all pins IOL(avg)
−
−
120
mA
IOL(peak)
Peak output “L”
current
mA
Except P2_0 to P2_7
−
−
10
P2_0 to P2_7
−
−
40
mA
Except P2_0 to P2_7
−
−
5
mA
IOL(avg)
Average output
“L” current
f(XIN)
XIN clock input oscillation frequency
−
−
20
mA
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
P2_0 to P2_7
f(XCIN)
XCIN clock input oscillation frequency
2.2 V ≤ VCC ≤ 5.5 V
0
−
70
kHz
−
System clock
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
FRA01 = 0
Low-speed on-chip
oscillator clock selected
−
125
−
kHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.7 V ≤ VCC ≤ 5.5 V
−
−
10
MHz
FRA01 = 1
High-speed on-chip
oscillator clock selected
2.2 V ≤ VCC ≤ 5.5 V
−
−
5
MHz
OCD2 = 0
XlN clock selected
OCD2 = 1
On-chip oscillator clock
selected
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
P0
P1
P2
P3
P4
P5
P6
P8
Figure 21.1
30pF
Ports P0 to P6, P8 Timing Measurement Circuit
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 521 of 580
R8C/2A Group, R8C/2B Group
Table 21.3
21. Electrical Characteristics
A/D Converter Characteristics(1)
Symbol
Parameter
−
Resolution
−
Absolute
accuracy
Conditions
Standard
Min.
Typ.
Max.
Unit
Vref = AVCC
−
−
10
Bit
10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±3
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
−
−
±2
LSB
10-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±5
LSB
8-bit mode
φAD = 10 MHz, Vref = AVCC = 3.3 V
−
−
±2
LSB
10-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±5
LSB
8-bit mode
φAD = 5 MHz, Vref = AVCC = 2.2 V
−
−
±2
LSB
Rladder
Resistor ladder
Vref = AVCC
10
−
40
kΩ
tconv
Conversion time 10-bit mode
φAD = 10 MHz, Vref = AVCC = 5.0 V
3.3
−
−
µs
φAD = 10 MHz, Vref = AVCC = 5.0 V
2.8
−
−
µs
2.2
−
AVCC
V
0
−
AVCC
V
0.25
−
10
MHz
8-bit mode
Vref
Reference voltage
VIA
Analog input voltage(2)
−
A/D operating
clock frequency
Without sample and hold
Vref = AVCC = 2.7 to 5.5 V
With sample and hold
Vref = AVCC = 2.7 to 5.5 V
1
−
10
MHz
Without sample and hold
Vref = AVCC = 2.2 to 5.5 V
0.25
−
5
MHz
With sample and hold
Vref = AVCC = 2.2 to 5.5 V
1
−
5
MHz
NOTES:
1. VCC/AVCC = Vref = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 21.4
D/A Converter Characteristics(1)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
−
Resolution
−
−
8
−
Absolute accuracy
−
−
1.0
%
tsu
Setup time
−
−
3
µs
RO
Output resistor
4
10
20
kΩ
IVref
Reference power input current
−
−
1.5
mA
(NOTE 2)
Bit
NOTES:
1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 522 of 580
R8C/2A Group, R8C/2B Group
Table 21.5
Flash Memory (Program ROM) Electrical Characteristics
Symbol
−
21. Electrical Characteristics
Parameter
Program/erase endurance(2)
Conditions
Standard
Unit
Min.
Typ.
Max.
R8C/2A Group
100(3)
−
−
times
R8C/2B Group
1,000(3)
−
−
times
µs
−
Byte program time
−
50
400
−
Block erase time
−
0.4
9
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time(7)
20
−
−
year
Ambient temperature = 55°C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 523 of 580
R8C/2A Group, R8C/2B Group
Table 21.6
21. Electrical Characteristics
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol
Parameter
−
Program/erase endurance(2)
−
Conditions
Standard
Min.
Typ.
Max.
Unit
10,000(3)
−
−
times
Byte program time
(program/erase endurance ≤ 1,000 times)
−
50
400
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
65
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
9
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
97+CPU clock
× 6 cycles
µs
−
Interval from erase start/restart until
following suspend request
650
−
−
µs
−
Interval from program start/restart until
following suspend request
0
−
−
ns
−
Time from suspend until program/erase
restart
−
−
3+CPU clock
× 4 cycles
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
2.2
−
5.5
V
−
Program, erase temperature
-20(8)
−
85
°C
−
Data hold time(9)
20
−
−
year
Ambient temperature = 55 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. -40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 524 of 580
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
time
Fixed time
Access restart
td(SR-SUS)
Figure 21.2
Table 21.7
Time delay until Suspend
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet0
Voltage detection level
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(2)
Vccmin
MCU operating voltage minimum value
VCA25 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.2
2.3
2.4
V
−
0.9
−
µA
−
−
300
µs
2.2
−
−
V
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 21.8
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Vdet1
Voltage detection level
−
Voltage monitor 1 interrupt request generation time(2)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
VCA26 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
2.70
2.85
3.00
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
Table 21.9
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
Parameter
Condition
Voltage detection level
−
Voltage monitor 2 interrupt request generation
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts(3)
time(2)
VCA27 = 1, VCC = 5.0 V
Standard
Unit
Min.
Typ.
Max.
3.3
3.6
3.9
V
−
40
−
µs
−
0.6
−
µA
−
−
100
µs
NOTES:
1. The measurement condition is VCC = 2.2 V to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 525 of 580
R8C/2A Group, R8C/2B Group
Table 21.10
21. Electrical Characteristics
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage(4)
−
−
0.1
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
−
Vdet0
V
trth
External power VCC rise gradient(2)
20
−
−
mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Vdet0(3)
2.2V
trth
External
Power VCC
Vdet0(3)
trth
Vpor2
Vpor1
Sampling time(1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Figure 21.3
Power-on Reset Circuit Electrical Characteristics
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 526 of 580
R8C/2A Group, R8C/2B Group
Table 21.11
21. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
fOCO40M
High-speed on-chip oscillator frequency
temperature • supply voltage dependence
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register
−
Value in FRA1 register after reset
−
Oscillation frequency adjustment unit of highspeed on-chip oscillator
−
−
Condition
Standard
Unit
Min.
Typ.
Max.
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2)
39.2
40
40.8
MHz
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2)
39.0
40
41.0
MHz
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(3)
35.2
40
44.8
MHz
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(3)
34.0
40
46.0
MHz
−
36.864
−
MHz
−3%
−
3%
%
VCC = 5.0 V, Topr = 25°C
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
08h
−
F7h
−
Adjust FRA1 register
(value after reset) to -1
−
+0.3
−
MHz
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
10
100
µs
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
550
−
µA
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the correction value in the FRA6 register is written to the FRA1 register.
Table 21.12
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
30
125
250
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
10
100
kHz
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
15
−
µA
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 21.13
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
1
−
2000
µs
td(R-S)
STOP exit time(3)
−
−
150
µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 527 of 580
R8C/2A Group, R8C/2B Group
Table 21.14
Symbol
21. Electrical Characteristics
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
tSUCYC
SSCK clock cycle time
4
−
−
tCYC(2)
tHI
SSCK clock “H” width
0.4
−
0.6
tSUCYC
tLO
SSCK clock “L” width
tRISE
SSCK clock rising
time
0.4
−
0.6
tSUCYC
Master
−
−
1
tCYC(2)
Slave
−
−
1
µs
Master
−
−
1
tCYC(2)
µs
tFALL
SSCK clock falling
time
−
−
1
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC(2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
−
−
1
tCYC(2)
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
2.2 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 528 of 580
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
SCS (output)
VIH or VOH
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
SCS (output)
VIH or VOH
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 21.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 529 of 580
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 21.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 530 of 580
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 21.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 531 of 580
R8C/2A Group, R8C/2B Group
Table 21.15
21. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
Symbol
Parameter
Standard
Condition
Unit
Min.
Typ.
Max.
12tCYC + 600(2)
−
−
ns
300(2)
ns
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
3tCYC +
−
−
tSCLL
SCL input “L” width
5tCYC + 500(2)
−
−
ns
tsf
SCL, SDA input fall time
−
−
300
ns
tSP
SCL, SDA input spike pulse rejection time
−
−
1tCYC(2)
ns
tBUF
SDA input bus-free time
5tCYC(2)
−
−
ns
tSTAH
Start condition input hold time
3tCYC(2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC(2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC(2)
−
−
ns
tSDAS
Data input setup time
1tCYC + 20(2)
−
−
ns
tSDAH
Data input hold time
0
−
−
ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 21.7
I/O Timing of I2C bus Interface
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 532 of 580
P(2)
tSDAS
tSDAH
R8C/2A Group, R8C/2B Group
Table 21.16
Electrical Characteristics (1) [VCC = 5 V]
Symbol
VOH
21. Electrical Characteristics
Parameter
Output “H” voltage
Condition
Max.
Unit
IOH = -5 mA
VCC − 2.0
−
VCC
V
IOH = -200 µA
VCC − 0.5
−
VCC
V
P2_0 to P2_7
Drive capacity HIGH IOH = -20 mA
VCC − 2.0
−
VCC
V
IOH = -5 mA
VCC − 2.0
−
VCC
V
Drive capacity HIGH IOH = -1 mA
VCC − 2.0
−
VCC
V
VCC − 2.0
−
VCC
V
XOUT
Drive capacity LOW
Output “L” voltage
Typ.
Except P2_0 to P2_7,
XOUT
Drive capacity LOW
VOL
Standard
Min.
IOH = -500 µA
Except P2_0 to P2_7,
XOUT
IOL = 5 mA
−
−
2.0
V
IOL = 200 µA
−
−
0.45
V
P2_0 to P2_7
Drive capacity HIGH IOL = 20 mA
−
−
2.0
V
Drive capacity LOW
IOL = 5 mA
−
−
2.0
V
Drive capacity HIGH IOL = 1 mA
−
−
2.0
V
−
−
2.0
V
0.1
0.5
−
V
0.1
1.0
−
V
−
−
5.0
µA
XOUT
Drive capacity LOW
IOL = 500 µA
VT+-VT-
Hysteresis
IIH
Input “H” current
VI = 5 V
IIL
Input “L” current
VI = 0 V
−
−
-5.0
µA
VI = 0 V
30
50
167
kΩ
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
RESET
RPULLUP Pull-up resistance
RfXIN
Feedback
resistance
XIN
−
1.0
−
MΩ
RfXCIN
Feedback
resistance
XCIN
−
18
−
MΩ
VRAM
RAM hold voltage
1.8
−
−
V
During stop mode
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 533 of 580
R8C/2A Group, R8C/2B Group
Table 21.17
Symbol
ICC
21. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 534 of 580
Min.
−
Standard
Typ.
Max.
12
20
Unit
mA
−
10
16
mA
−
7
−
mA
−
5.5
−
mA
−
4.5
−
mA
−
3
−
mA
−
6
12
mA
−
2.5
−
mA
−
150
400
µA
−
150
400
µA
−
35
−
µA
−
30
90
µA
−
18
55
µA
−
3.5
−
µA
−
2.3
−
µA
−
0.7
3.0
µA
−
1.7
−
µA
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 21.18
XIN Input, XCIN Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
50
−
ns
tWH(XIN)
XIN input “H” width
25
−
ns
tWL(XIN)
XIN input “L” width
25
−
ns
tc(XCIN)
XCIN input cycle time
14
−
µs
tWH(XCIN)
XCIN input “H” width
7
−
µs
tWL(XCIN)
XCIN input “L” width
7
−
µs
VCC = 5 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 21.8
Table 21.19
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
TRAIO Input, INT1 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
100
−
ns
tWH(TRAIO)
TRAIO input “H” width
40
−
ns
tWL(TRAIO)
TRAIO input “L” width
40
−
ns
VCC = 5 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 21.9
Table 21.20
TRAIO Input and INT1 Input Timing Diagram when VCC = 5 V
TRFI Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRFI)
TRFI input cycle time
400(1)
−
ns
tWH(TRFI)
TRFI input “H” width
200(2)
−
ns
tWL(TRFI)
TRFI input “L” width
200(2)
−
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 5 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 21.10
TRFI Input Timing Diagram when VCC = 5 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 535 of 580
R8C/2A Group, R8C/2B Group
Table 21.21
21. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
−
ns
tW(CKH)
CLKi input “H” width
100
−
ns
tW(CKL)
CLKi input “L” width
100
−
ns
td(C-Q)
TXDi output delay time
−
50
ns
th(C-Q)
TXDi hold time
0
−
ns
tsu(D-C)
RXDi input setup time
50
−
ns
th(C-D)
RXDi input hold time
90
−
ns
i = 0 to 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 21.11
Table 21.22
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 2, 3) Input
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INT0 input “H” width
250(1)
−
ns
INT0 input “L” width
250(2)
−
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 21.12
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 536 of 580
R8C/2A Group, R8C/2B Group
Table 21.23
Electrical Characteristics (3) [VCC = 3 V]
Symbol
VOH
21. Electrical Characteristics
Parameter
Output “H” voltage
Output “L” voltage
Standard
Unit
Min.
Typ.
Max.
VCC − 0.5
−
VCC
V
Except P2_0 to P2_7,
XOUT
IOH = -1 mA
P2_0 to P2_7
Drive capacity
HIGH
IOH = -5 mA
VCC − 0.5
−
VCC
V
Drive capacity
LOW
IOH = -1 mA
VCC − 0.5
−
VCC
V
Drive capacity
HIGH
IOH = -0.1 mA
VCC − 0.5
−
VCC
V
Drive capacity
LOW
IOH = -50 µA
VCC − 0.5
−
VCC
V
−
−
0.5
V
XOUT
VOL
Condition
Except P2_0 to P2_7,
XOUT
IOL = 1 mA
P2_0 to P2_7
Drive capacity
HIGH
IOL = 5 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 1 mA
−
−
0.5
V
Drive capacity
HIGH
IOL = 0.1 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 50 µA
−
−
0.5
V
0.1
0.3
−
V
0.1
0.4
−
V
−
−
4.0
µA
XOUT
VT+-VT-
Hysteresis
IIH
Input “H” current
VI = 3 V
IIL
Input “L” current
VI = 0 V
−
−
-4.0
µA
VI = 0 V
66
160
500
kΩ
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
RESET
RPULLUP Pull-up resistance
RfXIN
Feedback resistance
XIN
−
3.0
−
MΩ
RfXCIN
Feedback resistance
XCIN
−
18
−
MΩ
VRAM
RAM hold voltage
1.8
−
−
V
During stop mode
NOTE:
1. VCC =2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 537 of 580
R8C/2A Group, R8C/2B Group
Table 21.24
Symbol
ICC
21. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 538 of 580
Min.
−
Standard
Typ.
Max.
5.5
−
Unit
mA
−
2
−
mA
−
5.5
11
mA
−
2.2
−
mA
−
145
400
µA
−
145
400
µA
−
30
−
µA
−
28
85
µA
−
17
50
µA
−
3.3
−
µA
−
2.1
−
µA
−
0.65
3.0
µA
−
1.65
−
µA
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Table 21.25
XIN Input, XCIN Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
100
−
ns
tWH(XIN)
XIN input “H” width
40
−
ns
tWL(XIN)
XIN input “L” width
40
−
ns
tc(XCIN)
XCIN input cycle time
14
−
µs
tWH(XCIN)
XCIN input “H” width
7
−
µs
tWL(XCIN)
XCIN input “L” width
7
−
µs
VCC = 3 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 21.13
Table 21.26
TRAIO Input, INT1 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
300
−
ns
tWH(TRAIO)
TRAIO input “H” width
120
−
ns
tWL(TRAIO)
TRAIO input “L” width
120
−
ns
VCC = 3 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 21.14
Table 21.27
TRAIO Input and INT1 Input Timing Diagram when VCC = 3 V
TRFI Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRFI)
TRFI input cycle time
1200(1)
−
ns
tWH(TRFI)
TRFI input “H” width
600(2)
−
ns
tWL(TRFI)
TRFI input “L” width
600(2)
−
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 3 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 21.15
TRFI Input Timing Diagram when VCC = 3 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 539 of 580
R8C/2A Group, R8C/2B Group
Table 21.28
21. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
−
ns
tW(CKH)
CLKi input “H” width
150
−
ns
tW(CKL)
CLKi Input “L” width
150
−
ns
td(C-Q)
TXDi output delay time
−
80
ns
th(C-Q)
TXDi hold time
0
−
ns
tsu(D-C)
RXDi input setup time
70
−
ns
th(C-D)
RXDi input hold time
90
−
ns
i = 0 to 2
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 21.16
Table 21.29
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 2, 3) Input
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INT0 input “H” width
380(1)
−
ns
INT0 input “L” width
380(2)
−
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 21.17
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 540 of 580
R8C/2A Group, R8C/2B Group
Table 21.30
Electrical Characteristics (5) [VCC = 2.2 V]
Symbol
VOH
21. Electrical Characteristics
Parameter
Output “H” voltage
Output “L” voltage
Hysteresis
IIH
Input “H” current
IIL
Input “L” current
Unit
Typ.
Max.
VCC - 0.5
−
VCC
V
IOH = -1 mA
P2_0 to P2_7
Drive capacity
HIGH
IOH = -2 mA
VCC - 0.5
−
VCC
V
Drive capacity
LOW
IOH = -1 mA
VCC - 0.5
−
VCC
V
Drive capacity
HIGH
IOH = -0.1 mA
VCC - 0.5
−
VCC
V
Drive capacity
LOW
IOH = -50 µA
VCC - 0.5
−
VCC
V
−
−
0.5
V
Except P2_0 to P2_7,
XOUT
IOL = 1 mA
P2_0 to P2_7
Drive capacity
HIGH
IOL = 2 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 1 mA
−
−
0.5
V
Drive capacity
HIGH
IOL = 0.1 mA
−
−
0.5
V
Drive capacity
LOW
IOL = 50 µA
−
−
0.5
V
0.05
0.3
−
V
0.05
0.15
−
V
−
−
4.0
µA
XOUT
VT+-VT-
Standard
Min.
Except P2_0 to P2_7,
XOUT
XOUT
VOL
Condition
INT0, INT1, INT2,
INT3, KI0, KI1, KI2,
KI3, TRAIO, TRFI,
RXD0, RXD1, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
RESET
VI = 2.2 V
RPULLUP Pull-up resistance
VI = 0 V
−
−
-4.0
µA
VI = 0 V
100
200
600
kΩ
RfXIN
Feedback resistance
XIN
−
5
−
MΩ
RfXCIN
Feedback resistance
XCIN
−
35
−
MΩ
VRAM
RAM hold voltage
1.8
−
−
V
During stop mode
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 541 of 580
R8C/2A Group, R8C/2B Group
Table 21.31
Symbol
ICC
21. Electrical Characteristics
Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.2 to 2.7 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
on-chip
Low-speed on-chip oscillator on = 125 kHz
oscillator
No division
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed on- XIN clock off
chip oscillator High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
mode
Divide-by-8, FMR47 = 1
Low-speed
XIN clock off
High-speed on-chip oscillator off
clock mode
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1
Wait mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (high drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (low drive)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop mode
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Page 542 of 580
Min.
−
Standard
Typ.
Max.
2.5
−
Unit
mA
−
1
−
mA
−
4
−
mA
−
1.7
−
mA
−
110
300
µA
−
125
350
µA
−
27
−
µA
−
20
60
µA
−
12
40
µA
−
2.8
−
µA
−
1.9
−
µA
−
0.6
3.0
µA
−
1.60
−
µA
R8C/2A Group, R8C/2B Group
21. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
XIN Input, XCIN Input
Table 21.32
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
200
−
ns
tWH(XIN)
XIN input “H” width
90
−
ns
tWL(XIN)
XIN input “L” width
90
−
ns
tc(XCIN)
XCIN input cycle time
14
−
µs
tWH(XCIN)
XCIN input “H” width
7
−
µs
tWL(XCIN)
XCIN input “L” width
7
−
µs
VCC = 2.2 V
tC(XIN)
tWH(XIN)
XIN input
tWL(XIN)
Figure 21.18
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 21.33
TRAIO Input, INT1 Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRAIO)
TRAIO input cycle time
TBD
−
ns
tWH(TRAIO)
TRAIO input “H” width
TBD
−
ns
tWL(TRAIO)
TRAIO input “L” width
TBD
−
ns
VCC = 2.2 V
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 21.19
Table 21.34
TRAIO Input and INT1 Input Timing Diagram when VCC = 2.2 V
TRFI Input
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(TRFI)
TRFI input cycle time
2000(1)
−
ns
tWH(TRFI)
TRFI input “H” width
1000(2)
−
ns
tWL(TRFI)
TRFI input “L” width
1000(2)
−
ns
NOTES:
1. When using timer RF input capture mode, adjust the cycle time to (1/timer RF count source frequency × 3) or above.
2. When using timer RF input capture mode, adjust the pulse width to (1/timer RF count source frequency × 1.5) or above.
VCC = 2.2 V
tc(TRFI)
tWH(TRFI)
TRFI input
tWL(TRFI)
Figure 21.20
TRFI Input Timing Diagram when VCC = 2.2 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 543 of 580
R8C/2A Group, R8C/2B Group
Table 21.35
21. Electrical Characteristics
Serial Interface
Symbol
Standard
Parameter
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
800
−
ns
tW(CKH)
CLKi input “H” width
400
−
ns
tW(CKL)
CLKi input “L” width
400
−
ns
td(C-Q)
TXDi output delay time
−
200
ns
th(C-Q)
TXDi hold time
0
−
ns
tsu(D-C)
RXDi input setup time
150
−
ns
th(C-D)
RXDi input hold time
90
−
ns
i = 0 to 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 21.21
Table 21.36
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0, 2, 3) Input
Symbol
tW(INH)
tW(INL)
Standard
Parameter
Unit
Min.
Max.
INT0 input “H” width
1000(1)
−
ns
INT0 input “L” width
1000(2)
−
ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 2, 3
Figure 21.22
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 544 of 580
R8C/2A Group, R8C/2B Group
22. Usage Notes
22. Usage Notes
22.1
Notes on Clock Generation Circuit
22.1.1
Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit
to 1.
• Program example to enter stop mode
BCLR
BSET
FSET
BSET
JMP.B
LABEL_001 :
NOP
NOP
NOP
NOP
22.1.2
1,FMR0
0,PRCR
I
0,CM1
LABEL_001
; CPU rewrite mode disabled
; Protect disabled
; Enable interrupt
; Stop mode
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instruction
BCLR
1,FMR0
FSET
I
WAIT
NOP
NOP
NOP
NOP
22.1.3
; CPU rewrite mode disabled
; Enable interrupt
; Wait mode
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
22.1.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 545 of 580
R8C/2A Group, R8C/2B Group
22.2
22. Usage Notes
Notes on Interrupts
22.2.1
Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
22.2.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
22.2.3
External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 21.22 (VCC = 5V), Table 21.29 (VCC = 3V), Table 21.36 (VCC = 2.2V) External
Interrupt INTi (i = 0, 2, 3) Input and Table 21.19 (VCC = 5V), Table 21.26 (VCC = 3V), Table 21.33 (VCC
= 2.2V) TRAIO Input, INT1 Input.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 546 of 580
R8C/2A Group, R8C/2B Group
22.2.4
22. Usage Notes
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral
function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 22.1 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode
of peripheral function)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an
interrupt whose source is changed.
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated,
disable the peripheral function before changing the
interrupt source. In this case, use the I flag if all maskable
interrupts can be disabled. If all maskable interrupts cannot
be disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Figure 22.1
Example of Procedure for Changing Interrupt Sources
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 547 of 580
R8C/2A Group, R8C/2B Group
22.2.5
22. Usage Notes
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1:
Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
NOP
;
NOP
FSET
I
; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
MOV.W MEM,R0
; Dummy read
FSET
I
; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupts
AND.B #00H,0056H
; Set TRAIC register to 00h
POPC
FLG
; Enable interrupts
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 548 of 580
R8C/2A Group, R8C/2B Group
22.3
22. Usage Notes
Notes on Timers
22.3.1
Notes on Timer RA
• Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the
•
•
•
•
•
•
count starts.
Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instruction.
When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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22.3.2
22. Usage Notes
Notes on Timer RB
• Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
• Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the period when these two registers are being
read.
• In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR
register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in
programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer
count value before the timer stops.
• The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit.
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RB(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
• If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
• If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
22.3.2.1
Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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22.3.2.2
22. Usage Notes
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 22.2 and 22.3.
The following shows the detailed workaround examples.
• Workaround example (a):
As shown in Figure 22.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginning of period A.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
IR bit in
TRBIC register
Primary period
(a)
Interrupt request is
acknowledged
Secondary period
Ensure sufficient time
(b)
Interrupt request
is generated
Instruction in
Interrupt
sequence interrupt routine
Set the secondary and then
the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time
varies depending on the instruction being executed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 22.2
Workaround Example (a) When Timer RB interrupt is Used
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22. Usage Notes
• Workaround example (b):
As shown in Figure 22.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/
prescaler
underflow signal
TRBO pin output
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Primary period
Secondary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion
is detected at the end of the
secondary period.
Figure 22.3
Upon detecting (i), set the secondary and
then the primary register immediately.
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
22.3.2.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
• When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
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22.3.2.4
22. Usage Notes
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
• When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
• When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the
TOSST bit.
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22.3.3
22. Usage Notes
Notes on Timer RC
22.3.3.1
TRC Register
• The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTART bit in the TRCMR register
is set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register
is set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
• Reading from the TRC register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.W
#XXXXh, TRC
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.W
TRC,DATA
;Read
22.3.3.2
TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example
MOV.B
#XXh, TRCSR
;Write
JMP.B
L1
;JMP.B instruction
L1:
MOV.B
TRCSR,DATA
;Read
22.3.3.3
Count Source Switching
• Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
• After switching the count source from fOCO40M to another clock, allow a minimum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the settings of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator off).
22.3.3.4
Input Capture Function
• The pulse width of the input capture signal should be three cycles or more of the timer RC operation clock
(refer to Table 14.12 Timer RC Operation Clock).
• The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
22.3.3.5
TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
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22.3.4
22. Usage Notes
Notes on Timer RD
22.3.4.1
TRDSTR Register
• Set the TRDSTR register using the MOV instruction.
• When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
• Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the
CSELi bit is se to 0.
• To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi
bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be
stopped.
• Table 22.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j
= A, B, C, or D) pin with the timer RD output.
Table 22.1
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
Count Stop
When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count
stops.
When the CSELi bit is set to 0, the count stops at compare match of
registers TRDi and TRDGRAi.
22.3.4.2
TRDIOji Pin Output when Count Stops
Hold the output level immediately before the
count stops.
Hold the output level after output changes by
compare match.
TRDi Register (i = 0 or 1)
• When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then
write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to
the TRDi register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the
TRDCRi register.
- 001b (Clear by the TRDi register at compare match with the TRDGRAi register.)
- 010b (Clear by the TRDi register at compare match with the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear by the TRDi register at compare match with the TRDGRCi register.)
- 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
• When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.W
#XXXXh, TRD0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.W
TRD0,DATA
;Reading
22.3.4.3
TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Program example
MOV.B
#XXh, TRDSR0
;Writing
JMP.B
L1
;JMP.B
L1:
MOV.B
TRDSR0,DATA
;Reading
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22.3.4.4
22. Usage Notes
Count Source Switch
• Switch the count source after the count stops.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi register.
• When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO40M.
Change procedure
(1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops).
(2) Change bits TCK2 to TCK0 in the TRDCRi register.
(3) Wait 2 or more cycles of f1.
(4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
22.3.4.5
Input Capture Function
• Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.26 Timer RD Operation Clocks).
• The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD
operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or
D) (no digital filter).
22.3.4.6
Reset Synchronous PWM Mode
• When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
• Set to reset synchronous PWM mode by the following procedure:
Change procedure
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
22.3.4.7
Complementary PWM Mode
• When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
• Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
timing from the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Change procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
• Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
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22. Usage Notes
• If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR
register are set to 11b (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to
registers such as the TRDGRA0 register.
Count value in TRD0
register
Setting value in
TRDGRA0
register m
m+1
Set to 0 by a program
IMFA bit in
TRDSR0 register
No change
1
0
Transferred from
buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Figure 22.4
Not transferred from buffer register
Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Complementary PWM Mode
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22. Usage Notes
• The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation.
The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to
CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at
underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and
TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During
FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this
time, the OVF bit remains unchanged.
Count value in TRD0
register
1
0
FFFFh
Set to 0 by a program
UDF bit in
TRDSR0 register
1
OVF bit in
TRDSR0 register
1
0
No change
0
Transferred from
buffer register
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
Figure 22.5
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 10b
(transfer from the buffer register to the
general register when the TRD1 register
underflows).
Operation when TRD1 Register Underflows in Complementary PWM Mode
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22. Usage Notes
• Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the
following cases:
Value in buffer register ≥ value in TRDGRA0 register:
Transfer take place at underflow of the TRD1 register.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is
transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1
to CMD0.
n3
m+1
Count value in TRD0
register
n2
n1
Count value in TRD1
register
0000h
TRDGRD0 register
n2
n1
Transfer with timing set by
bits CMD1 to CMD0
n2
n1
Transfer
Transfer
Transfer
TRDGRB0 register
n2
n3
n3
Transfer at
underflow of TRD1
register because of
n3 > m
Transfer
n2
Transfer at
underflow of TRD1
register because
of first setting to
n2 < m
n1
Transfer with timing set by
bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match
between registers TRD0 and TRDGRA0 in complementary PWM mode).
• Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active ‘H” for normal-phase and counter-phase).
Figure 22.6
Operation when Value in Buffer Register ≥ Value in TRDGRA0 Register in
Complementary PWM Mode
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22. Usage Notes
When the value in the buffer register is set to 0000h:
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001h or above and a smaller value than the value of the
TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time
after setting, the value is transferred to the general register. After that, the value is transferred with the
timing selected by bits CMD1 to CMD0.
m+1
Count value in TRD0 register
n2
n1
Count value in TRD1 register
0000h
TRDGRD0 register
0000h
n1
Transfer
Transfer
TRDGRB0 register
n2
n1
n1
Transfer with timing
set by bits CMD1 to
CMD0
Transfer
0000h
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to
0000h.
Transfer
n1
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001h ≤ n1 < m
Transfer with timing
set by bits CMD1 to
CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register
The above applies under the following conditions:
• Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in
PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active “H” for normal-phase and counter-phase).
Figure 22.7
22.3.4.8
Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM
Mode
Count Source fOCO40M
• The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as
the count source).
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22.3.5
22. Usage Notes
Notes on Timer RE
22.3.5.1
Starting and Stopping Count
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register.
Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting
the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and
TRECSR.
22.3.5.2
Register Setting
Write to the following registers or bits when timer RE is stopped.
• Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2
• Bits H12_H24, PM, and INT in TRECR1 register
• Bits RCS0 to RCS3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
Figure 22.8 shows a Setting Example in Real-Time Clock Mode.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
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R8C/2A Group, R8C/2B Group
22. Usage Notes
TSTART in TRECR1 register = 0
TCSTF in
TRECR1 register = 0?
Stop timer RE operation
TREIC register←00h
(disable timer RE interrupt)
TRERST in TRECR1 register = 1
TRERST in TRECR1 register = 0
Setting of registers TRECSR,
TRESEC, TREMIN, TREHR,
TREWK, and bits H12_H24, PM,
and INT in TRECR1 register
Setting of TRECR2 register
Timer RE register
and control circuit reset
Select clock output
Select clock source
Seconds, minutes, hours, days of week, operating mode
Set a.m./p.m., interrupt timing
Select interrupt source
Setting of TREIC register (IR bit ←0,
select interrupt priority level)
TSTART in TRECR1 register = 1
Start timer RE operation
TCSTF in
TRECR1 register = 1?
Figure 22.8
Setting Example in Real-Time Clock Mode
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R8C/2A Group, R8C/2B Group
22.3.5.3
22. Usage Notes
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated
and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated).
Also, when reading several registers, an incorrect time will be read if data is updated before another register is
read after reading any register.
In order to prevent this, use the reading procedure shown below.
• Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register in the timer RE interrupt routine.
• Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC,
TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC
register is set to 1 (timer RE interrupt request generated).
• Monitoring with a program 2
(1) Monitor the BSY bit.
(2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY
bit is set to 1).
(3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register after the BSY bit is set to 0.
• Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the
TRECR1 register.
(2) Read the same register as (1) and compare the contents.
(3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read
contents match with the previous contents.
Also, when reading several registers, read them as continuously as possible.
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
22.3.6
22. Usage Notes
Notes on Timer RF
• Access registers TRF, TRFM0, and TRFM1 in 16-bit units.
Example of reading timer RF:
MOV.W
0290H,R0
; Read out timer RF
• In input capture mode, a capture interrupt request is generated by inputting an edge selected by bits
TRFC03 and TRFC04 in the TRFCR0 register even when the TSTART bit in the TRFCR0 register is set to
0 (count stops).
Rev.2.00 Nov 26, 2007
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R8C/2A Group, R8C/2B Group
22.4
22. Usage Notes
Notes on Serial Interface
• When reading data from the UiRB (i = 0 to 2) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the
UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0.
To check receive errors, read the UiRB register and then use the read data.
Example (when reading receive buffer register):
MOV.W
00A6H,R0
; Read the U0RB register
• When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B
#XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B
#XXH,00A2H ; Write the low-order byte of U0TB register
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R8C/2A Group, R8C/2B Group
22.5
22. Usage Notes
Notes on Clock Synchronous Serial Interface
22.5.1
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use
the clock synchronous serial I/O with chip select function.
22.5.2
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
22.5.2.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
• Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest
transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to
223 kbps (= 400/1.18) or more.
• Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS.
(b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the
MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0
again.
22.5.2.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode.
(a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register
before the rising edge of the 8th clock.
(b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
operation) to perform 1-byte communications.
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R8C/2A Group, R8C/2B Group
22.6
22. Usage Notes
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time
with a Synch Break detection interrupt as the starting point.
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R8C/2A Group, R8C/2B Group
22.7
22. Usage Notes
Notes on A/D Converter
• Write to each bit (other than ADST bit) in the ADCON0 register, each bit in the ADCON1 register, or the
•
•
•
•
•
•
•
SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
After changing the A/D operating mode, select an analog input pin again.
When using the one-shot mode, ensure that A/D conversion is completed before reading the AD0 register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
When using the repeat mode 0, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
Do not select the fOCO-F for the φAD.
If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD0 register.
Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
Do not enter stop mode during A/D conversion.
Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
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R8C/2A Group, R8C/2B Group
22.8
22. Usage Notes
Notes on Flash Memory
22.8.1
CPU Rewrite Mode
22.8.1.1
Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
22.8.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory:
UND, INTO, and BRK.
22.8.1.3
Interrupts
Table 22.2 lists the EW0 Mode Interrupts and Table 22.3 lists the EW1 Mode Interrupts.
Table 22.2
Mode
EW0 Mode Interrupts
When Watchdog Timer, Oscillation Stop
Detection, Voltage Monitor 1, or Voltage
Monitor 2 Interrupt Request is
Acknowledged
Any interrupt can be used Once an interrupt request is acknowledged,
by allocating a vector in auto-programming or auto-erasure is
RAM
forcibly stopped immediately and the flash
memory is reset. Interrupt handling starts
after the fixed period and the flash memory
restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it completes
normally.
Since the watchdog timer does not stop
during the command operation, interrupt
requests may be generated. Reset the
watchdog timer regularly.
When Maskable
Interrupt Request is
Acknowledged
Status
EW0 During auto-erasure
Auto-programming
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
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R8C/2A Group, R8C/2B Group
Table 22.3
Mode
22. Usage Notes
EW1 Mode Interrupts
When Watchdog Timer, Oscillation
Stop Detection, Voltage Monitor 1, or
Voltage Monitor 2 Interrupt Request is
Acknowledged
Auto-erasure is suspended after Once an interrupt request is
td(SR-SUS) and interrupt
acknowledged, auto-programming or
handling is executed. Autoauto-erasure is forcibly stopped
erasure can be restarted by
immediately and the flash memory is
setting the FMR41 bit in the
reset. Interrupt handling starts after the
FMR4 register to 0 (erase restart) fixed period and the flash memory
after interrupt handling
restarts. Since the block during autocompletes.
erasure or the address during autoAuto-erasure has priority and the programming is forcibly stopped, the
normal value may not be read. Execute
interrupt request
auto-erasure again and ensure it
acknowledgement is put on
completes normally.
standby. Interrupt handling is
Since the watchdog timer does not stop
executed after auto-erasure
during the command operation,
completes.
Auto-programming is suspended interrupt requests may be generated.
Reset the watchdog timer regularly
after td(SR-SUS) and interrupt
using the erase-suspend function.
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
When Maskable Interrupt
Request is Acknowledged
Status
EW1 During auto-erasure
(erase-suspend
function enabled)
During auto-erasure
(erase-suspend
function disabled)
During autoprogramming
(program suspend
function enabled)
During autoprogramming
(program suspend
function disabled)
NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
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R8C/2A Group, R8C/2B Group
22.8.1.4
22. Usage Notes
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
22.8.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
22.8.1.6
Program
Do not write additions to the already programmed address.
22.8.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
22.8.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
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R8C/2A Group, R8C/2B Group
22.9
22. Usage Notes
Notes on Noise
22.9.1
Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
22.9.2
Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
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R8C/2A Group, R8C/2B Group
23. Notes on On-Chip Debugger
23. Notes on On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/2A Group and R8C/2B Group take note
of the following.
(1)
(2)
(3)
(4)
(5)
Do not access the related UART1 registers.
Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
Do not use the BRK instruction in a user system.
Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for
details.
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R8C/2A Group, R8C/2B Group
24. Notes on Emulator Debugger
24. Notes on Emulator Debugger
When using the emulator debugger to develop the R8C/2A Group and R8C/2B Group program and debug, pay the
following attention.
(1)
Do not use the following flash memory areas because these areas are used for the emulator debugger.
When debugging of these areas, intensive evaluation on the real chip is required.
Target product: ROM capacity 128 MB product (Refer to Table 1.5 Product List for R8C/2A Group and
Table 1.6 Product List for R8C/2B Group)
Unusable area: Addresses 20000h to 23FFFh
Connecting and using the emulator debugger has some peculiar restrictions. Refer to each emulator debugger manual
for emulator debugger details.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 574 of 580
R8C/2A Group, R8C/2B Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
c
Reference
Symbol
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Terminal cross section
ZE
17
c1
*2
E
HE
b1
16
Index mark
ZD
c
A
*3
A1
y
e
A2
F
bp
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
A1
F
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
*3
Detail F
bp
x
Page 575 of 580
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
R8C/2A Group, R8C/2B Group
JEITA Package Code
P-TFLGA64-6x6-0.65
RENESAS Code
PTLG0064JA-A
Appendix 1. Package Dimensions
Previous Code
64F0G
MASS[Typ.]
0.07g
w S B
b1
D
S
AB
b
S
w S A
AB
e
A
e
H
G
F
E
E
D
C
B
A
y S
x4
v
Index mark
(Laser mark)
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 576 of 580
1
2
3
Index mark
4
5
6
7
8
Reference
Symbol
D
E
v
w
A
e
b
b1
x
y
Dimension in Millimeters
Min
Nom Max
6.0
6.0
0.15
0.20
1.05
0.65
0.31 0.35 0.39
0.39 0.43 0.47
0.08
0.10
R8C/2A Group, R8C/2B GroupAppendix 2. Connection Examples between Serial Writer and On-Chip Debugging
Appendix 2. Connection Examples between Serial Writer and On-Chip
Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2
shows a Connection Example with E8 Emulator (R0E000080KCE00).
TXD
6
7
9
10
11
12
49
50
51
52
53
43
42
41
40
39
38
37
31
32
53
52
30
29
28
27
26
25
RXD 4
22
33
21
34
16
20
35
15
19
36
14
17
7 VSS
44
13
18
TXD
54
45
8
10
55
46
4
24
VSS
56
47
3
R8C/2A Group,
R8C/2B Group
Connect oscillation
circuit(1)
57
48
2
5
RESET
58
59
60
61
62
1
23
MODE
63
64
VCC
1 VCC
M16C Flash Starter
(M3A-0806)
RXD
NOTE:
1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock.
Appendix Figure 2.1
Connection Example with M16C Flash Starter (M3A-0806)
Open collector buffer
4.7kΩ or more
User logic
14
13
12
RESET
4.7kΩ ±10%
MODE
8
49
50
51
45
6
7
8
9
11
44
43
42
41
40
39
38
37
NOTE:
1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock.
Appendix Figure 2.2
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Connection Example with E8 Emulator (R0E000080KCE00)
Page 577 of 580
32
31
30
29
28
27
26
17
E8 emulator
(R0E000080KCE00)
25
33
24
16
23
34
VSS
22
15
21
35
2
20
36
14
4
19
13
6
18
VCC
54
46
4
12
7 MODE
55
47
3
10
10
56
48
2
R8C/2A Group,
R8C/2B Group
VSS
57
1
5
Connect oscillation
circuit(1)
58
59
60
61
62
63
64
VCC
R8C/2A Group, R8C/2B Group
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
6
8
9
11
12
49
50
51
52
43
42
41
40
39
38
37
32
31
30
29
28
27
26
25
24
22
21
20
33
19
34
16
18
35
15
17
36
14
Example of Oscillation Evaluation Circuit
Page 578 of 580
44
13
NOTE:
1. After reset, the XIN and XCIN clocks stop.
Write a program to oscillate the XIN and XCIN clocks.
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
53
45
10
Appendix Figure 3.1
54
55
56
46
4
7
VSS
57
47
3
5
RESET
58
59
60
61
62
48
2
23
Connect
oscillation
circuit
1
R8C/2A Group,
R8C/2B Group
Connect
oscillation
circuit
63
64
VCC
R8C/2A Group, R8C/2B Group
Index
Index
[A]
AD0 ..................................................................................... 474
ADCON0 ............................................................................. 475
ADCON1 ............................................................................. 476
ADCON2 ............................................................................. 474
ADIC .................................................................................... 127
AIER .................................................................................... 143
[C]
CAPIC ................................................................................. 127
CM0 ....................................................................................... 96
CM1 ....................................................................................... 97
CMP0IC ............................................................................... 127
CMP1IC ............................................................................... 127
CPSRF ................................................................................ 101
CSPR .................................................................................. 152
[E]
DA0 to DA1 ......................................................................... 488
DACON ............................................................................... 488
[G]
FMR0 .................................................................................. 498
FMR1 .................................................................................. 499
FMR4 .................................................................................. 500
FRA0 ..................................................................................... 99
FRA1 ..................................................................................... 99
FRA2 ................................................................................... 100
FRA6 ................................................................................... 100
FRA7 ................................................................................... 100
[I]
ICCR1 ................................................................................. 427
ICCR2 ................................................................................. 428
ICDRR ................................................................................. 433
ICDRS ................................................................................. 433
ICDRT ................................................................................. 432
ICIER ................................................................................... 430
ICMR ................................................................................... 429
ICSR .................................................................................... 431
IICIC .................................................................................... 128
INT0IC ................................................................................. 129
INT1IC ................................................................................. 129
INT2IC ................................................................................. 129
INT3IC ................................................................................. 129
INTEN ................................................................................. 137
INTF .................................................................................... 138
[K]
KIEN .................................................................................... 141
KUPIC ................................................................................. 127
[M]
LINCR ................................................................................. 459
LINCR2 ............................................................................... 459
LINST .................................................................................. 460
MSTCR ............... 198, 250, 265, 283, 297, 308, 323, 396, 426
[O]
OCD ...................................................................................... 98
OFS ....................................................................... 36, 152, 493
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 579 of 580
[Q]
P2DRR .................................................................................. 70
PDi (i = 0 to 6 and 8) ............................................................. 68
PM0 ....................................................................................... 90
PM1 ....................................................................................... 90
PMR ....................................................... 70, 136, 380, 403, 433
PRCR .................................................................................. 121
PUR0 ..................................................................................... 71
PUR1 ..................................................................................... 71
PUR2 ..................................................................................... 71
Pi (i = 0 to 6 and 8) ................................................................ 69
[S]
S0RIC .................................................................................. 127
S0TIC .................................................................................. 127
S1RIC .................................................................................. 127
S1TIC ................................................................................... 127
S2RIC .................................................................................. 127
S2TIC .................................................................................. 127
SAR ..................................................................................... 432
RMAD0 ................................................................................ 143
RMAD1 ................................................................................ 143
SSCRH ................................................................................ 397
SSCRL ................................................................................. 398
SSER ................................................................................... 400
SSMR .................................................................................. 399
SSMR2 ................................................................................ 402
SSRDR ................................................................................ 403
SSSR ................................................................................... 401
SSTDR ................................................................................ 403
SSUIC .................................................................................. 128
[U]
U0C0 to U2C0 ..................................................................... 378
U0C1 to U2C1 ..................................................................... 379
U0BRG to U2BRG ............................................................... 377
U0MR to U2MR ................................................................... 377
U0RB to U2RB .................................................................... 379
U0TB to U2TB ..................................................................... 378
U1SR ................................................................................... 380
TRA ..................................................................................... 160
TRACR ................................................................................ 159
TRAIC .................................................................................. 127
TRAIOC ....................................... 159, 161, 164, 166, 168, 171
TRAMR ................................................................................ 160
TRAPRE .............................................................................. 160
TRC ..................................................................................... 202
TRBCR ................................................................................ 175
TRCCR1 ...................................................... 199, 222, 226, 231
TRCCR2 .............................................................................. 203
TRCDF ................................................................................ 204
TRCGRA ............................................................................. 202
TRCGRB ............................................................................. 202
TRCGRC ............................................................................. 202
TRCGRD ............................................................................. 202
TRBIC .................................................................................. 127
TRCIC .................................................................................. 128
TRCIER ............................................................................... 200
TRBIOC ............................................... 176, 178, 182, 184, 189
TRCIOR0 ............................................................. 206, 215, 220
TRCIOR1 ............................................................. 206, 216, 221
TRBMR ................................................................................ 176
TRCMR ................................................................................ 198
TRBOCR ............................................................................. 175
TRCOER ............................................................................. 205
R8C/2A Group, R8C/2B Group
TRBPR ................................................................................ 177
TRBPRE .............................................................................. 177
TRBSC ................................................................................ 177
TRCSR ................................................................................ 201
TRD0 ........................................... 259, 276, 291, 303, 316, 331
TRD0IC ............................................................................... 128
TRD1 ........................................................... 259, 276, 291, 316
TRD1IC ............................................................................... 128
TRDCR0 ...................................... 255, 271, 288, 301, 313, 329
TRDCR1 ...................................................... 255, 271, 288, 313
TRECR1 ...................................................................... 348, 355
TRECR2 ...................................................................... 349, 355
TRECSR ..................................................................... 350, 356
TRDDF0 .............................................................................. 254
TRDDF1 .............................................................................. 254
TRDFCR ..................................... 253, 268, 286, 299, 311, 326
TRDGRAi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TRDGRC1 ........................................................................... 316
TRDGRBi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TRDGRCi (i = 0 to 1) ........................... 260, 276, 292, 304, 332
TRDGRDi (i = 0 to 1) ................... 260, 276, 292, 304, 316, 332
TREIC ................................................................................. 127
TRDIER0 ..................................... 259, 275, 290, 303, 315, 331
TRDIER1 ..................................... 259, 275, 290, 303, 315, 331
TRDIORA0 .................................................................. 256, 272
TRDIORA1 .................................................................. 256, 272
TRDIORC0 .................................................................. 257, 273
TRDIORC1 .................................................................. 257, 273
TREHR ................................................................................ 347
TREMIN ...................................................................... 346, 354
TRDMR ....................................... 251, 266, 284, 298, 310, 325
TRDOCR ............................................................. 270, 288, 328
TRDOER1 ........................................... 269, 287, 300, 312, 327
TRDOER2 ........................................... 269, 287, 300, 312, 327
TRDPMR ............................................................. 252, 267, 285
TRDPOCR0 ........................................................................ 291
TRDPOCR1 ........................................................................ 291
TRESEC ...................................................................... 346, 354
TRDSR0 ...................................... 258, 274, 289, 302, 314, 330
TRDSR1 ...................................... 258, 274, 289, 302, 314, 330
TRDSTR ...................................... 251, 266, 284, 298, 309, 324
TREWK ............................................................................... 347
TRF ..................................................................................... 363
TRFCR0 .............................................................................. 364
TRFCR1 .............................................................................. 365
TRFIC .................................................................................. 127
TRFM0 ................................................................................ 363
TRFM1 ................................................................................ 363
TRFOUT .............................................................................. 365
[W]
VCA1 ..................................................................................... 45
VCA2 ............................................................................. 45, 101
WDC .................................................................................... 151
WDTR ................................................................................. 151
WDTS .................................................................................. 151
VW0C .................................................................................... 46
VW1C .................................................................................... 47
VW2C .................................................................................... 48
Rev.2.00 Nov 26, 2007
REJ09B0324-0200
Page 580 of 580
Index
REVISION HISTORY
REVISION HISTORY
R8C/2A Group, R8C/2B Group Hardware Manual
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Rev.
Date
0.01
Jul 28, 2006
−
First Edition issued
0.10
Sep 15, 2006
95
Figure 10.6 FRA1 register NOTE1 revised
110
Figure 10.14 revised
160
Table 14.5 revised
202
Figure 14.39 revised
254
Figure 14.80 revised
382
Figure 15.12 revised
428
Figure 16.33 revised
430
Figure 16.34, Figure 16.35 revised
432
Figure 16.36 revised
433
Figure 16.37 revised
461
Table 17.2 revised
496
18.6 revised
560
23 (2) revised, (5) deleted
1.00
Feb 09, 2007
Page
Summary
All pages “Preliminary” deleted
3
Table 1.2 revised
5
Table 1.4 revised
6
Table 1.5 and Figure 1.1 revised
7
Table 1.6 and Figure 1.2 revised
17
Figure 3.1 revised
18
Figure 3.2 revised
19
Table 4.1;
• 0008h: “Module Standby Control Register” → “Module Operation Enable Register” revised
• 000Ah: “00XXX000b” → “00h” revised
• 000Fh: “00011111b” → “00X11111b” revised
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6” added
23
Table 4.5;
0105h: “LIN Control Register 2” register name revised
36
5.2 and Figure 5.7 revised
42
Figure 6.5; VCA2 register NOTE6 revised
72
Table 7.17 and Table 7.19 revised
76
Table 7.29 and Table 7.31 revised
77
Table 7.35 revised
88
Table 9.1, Table 9.2 and Table 9.3 revised
89
Table 9.4 added
90
10 and Table 10.1 NOTE4 revised
91
Figure 10.1 revised
93
Figure 10.3 NOTE4 revised
96
Figure 10.6; FRA0 register NOTE2 revised
C-1
REVISION HISTORY
Rev.
Date
1.00
Feb 09, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
Summary
97
Figure 10.7; FRA2 register revised, FRA6 register added
98
Figure 10.9 NOTE6 revised
99
Figure 10.10 added
101
10.2.2 revised
106
10.5.1.2 and 10.5.1.4 revised
108
Table 10.3 revised
110
10.5.2.5 and Figure 10.14 revised
112
Figure 10.15 revised
117
10.7.1 and 10.7.2 revised
118
Figure 11.1 revised
121
12.1.3.1 revised
135
Figure 12.14 revised and Figure 12.15 added
136
Figure 12.16 NOTE1 revised
139
Table 12.6 revised
143
12.6.4 deleted
148
Figure 13.2; WDC register revised
180
Table 14.10 NOTE2 added
185
Table 14.11 NOTE2 added
192
Figure 14.25 revised
201
Table 14.15 revised
224
Table 14.23 revised
227
Figure 14.57 revised
244
Figure 14.67 revised
258
Table 14.40 revised
259
Figure 14.82 revised
260
Figure 14.83; TRDSTR register revised
271
Figure 14.95 revised
274
Figure 14.97 revised
276
Table 14.42 revised
277
Figure 14.99 revised
278
Figure 14.100; TRDSTR register revised
290
Table 14.44 revised
291
Figure 14.113 revised
292
Figure 14.114; TRDSTR register revised
302
Figure 14.124 revised
303
Figure 14.125 revised
316
Table 14.48 revised
317
Figure 14.137 revised
318
Figure 14.138 revised
C-2
REVISION HISTORY
Rev.
Date
1.00
Feb 09, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
331
355 to
367
Summary
14.4.12.1 and Table 14.51 revised
14.6; The following bit name is revised.
• TRFC00 → TSTART, TRFC01 → TCK0, TRFC02 → TCK1: Bits in
TRFCR0 register
• TRFC10 → TIPF0, TRFC11 → TIPF1, TRFC12 → CCLR, TRFC13 →
TMOD: Bits in TRFCR1 register
359
Figure 14.178 NOTE1 deleted
365
Figure 14.181 revised
367
14.6.3 revised
375
Table 15.1 NOTE2 revised
378
Figure 15.9 revised
381
Table 15.4 revised
384
Figure 15.12 revised
387
15.3 revised
390
Figure 16.2 MSTCR register added
395
Figure 16.7 NOTE2 revised
420
Figure 16.25 revised
421
Figure 16.26 NOTE7 added
423
Figure 16.28 NOTE3 revised
450
16.3.8.2 and 16.3.8.3 added
453
Figure 17.2; LINCR2 register revised
456
Figure 17.5 revised
460
Figure 17.9 revised
461
Figure 17.10 revised
462
17.4.3 and Figure 17.11 revised
463
17.4.4 added
469
Figure 18.3 NOTE4 revised
471
Table 18.2 revised
472
Figure 18.5 NOTE4 revised
475
Figure 18.7 NOTE4 revised
480
18.7 revised
483
Table 20.1 and Table 20.2 revised
484
20.2 and Figure 20.1 revised
485
Figure 20.2 revised
488
Table 20.3 NOTE1 revised
489
20.4.1 and 20.4.2; “td(SR-ES)” → “td(SR-SUS)” revised
490
20.4.2.3 and 20.4.2.4 revised
491
20.4.2.15 revised
492
Figure 20.5 revised
494
Figure 20.7 NOTE5 revised
C-3
REVISION HISTORY
Rev.
Date
1.00
Feb 09, 2007
2.00
Nov 26, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
Summary
496
Figure 20.9 “any area other than the flash memory” → “the RAM” revised
497
Figure 20.11; “any area other than the flash memory” → “the RAM”,
“15 µs” → “30 µs”, and NOTES 1 and 3 revised
499
20.4.3.4 revised
500
Figure 20.13 revised
501
20.4.3.5 revised
502
Figure 20.15 revised
504
Table 20.6 “FRM00 Register” → “FRM0 Register” revised
506
Table 20.7 revised
514
Table 21.2 revised
515
Table 21.3 and Table 21.4; NOTE1 revised
520
Table 21.11 revised
527
Table 21.17 revised
529
Table 21.21 and Figure 21.11; “i = 0 to 2” revised
531
Table 21.24 revised
533
Table 21.28 revised, Figure 21.16 “i = 0 to 2” revised
535
Table 21.31 revised
536
Table 21.34 revised
537
Table 21.35 and Figure 21.21; “i = 0 to 2” revised
538
22.1.1 and 22.1.2 revised
539
22.2.4 deleted
545
22.3.4.1 and Table 22.1 revised
554
22.3.6 revised
555
22.4 revised
557
22.5.2.2 and 22.5.2.3 added
559
22.7 revised
565
24. Notes on Emulator Debugger added
567
Appendix Figure 2.1 and Appendix Figure 2.2 revised
568
Appendix Figure 3.1 NOTE1 revised
−
“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A164A/E, TN-16C-A167A/E
All pages “PTLG0064JA-A (64F0G) package” added
2, 4
Table 1.1, Table 1.3 Clock: “Real-time clock (timer RE)” added
3, 5
Table 1.2 and Table 1.4;
• Operating Ambient Temperature: Y version added
• Package: 64-pin FLGA added
NOTE1 added
6, 7
Table 1.5 and Figure 1.1 revised
8, 9
Table 1.6 and Figure 1.2 revised
11
Figure 1.4 “64-pin LQFP Package” added
C-4
REVISION HISTORY
Rev.
Date
2.00
Nov 26, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
12
20, 21
Summary
Figure 1.5 added
Figure 3.1 and Figure 3.2 revised
22
Table 4.1 002Ch: High-Speed On-Chip Oscillator Control Register 7
added
25
Table 4.4 00F5h: After reset “00h” → “000000XXb” revised
36
Figure 5.3 revised
36, 152, Figure 5.4, Figure 13.3, Figure 20.4 OFS NOTE1 revised
493
37
5.1.1, 5.1.2 “Wait for 1/fOCO-S × 20.” → “Wait for 10 µs or more.”
38
Figure 5.5, Figure 5.6 revised
75
Table 7.17 Function: RXD0 input NOTE1 added
79
Table 7.29 revised
85
Table 7.54 Function: Input port NOTE1 added
Table 7.55 Function: RXD2 input NOTE1 added
86
Table 7.58 Function: RXD1 input NOTE1 added
94
Figure 10.1 “Clock prescaler” added
99
Figure 10.6 FRA1 revised
100
Figure 10.7 FRA2: NOTE2 deleted, FRA7 added
104
10.2.2 “The frequency correction .... to the FRA1 before use.” added
117
10.6.1 “To use the high-speed on-chip oscillator clock for the CPU clock
.... and then set bits OCD1 to OCD0 to 11b.” revised
136
12.2.1 “.... with the pulse output forced cutoff of timer RD and the INT1
pin is shared with the external trigger input pin of timer RA.”
→ “.... with the pulse output forced cutoff of timer RC and timer
RD, and the external trigger input of timer RB.”
147
Figure 12.22 NOTE2 revised
156
Table 14.1 Timer RE: Count sources “• fC32” deleted
157
Table 14.2 Timer RC: “TRDIOA” → “TRCIOA”, “TRDIOB” → “TRCIOB”,
“TRDIOC” → “TRCIOC”, “TRDIOD” → “TRCIOD”
Timer RF: Input pin “TCIN” → “TRFI”
158
Figure 14.1 “TSTART” → “TCSTF”
162
Figure 14.5 “Both bits TSTART ... are set to 0 (During count).”
→ “Both bits TSTART ... are set to 1 (During count).”
173
14.1.6 “• When the TRAPRE register is .... for each write interval.
• When the TRA register is .... for each write interval.” added
174
14.2 “The reload register and counter are allocated at the same
address” deleted
177
Figure 14.15 “Programmable one-shot mode” → “Programmable oneshot generation mode”
180
Figure 14.17 “Both bits TSTART .... are set to 0 (During count).”
→ “Both bits TSTART .... are set to 1 (During count).”
C-5
REVISION HISTORY
Rev.
Date
2.00
Nov 26, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
Summary
183
Table 14.10 Count stop conditions:
“• When the TOSSP .... is set to 0 (one-shot stops).”
→ “• When the TOSSP .... is set to 1 (one-shot stops).”
191
14.2.5 NOTE TRBIOC added
191 to 194 14.2.5.1, 14.2.5.2, 14.2.5.3, 14.2.5.4 added
204
Figure 14.37 TRCIOR0: b3 revised, NOTE4 added
213
14.3.4 “The TRCGRA register can .... input-capture trigger input.” added
Table 14.17 revised
214
Figure 14.43 revised
215
Figure 14.44 b3 revised, NOTE3 added
218
Table 14.19 Select functions:
“or output level inverted” → “or toggle output”
220
Figure 14.48 b3 revised
223
Figure 14.51 “• The CCLR bit in the TRCCR1 register is set to 0 ....”
→ “• The CCLR bit in the TRCCR1 register is set to 1 ....”
269
Figure 14.88 TRDOER1 revised
274
Figure 14.93 revised
280
Figure 14.99 revised
289
Figure 14.107 revised
298
Figure 14.116 “TRD” → “TRD0”
302
Figure 14.120 revised
304
Figure 14.123 NOTE1 revised
309
Figure 14.127 b0, b1 revised
310
Figure 14.128 “TRD” → “TRD0”
314
Figure 14.132 revised
324
Figure 14.140 revised
330
Figure 14.146 revised
334
Figure 14.150 “TSTP0 bit in TRDSTR register” → “CSEL0 bit in
TRDSTR register”
350
Figure 14.164 b0, b1: “Set to 00 in real-time clock mode.” → “Set to 00b
in real-time clock mode.”
359
Figure 14.173 revised
365
Figure 14.179 NOTE4 added
377
Figure 15.4 UARTi Transmit/Receive Mode Register revised
380
Figure 15.7 After Reset: “00h” → “000000XXb”, b1-b0 revised
388
Table 15.5 NOTE2 added
397
Figure 16.3 NOTE4 deleted
398
Figure 16.4 SOLP: “Cannot w rite to this.” → “The SOLP bit remains
unchanged even if 1 is written to it.”, NOTE4 deleted
399
Figure 16.5 NOTE2 deleted
C-6
REVISION HISTORY
Rev.
Date
2.00
Nov 26, 2007
R8C/2A Group, R8C/2B Group Hardware Manual
Description
Page
Summary
400
Figure 16.6 NOTE1 deleted
401
Figure 16.7 NOTE7 revised
402
Figure 16.8 NOTE5 revised
403
Figure 16.9 SSTDR NOTE1 deleted, SSRDR NOTE2 deleted
417
Figure 16.19 revised
423
16.2.8.1 deleted
427
Figure 16.26 NOTE6 deleted
428
Figure 16.27 NOTE5 deleted
429
Figure 16.28 NOTE7 deleted
430
Figure 16.29 NOTE3 deleted
431
Figure 16.30 NOTE7 deleted
432
Figure 16.31 SAR, ICDRT NOTE1 deleted
433
Figure 16.31 ICDRR NOTE1 deleted
456
16.3.8.1 deleted
457
Figure 17.1 revised
459
17.3 “• LIN Special Function Register (LINCR2)” → “• LIN Control
Register 2 (LINCR2)”
462, 463 Figure 17.5, Figure 17.6 revised
464
Figure 17.7 revised
466
Figure 17.9 revised
469
Figure 17.12 revised
484
Figure 18.11 revised
494
Table 20.3 Areas in which a rewrite control program can be executed:
EW1 Mode “Executing directly in user ROM area is possible”
→ “Executing directly in user ROM or RAM area possible”
500
Figure 20.7 NOTE5 revised
502
Figure 20.9 NOTE2 “Write to the FMR01 bit in the RAM.” added
503
Figure 20.11 NOTE4 deleted
506, 508 Figure 20.13, Figure 20.15 revised
520
Table 21.1 Pd: Rated Value “TBD” → “700” revised
521
Table 21.2 NOTE2 revised
527
Table 21.11 revised
562
Figure 22.8 revised
566
22.5.1.1, 22.5.2.1 deleted
577
Package Dimensions “PTLG0064JA-A (64F0G) package” added
578
Appendix Figure 2.1, Appendix Figure 2.2 revised
579
Appendix Figure 3.1 revised
C-7
R8C/2A Group, R8C/2B Group Hardware Manual
Publication Date:
Published by:
Rev.0.01
Rev.2.00
Jul 28, 2006
Nov 26, 2007
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan
R8C/2A Group, R8C/2B Group
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan