LC898214XD CMOS LSI AF Controller www.onsemi.com Overview This LSI is AF control LSI. It consists of 1 system of feedback circuit for AF control. Features Built-in equalizer circuit using digital operation - AF control equalize circuit - Any coefficient can be specified by I2C I/F WLCSP8, 1.15x2.37, 0.5P I2C Interface Built-in A/D converter - Maximum 10-bit - Input 2 channel Built-in D/A converter - 8-bit - Output 2-channel (Hall offset, Constant current Bias) Built-in Hall Sensor - Si Hall sensor Built-in EEPROM - 128 byte (8 byte/page) Built-in VGA - Hall Amp Built-in OSC - 48MHz Built-in Constant Current Driver Package - WL-CSP 8-pin - Pb-Free, Halogen Free Supply voltage - VDD (2.6V to 3.6V) * I2C Bus is a trademark of Philips Corporation. ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2015 January 2015 - Rev. 1 1 Publication Order Number : LC898214XD/D LC898214XD Pin Description I INPUT O B OUTPUT BIDIRECTION P TYPE Power supply, GND NC ■ I2C interface I2CCK I2CDT B B I2C Clock pin I2C Data pin ■ Hall interface HALL O Hall amp output ■ Driver interface OUT1 OUT2 O O Actuator output pin Actuator output pin ■ Power supply pin VDD VSS P P Power supply GND O Test pin NOT CONNECT ■ Test pin TEST *Process when pins are not used PIN TYPE “O” – Ensure that it is set to OPEN. PIN TYPE “I” – OPEN is inhibited. Ensure that it is connected to the VDD or VSS even when it is unused. (Please contact ON Semiconductor for more information about selection of VDD or VSS.) PIN TYPE “B” – If you are unsure about processing method on the pin description of pin layout table, please contact us. Note that incorrect processing of unused pins may result in defects. www.onsemi.com 2 LC898214XD Pin Layout Circuit Name Analog Logic Number of Pins 4 2 Circuit Name Driver Number of Pins 2 Backside pin layout diagram (Top View from the mold side) 4 TEST HALL 3 I2CDT I2CCK 2 VSS VDD 1 OUT2 OUT1 A B Block Diagram I2CDT I2CCK I2C I/F VDD EEPROM DA + - Hall Driver VDD + - Constant Current Driver Hall OUT1 OUT2 VGA AD Control logic EQ VDD Temp VDD OSC POR LDO TEST VSS HALL 0.01uF www.onsemi.com 3 LC898214XD Package Dimensions unit : mm WLCSP8, 1.15x2.37, 0.5P CASE 567KL ISSUE A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO THE SPHERICAL CROWNS OF SOLDER BALLS. A B E PIN A1 REFERENCE D DIM A A1 b D E e TOP VIEW 0.10 C A 0.08 C A1 NOTE 3 C SIDE VIEW MILLIMETERS MIN MAX 0.33 0.27 0.04 REF 0.12 0.22 1.12 1.18 2.34 2.40 0.50 BSC RECOMMENDED SOLDERING FOOTPRINT* SEATING PLANE PACKAGE OUTLINE A1 0.50 PITCH e/2 e/2 e e 8X 0.17 B 0.50 PITCH A 1 2 3 4 BOTTOM VIEW 8X b 0.05 C A B 0.03 C DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 4 LC898214XD Electrical Characteristics 1) Absolute maximum rating at VSS = 0V Item Symbol Condition Rating Unit Supply voltage VDD33 max Ta ≤25°C 0.3 to 4.6 V Input/output voltage VI33,VO33 Ta ≤25°C 0.3 to VDD33+0.3 V 55 to 125 °C Storage ambient temperature Tstg Operating ambient temperature Topr Continuous output current Iomax 30 to 70 °C 150 mA OUT1,OUT2 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2) Acceptable operation range at Ta = 30 to 70 °C, VSS = 0V 3V power supply (VDD) Item Supply voltage Symbol Min Std VDD33 2.6 2.8 3.6 V VIN 0 - VDD33 V Input voltage range Max Unit Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 3) DC characteristics : Input/output level at VSS = 0V, VDD = 2.6V to 3.6V, Ta = 30 to 70 °C Item Symbol Condition Min High-level input voltage VIH 1.4 Low-level input voltage VIL CMOS compliant Schmidt Low-level output voltage VOL IOL= 2mA Std Max Unit V 0.4 V 0.4 V Applicable pins I2CCK, I2CDT, I2CDT Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4) Driver output (OUT1, OUT2) at VSS = 0V, VDD = 2.8V, Ta = 25 °C Item Maximum current Output ON resistance Symbol Condition Min Ifull Ronu Compliance voltage Vcomp Output leak current Ioleak Std 108 Io=120mA Pch Max Unit 137 mA 2.8 Ω 1 A 0.9 V 0.5 Diode forward voltage VD ID=120mA Actuator resistance (Ract) = (VM-(Ronu*Io+Vcomp)) / Io [Ω] V Applicable pins OUT1, OUT2 5) Non-volatile Memory Characteristics Item Symbol Endurance EN Data retention RT Condition Min 10 www.onsemi.com 5 Std Max Unit 1000 Cycles Years Applicable pins E2PROM LC898214XD Hall element position Figure 1 : Hall element position Please refer to package diagram for each dimension. www.onsemi.com 6 LC898214XD AC Characteristics VDD supply timing Figure 2 : VDD supply timing It is available to use I2C 2ms later for Power On Reset of VDD. Item VDD turn on time 2 Symbol Min t1 Typ Max Unit 3 ms I C start time from VDD on t2 2 ms VDD off time t3 10 ms www.onsemi.com 7 LC898214XD AC specification Figure 2 shows interface timing definition and Table 1 shows electric characteristics. Figure 3 : I2C interface timing definition Table 1 : Electric characteritics for I2C interface (AC characteristics) Item I2CCK clock frequency START condition hold time I2CCK clock Low period I2CCK clock High period Setup time for repetition START condition Pin name Symbol Unit 400 kHz I2CCK tHD,STA 0.6 s tLOW I2CCK 1.3 s tHIGH I2CCK 0.6 s 0.6 s tSU,STA Data setup time tSU,DAT Bus free time between STOP and START Max I2CCK I2CDT tHD,DAT STOP condition setup time Typ Fi2cck Data hold time I2CDT, I2CCK rising time I2CDT, I2CCK falling time Min tr tf tSU,STO tBUF I2CCK I2CDT I2CCK I2CDT I2CCK I2CDT I2CCK I2CDT I2CCK I2CDT I2CCK I2CDT I2CCK I2CDT 0 (*) 0.9 100 s ns 300 ns 300 ns 0.6 s 1.3 s * : Although the I2C specification defines a condition that 300 ns of hold time is required internally, LC898214XD is designed for a condition with typ. 20 ns of hold time. If I2CDT signal is unstable around falling point of I2CCK signal, please implement an appropriate treatment on board, such as inserting a resistor. www.onsemi.com 8 LC898214XD ORDERING INFORMATION Device LC898214XD-MH Package WLCSP8, 1.15x2.37, 0.5P (Pb-Free / Halogen Free) Shipping (Qty / Packing) 5000 / Tape & Reel ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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