NL7SZ57 Configurable Multifunction Gate The NL7SZ57 is an advanced high−speed CMOS multifunction gate. The device allows the user to choose logic functions AND, OR, NAND, NOR, XNOR, INVERT and BUFFER. The device has Schmitt−trigger inputs, thereby enhancing noise immunity. The NL7SZ57 input and output structures provide protection when voltages up to 7.0 V are applied, irregardless of the supply voltage. http://onsemi.com 1 SC−88 (SOT−363) CASE 419B Features • • • • • • • High Speed: tPD = 3.2 ns (Typ) @ VCC = 5.0 V Low Power Dissipation: ICC = 1 mA (Maximum) at TA = 25°C Power Down Protection Provided on inputs Balanced Propagation Delays Overvoltage Tolerant (OVT) Input and Output Pins Ultra−Small Package This is a Pb−Free Device MARKING DIAGRAM 6 MN MG G 1 MN = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. PIN ASSIGNMENTS IN B 1 6 IN C GND 2 5 VCC IN A 3 4 OUT Y (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. 2 1 Publication Order Number: NL7SZ57/D NL7SZ57 IN A OUT Y IN B IN C Figure 1. Function Diagram PIN ASSIGNMENT FUNCTION TABLE* 1 IN B 2 GND A B C Y 3 IN A L L L H 4 OUT Y L L H L 5 VCC L H L H 6 IN C L H H H H L L L H L H L H H L L H H H H Input Output *To select a logic function, please refer to “Logic Configurations section”. http://onsemi.com 2 NL7SZ57 LOGIC CONFIGURATIONS B C B C VCC Y B Y 1 6 2 5 3 4 VCC B C Y C B Y Y C Figure 2. 2−Input AND (When A = “H”) B 1 6 2 5 3 4 C Y Figure 3. 2−Input NAND with input B inverted (When A = “L”) VCC VCC A C A C A Y A Y 1 6 2 5 3 4 C Y C A Y C Figure 4. 2−Input NAND with Input C Inverted (When B = “H”) A Y 1 6 2 5 3 4 C B Y 1 6 2 5 3 4 VCC C A Y A Y Figure 6. 2−Input XNOR (When A = B) 1 6 2 5 3 4 Y Figure 7. Inverter (When B = C = “L”) VCC B B Y Figure 5. 2−Input NOR (When B = “L”) VCC B C Y 1 6 2 5 3 4 Y Figure 8. Buffer (When A = “L” and C = “H”) http://onsemi.com 3 NL7SZ57 MAXIMUM RATINGS Symbol Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VIN DC Input Voltage −0.5 to +7.0 V DC Output Voltage −0.5 to +7.0 V VIN < GND −50 mA VOUT < GND −50 mA VOUT Parameter IIK DC Input Diode Current IOK DC Output Diode Current IO DC Output Source/Sink Current $50 mA ICC DC Supply Current Per Supply Pin $100 mA IGND DC Ground Current per Ground Pin $100 mA TSTG Storage Temperature Range −65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 °C TJ Junction Temperature Under Bias +150 °C qJA Thermal Resistance (Note 1) SC−88 350 °C/W PD Power Dissipation in Still Air at 85°C SC−88 200 mW MSL FR VESD ILATCHUP Moisture Sensitivity Level 1 Flammability Rating Oxygen Index: 28 to 34 ESD Withstand Voltage UL 94 V−0 @ 0.125 in Human Body Mode (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Latchup Performance Above VCC and Below GND at 125°C (Note 5) >2000 >200 N/A V $500 mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm by 1 inch, 2 ounce copper trace no air flow. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 1.65 5.5 V VCC Positive DC Supply Voltage VIN Digital Input Voltage 0 5.5 V Output Voltage 0 5.5 V −55 +125 °C 0 0 0 No Limit No Limit No Limit nS/V VOUT TA Operating Free−Air Temperature Dt/DV Input Transition Rise or Fall Rate VCC = 2.5 V $ 0.2 V VCC = 3.3 V $ 0.3 V VCC = 5.0 V $ 0.5 V http://onsemi.com 4 NL7SZ57 DC ELECTRICAL CHARACTERISTICS Symbol Parameter VT+ Positive Threshold Voltage VT− VH VOH VOL Conditions Negative Threshold Voltage Hysteresis Voltage Minimum High−Level Output Voltage Maximum Low−Level Output Voltage TA = 255C VCC (V) Min 1.65 0.79 1.16 2.3 1.11 3.0 4.5 5.5 Typ Max TA v +855C TA = −555C to +1255C Min Min Max Max Unit 1.16 1.16 V 1.56 1.56 1.56 1.5 1.87 1.87 1.87 2.16 2.74 2.74 2.74 2.61 3.33 3.33 3.33 1.65 0.35 0.62 0.35 0.35 2.3 0.58 0.87 0.58 0.58 3.0 0.84 1.19 0.84 0.84 4.5 1.41 1.9 1.41 1.41 5.5 1.78 2.29 1.78 1.78 1.65 0.30 0.62 0.30 0.62 0.30 0.62 2.3 0.40 0.8 0.40 0.8 0.40 0.8 3.0 0.53 0.87 0.53 0.87 0.53 0.87 4.5 0.71 1.04 0.71 1.04 0.71 1.04 1.2 0.8 1.2 0.8 1.2 V 5.5 0.8 1.65 − 5.5 VCC − 0.1 VCC − 0.1 VCC − 0.1 IOH = −4 mA 1.65 1.2 1.2 1.2 IOH = −8 mA 2.3 1.9 1.9 1.9 IOH = −16 mA 3.0 2.4 2.4 2.4 IOH = −24 mA 3.0 2.3 2.3 2.3 IOH = −32 mA 4.5 3.8 3.8 3.8 VIN w VT+MAX IOL = 50 mA 1.65 − 5.5 0.1 0.1 0.1 IOL = 4 mA 1.65 0.45 0.45 0.45 IOL = 8 mA 2.3 0.3 0.3 0.3 IOL = 16 mA 3.0 0.4 0.4 0.4 IOL = 24 mA 3.0 0.55 0.55 0.55 IOL = 32 mA 4.5 0.55 0.55 0.55 VIN v VT−MIN IOH = −50 mA V V VIN v VT−MIN V VIN w VT+MAX IIN Input Leakage Current 0 v VIN v 5.5 V 0 to 5.5 $0.1 $1.0 $1.0 mA ICC Quiescent Supply Current 0 v VIN v VCC 5.5 1.0 10 10 mA http://onsemi.com 5 NL7SZ57 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns) TA = 255C Typ Max Min Max Min Max Unit 1.65 − 1.95 3.2 8.5 14.4 3.2 14.4 3.2 14.4 ns 2.3 − 2.7 2 4.9 8.3 2 8.3 2 8.3 3.0 − 3.6 1.5 3.8 6.3 1.5 6.3 1.5 6.3 4.5 − 5.5 1.1 3.2 5.1 1.1 5.1 1.1 5.1 Parameter VCC (V) tPLH, tPHL Propagation Delay, Any Input to Output Y (See Test Circuit) Input Capacitance CPD Power Dissipation Capacitance (Note 6) TA = −555C to +1255C Min Symbol CIN TA v +855C Test Condition 5.0 f = 10 MHz 3.5 pF 22 pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the dynamic operating current consumption without load. Average operating current can be obtained by the equation ICC(OPR) = CPD • VCC • fin + ICC. CPD is used to determine the no−load dynamic power consumption: PD = CPD • VCC2 • fin + ICC • VCC. TEST CIRCUIT AND VOLTAGE WAVEFORMS From Output Under Test VLOAD RL Test S1 tPLH/tPHL Open tPLZ/tPZL VLOAD tPHZ/tPZH GND Open GND CL * RL *CL includes probes and jig capacitance. Figure 9. Load Circuit Inputs VCC VI tr/tf VM VLOAD CL RL VD 1.8 V $ 0.15 V VCC v 2 ns VCC/2 2 x VCC 30 pF 1 kW 0.15 V 2.5 V $ 0.2 V VCC v 2 ns VCC/2 2 x VCC 30 pF 500 W 0.15 V 3.3 V $ 0.3 V 3V v 2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V 5.5 V $ 0.5 V VCC v 2.5 ns VCC/2 2 x VCC 50 pF 500 W 0.3 V http://onsemi.com 6 NL7SZ57 Timing Input tW Input VI VM VM tsu 0V Data Input Figure 10. Voltage Waveforms Pulse Duration Input VM VM tPHL Output VM tPLH VM Output Control 0V tPHL tPLH Output VM Output Waveform 1 S1 at VLOAD (Note 1) VOH VOL th VM VI VM VM VM VM tPZH VOH Output Waveform 2 S1 at GND (Note 2) VOL Figure 12. Voltage Waveforms Propagation Delay Times Inverting and Noninverting Outputs 1. 2. 3. 4. 5. 0V 0V Figure 11. Voltage Waveforms Setup and Hold Times VI VM VI VM VM VI 0V VLOAD/2 VOL + VD VOL tPHZ VOH VOH − VD [0 V Figure 13. Voltage Waveforms Enable and Disable Times Low− and High−Level Enabling Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 W. The outputs are measured one at a time, with one transition per measurement. All parameters are waveforms are not applicable to all devices. ORDERING INFORMATION Device NL7SZ57DFT2G Package Shipping† SC−88 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NL7SZ57 PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE W NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419B−01 OBSOLETE, NEW STANDARD 419B−02. D e 6 5 4 1 2 3 HE DIM A A1 A3 b C D E e L HE −E− b 6 PL 0.2 (0.008) M E M MILLIMETERS MIN NOM MAX 0.80 0.95 1.10 0.00 0.05 0.10 0.20 REF 0.10 0.21 0.30 0.10 0.14 0.25 1.80 2.00 2.20 1.15 1.25 1.35 0.65 BSC 0.10 0.20 0.30 2.00 2.10 2.20 INCHES NOM MAX 0.037 0.043 0.002 0.004 0.008 REF 0.004 0.008 0.012 0.004 0.005 0.010 0.070 0.078 0.086 0.045 0.049 0.053 0.026 BSC 0.004 0.008 0.012 0.078 0.082 0.086 MIN 0.031 0.000 SOLDERING FOOTPRINT* A3 C 0.50 0.0197 A A1 L 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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