8ch LED Driver - ON Semiconductor

Ordering number : ENA1585B
LV5212VH
Bi-CMOS IC
8ch LED Driver
http://onsemi.com
Overview
The LV5212VH is a semiconductor integrated circuit that incorporates a serial input and serial or parallel output
8-stage shift register that features a CMOS structure based on Bi-CMOS process technology. The LV5212VH also
contains an n-channel CMOS construction high-withstand-voltage, large-current drive 8-stage parallel output driver.
Function
• Serial input and serial or parallel output
• Enable input for output control
• Serial output enables cascade connection
• Low supply current (0.0μA typ. during standby)
• Serial input/output levels compatible with typical CMOS devices
• High-withstand-voltage LED driver with open drain output
High withstand voltage (VDS < 50V)
High-current drive (IO max = 300mA)
• Operating temperature range Ta = -25 to 75°C
HSSOP16(275mil)
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
SVCC
Output voltage
VO max
LEDO1 to LEDO8 off
Output current
IO max
Allowable power dissipation
Pd max
Operating temperature
Topr
-25 to +75
°C
Storage temperature
Tstg
-40 to +125
°C
Ta ≤ 25°C *
6
V
50
V
300
mA
1000
mW
* Specified board : 114.3mm × 76.1mm × 1.6mm, glass epoxy board.
* The device must be used within the ranges warranted for its specifications so as to ensure its specified ratings (such as maximum ratings and operating
condition ranges) are not exceeded even momentarily.
Use of the device in such a way that its ratings are exceeded may cause failures, damage and other problems.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of this data sheet.
Semiconductor Components Industries, LLC, 2014
March, 2014
30614NK/00610SY/N1109SYPC 20091002-S00003 No.A1585-1/10
LV5212VH
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Recommended supply voltage
VCC
SVCC
5.0
V
Operating supply voltage range
VCC op
SVCC
3.0 to 5.5
V
Output applied voltage
VO
Output current
IO
Duty = 45% to 55%
50
V
300
mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics at Ta = 25°C, VCC = 5V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Quiescent current drain
ICC1
LEDO driver off (standby)
0
LEDO output on resistance
Ron
IO = 100mA
3
OFF leak current
Ileak
VO = 50V
0
VINH1
Input H level
L level 1
VINL1
Input L level
H level 2
VOUTH1
SOUT IO = -1mA
L level 2
VOUTL1
SOUT IO = 1mA
5
μA
Ω
10
μA
Control circuit block
H level 1
VCC × 0.8
0
V
VCC × 0.2
VCC -0.3
0
V
V
0.3
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
Pd max -- Ta
Allowable power dissipation, Pd max -- W
1.5
Specified board : 114.3 × 76.1 × 1.6mm3
glass epoxy
1.0
0.50
0.5
0
--25
0
25
50
75
100
Ambient temperature, Ta -- °C
No.A1585-2/10
LV5212VH
Package Dimensions
unit : mm
SOLDERING FOOTPRINT*
(Unit: mm)
1.00
HSSOP16 (275 mil)
CASE 943AF
ISSUE A
7.00
GENERIC
MARKING DIAGRAM*
0.80
0.42
NOTE: The measurements are not to guarantee but for reference only.
Land pattern design in Fin area to be altered in response to
customers’ individual application.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
No.A1585-3/10
LV5212VH
Pin Assignment
PGND2
LEDO7
LEDO8
SCK
SGND
PGND1
LEDO2
LEDO1
SDATAIN
XRESET
9
LEDO6
10
LEDO3
11
LEDO5
12
LEDO4
PGND2
LATCH
13
SOUT
14
XEN
15
SVCC
16
1
2
3
4
PGND1
5
6
7
8
Top view
Pin Descriptions
Pin No.
1
Pin name
I/O
SVCC
Description
Power supply
2
SOUT
O
shift register output (final-stage shift register)
3
LEDO4
O
LEDO4 Latch output (LEDO4 of shift register)
4
LEDO3
O
LEDO3 Latch output (LEDO3 of shift register)
5
LEDO2
O
LEDO2 Latch output (LEDO2 of shift register)
6
LEDO1
O
LEDO1 Latch output (LEDO1 of shift register)
7
SDATAIN
I
Serial input
8
XRESET
I
9
SGND
10
SCK
I
Clock input (for shift register)
11
LEDO8
O
LEDO8 Latch output (LEDO8 of shift register)
12
LEDO7
O
LEDO7 Latch output (LEDO7 of shift register)
13
LEDO6
O
LEDO6 Latch output (LEDO6 of shift register)
14
LEDO5
O
LEDO5 Latch output (LEDO5 of shift register)
15
LATCH
I
Reset input (shift register and latch)
GND
Latch input
When the latch input is held low, the LED0 output status is retained.
When a high-level is input, the LED0 outputs change when the status of the shift register changes.
16
XEN
I
Enable inputs (LEDO1 to LEDO8)
When a high-level is input, all the LED0 outputs are turned off.
When a low-level is input, the shift register data is output to LED0.
PGND1
PGND1
GND
PGND1
PGND2
GND
No.A1585-4/10
LV5212VH
Block Diagram
SCK SDATAIN LATCH XEN
SVCC
XRESET
LEDO1
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
LEDO2
LEDO3
D Q
C Q
R
D Q
C Q
R
LEDO4
D Q
C Q
R
D Q
C Q
R
LEDO5
D Q
C Q
R
D Q
C Q
R
LEDO6
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
D Q
C Q
R
LEDO7
LEDO8
D Q
C Q
R
SOUT SGND PGND1PGND2
Function
The LV5212VH consists of 1) an 8-stage D-type flip-flop and 2) an 8-stage D-type flip-flop connected to the output of
1). When data is supplied to the serial data input (SDATAIN) and the clock pulse is supplied to the clock input (SCK),
the serial data input signal is input to the internal shift register and the data already in the shift register shifted
sequentially when the clock changes from low to high.
The serial output (SOUT) is used to connect multiple LV5212VH to expand the number of bits and is connected to the
SDATAIN of the next stage. (Cascade connection supported.)
For parallel output, when the output control enable input (XEN) is low, the latch input (LATCH) changes from low to
high and the clock pulse input changes from low to high, the serial data input signal is output to LED01, and the output
is shifted sequentially. For parallel outputs (LED2 to LED8), the signals whose polarities inverted from those of the
serial data input (SDATAIN) are output.
When the EN input is high, outputs LED01 through LED01 all turn off.
When the reset input is low, outputs LED01 through LED8 and SOUT outputs all turn off. The power must be turned
on after checking that the reset input is low.
No.A1585-5/10
LV5212VH
Pin Functions
Pin No.
Pin Name
7
SDATAIN
10
SCK
Pin function
Equivalent Circuit
Pull-down input
SVCC
SGND
8
XRESET
15
LATCH
16
XEN
Pull-up input
SVCC
SGND
2
SOUT
SOUT output
SVCC
SOUT
SGND
3
LEDO4
4
LEDO3
5
LEDO2
6
LEDO1
11
LEDO8
12
LEDO7
13
LEDO6
14
LEDO5
LEDO outputs
LEDO1 to LEDO8
SVCC
SGND
PGND
No.A1585-6/10
LV5212VH
Timing conditions
Parameter
symbol
Conditions
min
typ
max
SCK Duty = 50%
unit
Clock frequency
fs1
10
Clock pulse width
twck
SCK
50
ns
Latch pulse width
twla
LATCH
50
ns
Data set up time
ts1
SDATAIN setup time relative to the rise of SCK
25
ns
Data hold time
th1
SDATAIN data hold time relative to the rise of SCK
25
ns
Clock latch time
tla1
Input conditions 1
ton
SCK and SDATAIN rise time
100
ns
Input conditions 2
toff
SCL and SDATAIN fall time
100
ns
100
MHz
ns
twck
SCK
2.5V
ts1
90%
2.5V
90%
10%
10%
th1
ton
2.5V
SDATAIN
toff
2.5V
twla
tla1
2.5V
LATCH
2.5V
SOUT output timings
Parameter
symbol
Conditions
min
typ
max
unit
SOUT delay time 1
tdso1
The time from a SCK falling edge to SOUT rising edge
50
MHz
SOUT delay time 2
tdso2
The time from a SCK falling edge to SOUT falling edge
50
ns
SCK
2.5V
2.5V
tdso1
tdso2
2.5V
2.5V
SOUT
No.A1585-7/10
LV5212VH
LEDO output timings
Parameter
symbol
LEDO delay time 1
tdled1
Conditions
min
The time from an XEN rising edge to LEDO rising edge
typ
max
unit
100
ns
100
ns
200
ns
200
ns
200
ns
CL = 30pF, IO = 100mA, VO = 30V
LEDO delay time 2
tdled2
The time from an XEN falling edge to LEDO falling edge
CL = 30pF, IO = 100mA, VO = 30V
LEDO rise time
trled
LEDO rise time
CL = 30pF, IO = 100mA, VO = 30V
LEDO fall time
tfled
LEDO fall time
CL = 30pF, IO = 100mA, VO = 30V
LEDO delay time 3
tdled3
The time from a LATCH rising edge to LEDO falling edge
CL = 30pF, IO = 100mA, VO = 30V
XEN
2.5V
2.5V
tdled2
tdled1
90%
LEDO
90%
90%
10%
10%
trled
tfled
tdled3
2.5V
LATCH
No.A1585-8/10
LV5212VH
Application Circuit Example
• When parallel output is used
max : 50V
max : 50V
SCK
LATCH
XEN
SDATAIN
sub CPU
SCK
LATCH
XEN
XRESET
PGND2
PGND1
SGND1
XRESET
SVCC
PGND1
sub CPU
SDATAIN
LEDO1
LEDO2
LEDO3
LEDO4
LEDO5
LEDO6
LEDO7
LEDO8
SOUT
SGND1
SVCC
5V
LEDO1
LEDO2
LEDO3
LEDO4
LEDO5
LEDO6
LEDO7
LEDO8
SOUT
Max IO : 300mA
PGND2
5V
• When serial output is used (SOUT cascade connection)
max:50V
5V
XEN
PGND1
XRESET
SCK
LATCH
XEN
XRESET
LEDO1
LEDO2
LEDO3
LEDO4
LEDO5
LEDO6
LEDO7
LEDO8
SOUT
To
SDATAIN
PGND2
LATCH
SDATAIN
PGND1
SCK
SVCC
SGND1
SDATAIN
SGND1
sub CPU
LEDO1
LEDO2
LEDO3
LEDO4
LEDO5
LEDO6
LEDO7
LEDO8
SOUT
PGND2
SVCC
No.A1585-9/10
LV5212VH
Allowable output current characteristics
IO -- LEDO
Ta
=
Output current, IO -- mA
250
25°
C
50°C
200
75°C
150
100
50
0
Ta = 25°C
250
50°C
200
75°C
150
100
50
duty cycle 100%
0
1
2
3
4
5
6
7
8
Number of output ports, LEDO
0
duty cycle 80%
0
1
2
3
4
5
6
7
8
Number of output ports, LEDO
IO -- LEDO
300
Ta = 25°C
50°C
250
Output current, IO -- mA
IO -- LEDO
300
Output current, IO -- mA
300
75°C
200
150
100
50
0
duty cycle 50%
0
1
2
3
4
5
6
7
8
Number of output ports, LEDO
ORDERING INFORMATION
Device
LV5212VH-MPB-H
Package
HSSOP16 (275mil)
(Pb-Free / Halogen Free)
LV5212VH-TLM-H
HSSOP16 (275mil)
(Pb-Free / Halogen Free)
Shipping (Qty / Packing)
48 / Fan-Fold
1000 / Tape & Reel
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PS No.A1585-10/10