LE25U40CQE

Ordering number : ENA2163
LE25U40CQE
CMOS IC
4M-bit (512K×8)
Serial Flash Memory
http://onsemi.com
Overview
The LE25U40CQE is a SPI bus flash memory device with a 4M bit (512K × 8-bit) configuration that adds a high
performance Dual output and Dual I/O function. It uses a single 2.5V power supply. While making the most of the
features inherent to a serial flash memory device, the LE25U40CQE is housed in an 8-pin ultra-miniature package.
All these features make this device ideally suited to storing program in applications such as portable information
devices, which are required to have increasingly more compact dimensions. The LE25U40CQE also has a small
sector erase capability which makes the device ideal for storing parameters or data that have fewer rewrite cycles and
conventional EEPROMs cannot handle due to insufficient capacity.
Features
• Read/write operations enabled by single 2.5V power supply: 2.3 to 3.6V supply voltage range
• Operating frequency
: 40MHz
• Temperature range
: -40 to 85°C
• Serial interface
: SPI mode 0, mode 3 supported / Dual Output, Dual I/O supported
• Sector size
: 4K bytes/small sector, 64K bytes/sector
• Small sector erase, sector erase, chip erase functions
• Page program function (256 bytes / page)
• Block protect function
• Highly reliable read/write
Number of rewrite times : 100,000 times
Small sector erase time : 40ms (typ.), 150ms (max.)
Sector erase time
: 80ms (typ.), 250ms (max.)
Chip erase time
: 250ms (typ.), 2.0s (max.)
Page program time
: 4.0ms/256 bytes (typ.), 5.0ms/256 bytes (max.)
• Status functions
: Ready/busy information, protect information
• Data retention period
: 20 years
• Package
: VSON8T(6.0¯5.0)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
D1912HK 20121120-S00004 No.A2163-1/22
LE25U40CQE
Package Dimensions
Figure 1 Pin Assignments
unit:mm (typ)
3447
TOP VIEW
8 VDD
CS 1
SIDE VIEW
BOTTOM VIEW
5.0
8
7 HOLD
SO/SIO1 2
6 SCK
(4.0)
VSS 4
0.6
5 SI/SIO0
(3.4)
6.0
WP 3
Top view
1
2
2
1
(0.595)
1.27
0.4
0.8 MAX
0.05 MAX
(0.75)
SIDE VIEW
SANYO : VSON8T(6.0X5.0)
Figure 2 Block Diagram
4M Bit
ADDRESS
XDECODER
BUFFERS
Flash EEPROM
Cell Array
&
LATCHES
Y-DECODER
I/O BUFFERS
&
DATA LATCHES
CONTROL
LOGIC
SERIAL INTERFACE
CS
SCK
SI/SIO0
SO/SIO1
WP
HOLD
Table 1 Pin Description
Symbol
SCK
Pin Name
Serial clock
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
SI/SIO0
SO/SIO1
CS
Serial data input
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
/ Serial data input output
serial clock. It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
Serial data input
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.
/ Serial data input output
It changes into the output pin at Dual Output and it changes into the input output pin at Dual I/O.
Chip select
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby
status when the logic level of the pin is high.
WP
Write protect
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
HOLD
Hold
Serial communication is suspended when the logic level of this pin is low.
VDD
Power supply
This pin supplies the 2.3 to 3.6V supply voltage.
VSS
Ground
This pin supplies the 0V supply voltage.
No.A2163-2/22
LE25U40CQE
Device Operation
The read, erase, program and other required functions of the device are executed through the command registers. The
serial I/O corrugate is shown in Figure 3 and the command list is shown in Table 2. At the falling CS edge the device is
selected, and serial input is enabled for the commands, addresses, etc. These inputs are normalized in 8 bit units and
taken into the device interior in synchronization with the rising edge of SCK, which causes the device to execute
operation according to the command that is input.
The LE25U40CQE supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is
automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of
SCK is high.
Figure 3 I/O waveforms
CS
Mode3
SCK
Mode0
8CLK
SI
1st bus
Nth bus
2nd bus
LSB
(Bit0)
MSB
(Bit7)
High Impedance
DATA
DATA
SO
Table 2 Command Settings
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
5th bus cycle
6th bus cycle
Nth bus cycle
Read
Command
03h
A23-A16
A15-A8
A7-A0
RD *1
RD *1
RD *1
High Speed Read
0Bh
A23-A16
A15-A8
A7-A0
X
RD *1
RD *1
Dual Read
3Bh
A23-A16
A15-A8
A7-A0
Z
RD *1
RD *1
Dual I/O Read
BBh
A23-A8
A7-A0,X, Z
RD *1
RD *1
RD *1
RD *1
20h / D7h
A23-A16
A15-A8
A7-A0
D8h
A23-A16
A15-A8
A7-A0
A23-A16
A15-A8
A7-A0
PD *2
PD *2
PD *2
X
X
Small sector erase
Sector erase
Chip erase
60h / C7h
Page program
02h
Write enable
06h
Write disable
04h
Power down
B9h
Status register read
05h
Status register write
01h
JEDEC ID read
9Fh
ID read
ABh
power down
B9h
Exit power down mode
ABh
DATA
X
Explanatory notes for Table 2
"X" signifies "don't care" (that is to say, any value may be input)., "Z” signifies " High Impedance ".
The "h" following each code indicates that the number given is in hexadecimal notation.
Addresses A23 to A19 for all commands are "Don't care".
*1: "RD" stands for read data. *2: "PD" stands for page program data.
No.A2163-3/22
LE25U40CQE
Table 3 Command Settings
4M Bit
sector(64KB)
7
6
5
4
3
2
1
0
small sector
127
to
112
111
to
96
95
to
80
79
to
64
63
to
48
47
to
32
31
to
16
15
to
2
1
0
address space(A23 to A0)
07F000h
07FFFFh
070000h
06F000h
070FFFh
06FFFFh
060000h
05F000h
060FFFh
05FFFFh
050000h
04F000h
050FFFh
04FFFFh
040000h
03F000h
040FFFh
03FFFFh
030000h
02F000h
030FFFh
02FFFFh
020000h
01F000h
020FFFh
01FFFFh
010000h
00F000h
010FFFh
00FFFFh
002000h
001000h
000000h
002FFFh
001FFFh
000FFFh
No.A2163-4/22
LE25U40CQE
Description of Commands and Their Operations
A detailed description of the functions and operations corresponding to each command is presented below.
1. Standard SPI read
There are two read commands, the standard SPI read command and High-speed read command.
1-1. Read command
Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following
(03h). The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 4-a Read"
shows the timing waveforms.
Figure 4-a Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
Mode0
8CLK
SI
03h
Add.
Add.
Add.
N
High Impedance
SO
DATA
MSB
N+1
N+2
DATA
DATA
MSB
MSB
1-2. High-speed Read command
Consisting of the first through fifth bus cycles, the High-speed read command inputs the 24-bit addresses and 8 dummy
bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference.
"Figure 4-b High-speed Read" shows the timing waveforms.
Figure 4-b High-speed Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55
Mode0
8CLK
SI
0Bh
Add.
Add.
Add.
X
MSB
SO
High Impedance
N
N+1
N+2
DATA
DATA
DATA
MSB
MSB
MSB
No.A2163-5/22
LE25U40CQE
2. Dual read
There are two Dual read commands, the Dual read command and the Dual I/O read command. They achieve the twice
speed-up from a High-speed read command.
2-1. Dual Read command
The Dual read command changes SI/SIO0 into the output pin function in addition to SO/SIO1, makes the data output x2
bit and has achieved a high-speed output. Consisting of the first through fifth bus cycles, the Dual read command inputs
the 24-bit addresses and 8 dummy bits following (3Bh). DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and
DATA0 (Bit6, Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of fifth bus cycle bit 0 as a
reference. "Figure 5-a Dual Read" shows the timing waveforms.
Figure 5-a Dual Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
43 44
47
Mode0
8CL
3Bh
SI/SIO0
Add.
Add.
DATA0
b6,b4,b2,b0
DATA1 DATA1 DATA1
DATA1
b7,b5,b3,b1
4CL
High Impedance
N+2
DATA0
DATA0 DATA0
MSB
SO/SIO1
N+1
N
dummy
bit
Add.
MSB
4CL
MSB
MSB
2-2. Dual I/O Read command
The Dual I/O read command changes SI/SIO0 and SO/SIO1 into the input output pin function, makes the data input and
output x2 bit and has achieved a high-speed output. Consisting of the first through third bus cycles, the Dual I/O read
command inputs the 24-bit addresses and 4 dummy clocks following (BBh). The format of the address input and the
dummy bit input is the x2 bit input. Add1 (A23, A21, -, A3 and A1) is input from S0/SIO1 and Add0 (A22, A20, -, A2
and A0) is input from SI/SIO0. 2CLK of the latter half of the dummy clock is in the state of high impedance, the
controller can switch I/O for this period. DATA1 (Bit7, BIt5, Bit3 and Bit1) is output from SI/SIO0 and DATA0 (Bit6,
Bit4, Bit2 and Bit0) is output from SO/SIO1 on the falling clock edge of third bus cycle bit 0 as a reference. "Figure 5-b
Dual I/O Read" shows the timing waveforms.
Figure 5-b Dual I/O Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
19 20 21 22 23 24
31
Mode0
dummy
bit
8CL
BBh
SI/SIO0
MSB
SO/SIO1
27 28
High Impedance
Add1:A22,A20-A2,A0
12CLK
Add2:A23,A21-A3,A1
X
N
N+2
DATA0
DATA0
b6,b4,b2,b0
DATA1 DATA1 DATA1
DATA1
b7,b5,b3,b1
4CLK
2CLK 2CLK
X
N+1
DATA0 DATA0
MSB
MSB
MSB
When SCK is input continuously after the read command has been input and the data in the designated addresses has
been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding
data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address
(7FFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic
level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO
is in a high-impedance state.
No.A2163-6/22
LE25U40CQE
3. Status Registers
The status registers hold the operating and setting statuses inside the device, and this information can be read (status
register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 4
Status registers" gives the significance of each bit.
Table 4 Status Registers
Bit
Bit0
Bit1
Bit2
Name
RDY
WEN
Logic
Function
0
Ready
Power-on Time Information
1
Erase/Program
0
Write disabled
1
Write enabled
0
0
BP0
0
Nonvolatile information
1
Bit3
Bit4
BP1
0
Block protect information
1
Protecting area switch
0
BP2
Nonvolatile information
Nonvolatile information
1
Bit5
TB
0
Block protect
1
Upper side/Lower side switch
0
Status register write enabled
1
Status register write disabled
Bit6
Bit7
Reserved bits
SRWP
Nonvolatile information
0
Nonvolatile information
3-1. Status register read
The contents of the status registers can be read using the status register read command. This command can be executed
even during the following operations.
• Small sector erase, sector erase, chip erase
• Page program
• Status register write
"Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus
cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the
clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first
to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized
to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by
returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is
continued. The data can be read by the status register read command at any time (even during a program or erase cycle).
Figure 6 Status Register Read
CS
Mode 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23
Mode 0
8CLK
SI
05h
MSB
SO
High Impedance
DATA
MSB
DATA
MSB
DATA
MSB
No.A2163-7/22
LE25U40CQE
3-2. Status register write
The information in status registers BP0, BP1, BP2, TB and SRWP can be rewritten using the status register write
command. RDY, WEN and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, TB
and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at
power-down. "Figure 6 Status Register Write" shows the timing waveforms of status register write, and Figure 20
shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command
initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and
program are performed automatically inside the device by status register write so that erasing or other processing is
unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2,
TB and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1) and bit 6 of the status register cannot be written,
no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register
write ends can be detected by RDY of status register read. To initiate status register write, the logic level of the WP pin
must be set high and status register WEN must be set to "1".
Figure 6 Status Register Write
Self-timed
Write Cycle
tSRW
CS
tWPH
tWPS
WP
Mode3
SCK
0 1 2 3 4 5 6 7 8
15
Mode0
8CLK
SI
01h
DATA
MSB
SO
High Impedance
3-3. Contents of each status register
RDY (Bit 0)
The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is
in a busy state, and when it is "0", it means that write is completed.
WEN (bit 1)
The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not
perform the write operation even if the write command is input. If it is set to "1", the device can perform write
operations in any area that is not block-protected.
WEN can be controlled using the write enable and write disable commands. By inputting the write enable command
(06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states,
WEN is automatically set to "0" in order to protect against unintentional writing.
• At power-on
• Upon completion of small sector erase, sector erase or chip erase
• Upon completion of page program
• Upon completion of status register write
* If a write operation has not been performed inside the LE25U40CQE because, for instance, the command input for
any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has
failed or a write operation has been performed for a protected address, WEN will retain the status established prior to
the issue of the command concerned. Furthermore, its state will not be changed by a read operation.
No.A2163-8/22
LE25U40CQE
BP0, BP1, BP2, TB (Bits 2, 3, 4, 5)
Block protect BP0, BP1, BP2 and TB are status register bits that can be rewritten, and the memory space to be protected
can be set depending on these bits. For the setting conditions, refer to "Table 5 Protect level setting conditions".
BP0, BP1, and BP2 are used to select the protected area and TB to allocate the protected area to the higher-order
address area or lower-order address area.
Table 5 Protect Level Setting Conditions
Status Register Bits
Protect Level
Protected Area
TB
BP2
BP1
BP0
0 (Whole area unprotected)
X
0
0
0
None
T1 (Upper side 1/8 protected)
0
0
0
1
07FFFFh to 070000h
T2 (Upper side 1/4 protected)
0
0
1
0
07FFFFh to 060000h
T3 (Upper side 1/2 protected)
0
0
1
1
07FFFFh to 040000h
B1 (Lower side 1/8 protected)
1
0
0
1
00FFFFh to 000000h
B2 (Lower side 1/4 protected)
1
0
1
0
01FFFFh to 000000h
B3 (Lower side 1/2 protected)
1
0
1
1
03FFFFh to 000000h
4 (Whole area protected)
X
1
X
X
07FFFFh to 000000h
* Chip erase is enabled only when the protect level is 0.
SRWP (bit 7)
Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten.
When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status
registers BP0, BP1, BP2, TB and SRWP are protected. When the logic level of the WP pin is high, the status registers
are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 6 SRWP setting
conditions".
Table 6 SRWP Setting Conditions
WP Pin
0
1
SRWP
Status Register Protect State
0
Unprotected
1
Protected
0
Unprotected
1
Unprotected
Bit 6 are reserved bits, and have no significance.
No.A2163-9/22
LE25U40CQE
4. Write Enable
Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is
the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command.
"Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable
command consists only of the first bus cycle, and it is initiated by inputting (06h).
• Small sector erase, sector erase, chip erase
• Page program
• Status register write
5. Write Disable
The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable"
shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by
inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command
(06h).
Figure 8 Write Enable
Figure 9 Write Disable
CS
CS
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
8CLK
SI
06h
04h
MSB
MSB
High Impedance
SO
High Impedance
SO
6. Power-down
The power-down command sets all the commands, with the exception of the silicon ID read command and the
command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows
the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting
(B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down
state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the
silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of
the power-down exit command.
Figure 10 Power-down
Figure 11 Exiting from Power-down
Power down
mode
Power down
mode
CS
CS
tPDR
tDP
Mode3
SCK
Mode3
0 1 2 3 4 5 6 7
SCK
Mode0
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
B9h
8CLK
SI
MSB
MSB
SO
High Impedance
ABh
SO
High Impedance
No.A2163-10/22
LE25U40CQE
7. Small Sector Erase
Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of
4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase
flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting
the 24-bit addresses following (20h) or (D7h). Addresses A18 to A12 are valid, and Addresses A23 to A19 are "don't
care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends
automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY.
Figure 12 Small Sector Erase
Self-timed
Erase Cycle
tSSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
Mode0
8CLK
SI
20h / D7h
Add.
Add.
Add.
MSB
High Impedance
SO
8. Sector Erase
Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure
13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command
consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h).
Addresses A18 to A16 are valid, and Addresses A23 to A19 are "don't care". After the command has been input, the
internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal
timer. Erase end can also be detected using status register RDY.
Figure 13 Sector Erase
Self-timed
Erase Cycle
tSE
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
Mode0
8CLK
SI
D8h
Add.
Add.
Add.
MSB
SO
High Impedance
No.A2163-11/22
LE25U40CQE
9. Chip Erase
Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the
timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus
cycle, and it is initiated by inputting (60h) or (C7h). After the command has been input, the internal erase operation
starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can
also be detected using status register RDY.
Figure 14 Chip Erase
Self-timed
Erase Cycle
tCHE
CS
Mode3
SCK
0 1 2 3 4 5 6 7
Mode0
8CLK
SI
60h / C7h
MSB
High Impedance
SO
10. Page Program
Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page
addresses: A18 to A8). Before initiating page program, the data on the page concerned must be erased using small
sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and
Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24bit addresses. Addresses A18 to A0 are valid. The program data is then loaded at each rising clock edge until the rising
CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256
bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is
not performed at the rising CS edge occurring at any other timing.
Figure 15 Page Program
Self-timed
Program Cycle
tPP
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
2079
Mode0
8CLK
SI
02h
Add.
Add.
Add.
PD
PD
PD
MSB
SO
High Impedance
No.A2163-12/22
LE25U40CQE
11. Silicon ID Read
ID read is an operation that reads the manufacturer code and device ID information. The silicon ID read command is not
accepted during writing. There are two methods of reading the silicon ID, each of which is assigned a device ID. In the
first method, the read command sequence consists only of the first bus cycle in which (9Fh) is input. In the subsequent
bus cycles, the manufacturer code 62h which is assigned by JEDEC, 2-byte device ID code (memory type, memory
capacity), and reserved code are output sequentially. The 4-byte code is output repeatedly as long as clock inputs are
present, "Table 7-1 JEDEC ID code " lists the silicon ID codes and "Figure 16-a JEDEC ID read" shows the JEDEC ID
read timing waveforms.
The second method involves inputting the ID read command. This command consists of the first through fourth bus
cycles, and the one bite silicon ID can be read when 24 dummy bits are input after (ABh). "Table 7-2 ID code " lists the
silicon ID codes and "Figure 16-b ID read" shows the ID read timing waveforms.
If the SCK input persists after a device code is read, that device code continues to be output. The data output is
transmitted starting at the falling edge of the clock for bit 0 in the fourth bus cycle and the silicon ID read sequence is
finished by setting CS high.
Table 7-1 JEDEC ID code
Table 7-2 ID code
Output code
1 byte device ID
Memory type
06h
Memory capacity code
13h(4M Bit)
1
00h
2 byte device ID
Device code
Output Code
62h
Manufacturer code
6E
(LE25U40C)
Figure 16-a JEDEC ID Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39
Mode0
8CL
SI
SO
9Fh
High Impedance
62h
MSB
06h
MSB
00h
13h
MSB
MSB
62h
MSB
Figure 16-b ID Read
CS
Mode3
SCK
0 1 2 3 4 5 6 7 8
15 16
31 32
23 24
39
Mode0
8CL
SI
SO
ABh
X
High Impedance
X
X
6Eh
MSB
6Eh
MSB
No.A2163-13/22
LE25U40CQE
12. Hold Function
Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure17
HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic
level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high,
HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited
and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state,
and SI and SCK are "don't care".
Figure 17 HOLD
Active
CS
Active
HOLD
tHS
tHS
SCK
tHH
tHH
HOLD
tHHZ
tHLZ
High Impedance
SO
13. Power-on
In order to protect against unintentional writing, CS must be within at VDD-0.3 to VDD+0.3 on power-on. After poweron, the supply voltage has stabilized at VDD min. or higher, waits for tPU before inputting the command to start a
device operation. The device is in the standby state and not in the power-down state after power is turned on. To put the
device into the power-down state, it is necessary to enter a power-down command.
Figure 18 Power-on Timing
CS = VDD level
VDD
Full Access Allowed
VDD(Max)
VDD(Min)
tPU
0V
No.A2163-14/22
LE25U40CQE
14. Hardware Data Protection
LE25U40CQE incorporates a power-on reset function. The following conditions must be met in order to ensure that the
power reset circuit will operate stably.
No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period.
Figure 19 Power-down Timing
VDD
VDD(Max)
VDD(Min)
tPD
0V
vBOT
Power-on timing
Parameter
power-on to operation time
Symbol
power-down time
tPU
tPD
power-down voltage
tBOT
spec
min
max
unit
100
µs
10
ms
0.2
V
14. Software Data Protection
The LE25U40CQE eliminates the possibility of unintentional operations by not recognizing commands under the
following conditions.
• When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK)
• When the page program data is not in 1-byte increments
• When the status register write command is input for 2 bus cycles or more
15. Decoupling Capacitor
A 0.1μF ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure
that the device will operate stably.
No.A2163-15/22
LE25U40CQE
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Maximum supply voltage
Conditions
Ratings
unit
VDDmax
With respect to VSS
-0.5 to +4.6
V
DC voltage (all pins)
VIN/VOUT
With respect to VSS
-0.5 to VDD+0.5
V
Storage temperature
Tstg
-55 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Operating Conditions
Parameter
Symbol
Conditions
Ratings
unit
Operating supply voltage
VDD
2.3 to 3.6
V
Operating ambient temperature
Topr
-40 to 85
°C
Allowable DC Operating Conditions
Parameter
Symbol
Ratings
Conditions
min
Read mode operating current
ICCR
SCK=0.1VDD/0.9VDD,
unit
max
25MHz
6
mA
40MHz
10
mA
40MHz
12
mA
15
mA
Single
HOLD=WP=0.9VDD,
Output=open
Dual
Write mode operating current
typ
ICCW
tSSE= tSE= tCHE=typ., tPP=max
CMOS standby current
ISB
CS=VDD, HOLD=WP=VDD,
SI=VSS/VDD, SO=open,
50
μA
Power-down standby current
IDSB
CS=VDD, HOLD=WP=VDD,
SI=VSS/VDD, SO=open,
10
μA
Input leakage current
ILI
2
μA
Output leakage current
ILO
2
μA
Input low voltage
VIL
-0.3
0.3VDD
V
Input high voltage
VIH
0.7VDD
VDD+0.3
V
Output low voltage
VOL
(erase+page program)
Output high voltage
VOH
IOL=100μA, VDD=VDD min
0.2
IOL=1.6mA, VDD=VDD min
0.4
IOH=-100μA, VDD=VDD min
V
VDD-0.2
V
Data hold, Rewriting frequency
Parameter
condition
Program/Erase
Rewriting frequency
min
max
unit
100,000
Status resister write
Data hold
times/Sector
1,000
times
20
year
Pin Capacitance at Ta=25°C, f=1MHz
Parameter
Symbol
Conditions
Ratings
unit
max
Output pin capacitance
CSO
VSO=0V
12
pF
Input pin Capacitance
CIN
VIN=0V
6
pF
Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values
for some of the sampled devices.
No.A2163-16/22
LE25U40CQE
AC Characteristics
Parameter
Ratings
Symbol
min
unit
typ
max
Read instruction(03h)
Clock frequency
All instructions except for read(03h)
Input signal rising/falling time
SCK logic high level pulse width
SCK logic low level pulse width
fCLK
tRF
25MHz
40MHz
25MHz
40MHz
tCLHI
tCLLO
25
MHz
40
MHz
0.1
V/ns
16
ns
11.5
ns
16
ns
11.5
ns
CS setup time
tCSS
8
ns
CS hold time
tCSH
8
ns
Data setup time
tDS
2
ns
Data hold time
tDH
5
ns
CS wait pulse width
tCPH
Output high impedance time from CS
tCHZ
Output data time from SCK
tV
Output data hold time
tHO
1
Output low impedance time from SCK
tCLZ
0
ns
HOLD setup time
tHS
5
ns
HOLD hold time
tHH
3
Output low impedance time from HOLD
tHLZ
9
ns
Output high impedance time from HOLD
tHHZ
9
ns
WP setup time
tWPS
20
ns
WP hold time
tWPH
20
ns
Power-down time
tDP
Power-down recovery time
tPDR
Write status register time
tSRW
5
Page programming cycle time
Small sector erase cycle time
tPP
tSSE
Sector erase cycle time
tSE
Chip erase cycle time
tCHE
25
ns
8
8
ns
11
ns
ns
ns
μs
3
3
μs
15
ms
4
5
ms
40
150
ms
80
250
ms
0.25
2.0
s
AC Test Condtions
Input pulse level··············· 0.2VDD to 0.8VDD
Input rising/falling time···· 5ns
Input timing level············· 0.3VDD, 0.7VDD
Output timing level ·········· 1/2×VDD
Output load ······················ 30pF
Note: As the test conditions for "typ", the measurements are conducted using 2.5V for VDD at room temperature.
0.8VDD
input level
input / output timing level
0.7VDD
1/2VDD
0.2VDD
0.3VDD
No.A2163-17/22
LE25U40CQE
Timing waveforms
Serial Input Timing
tCPH
CS
tCSH
tCSS
tCLHI
tCLLO tCSH
tCSS
SCK
tDS
SI
tDH
DATA VALID
High Impedance
SO
High Impedance
Serial Output Timing
CS
SCK
tCLZ
SO
tHO
tCHZ
DATA VALID
tV
SI
Hold Timing
CS
tHS
tHH
tHH
tHS
SCK
HOLD
tHLZ
tHHZ
High Impedance
SI
Status resistor write Timing
CS
tWPS
tWPH
WP
No.A2163-18/22
LE25U40CQE
Figure 20 Status Register Write Flowchart
Status register write
Start
06h
01h
Write enable
Set status register write
command
Data
status register write start
on rising edge of CS
05h
NO
Set status register read
command
Bit 0= “0” ?
YES
End of status register
write
* Automatically placed in write disabled state
at the end of the status register write
No.A2163-19/22
LE25U40CQE
Figure 21 Erase Flowcharts
Small sector erase
Sector erase
Start
Start
06h
Write enable
06h
D8h
20h / D7h
Address 1
NO
Address 1
Set small sector erase
command
Address 2
Address 2
Address 3
Address 3
Start erase on rising
edge of CS
Start erase on rising
edge of CS
Set status register read
command
05h
Write enable
05h
NO
Bit 0 = “0” ?
YES
End of erase
* Automatically placed in write disabled
state at the end of the erase
Set sector erase
command
Set status register read
command
Bit 0 = “0” ?
YES
End of erase
* Automatically placed in write disabled
state at the end of the erase
No.A2163-20/22
LE25U40CQE
Figure 22 Page Program Flowchart
Page program
Chip erase
Start
Start
06h
06h
Write enable
60h / C7h
Set chip erase
command
Write enable
02h
Address 1
Start erase on rising edge
of CS
05h
Set page program
command
Address 2
Address 3
Set status register read
command
Data 0
Bit 0 = “0” ?
Data n
YES
NO
Start program on rising
edge of CS
End of erase
* Automatically placed in write disabled state at
the end of the erase
Set status register read
command
05h
NO
Bit 0= “0” ?
YES
End of
programming
* Automatically placed in write disabled state at
the end of the programming operation.
No.A2163-21/22
LE25U40CQE
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PS No.A2163-22/22