LE25W81QE Advance Information www.onsemi.com CMOS LSI 8M-bit (1024K x 8) Serial Flash Memory Overview The LE25W81QE is a serial interface-compatible flash memory device with a 1M 8-bit configuration. It uses a single 2.6V power supply for both reading and writing (program and erase functions) and does not require a special power supply. As such, it can support on-board programming. It has three erase functions, each of which corresponds to the size of the memory area in which the data is to be erased at one time: the small sector (4K bytes) erase function, the sector (64K bytes) erase function, and the chip erase function (for erasing all the data together). The memory space can be efficiently utilized by selecting one of these functions depending on the application. A page program method is supported for data writing. The page VDFN8 5x6, 1.27P / VSON8T (6x5) program method of LE25W81QE can program any amount of data from 1 to 256 bytes. This IC incorporates ON Semi’s unique high-speed programming function which enables fast 0.3ms (typ.) page program time. The program time of 1.5s (typ.) when programming 8-Mbit full-memory space makes for fast data writing when the chip erase function is used. While making the most of the features inherent to a serial flash memory device, the LE25W81QE is housed in an 8-pin ultra-miniature package. Serial flash memory devices tend to be at a disadvantage in terms of their read speed, but the LE25W81QE has maximally eliminated this speed-related disadvantage by supporting clocks with frequencies up to 50MHz under SPI bus specifications. All these features make this device ideally suited to storing program codes in applications such as portable information devices and small disk systems, which are required to have increasingly more compact dimensions. Features Read/write operations enabled by single 2.6V power supply : 2.45 to 3.6V supply voltage range Operating frequency : 30MHz Temperature range : –20 to +70C (Read operation) 0 to +70C (Write operation) Serial interface : SPI mode 0, mode 3 supported Sector size : 4K bytes/small sector, 64K bytes/sector Small sector erase, sector erase, chip erase functions Page program function (256 bytes / page) Block protect function Highly reliable read/write Number of rewrite times: 100,000 times Small sector erase time : 80ms (typ.), 300ms (max.) Sector erase time : 100ms (typ.), 400ms (max.) Chip erase time : 250ms (typ.), 3.0s (max.) Page program time : 0.3ms/256 bytes (typ.), 1ms/256 bytes (max.) Status functions : Ready/busy information, protect information Data retention period : 20 years Package : VDFN8 56 * This product is licensed from Silicon Storage Technology, Inc. (USA). This document contains information on a new product. Specifications and information herein are subject to change without notice. ORDERING INFORMATION See detailed ordering and shipping information on page 21 of this data sheet. © Semiconductor Components Industries, LLC, 2014 November 2014 - Rev. P0 1 Publication Order Number : LE25W81QE/D LE25W81QE Package Dimensions unit : mm VDFN8 5x6, 1.27P / VSON8T (6x5) CASE 509AG ISSUE O Figure 1 Pin Assignments CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK 5 SI VSS 4 Top view www.onsemi.com 2 LE25W81QE Figure 2 Block Diagram 8M Bit Flash EEPROM Cell Array XDECODER ADDRESS BUFFERS & LATCHES Y-DECODER I/O BUFFERS & DATA LATCHES CONTROL LOGIC SERIAL INTERFACE CS SCK SI SO WP HOLD Table 1 Pin Description Symbol Pin Name Description This pin controls the data input/output timing. SCK Serial clock The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is output synchronized to the falling edge of the serial clock. The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the SI Serial data input SO Serial data output CS Chip select WP Write protect The status register write protect (SRWP) takes effect when the logic level of this pin is low. HOLD Hold Serial communication is suspended when the logic level of this pin is low. VDD Power supply This pin supplies the 2.45 to 2.75V supply voltage. VSS Ground This pin supplies the 0V supply voltage. serial clock. The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock. The device becomes active when the logic level of this pin is low; it is deselected and placed in standby status when the logic level of the pin is high. www.onsemi.com 3 LE25W81QE Table 2 Command Settings Command Read Small sector erase 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 03h A23-A16 A15-A8 A7-A0 0Bh A23-A16 A15-A8 A7-A0 D7h or 20h A23-A16 A15-A8 A7-A0 Sector erase D8h A23-A16 A15-A8 A7-A0 Chip erase C7h Page program 02h A23-A16 A15-A8 A7-A0 Write enable 06h X A7-A0 Write disable 04h Power down B9h Status register read 05h Status register write 01h Read silicon ID 1 *2 9Fh Read silicon ID 2 *3 ABh Exit power down mode ABh 5th bus cycle 6th bus cycle Nth bus cycle PD *1 PD *1 X PD *1 DATA X Explanatory notes for Table 2 "X" signifies "don't care" (that is to say, any value may be input). The "h" following each code indicates that the number given is in hexadecimal notation. Addresses A23 to A20 for all commands are "Don't care". In order for commands other than the read command to be recognized, CS must rise after all the bus cycle input. *1: "PD" stands for page program data. Any amount of data from 1 to 256 bytes in 1-byte unit is input. *2: Of the two silicon ID commands, it is for the command with the 9Fh setting that the manufacturer code 62h is first output. For as long as the clock input is continued, 26h of the device code is output continuously, followed by the repeated output of 62h and 26h. *3: Of the two silicon ID commands, it is for the command with the ABh setting that manufacturer code 62h is first output when address A0 is "0", and the device code 27h is first output when address A0 is "1". Addresses A7 to A1 are "don't care". For as long as the clock input is continued, 62h and 26h are repeatedly output. www.onsemi.com 4 LE25W81QE Device Operation The LE25W81QE features electrical on-chip erase functions using a single 2.6V power supply, that have been added to the EPROM functions of the industry standard that support serial interfaces. Interfacing and control are facilitated by incorporating the command registers inside the chip. The read, erase, program and other required functions of the device are executed through the command registers. The command addresses and data input in accordance with "Table 2 Command Settings" are latched inside the device in order to execute the required operations. "Figure 3 Serial Input Timing" shows the timing waveforms of the serial data input. First, at the falling CS edge the device is selected, and serial input is enabled for the commands, addresses, etc. These inputs are introduced internally in sequence starting with bit 7 in synchronization with the rising SCK edge. At this time, output pin SO is in the high-impedance state. The output pin is placed in the low-impedance state when the data is output in sequence starting with bit 7 synchronized to the falling clock edge during read, status register read and silicon ID. Refer to "Figure 4 Serial Output Timing" for the serial output timing. The LE25W81QE supports both serial interface SPI mode 0 and SPI mode 3. At the falling CS edge, SPI mode 0 is automatically selected if the logic level of SCK is low, and SPI mode 3 is automatically selected if the logic level of SCK is high. Figure 3 Serial Input Timing tCPH CS tCLS tCLHI tCSS tCLLO tCSH tCLH SCK tDS SI SO tDH DATA VALID High Impedance High Impedance Figure 4 Serial Output Timing CS SCK tCLZ SO tHO tCHZ DATA VALID tV SI www.onsemi.com 5 LE25W81QE Description of Commands and Their Operations "Table 2 Command Settings" provides a list and overview of the commands. A detailed description of the functions and operations corresponding to each command is presented below. 1. Read There are two read commands, the 4 bus cycle read command and 5 bus cycle read command. Consisting of the first through fourth bus cycles, the 4 bus cycle read command inputs the 24-bit addresses following (03h), and the data in the designated addresses is output synchronized to SCK. The data is output from SO on the falling clock edge of fourth bus cycle bit 0 as a reference. "Figure 5-a 4 Bus Read" shows the timing waveforms. Consisting of the first through fifth bus cycles, the 5 bus cycle read command inputs the 24-bit addresses and 8 dummy bits following (0Bh). The data is output from SO using the falling clock edge of fifth bus cycle bit 0 as a reference. "Figure 5-b 5 Bus Read" shows the timing waveforms. The only difference between these two commands is whether the dummy bits in the fifth bus cycle are input. When SCK is input continuously after the read command has been input and the data in the designated addresses has been output, the address is automatically incremented inside the device while SCK is being input, and the corresponding data is output in sequence. If the SCK input is continued after the internal address arrives at the highest address (FFFFFh), the internal address returns to the lowest address (00000h), and data output is continued. By setting the logic level of CS to high, the device is deselected, and the read cycle ends. While the device is deselected, the output pin SO is in a high-impedance state. Figure 5-a 4 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 31 32 23 24 39 40 47 Mode0 8CLK SI 03h Add. Add. Add. N High Impedance SO DATA MSB N+1 N+2 DATA DATA MSB MSB Figure 5-b 5 Bus Read CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 Mode0 8CLK SI SO 0Bh Add. Add. High Impedance Add. X N N+1 N+2 DATA DATA DATA MSB www.onsemi.com 6 MSB MSB LE25W81QE 2. Status Registers The status registers hold the operating and setting statuses inside the device, and this information can be read (status register read) and the protect information can be rewritten (status register write). There are 8 bits in total, and "Table 3 Status registers" gives the significance of each bit. Table 3 Status Registers Bit Bit0 Bit1 Name RDY Logic Function 0 Ready Power-on Time Information 1 Erase/Program 0 Write disabled 1 Write enabled 0 WEN 0 0 Bit2 Nonvolatile information BP0 1 Bit3 0 Block protect information 1 See status register descriptions on BP0, BP1, and BP2. BP1 Nonvolatile information 0 Bit4 BP2 Nonvolatile information 1 Bit5 0 Reserved bits Bit6 Bit7 0 0 Status register write enabled 1 Status register write disabled SRWP Nonvolatile information 2-1. Status register read The contents of the status registers can be read using the status register read command. This command can be executed even during the following operations. Small sector erase, sector erase, chip erase Page program Status register write "Figure 6 Status Register Read" shows the timing waveforms of status register read. Consisting only of the first bus cycle, the status register command outputs the contents of the status registers synchronized to the falling edge of the clock (SCK) with which the eighth bit of (05h) has been input. In terms of the output sequence, SRWP (bit 7) is the first to be output, and each time one clock is input, all the other bits up to RDY (bit 0) are output in sequence, synchronized to the falling clock edge. If the clock input is continued after RDY (bit 0) has been output, the data is output by returning to the bit (SRWP) that was first output, after which the output is repeated for as long as the clock input is continued. The data can be read by the status register read command at any time (even during a program or erase cycle). Figure 6 Status Register Read CS Mode 3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode 0 8CLK SI SO 05h High Impedance DATA MSB DATA MSB www.onsemi.com 7 DATA MSB LE25W81QE 2-2. Status register write The information in status registers BP0, BP1, BP2 and SRWP can be rewritten using the status register write command. RDY, WEN, bit 5, and bit 6 are read-only bits and cannot be rewritten. The information in bits BP0, BP1, BP2, and SRWP is stored in the non-volatile memory, and when it is written in these bits, the contents are retained even at powerdown. "Figure 7 Status Register Write" shows the timing waveforms of status register write, and Figure 20 shows a status register write flowchart. Consisting of the first and second bus cycles, the status register write command initiates the internal write operation at the rising CS edge after the data has been input following (01h). Erase and program are performed automatically inside the device by status register write so that erasing or other processing is unnecessary before executing the command. By the operation of this command, the information in bits BP0, BP1, BP2, and SRWP can be rewritten. Since bits RDY (bit 0), WEN (bit 1), 4, 5, and 6 of the status register cannot be written, no problem will arise if an attempt is made to set them to any value when rewriting the status register. Status register write ends can be detected by RDY of status register read. Information in the status registers can be rewritten 1,000 times (min.). To initiate status register write, the logic level of the WP pin must be set high and status register WEN must be set to "1". Figure 7 Status Register Write Self-timed Write Cycle tSRW CS tWPH tWPS WP Mode3 SCK 0 1 2 3 4 5 6 7 8 15 Mode0 8CLK SI SO 01h DATA High Impedance 2-3. Contents of each status register RDY (bit 0) The RDY register is for detecting the write (program, erase and status register write) end. When it is "1", the device is in a busy state, and when it is "0", it means that write is completed. www.onsemi.com 8 LE25W81QE WEN (bit 1) The WEN register is for detecting whether the device can perform write operations. If it is set to "0", the device will not perform the write operation even if the write command is input. If it is set to "1", the device can perform write operations in any area that is not block-protected. WEN can be controlled using the write enable and write disable commands. By inputting the write enable command (06h), WEN can be set to "1"; by inputting the write disable command (04h), it can be set to "0." In the following states, WEN is automatically set to "0" in order to protect against unintentional writing. At power-on Upon completion of small sector erase, sector erase or chip erase Upon completion of page program Upon completion of status register write * If a write operation has not been performed inside the LE25W81QE because, for instance, the command input for any of the write operations (small sector erase, sector erase, chip erase, page program, or status register write) has failed or a write operation has been performed for a protected address, WEN will retain the status established prior to the issue of the command concerned. Furthermore, its state will not be changed by a read operation. BP0, BP1, BP2 (bits 2, 3, 4) Block protect BP0, BP1, and BP2 are status register bits that can be rewritten, and the memory space to be protected can be set depending on these bits. For the setting conditions, refer to "Table 4 Protect level setting conditions". Table 4 Protect Level Setting Conditions Status Register Bits Protect Level Protected Area BP2 BP1 BP0 0 (Whole area unprotected) 0 0 0 1 (1/16 protected) 0 0 1 F0000h to FFFFFh 2 (1/8 protected) 0 1 0 E0000h to FFFFFh 3 (1/4 protected) 0 1 1 C0000h to FFFFFh None 4 (1/2 protected) 1 0 0 80000h to FFFFFh 5 (Whole area protected) 1 0 1 00000h to FFFFFh 5 (Whole area protected) 1 1 0 00000h to FFFFFh 5 (Whole area protected) 1 1 1 00000h to FFFFFh * Chip erase is enabled only when the protect level is 0. SRWP (bit 7) Status register write protect SRWP is the bit for protecting the status registers, and its information can be rewritten. When SRWP is "1" and the logic level of the WP pin is low, the status register write command is ignored, and status registers BP0, BP1, BP2, and SRWP are protected. When the logic level of the WP pin is high, the status registers are not protected regardless of the SRWP state. The SRWP setting conditions are shown in "Table 5 SRWP setting conditions". Table 5 SRWP Setting Conditions WP Pin SRWP Status Register Protect State 0 Unprotected 1 Protected 0 Unprotected 1 Unprotected 0 1 Bits 5 and 6 are reserved bits, and have no significance. www.onsemi.com 9 LE25W81QE 3. Write Enable Before performing any of the operations listed below, the device must be placed in the write enable state. Operation is the same as for setting status register WEN to "1", and the state is enabled by inputting the write enable command. "Figure 8 Write Enable" shows the timing waveforms when the write enable operation is performed. The write enable command consists only of the first bus cycle, and it is initiated by inputting (06h). Small sector erase, sector erase, chip erase Page program Status register write 4. Write Disable The write disable command sets status register WEN to "0" to prohibit unintentional writing. "Figure 9 Write Disable" shows the timing waveforms. The write disable command consists only of the first bus cycle, and it is initiated by inputting (04h). The write disable state (WEN "0") is exited by setting WEN to "1" using the write enable command (06h). Figure 8 Write Enable Figure 9 Write Disable CS CS Mode3 SCK Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI 8CLK SI 06h High Impedance SO 0 1 2 3 4 5 6 7 Mode0 04h High Impedance SO 5. Power-down The power-down command sets all the commands, with the exception of the silicon ID read command and the command to exit from power-down, to the acceptance prohibited state (power-down). "Figure 10 Power-down" shows the timing waveforms. The power-down command consists only of the first bus cycle, and it is initiated by inputting (B9h). However, a power-down command issued during an internal write operation will be ignored. The power-down state is exited using the power-down exit command (power-down is exited also when one bus cycle or more of the silicon ID read command (ABh) has been input). "Figure 11 Exiting from Power-down" shows the timing waveforms of the power-down exit command. Figure 10 Power-down Figure 11 Exiting from Power-down Power down mode Power down mode CS CS tPRB tDP Mode3 SCK Mode3 0 1 2 3 4 5 6 7 SCK Mode0 8CLK SI SO 0 1 2 3 4 5 6 7 Mode0 8CLK SI B9h High Impedance SO www.onsemi.com 10 ABh High Impedance LE25W81QE 6. Small Sector Erase Small sector erase is an operation that sets the memory cell data in any small sector to "1". A small sector consists of 4Kbytes. "Figure 12 Small Sector Erase" shows the timing waveforms, and Figure 21 shows a small sector erase flowchart. The small sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D7h or 20h). Addresses A19 to A12 are valid, and Addresses A23 to A20 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 12 Small Sector Erase Self-timed Erase Cycle tSSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 Mode0 8CLK SI D7h or 20h Add. Add. Add. High Impedance SO 7. Sector Erase Sector erase is an operation that sets the memory cell data in any sector to "1". A sector consists of 64Kbytes. "Figure 13 Sector Erase" shows the timing waveforms, and Figure 21 shows a sector erase flowchart. The sector erase command consists of the first through fourth bus cycles, and it is initiated by inputting the 24-bit addresses following (D8h). Addresses A19 to A16 are valid, and Addresses A23 to A20 are "don't care". After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 13 Sector Erase Self-timed Erase Cycle tSE CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 Mode0 8CLK SI SO D8h Add. Add. Add. High Impedance www.onsemi.com 11 31 LE25W81QE 8. Chip Erase Chip erase is an operation that sets the memory cell data in all the sectors to "1". "Figure 14 Chip Erase" shows the timing waveforms, and Figure 21 shows a chip erase flowchart. The chip erase command consists only of the first bus cycle, and it is initiated by inputting (C7h). After the command has been input, the internal erase operation starts from the rising CS edge, and it ends automatically by the control exercised by the internal timer. Erase end can also be detected using status register RDY. Figure 14 Chip Erase Self-timed Erase Cycle tCHE CS Mode3 SCK 0 1 2 3 4 5 6 7 Mode0 8CLK SI C7h High Impedance SO 9. Page Program Page program is an operation that programs any number of bytes from 1 to 256 bytes within the same sector page (page addresses: A19 to A8). Before initiating page program, the data on the page concerned must be erased using small sector erase, sector erase, or chip erase. "Figure 15 Page Program" shows the page program timing waveforms, and Figure 22 shows a page program flowchart. After the falling CS, edge, the command (02H) is input followed by the 24bit addresses. Addresses A19 to A0 are valid. The program data is then loaded at each rising clock edge until the rising CS edge, and data loading is continued until the rising CS edge. If the data loaded has exceeded 256 bytes, the 256 bytes loaded last are programmed. The program data must be loaded in 1-byte increments, and the program operation is not performed at the rising CS edge occurring at any other timing. The page programming time of 0.3ms (typ.) when programming 256 bytes (1 page) at one time makes for fast data writing. Figure 15 Page Program Self-timed Program Cycle tPP CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 2079 Mode0 8CLK SI SO 02h Add. Add. Add. High Impedance www.onsemi.com 12 PD PD PD LE25W81QE 10. Silicon ID Read Silicon ID read is an operation that reads the manufacturer code and device code information. "Table 6 Silicon ID codes table" lists the silicon ID codes. The silicon ID read command is not accepted during writing. Two methods are used for silicon ID reading. The first method involves inputting the 9Fh command: the setting is completed with only the first bus cycle input, and in subsequent bus cycles the manufacturer code 62h and device code 26h are repeatedly output in succession so long as the clock input is continued. Refer to "Figure 16-a Silicon ID read 1" for the waveforms. The second method involves inputting the ABh command. This command consists of the first through fourth bus cycles, and the silicon ID can be read when 16 dummy bits and an 8-bit address are input after (ABh). When address A0 is "0", the manufacturer code 62h is read in the fifth bus cycle, and the device code 26h is read in the sixth bus cycle. "Figure 16-b Silicon ID read 2" shows the timing waveforms. If, after the manufacturer code or device code has been read, the SCK input is continued, the manufacturer code and device code are output alternately with each bus cycle. When address A0 is "1", reading starts with device code 26h in the fifth bus cycle. Table 6 Silicon ID Codes Address Output Code A0 Manufacturer code 0 62h Device code 1 27h The data is output starting with the falling clock edge of the fourth bus cycle bit 0, and silicon ID reading ends at the rising CS edge. Figure 16-a Silicon ID Read 1 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 Mode0 8CLK SI 9Fh High Impedance SO N N+1 N SiID SiID SiID MSB MSB MSB Figure 16-b Silicon ID Read 2 CS Mode3 SCK 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 Mode0 8CLK SI ABh X X Add. N SO High Impedance SiID MSB www.onsemi.com 13 N+1 SiID MSB N SiID MSB LE25W81QE 11. Hold Function Using the HOLD pin, the hold function suspends serial communication (it places it in the hold status). "Figure 17 HOLD" shows the timing waveforms. The device is placed in the hold status at the falling HOLD edge while the logic level of SCK is low, and it exits from the hold status at the rising HOLD edge. When the logic level of SCK is high, HOLD must not rise or fall. The hold function takes effect when the logic level of CS is low, the hold status is exited and serial communication is reset at the rising CS edge. In the hold status, the SO output is in the high-impedance state, and SI and SCK are "don't care". Figure 17 HOLD Active CS Active HOLD tHS tHS SCK tHH tHH HOLD tHLZ tHHZ High Impedance SO 12. Power-on In order to protect against unintentional writing, CS must be kept at VDD At power-on. After power-on, the supply voltage has stabilized at 2.70V or higher, wait for 100s (tPU_READ) before inputting the command to start a read operation. Similarly, wait for 10ms (tPU_WRITE) after the voltage has stabilized before inputting the command to start a write operation. Figure 18 Power-on Timing Program, Erase and Write Command not Allowed Full Access Allowed VDD Chip selection not Allowed Read Access Allowed VDD(Max) VDD(Min) tPU_READ tPU_WRITE 0V www.onsemi.com 14 LE25W81QE 13. Hardware Data Protection In order to protect against unintentional writing at power-on, the LE25W81QE incorporates a power-on reset function. The following conditions must be met in order to ensure that the power reset circuit will operate stably. No guarantees are given for data in the event of an instantaneous power failure occurring during the writing period. Figure 19 Power-down Timing Program, Erase and Write Command not Allowed VDD VDD(Max) No Device Access Allowed VDD(Min) tPU_READ tPU_WRITE tPD 0V vBOT 14. Software Data Protection The LE25W81QE eliminates the possibility of unintentional operations by not recognizing commands under the following conditions. When a write command is input and the rising CS edge timing is not in a bus cycle (8 CLK units of SCK) When the page program data is not in 1-byte increments When the status register write command is input for 2 bus cycles or more 15. Decoupling Capacitor A 0.1F ceramic capacitor must be provided to each device and connected between VDD and VSS in order to ensure that the device will operate stably. www.onsemi.com 15 LE25W81QE Specifications Absolute Maximum Ratings Parameter Symbol Conditions Ratings unit Maximum supply voltage VDD max With respect to VSS 0.5 to +4.6 V DC voltage (all pins) VIN/VOUT With respect to VSS 0.5 to VDD+0.5 V Storage temperature Tstg 55 to +150 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Operating Conditions Parameter Operating supply voltage Operating ambient temperature Symbol Conditions Ratings VDD Topr unit 2.45 to 3.6 V Read Operation 20 to 70 C Write Operation 0 to 70 C Allowable DC Operating Conditions Parameter Symbol Read mode operating current ICCR Write mode operating current (erase+page program) ICCW CMOS standby current ISB Input leakage current ILI Output leakage current ILO Input low voltage VIL VIH Input high voltage Output low voltage VOL Output high voltage VOH Ratings Conditions min typ CS=0.1VDD, HOLD=WP=0.9VDD operating SI=0.1VDD/0.9VDD, frequency=30MHz SO=open VDD=VDD max VDD=VDD max, tSSE=80ms, tSE=100ms, tCHE=250ms, tPP=0.5ms CS=HOLD=WP =VDD0.3V, SI=VIH/VIL, SO=open, VDD=VDD max 6 mA 15 mA 10 A 2 A 2 A 0.3 0.3VDD V 0.7VDD VDD+0.3 V 0C to 70C VIN=VSS to VDD, VDD=VDD max VIN=VSS to VDD, VDD=VDD max VDD=VDD max VDD=VDD min IOL=100A, VDD=VDD min unit max 0.2 IOL=1.6mA, VDD=VDD min 0.4 IOH=100A, VDD=VDD min VDD0.2 V V Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Power-on Timing Parameter Ratings Symbol min unit max Time from power-on to read operation tPU_READ 100 s Time from power-on to write operation tPU_WRITE 10 ms Power-down time tPD 10 Power-down voltage vBOT ms 0.2 V Pin Capacitance at Ta=25C, f=1MHz Parameter Output pin capacitance Input pin Capacitance Symbol CDQ CIN Conditions VDQ=0V VIN=0V Ratings unit max 12 pF 6 pF Note: These parameter values do not represent the results of measurements undertaken for all devices but rather values for some of the sampled devices. www.onsemi.com 16 LE25W81QE AC Characteristics Ratings Parameter Symbol unit min typ max Clock frequency fCLK SCK logic high level pulse width tCLHI 16 30 MHz SCK logic low level pulse width tCLLO 16 Input signal rising/falling time tRF CS setup time tCSS 10 ns SCK setup time tCLS 10 ns Data setup time tDS 5 ns Data hold time tDH 5 ns ns ns 20 ns CS hold time tCSH 10 ns SCK hold time tCLH 10 ns CS wait pulse width tCPH 25 ns Output high impedance time from CS tCHZ Output data time from SCK tV Output data hold time 12 15 ns 15 ns tHO 1 HOLD setup time tHS 7 ns HOLD hold time tHH 3 ns Output low impedance time from HOLD tHLZ 9 ns Output high impedance time from HOLD tHHZ 9 ns WP setup time tWPS 20 WP hold time tWPH 20 Write status register time tSRW Page programming cycle time tPP Small sector erase cycle time tSSE Sector erase cycle time tSE ns ns ns 5 15 ms 0.3 1.0 ms 0.08 0.3 s 0.1 0.4 s 0.25 Chip erase cycle time tCHE 3 s Power-down time tDP 3 s Power-down recovery time tPRB 3 s Output low impedance time from SCK tCLZ 0 ns Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. AC Test Conditions Input pulse level ··········· 0V, 2.6V Input rising/falling time ·· 5ns Input timing level ········· 0.3VDD, 0.7VDD Output timing level ······· 1/2VDD Output load ················ 30pF Note: As the test conditions for "typ", the measurements are conducted using 2.6V for VDD at room temperature. www.onsemi.com 17 LE25W81QE Figure 20 Status Register Write Flowchart Status register write Start 06h 01h Write enable Set status register write command Data Program start on rising edge of CS 05h NO Set status register read command Bit 0= “0” ? YES End of status register write * Automatically placed in write disabled state at the end of the status register write www.onsemi.com 18 LE25W81QE Figure 21 Erase Flowcharts Small sector erase Sector erase Start Start 06h Write enable 06h D8h D7h or 20h Address 1 NO Address 1 Set small sector erase command Address 2 Address 2 Address 3 Address 3 Start erase on rising edge of CS Start erase on rising edge of CS Set status register read command 05h Write enable 05h NO Bit 0 = “0” ? Set sector erase command Set status register read command Bit 0 = “0” ? YES YES End of erase End of erase * Automatically placed in write disabled state at the end of the erase * Automatically placed in write disabled state at the end of the erase www.onsemi.com 19 LE25W81QE Figure 22 Page Program Flowchart Page program Chip erase Start Start 06h 06h Write enable C7h Set chip erase command Write enable 02h Address 1 Start erase on rising edge of CS 05h Set page program command Address 2 Address 3 Set status register read command Data 0 NO Bit 0 = “0” ? Data n YES Start program on rising edge of CS End of erase * Automatically placed in write disabled state at the end of the erase Set status register read command 05h NO Bit 0= “0” ? YES End of programming * Automatically placed in write disabled state at the end of the programming operation. www.onsemi.com 20 LE25W81QE Figure 23 Making Diagrams 25W81 00 25W81 Y M XXX =Specific Device Code =Production Year, Last Number of A.D. = Production month =Serial No. YMXXX ORDERING INFORMATION Device LE25W81QES00-AH-1 Package VDFN8 5x6, 1.27P (Pb-Free / Halogen Free) Shipping (Qty / Packing) 2000 / Tape & Real ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. 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