LB11696V Monolithic Digital IC Direct PWM Drive Brushless Motor Predriver IC www.onsemi.com Overview The LB11696V is a direct PWM drive predriver IC designed for threephase power brushless motors. A motor driver circuit with the desired output power (voltage and current) can be implemented by adding discrete transistors in the output circuits. Furthermore, the LB11696V provides a full complement of protection circuits allowing it to easily implement high-reliability drive circuits. This device is optimal for driving all types of large-scale motors such as those used in air conditioners and on-demand water heaters. SSOP30 (275mil) Features Three-phase bipolar drive Direct PWM drive (controlled either by control voltage or PWM variable duty pulse input) Built-in forward/reverse switching circuit Start/stop mode switching circuit (stop mode power saving function) Built-in input amplifier 5 V regulator output (VREG pin) Current limiter circuit (Supports 0.25 V (typical) reference voltage sensing based high-precision detection) Undervoltage protection circuit (The operating voltage can be set with a zener diode) Automatic recovery type constraint protection circuit with protection operating state discrimination output (RD pin) Four types of Hall signal pulse outputs Supports thermistor based thermal protection of the output transistors Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Ratings unit Supply voltage 1 VCC max VCC pin 18 V Output current IO max UL, VL, WL, UH, VH, and WH pins 30 mA LVS pin applied voltage LVS max LVS pin Allowable power dissipation 1 Pd max 1 Allowable power dissipation 2 Pd max 2 Independent IC When mounted on a 114.3 76.1 1.6 mm glass epoxy board Operating temperature Storage temperature 18 V 0.45 W 1.05 W Topr –20 to +100 C Tstg –55 to +150 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 17 of this data sheet. © Semiconductor Components Industries, LLC, 2015 March 2015 - Rev. 1 1 Publication Order Number : LB11696V/D LB11696V Allowable Operating Ranges at Ta = 25 C Parameter Symbol Conditions Supply voltage range 1-1 VCC1-1 VCC pin Supply voltage range 1-2 VCC1-2 VCC pin, when VCC is shorted to VREG. Output current IO Ratings Unit 8 to 17 4.5 to 5.5 UL, VL, WL, UH, VH, and WH pins 25 V V mA 5 V constant voltage output current IREG HP pin applied voltage VHP 0 to 17 V HP pin output current IHP 0 to 15 mA RD pin applied voltage VRD 0 to 17 V RD pin output current IRD 0 to 15 mA Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics at Ta = 25 C, VCC = 12 V Parameter Ratings Symbol min typ Unit max Current drain 1 ICC1 12 16 mA Current drain 2 ICC2 2.5 4 mA [5 V Constant Voltage Output (VREG pin)] Output voltage VREG 5.0 5.3 V Line regulation ΔVREG1 V 4.7 40 100 mV Load regulation ΔVREG2 I 10 30 mV Temperature coefficient Δ 0 [Output Block] Output voltage 1-1 VOUT Output voltage 1-2 VOUT Output voltage 2 VOUT Output leakage current IOleak [Hall Amplifier Block] Input bias current Common-mode input voltage range 2 IHB (HA) VICM2 Hall Input Sensitivity Hysteresis ΔVIN (HA) Input voltage low → high VSLH (HA) Input voltage high → low VSHL (HA) [CTL Amplifier] Input offset voltage Input bias current Common-mode input voltage range VIO (CTL) IB (CTL) VICM High-level output voltage VOH Low-level output voltage VOL Open-loop gain [PWM Oscillator (PWM pin)] High-level output voltage VOH (PWM) Low-level output voltage VOL (PWM) External capacitor charge current ICHG Oscillator frequency f (PWM) Amplitude V (PWM) VPWM = 2.1 V C = 2000 pF [TOC pin] Input voltage 1 VTOC1 Output duty: 100% Input voltage 2 VTOC2 Output duty: 0% 2.68 3.0 3.34 1.2 1.35 1.5 Input voltage 1 low VTOC1L Input voltage 2 low Input voltage 1 high Input voltage 2 high VTOC2H V V Design target value, when VREG = 4.7 V, 100% 2.68 2.82 2.96 V VTOC2L Design target value, when VREG = 4.7 V, 0% 1.23 1.29 1.34 V VTOC1H Design target value, when VREG = 5.3 V, 100% 3.02 3.18 3.34 V Design target value, when VREG = 5.3 V, 0% 1.37 1.44 1.50 V 0.2 0.5 V 10 μA [HP Pin] Output saturation voltage Output leakage current VHPL IO = 10 mA IHPleak VO = 18 V Continued on next page. www.onsemi.com 2 LB11696V Continued from preceding page. Parameter Symbol Conditions Ratings min typ max Unit [CSD Oscillator (CSD pin)] High-level output voltage VOH (CSD) Low-level output voltage VOL (CSD) External capacitor charge current ICHG1 External capacitor discharge current ICHG2 VCSD = 2 V VCSD = 2 V Charge/discharge current ratio RCSD (Charge current)/(discharge current) Low-level output voltage VRDL IO = 10 mA Output leakage current IL (RD) VO = 18 V times [RD Pin] [Current Limiter Circuit (RF pin)] Limiter voltage VRF RF-RFGND [Undervoltage Protection Circuit (LVS pin)] Operating voltage VSDL Release voltage VSDH Hysteresis VSD [PWMIN Pin] Input frequency High-level input voltage kHz f (PI) VIH (PI) Low-level input voltage VIL (PI) Input open voltage VIO (PI) Hysteresis VIS (PI) High-level input current IIH (PI) VPWMIN = VREG Low-level input current IIL (PI) VPWMIN = 0 V μA [S/S Pin] High-level input voltage VIH (SS) Low-level input voltage VIL (SS) Hysteresis VIS (SS) High-level input current IIH (SS) VS/S = VREG Low-level input current IIL (SS) VS/S = 0 V μA [F/R Pin] High-level input voltage VIH (FR) Low-level input voltage VIL (FR) Input open voltage VIO (FR) Hysteresis VIS (FR) High-level input current IIH (FR) VF/R = VREG Low-level input current IIL (FR) VF/R = 0 V μA [N1 Pin] High-level input voltage VIH (N1) Low-level input voltage VIL (N1) Input open voltage VIO (N1) High-level input current IIH (N1) VN1 = VREG Low-level input current IIL (N1) VN1 = 0 V μA [N2 Pin] High-level input voltage VIH (N2) Low-level input voltage VIL (N2) Input open voltage VIO (N2) High-level input current IIH (N2) VN2 = VREG Low-level input current IIL (N2) VN2 = 0 V μA Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 3 LB11696V F/R = L F/R = H Output 1 H L H L H L VH UL 2 H L L L H H WH UL 3 H H L L L H WH VL 4 L H L H L H UH VL 5 L H H H L L UH WL 6 L L H H H L VH WL S/S Pin PWMIN Pin Input state State Input state State H Stop High or open Output off L Start L Output on N1 and N2 Pins Input state N1 pin HP output N2 pin L L L High or open Single Hall sensor period divided by 2 Single Hall sensor period High or open L Three Hall sensor synthesized period divided by 2 High or open High or open Three Hall sensor synthesized period Since the S/S pin does not have an internal pull-up resistor, an external pull-up resistor or equivalent is required to set the IC to the stop state. If either the S/S or PWMIN pins are not used, the unused pin input must be set to the low-level voltage. The HP output can be selected (by the N1 and N2 settings) to be one of the following four functions: the IN1 Hall input converted to a pulse output (one-Hall output), the one-Hall output divided by two, the three-phase output synthesized from the Hall inputs (three-Hall synthesized output) or the three-Hall synthesized output divided by two. Allowable power dissipation, Pdmax — W 1.2 1.05 1 114.3mm × 76.1mm × 1.6mm glass epoxy board 0.8 0.6 0.45 0.4 Independent 0.42 0.2 0 0.18 0 20 40 60 www.onsemi.com 4 80 100 120 LB11696V Package Dimensions unit : mm SSOP30 (275mil) CASE 565AT ISSUE A to (Unit: mm) 1.00 SOLDERING FOOTPRINT* 7.00 GENERIC MARKING DIAGRAM* 0.65 XXXXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.32 NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 5 *This information is generic. Please refer to device data sheet for actual part marking. LB11696V Pin Assignment VCC VREG LVS N2 N1 HP F/R PWMIN S/S 30 27 26 25 24 29 28 23 22 CSD RD 21 20 19 11 12 PWM TOC EI– EI+ 18 17 16 13 14 15 LB11696V 1 2 3 GND RFGND RF 4 5 6 7 8 9 10 WH WL VH VL UH UL IN1– IN1+ IN2– IN2+ IN3– IN3+ Top view Pin Functions Pin No. Symbol 1 GND Pin Description Equivalent circuit Ground VREG 2 RF GND Output current detection reference Connect the ground terminal of the external resistor RF to this pin. 2 VREG 3 RF Output current detection Connect a resistor with a small value between this pin and RFGND. This sets the maximum output current IOUT to be 0.25/Rf. 3 VCC 4 6 8 5 7 9 WH VH UH WL VL UL Outputs (External transistor drive outputs) The duty control applies to the UH, VH, and WH pins. 50 kΩ 4 6 8 5 7 9 Continued on next page. Page. 6 LB11696V Continued from preceding page. Pin No. Pin Name Pin Description Equivalent circuit VCC 10 11 12 13 14 15 IN1– IN1+ IN2– IN2+ IN3– IN3+ Hall sensor inputs A high-level state is recognized when IN+ > IN–, and a low-level state is recognized under the reverse condition. If noise on the Hall sensor signals becomes a problem, insert capacitors between the IN+ and IN– inputs. 300 Ω 11 13 15 300 Ω 10 12 14 VREG 16 17 EI+ EI– Control amplifier inputs The PWMIN pin must be held at the low level for control using this pin to function. 300 Ω 17 300 Ω 16 VREG 18 TOC Control amplifier output When the TOC pin voltage rises, the IC changes the UH, VH, and WH output signal PWM duty to increase the torque output. 300 Ω 18 40 kΩ VREG 19 PWM Shared function pin: PWM oscillator frequency setting and initial reset pulse generation Insert a capacitor between this pin and ground. A capacitor of 2000 pF sets a frequency of about 22 kHz. 200 Ω 19 2 kΩ VREG 20 RD Motor constraint detection output This pin output is on when the motor is turning and off when the constraint protection circuit operates. 20 Continued on next page. Page. 7 LB11696V Continued from preceding page. Pin No. Pin Name Pin Description Equivalent circuit VREG 21 CSD Constraint protection circuit operating time setting Insert a capacitor between this pin and ground. This pin must be connected to ground if the constraint protection circuit is not used. 300 Ω 21 VREG 22 S/S Start/Stop input A low-level input sets the IC to start mode, and a highlevel input sets it to stop mode. 3.5 kΩ 22 VREG 23 PWM IN 50 kΩ PWM pulse input A low-level input specifies the output drive state, and a high-level or open input specifies the output off state. When this pin is used for control, the TOC pin voltage must be set to a control amplifier input that results in a 100% duty. 3.5 kΩ 23 VREG 50 kΩ 24 F/R 3.5 kΩ Forward/reverse input 24 VREG 25 HP Hall signal output (This is an open-collector output) One of four output types is selected by the N1 and N2 pin settings. 25 Continued on next page. Page. 8 LB11696V Continued from preceding page. Pin No. Pin Name Pin Description Equivalent circuit VREG 50 kΩ 26 N1 300 Ω Hall signal output (HP signal) type selector 26 VREG 50 kΩ 27 N2 300 Ω Hall signal output (HP signal) type selector 27 VCC 28 28 LVS Undervoltage protection voltage detection If a 5 V or higher supply voltage is to be detected, set the detection voltage by inserting an appropriate zener diode in series. VCC 29 VREG Stabilized power supply output (5 V output) Insert a capacitor (about 0.1 µF) between this pin and ground for stabilization. 30 VCC Power supply. Insert a capacitor between this pin and ground for stabilization. 29 Page. 9 LB11696V Hall Sensor Signal Input/Output Timing Chart F/R = L IN1 IN2 IN3 UH VH WH UL VL WL F/R = H IN1 IN2 IN3 UH VH WH UL VL WL Areas shown in gray ( ) indicate PWM output. Page. 10 CTL VREG HP S/S S/S VREF PWM IN PWMIN VREG PWM OSC + – PWM EI+ EI– TOC F/R F/R N1 N1 COMP N2 N2 HP LOGIC LVSD HYS AMP HALL HALL LOGIC CONTROL LOGIC CSD OSC CSD VCC IN1+ IN1– IN2+ IN2– IN3+ IN3– RD RD VREG GND LIM CURR PRI DRIVER VREG RFGND RF WL WH VL VH UL UH VCC VREG LVS 5V VM LB11696V Application Circuit Examples Bipolar transistor drive (high side PWM) using a 5 V power supply Page. 11 CTL VREG HP S/S S/S VREF PWM IN PWMIN VREG PWM OSC + – PWM EI+ EI– TOC F/R F/R N1 N1 COMP N2 N2 HP LOGIC LVSD HYS AMP HALL HALL LOGIC CONTROL LOGIC CSD OSC CSD VCC IN1+ IN1– IN2+ IN2– IN3+ IN3– RD RD VREG GND CURR LIM PRI DRIVER VREG RFGND RF WH WL VH VL UH UL VCC VREG LVS 12 V VM LB11696V MOS transistor drive (low side PWM) using a 12 V power supply Page. 12 Thermistor VREG HP S/S S/S VREF PWM IN Variable duty PWMIN pulse input VREG PWM OSC + – PWM EI+ EI– TOC F/R F/R N1 N1 COMP N2 N2 HP LOGIC LVSD HYS AMP HALL HALL LOGIC CONTROL LOGIC CSD OSC CSD VCC IN1+ IN1– IN2+ IN2– IN3+ IN3– RD RD VREG RF WH WL VH VL UH UL VCC VREG GND RFGND LIM CURR PRI DRIVER VREG LVS 12 V VM LB11696V NMOS transistor + PNP transistor drive (low side PWM) using a 12 V power supply with thermal protection implemented using a thermistor Page. 13 LB11696V LB11696V Functional Description 1. Output Drive Circuit The LB11696V adopts direct PWM drive to minimize power loss in the outputs. The output transistors are always saturated when on, and the motor drive power is adjusted by changing the on duty of the output. The output PWM switching is performed on the UH, VH, and WH outputs. Since the UL to WL and UH to WH outputs have the same output form, applications can select either low side PWM or high side PWM drive by changing the way the external output transistors are connected. Since the reverse recovery time of the diodes connected to the non-PWM side of the outputs is a problem, these devices must be selected with care. (This is because through currents will flow at the instant the PWM side transistors turn on if diodes with a short reverse recovery time are not used.) 2. Current Limiter Circuit The current limiter circuit limits the output current peak value to a level determined by the equation I = VFR/Rf (VRF = 0.25 V typical, Rf: To the RF pin Current current detection resistor). This circuit suppresses the output current by detection reducing the output on duty. resistor High-precision detection can be implemented by connecting the lines from the RF and RFGND pins close to the two terminal of the current detection resistor Rf. The current limiter circuit includes an internal filter circuit to prevent incorrect current limiter circuit operation due to detecting the output diode reverse recovery current due to PWM operation. Although there should be no problems with the internal filter circuit in normal applications, applications should add an external filter circuit (such as an RC low-pass filter) if incorrect operation occurs (if the diode reverse recovery current flows for longer than 1 µs). 3. Power Saving Circuit This IC goes to a low-power mode (power saving state) when set to the stop state with the S/S pin. In the power saving state, the bias currents in most of the circuits are cut off. However, the 5 V regulator output (VREG) is still provided in the power saving state. If it is also necessary to cut the Hall device bias current, this function can be provided by an application that, for example, connects the Hall devices to 5 V through PNP transistors. To the VREG pin To the S/S pin Hall device 4. Notes on the PWM Frequency The PWM frequency is determined by the capacitor C (F) connected to the PWM pin. fPWM ≈ 1/(22500 × C) If a 2000 pF capacitor is used, the circuit will oscillate at about 22 kHz. If the PWM frequency is too low, switching noise will be audible from the motor, and if it is too high, the output power loss will increase. Thus a frequency in the range 15 to 50 kHz must be used. The capacitor's ground terminal must be placed as close as possible to the IC’s ground pin to minimize the influence of output noise and other noise sources. 5. Control Methods The output duty can be controlled by either of the following methods • Control based on comparing the TOC pin voltage to the PWM oscillator waveform The low side output transistor duty is determined according to the result of comparing the TOC pin voltage to the PWM oscillator waveform. When the TOC pin voltage is 1.35 V or lower, the duty will be 0%, and when it is 3.0 V or higher, the duty will be 100%. Since the TOC pin is the output of the control amplifier (CTL), a control voltage cannot be directly input to the TOC pin. Normally, the control amplifier is used as a full feedback amplifier (with the EI- pin connected to the TOC pin) and a DC voltage is input to the EI+ pin (the EI+ pin voltage will become equal to the TOC pin voltage). When the EI+ pin voltage becomes higher, the output duty increases. Since the motor will be driven when the EI+ pin is in the open state, a pull-down resistor must be connected to the EI+ pin if the motor should not operate when EI+ is open. When TOC pin voltage control is used, a low-level input must be applied to the PWMIN pin or that pin connected to ground. Page. 14 LB11696V • Pulse Control Using the PWMIN Pin A pulse signal can be input to the PWMIN pin, and the output can be controlled based on the duty of that signal. Note that the output is on when a low level is input to the PWMIN pin, and off when a high level is input. When the PWMIN pin is open it goes to the high level and the output is turned off. If inverted input logic is required, this can be implemented with an external transistor (npn). When controlling motor operation from the PWMIN pin, the EI– pin must be connected to ground, and the EI+ pin must be connected to the TOC pin. Note that since the PWM oscillator is also used as the clock for internal circuits, a capacitor (about 2000 pF) must be connected to the PWM pin even if the PWMIN pin is used for motor control. 6. Hall Input Signals A signal input with an amplitude in excess of the hysteresis (80 mV maximum) is required for the Hall inputs. Considering the possibility of noise and phase displacement, an even larger amplitude is desirable. If disruptions to the output waveforms (during phase switching) or to the HP output (Hall signal output) occur due to noise, this must be prevented by inserting capacitors across the inputs. The constraint protection circuit uses the Hall inputs to discriminate the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise, care is required when using the constraint protection circuit. If all three phases of the Hall input signal system go to the same input state, the outputs are all set to the off state (the UL, VL, WL, UH, VH, and WH outputs all go to the low level). If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or – side) at a voltage within the common-mode input voltage range allows the other input side to be used as an input over the 0 V to VCC range. 7. Undervoltage Protection Circuit The undervoltage protection circuit turns one side of the outputs (UH, VH, and WH) off when the LVS pin voltage falls below the minimum operation voltage (see the Electrical Characteristics). To prevent this circuit from repeatedly turning the outputs on and off in the vicinity of the protection To the power operating voltage, this circuit is designed with hysteresis. Thus the output supply detected will not recover until the operating voltage rises 0.45 V (typical). The protection operating voltage detection level is set up for 5 V systems. To the LVS pin The detected voltage level can be increased by shifting the voltage by inserting a zener diode in series with the LVS pin to shift the detection level. The LVS influx current during detection is about 75 µA. To increase the diode current to stabilize the zener diode voltage rise, insert a resistor between the LVS pin and ground. If the LVS pin is left open, the internal pull-down resistor will result in the IC seeing a ground level input, and the output will be turned off. Therefore, a voltage in excess of the LVS circuit clear voltage (about 4.35 V) must be applied to the LVS pin if the application does not use the undervoltage protection circuit. The maximum rating for the LVS pin applied voltage is 18 V. 8. Constraint Protection Circuit When the motor is physically constrained (held stopped), the CSD pin external capacitor is charged (to about 3.0 V) by a constant current of about 2.5 µA and is then discharged (to about 1.0 V) by a constant current of about 0.14 µA. This process is repeated, generating a sawtooth waveform. The constraint protection circuit turns motor drive on and off repeatedly based on this sawtooth waveform. (The UH, VH, and WH side outputs are turned on and off.) Motor drive is on during the period the CSD pin external capacitor is being charged from about 1.0 V to about 3.0 V, and motor drive is off during the period the CSD pin external capacitor is being discharged from about 3.0 V to about 1.0 V. The IC and the motor are protected by this repeated drive on/off operation when the motor is physically constrained. The motor drive on and off times are determined by the value of the connected capacitor C (in µF). TCSD1 (drive on period) ≈ 0.8 × C (seconds) TCSD2 (drive off period) ≈ 14.3 × C (seconds) When a 0.47 µF capacitor is connected externally to the CSD pin, this iterated operation will have a drive on period of about 0.38 seconds and a drive off period of about 6.7 seconds. Page. 15 LB11696V While the motor is turning, the discharge pulse signal (generated once for each Hall input period) that is created by combining the Hall inputs internally in the IC discharges the CSD pin external capacitor. Since the CSD pin voltage does not rise, the constraint protection circuit does not operate. When the motor is physically constrained, the Hall inputs do not change and the discharge pulses are not generated. As a result, the CSD pin external capacitor is charged by a constant current of 2.5 µA to about 3.0 V, at which point the constraint protection circuit operates. When the constraint on the motor is released, the constraint protection function is released. Connect the CSD pin to ground if the constraint protection circuit is not used. 9. Forward/Reverse Direction Switching This IC is designed so that through currents (due to the output transistor off delay time when switching) do not flow in the output when switching directions when the motor is turning. However, if the direction is switched when the motor is turning, current levels in excess of the current limiter value may flow in the output transistors due to the motor coil resistance and the motor back EMF state when switching. Therefore, designers must consider selecting external output transistors that are not destroyed by those current levels or only switching directions after the speed has fallen below a certain speed. 10. Handling Different Power Supply Types When this IC is operated from an externally supplied 5 V power supply (4.5 to 5.5 V), short the VCC pin to the VREG pin and connect them to the external power supply. When this IC is operated from an externally supplied 12 V power supply (8 to 17 V), connect the VCC pin to the power supply. (The VREG pin will generate a 5 V level to function as the control circuit power supply.) 11. Power Supply Stabilization Since this IC uses a switching drive technique, the power supply line level can be disturbed easily. Therefore capacitors with adequate capacitance to stabilize the power supply line must be inserted between VCC and ground. If diodes are inserted in the power supply lines to prevent destruction if the power supply is connected with reverse polarity, the power supply lines are even more easily disrupted, and even larger capacitors are required. If the power supply is turned on and off by a switch, and if there is a significant distance between that switch and the stabilization capacitor, the supply voltage can be disrupted significantly by the line inductance and surge current into the capacitor. As a result, the withstand voltage of the device may be exceeded. In application such as this, the surge current must be suppressed and the voltage rise prevented by not using ceramic capacitors with a low series impedance, and by using electrolytic capacitors instead. 12. VREG Stabilization To stabilize the VREG voltage, which is the control circuit power supply, a 0.1 µF or larger capacitor must be inserted between the VREG pin and ground. The ground side of this capacitor must connected to the IC ground pin with a line that is as short as possible. Page. 16 LB11696V ORDERING INFORMATION Device Package Shipping (Qty / Packing) LB11696V-MPB-E SSOP30 (275mil) (Pb-Free) 48 / Fan-Fold LB11696V-TLM-E SSOP30 (275mil) (Pb-Free) 1000 / Tape & Reel LB11696V-TRM-E SSOP30 (275mil) (Pb-Free) 1000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 17