Standard Products CT1611 Microprocessor Interface DMA Controller with Buffer Memory, MIL-STD-1750A Compatible www.aeroflex.com September 16, 2003 FEATURES Full Bus Control and RTU Operation Low Software Overhead Complete BI-Directional Message Buffer Memory-Mapped DMA Message Transfers Simple Programmable Polling Operation in Bus Controller Mode Pin Programmable for both 8 and 16 Bit Microprocessors Monolithic construction using linear ASICs Processed and screened to MIL-STD-883 specs Aeroflex is a Class H & K MIL-PRF-38534 Manufacturer MIL-PRF-38534 Compliant Devices Available GENERAL The CT1611 provides a complete Bus Controller and Remote Terminal interface between the MIL-STD-1553B chip set (CT1561, CT1602, CT1610, etc.) and most microprocessor-based systems (F9450A, 68000, 8086, VME bus, Multibus, etc.). The unit is constructed totally with CMOS technology and includes a custom CMOS chip, two HC CMOS FIFO's and HCT CMOS buffers. Thus the interface has extremly low power requirements. The CT1611 interface permits the use of all 15 mode codes and all types of data transfers as specified in MIL-STD-1553B in both Bus Controller and Remote Terminal operating modes. A Remote Terminal is capable of switching to a Bus Controller when requested via the Dynamic Bus Control mode code. DATA TRANSFERS Data transfers in both Bus Controller and Remote Terminal operation are performed via a DMA burst. This powerful feature insures that the host microprocessor system will never be held up more than 16.5 usec when transferring 32 data words into or out of the interface. It also insures that only good and complete messages will be transferred to the host's memory. Operation of the DMA is as follows: When data is received from the 1553 cable via the chip set, it is loaded into an internal FIFO at the 20 µsec/word 1553 rate. Once the complete message has been received and has passed all validity tests, the CT1611 issues the signal DMA REQ to the subsystem. (This signal corresponds to a HOLD request in many systems.) The host microprocessor then acknowledges and grants this request by issuing the signal DMA ACK. The CT1611 then becomes the bus master of the subsystem and transfers all the data on a memory-mapped basis. When the transfer is complete, the CT1611 removes its DMA REQ and returns control of the microprocessor bus to the microprocessor. When data is to be transmitted on the 1553 cable, a similar DMA takes place. Data is preloaded into the FIFO via a single DMA burst and then transmitted. As a failsafe, an internal timeout is provided to insure that the CT1611 can never control the microprocessor bus longer than 80 µsec. In addition, a hard-wired Master Reset input signal is provided that will place all output signals in a tri-state condition. Therefore, in the unlikely condition of a failure in the CT1611, the host microprocessor system can never be brought down or placed in a non-recoverable state. SCDCT1611 Rev A A built-in test function has been included to exercise the DMA operation and verify the message data path. This function is initiated by an I/O command from the subsystem. I/O CONTROL The CT1611 can be addressed, written to, read from, and programmed much like any peripheral device located on a microprocessor bus. The address lines and a device select input signal allow the subsystem to read or write to the CT1611 as if it were memory. In view of the fact that microprocessors are becoming very fast, two types of handshake signals were incorporated into the CT1611, either of which may be used to permit asynchronous read and write operations. Handshaking directly with the 9450A, 8085, 8086 and the 6802 is the active high Ready signal. Handshaking directly with the 68000 or VME and Multibus busses is the active low Acknowledge signal. INTERFACING To accomodate both 8 and 16 bit microprocessor data busses, the CT1611 data path is pin programmable for either operation. When operating in 8 bit mode, data is DMA'd in 8 bit bytes and therefore requires twice the time to be transferred. Bus control signals are pin programmable for either individual read and write strobes or a common read/write signal and data strobe. Individual read and write strobes are used with the Intel 8085, 8086 and Multibus. A common read/write signal and data strobe are used with the 9450A, 6802, 68000 and VME bus. Two separate pins are provided for input and output data strobes. These signals may be connected or kept separate to insure that 1553 data can never be written into a protected area of memory. RTU OPERATION The CT1611 is powered-up and reset as a Remote Terminal. In addition, in Bus Controller mode, it can be changed into a Remote Terminal via an I/O command. In Remote Terminal mode, the CT1611 uses dedicated registers for the received command word, the sync data word, and the vector word. The command word register contains a second tier so that receive command words are double buffered. This feature maximizes the allowable I/O access time. Four interrupts are provided to alert the subsystem that a valid message has been received or transmitted or that a mode command has been serviced. Use of the interrupts is optional. The interrupt signals are the same for bus control operation although different in meaning. Interrupts for received or transmitted data messages are generated after the DMA transfers have been completed. The Busy, Service Request, and Subsystem Error bits for the status word are contained in a dedicated register accessible via I/O. The Busy bit is set high at power-up as well as via a subsystem reset. The CT1611 provides full validity checking for all 1553 transfers and alerts the subsystem, via interrupts, as to whether the transfer was valid or not. The two status word registers are preset high at the initiation of a transfer and may be read at completion. The second status word is provided for RT to RT transfers. The error latch may be used to determine the nature of a failure should a transfer be unsuccessful. The transaction word register is used to define the type of transfer to be performed, to which bus the transfer is to be made, and to define which bits (when set) in the returned status word constitute an invalid transfer. A polling operation has also been included that enables the CT1611 to automatically load the command words and transaction words from main memory via DMA. This function allows a preprogrammed polling sequence of the remote terminals to be implemented with a minimum of subsystem intervention. BC OPERATION The CT1611 is programmable into Bus Controller operation via I/O from the subsystem. Under Bus Controller mode, there are two command word registers, a received mode data register, two returned status word registers, an error latch and a transaction word register. The first command register is used for all 1553 bus transfers. The second command register is for the second command word used in RT to RT transfers or for the associated mode data required for certain mode codes. SCDCT1611 Rev A 2 Absolute Maximum Ratings Parameter Range Units Operating Free-air Temperature -55°C to +125 °C Storage Case Temperature -55°C to +155 °C -0.3 to +7 Volts -0.3 to VDD +0.3 Volts Supply Voltage (VDD) Input and Output Voltage at any Pad Recommended Operating Conditions Parameter Min Typ Max Unit Supply Voltage VDD 4.5 5.0 5.5 V Operating Temperature -55 - +125 °C Electrical Characteristics (VDD = +5.0V ±10%, TA = -55°C to +125°C, unless otherwise specified) Parameter Conditions Min Max Unit VIH High Level Input Voltage 2.0 - V VIL Low Level Input Voltage - 0.8 V -10 +10 µA IIN Input Current IIL Low Level Input Current Note 4A -25 -400 µA IIH High Level Input Current Note 4B -25 -400 µA VOH High Level Output Voltage Note 1 2.4 - V VOL Low Level Output Voltage Note 2 - 0.4 V IDD1 Quiescent Supply Current Note 3 5 30 mA IDD2 Dynamic Supply Current Note 5 - 200 mA Note 1. IOH = -2mA for I/O BUS, ADDRESS, R/W & STROBE signal pads (FP and DIP Pins 12->27 / 28->33 / 5,7) IOH = -1mA for OUTPUT ONLY signal pads (FP Pins 1->3,6,9,10,39->42,55->58,65,67->69,79,81->83) (DIP Pins 1->3,6,9,10,39->42,57->60,67,69->71,81,83->85) Note 2. IOL = 4mA for I/O BUS, ADDRESS, R/W & STROBE signal pads (FP and DIP Pins 12->27 / 28->38 / 5,7) IOL = 2mA for OUTPUT ONLY signal pads (FP Pins 1->3,6,9,10,39->42,55->58,65,67->69,79,81->83) (DIP Pins 1->3,6,9,10,39->42,57->60,67,69->71,81,83->85) Note 3. Bidirectional I/O at VDD (FP Pins 12->27 / 28->38 / 45->52 / 5) (DIP Pins 12->27 / 28->38 / 47->54 / 5) I/O Address Lines (FP and DIP Pins 34->38) at VDD, remaining OUTPUTS = N/C, remaining INPUTS at VDD, MRB at VIL < 0.4V. Note 4. For INPUTS (FP Pins 59,62,63,64,66,77,86) (DIP Pins 61,64,65,66,68,79,88) @VDD = 5.5V A. @VIL = 0.4V B. @VIH = 2.4V Note 5. During typical 32 Word DMA (Output Loading = 0) SCDCT1611 Rev A 3 (REGISTERS) 00 BIDIRECTIONAL I/O DATA BUFFER BC CW1 IH 02 8 OR 16 BIT SUBSYSTEM DATA BUS BC CW2 / AMD / VEC 0C TRANSACTION WD HANDSHAKE AND CONTROL DMA CONTROLLER 0A OPERATION WD ADDRESS AND CONTROL SIGNALS I/O DECODER 36 RTU CW 16 BIT INTERNAL DATA BUS 8 BIT INTERNAL HIGHWAY 38 RTU RCV CW 3C STAT WD1 3A STAT WD2 / RMD / SYNC 32 ERROR 0 INTERRUPT GENERATOR 1 2 3 ⎫ ⎬ INTERRUPTS ⎭ 0E POLL TRANS OFFSET BUS CONTROLLER SEQUENCER 34 LAST POLL TRANS ADD BIDIRECTIONAL 32 WORD DMA DATA BUFFER FIFO WATCH DOG DMA TIMER TO PROTOCOL HYBRID TO SUBSYSTEM CT1611 FUNCTIONAL BLOCK DIAGRAM SCDCT1611 Rev A 4 SCDCT1611 Rev A 5 DATA DATA DATA DATA 10µF .1µF +5V T1 3 2 1 -15V +15V .01µF 4 5 6 7 8 T2 3 2 1 T1 - T2 are Technitrol X-1296-1 or T-1553-2 (See Note 4) 4 5 6 7 8 .1µF + CT1610, CT1612, and CT1560 Thru CT1563 are fully compatabile MIL-PRF-1553B Chip Set Pin outs shown are for CT1487D and CT1487DF All Series CT1487, CT1589, CT3231 and CT3232 are fully compatable ** Driver / Receiver Bus "B" Stub Coupling Bus "A" Stub Coupling -15V +15V GND +5V Pin outs shown for Spectrum Technology Series 7111 TTL 5/8" 20 lead flat-pack. Possible alternate, Q-TECH Series QT21 TTL 5/8" 20 lead flat-pack (Not totally pin compatable with Spectrum Tecnology). * Typical 14 20 VCC 0.01µF 33 24 0.01µF 6.8µF -15V -15V (1) (2) 32 23 8 11 RTAD 0 3 RTAD 2 RTAD 3 ERROR CT1602 *** Use (XX) Numbers 73 61 (75) (63) 76 (78) 15 (15) 14 (14) 5 (5) 4 (4) 3 (3) 84 (86) 87 (89) 86 (88) 83 (85) 82 (84) 2 (2) 9 (9) 8 (8) 7 (7) 6 (69) 74 (76) 85 (87) 62 (64) 36 (36) 34 (34) 31 (31) 32 (32) 57 (59) IH715 44 (44) IH412 41 (41) IH513 42 (42) IH614 43 (43) IH 08 37 (37) IH 19 38 (38) IH210 39 (39) IH311 40 (40) RT0 REQ BUS A REQ BUS B IHDIR IHEN BCOP A 26 (26) BCOP B 28 (28) BCOP STB 27 (27) DTRQ 18 (18) DTACK 25 (25) NBGT SYNC 21 (21) INCMD 16 (16) IUSTB 23 (23) 20 (20) H/L 11 (11) 12 (12) STATEN/STATSTB SERVRFQ 72 (74) EOT 13 (13) VECTEN / DWEN 19 (19) Test Points (May be Used) Test Points (May be used) ERROR HSFAIL LTFAIL PARER MANER 78 60 (62) (80) RTADER TXTO MANER PARER LTFAIL MSFAIL (66) 64 (61) 59 (48) 46 RTAD 0 (49) 47 RTAD 1 (50) 48 RTAD 2 (51) 49 RTAD 3 (52) 50 RTAD 4 (47) 45 RTAD PAR (46) NC (90) 88 NC (1) 1 NC (45) NC (58) 66 Rx DATA 1 RT/BC SA0 SA1 SA2 SA3 SA4 WC0 WC1 WC2 WC3 WC4 CWC0 CWC1 CWC2 CWC3 CWC4 DBACC SSERA .1µF TBDµF +5V 1Ω Optical discrete Output Optical discrete input INT 3 INT 1 INT 0 INT2 60 (62) TXTO RTADER (86) 84 62 (64) 39 (39) 40 (40) 41 (41) 42 (42) (LSB) D0 12 (12) 27 (27) 26 (26) D13 25 (25) D12 24 (24) D11 23 (23) D10 22 (22) D9 21 (21) D8 20 (20) D7 19 (19) D6 18 (18) 17 (17) D5 16 (16) D4 5 (5) D3 D2 14 (14) D1 13 (13) 61 (63) 64 (66) RTU Mode Valid Msg rcv’d Sync w/Data Sync (w/o Data), Reset, DBC Msg xmt’d, vector wd 6. ACK, RDYD are handshake signals used in asynchronous I/O Data transfers. Either signal may be used depending on system requirements. 7. DMA DATA ACK may be used to extend the data transfer time during DMA. 8. Pin 69 defines µP interface, i.e R/W, & STRBD or ADSTB & WRTSTB. (Pins 7 & 8 must be tied together) 5. Interrupt Functions: SIGNAL BC Mode INTR 0 Good Xfer INTR 1 Invalid Xfer INTR 2 Poll Op Cmplt INTR 3 Subsystem I/O Address (16 Lines) 4. Pin numbers for T1 & T2 in DIP & Flat Pack package are the same. X-1269-1 (DIP) X-1269-1FP (Flat Pack) T-1553-2 (DIP) T-1553-2FP (Flat Pack) X-1269-1 & T1553-2 are identical, except T-1553-2 has guaranteed -55°C Input Impedance 23KΩ per MIL-STD-1553B. Subsystem I/O Address (10 Lines) 1. XX Pin numbers are for flat packs CT1608FP & CT1611FP. 2. (XX) Pin numbers are for plug in package CT1608 & CT1611. 3. Pin numbers for CT1487D (Plug in) and CT1487DF (flat pack) are the same. NOTES: Subsystem Control, Handshake and Interrupt Lines ⎤ ⎦ CT1611 Typical Application "Hardwired" reset from System (i.e. power on reset) or AC network DUAL Redundant BC/RTU 1553B To µP Interface 78 (80) 30 (30) 29 (29) 28 (28) 32 (32) 31 (31) 33 (33) 35 (35) 34 (34) 8 (8) 38 (38) 37 (37) 36 (36) 5 (5) R/W RDYD 6 (6) (STRBD / WRSTB) STRB DO 7 (7) (R/W, RDSTB) DMA REQ 10 (10) DMA ACK 11 (11) Interrupt Outputs HSFAIL LTFAIL PARER MANER TXTO RTADER (49) 47 IH513 (48) 46 IH614 (47) 45 IH715 (53) 51 IH 19 (52) 50 IH210 (51) 49 IH311 (50) 48 IH412 (59) 57 RT0 (57) 55 REQ BUS A (58) 56 REQ BUS B (56) 54 IHDIR (55) 53 IHEN (54) 52 IH 08 43 (43) 59 (61) 2 (2) 3 (3) DEVICE SEL 4 (4) ACK 5 (5) (85) 83 GBR OUT (STRBD / WRSTB) STRB DI (84) 82 H/L IN (A10, 8 Bit Mode only) NC (83) 81 STATEN/STATSTB (MSB) A9 (79) 77 SERVRFQ A8 (77) 75 EOT A7 (75) 73 VECTEN / DWEN A6 (74) 72 NBGT A5 (73) 71 SYNC A4 (78) 76 INCMD CT1611 A3 DMA Controller (70) 68 IUSTB A2 µProcessor Interface (76) 74 DTRQ with FIFO A1 (69) 67 DTACK (LSB) A0 (63) 66 BCOP A (65) 63 BCOP B (MSB) D15 (67) 65 BCOP STB D14 (81) 79 DBACC (1) 1 SSERA (89) 87 BUSY (88) 86 BITEN/RMDSTB (87) 85 LSTCMD/CWEN (45) NC (46) NC 58 (60) 88 (90) 44 (44) 6 MHz +5V IN COMMON/CASE (82) 80 RT / BC MASTER RESET +5V DMA DATA ACK (72) 79 16 / B TRANSMIT / RECEIVE (71) 69 MODE 0 / MODE 1 POLL / DATA SSERR SYNC BUSY 81 (83) BITEN/RMDSTB 80 (82) LSTCMD/CWEN 79 (81) GBR 10 (10) MIL-PRF-1553B Chipset *** (67) 65 Rx DATA 1 (70) 68 Tx INH 1 (72) 70 Tx DATA (73) 71 Tx DATA (57) 55 Rx DATA 0 (56) 54 Rx DATA 0 (71) 69 Tx INH 0 (79) 77 DBREQ (77) 75 RESET (65) 63 VALD (58) 56 BCSTEN 1 (55) 53 BCSTEN 0 (54) 52 DWSYNC (53) 51 CMSYNC (24) 24 BUFINH (17) 17 Tx / Rx (22) 22 INCLK (2 MHz Clock) (30) 30 NDRQ RTAD 4 RTAD PAR 2KΩ 2KΩ Test Points (May be used) TBDµF .1µF 67 (69) 33 (33) +5V IN GND/CASE 1Ω +5V Optional discrete output indicating R.T.U. has accepted Dynamic Bus Control request. (60) +5V 58 6 MHz (29) 29 PASMON RESET DBREQ Terminal Address + Parity (ODD) RTAD 1 7 12 16 22 31 GND GND GND GND GND GND Rx DATA OUT 2 17 Tx INHIBIT 2 25 11 Tx DATA OUT 2 Rx DATA IN 2 14 21 Rx DATA IN 2 Tx INHIBIT 1 34 29 Rx DATA IN 1 Rx DATA OUT 1 5 1 Tx DATA OUT 1 Rx DATA OUT 1 8 Tx DATA IN 1 36 2 Tx DATA OUT 1 Tx DATA IN 1 35 30 Rx DATA IN 1 STROBE 1 6 4 NC 9 NC CT-1487D and DF 13 NC Dual Driver / Receiver ** +5V 18 NC STROBE 2 15 20 Rx DATA IN 2 20 10 Tx DATA OUT 2 Tx DATA IN 2 Tx DATA IN 2 27 +15V+15V +5V +5V (1) (2) (1) (2) 28 19 6.8µF 7 GND/Case 10 * 6MHz Oscillator Out .1µF +5V Optional discrete output indicating R.T.U. has accepted RESET mode code + ⎤ ⎦ + CT 1611 User’s Guide SCDCT1611 Rev A 6 Example of DMA Data Transfer Transfer = 3-Word Receive Message in RTU Mode CW RT SubAddress T/R Address DW1 DW2 Word Count 10010 0 11101 00011 18 0 29 3 DW3 SW Subsystem Address Memory Data XXX 11101 00001 DW1 XXX 11101 00000 DW2 XXX 11101 00010 DW3 Receive Command Register MSB’s determined by subsystem address selector SCDCT1611 Rev A 7 Subsystem Address 29 Continuous word count R/W (From UP System) TRISTATE ADDRESS ADDRESS VALID TRISTATE (From UP System) DEVICE SELECT (From UP System) 40ns MIN STRBD (From up System) 200ns to 400ns Tristate with Pullup RDYD (From DMA Controller) 60ns MAX (Note 1) 100ns MIN (Note 2) TRISTATE DATA VALID 65ns MAX TRISTATE (From DMA Controller) 100ns MAX 65ns MAX Tristate with Pullup ACK (From DMA Controller) 180ns to 375ns Notes: 1. Requires BOTH STRBD or DEVICE SELECT to be LOW. 2. DATA will be valid 100ns before RDYD goes HIGH, and ACK goes LOW. I / O READ OPERATION R/W (From UP System) ADDRESS TRISTATE ADDRESS VALID TRISTATE (From UP System) DEVICE SELECT (From UP System) STRBD (From up System) 200ns to 400ns Tristate with Pullup RDYD (From DMA Controller) DATA (From UP System) 60ns MAX (Note 1) TRISTATE VALID TRISTATE 100ns MAX DATA Latched Tristate with Pullup ACK (From DMA Controller) 180ns to 375ns Notes: 1. Measured from STRBD or DEVICE SELECT whichever is valid LAST. RDYD requires the coincidence of STRBD and DEVICE SELECT. I / O WRITE OPERATION SCDCT1611 Rev A 8 65ns MAX 500ns ADDRESS TRISTATE 666ns FIRST (From DMA Controller) Extended 1 Cycle 50ns MIN 50ns MIN TRISTATE LAST DMA STRBD (From DMA Controller) 333ns MIN 120ns MAX or Cycle Extended DMA DATA ACK (From UP System) 250ns MIN DATA 220ns MAX TRISTATE Note 2 TRISTATE VALID (From UP System) 330ns MIN DMA ACK (From UP System) DMA REQ (From DMA Controller) 100ns MIN 0ns MIN / 18µs MAX Notes: 1. R / W from DMA Controller = Logic "1". 2. DATA will be valid within 220ns of STRBD or VALID with DMA DATA ACK. DMA READ OPERATION Tristate pulled HIGH Tristate pulled HIGH R/W (From DMA Controller) 500ns ADDRESS / DATA TRISTATE (From DMA Controller) 666ns 500ns LAST FIRST 50ns MIN 50ns MIN Extended 1 Cycle DMA STRBD (From DMA Controller) 250ns MIN 65ns MAX or Cycle Extended DMA DATA ACK (From UP System) 250ns MIN 330ns MAX DMA ACK (From UP System) DMA REQ (From DMA Controller) 0ns MIN /27µs MAX 100ns MAX VALID MSG RCV’D (Interrupt from DMA Controller) Notes: 1. If a DMA DATA ACK is not implemented in system, DMA DATA ACK should be either connected to DMA STRBD (preferred) or tied LOW. 2. Preferred method for resetting DMA DATA ACK HIGH is with trailing edge of DMA STRBD. DMA WRITE OPERATION SCDCT1611 Rev A 9 500ns TYP TRISTATE Summary of I/O Commands for CT1611 1553B Interface (All Codes HEX) Bus Controller I/O Address Code (8 Bit Mode) Description (Read or Write) Command Word # 1 XX00 (Low) XX01 (High) All Transfers (Read or Write) Command Word # 2 XX02 1. Second command word for RT to RT Transfers 2. Also associated mode data for mode change such as sync w/data 3. Also used for RTU vector word (Read or Write) Transaction Word XX0C Defines type of transfer and BUS selection Examples Function Data Normal xfer Normal xfer Bus 0 Bus 1 0000 0008 RT to RT Bus 0 Bus 1 0001 0009 Mode (No Data) Mode (No Data) Bus 0 Bus 1 0003 000B Mode (Rtn’d Data), i.e. vector word last cmd, etc. Bus 0 Bus 1 0005 000D Mode (ass’td Data), i.e. sync w/data Bus 0 Bus 1 0007 000F (Write Only) Trigger XX2A Triggers Bus Transaction Note: Command word(s) and transaction code must be loaded (Read Only) Status Word 1 XX3C Return status word for all transactions (first for RT to RT). Note: This register is preset to FFFF at beginning of transaction and at reset. Status Word 2 Rtn’d Mode Data XX3A Second returned status word for RT to RT xfers, also preset FFFF. Also returned mode data, such as vector word and last command. BC (Read Only) RTU (Read Only) Sync w/Data Sync Word (Read Only) Command Word XX36 Received command word for all transactions. i.e. transmit, receive* and mode. * use XX38 (Read Only) Receive Command Word XX38 Double Buffered version of above for valid receive commands (provides more I/O time). Vector Word XX02 Mode Data -to be transmitted - same reg as CW # 2 (Read or Write) SCDCT1611 Rev A 10 Summary of I/O Commands for CT1611 1553B Interface (All Codes HEX) Address Code (8 Bit Mode) Bus Controller I/O Description (Read Only) Sync Word XX3A 1. Mode Data -to be received 2. Same as returned mode in BC mode (Write Only) Reset I XX2E Resets CT1611 interface only (Write Only) Reset II XX2C Resets CT1611 and CT1610 front end, will reset bits in returning status word such as "TF" flag. Same as hard wired master reset used on power up. Operational word XX0A Defines BC mode and RTU mode. Data FFF0 = RTU FFF1 = BC Note: Powers up and is reset to busy RTU. (Read or Write) RTU Mode 1. Conditions for Busy When the CT1611 is declared busy, the DMA data transfer operation is inhibited. Mode data is stored in internal registers, and is therefore unaffected by busy. The bust bit is located in the Operation Register. 1.1 Busy Set by I/O and POR / RESET 1.2 DMA not complete (This in general should never occur). 1.3 FIFO Test 1.4 Receive Commands If a Terminal is declared busy during the reception of a valid message, that message will be received and a DMA request will be generated. Data will be held indefinately until the DMA request is acknowledged. Once the DMA is completed, a valid message received interrupt will be generated. 1.5 Transmit Commands If the subsystem is going to enter a non-interruptable mode and therefore declares itself busy and the condition exists that a transmit command may be received "simultaneously", the subsystem should wait 6µsec before beginning. (If a DMA request is not made during this time, none will be made until the terminal is declared not busy). This insures: a. HSFAIL will not occur because of the busy condition missing the command word. b. DMA issued, that can’t be acknowledged at a "non-interruptable time" by the microprocessor subsystem. SCDCT1611 Rev A 11 Interface Mode MODE 1 / MODE 0 → "0" is Motorola/Fairchild 9450 compatibility "1" is Intel compatibility M1 / M0 Write Operations Read Operations RDSTB / R/W → R/W - Same- WTSTB / STRBD → STRBD 0 R/W = 0 R/W = STRBD = STRBD = RDSTB / R / W → RDSTB - Same- WTSTB / STRBD → WTSTB 1 1 RDSTB = 0 RDSTB = WTSTB = WTSTB = 1 Operational Commands other than register reads and writes Operation Op Code (DS = 0) Test Triggers - must be in test mode, otherwise no operation results FIFO Reset Test trigger (load) Test trigger (unload) X10100X XX28H X10000X X10001X XX20H XX22H X10010X XX24H X10111X X10110X 2EH 2CH Operational Triggers Must be in poll mode START POLL (from offset) START POLL (from 0) (resets offset reg.) Reg. Address 000EH CONTINUE POLL (from next address) CONTINUOUS MODE- starts new poll from beginning after "poll op cmplt" INTERRUPT Non-CONTINUOUS - "poll op cmplt" INTERRUPT - then no action Note: Trigger (does not load new cmd WD (1) or transaction) generally used for non chained poll, single transaction in polling mode. This operation will repeat last, then continue. Resets Reset I resets interface only Reset II same as master reset (hardware), also resets chip set Note: All Operational Codes are Write Operations. SCDCT1611 Rev A 12 BC Criteria for Valid Transactions Valid Transactions result in generation of GOOD XFER (INT 0) Interrupt. Invalid Transfer result in generation of INVALID TRANSFER (INT 1) Interrupt. See Transaction Word for additional Status Word Criterion (i.e. bit masks) Transaction Type 1. Normal Data Transfer A. RT to BC B. BC to RT C. Broadcast 2. RT to RT Transfer A. Normal B. Broadcast Specific Validity Criteria (Tx/Rx = 1) (Tx/Rx = 0) (Tx/Rx = 0) Status, then Valid Message Status No Status (Tx/Rx = 1) (Tx/Rx = 1) Status, Valid Message,then Status Status, then Valid Message only 3. Mode (no data) A. Normal B. Broadcast Status No Status 4. Mode (associated data) A. Normal B. Broadcast Status No Status 5. Mode (returned data) Status, then returned data General Validity Criteria - Applies to all transfers A. Bus must be quiet, i.e. no additional data words, status words or command words after correct RT response before transaction is declared valid. B. If data is returned, word count, must be correct. Data must also be contiguous, i.e. no gaps. C. RTU Address(s) must be correct in returned status word(s). D. RTU must respond within 14µsec (except for non RT to RT Broadcast). E. No bits set in returned status word(s), except where masked in transaction word. Interrupts In BC Mode BC Interrupt Name Signal Name Conditions and Actions Good Transfer INT 0 1. Indicates fully valid transaction. 2. Initiates next poll operation, when in polling mode. Invalid Transfer INT 1 1. Non masked bits set (includes reserved bits). 2. No status (2 for non BCST RT to RT) word returned. 3. Status word has incorrect address. 4. Fail safe time out (1 millisec)for bus (RTU) to go quiet i.e. RTU loudmouthing. 5. Incorrect number of data words. 6. Busy (even if busy masked) when RTU should receive or transmit data. Note: busy mask only masks busy for mode cmds. Poll Operation Complete INT 2 1. Indicates end of poll,when end of poll is a valid transaction. 2. Delayed from good transfer interrupt. 3. Initiates poll sequence again (from offset) if in continuous mode. 4. If the I/O command "continue at next transaction" is issued at the last transaction command, this interrupt will be issued. SCDCT1611 Rev A 13 Interrupts in RTU Mode RTU Interrupt Name Signal Name Conditions and Actions Valid Message Received INT 0 1. Indicates the reception of a complete and valid block of data. 2. Interrupt issued after complete block of data has been DMA'd to subsystem memory. 3. Command word for receive data block is located in double buffered receive command register. SYNC With Data INT 1 1. Issued after reception of valid SYNCHRONIZE with data mode command. (Interrupt is not generated if word count is high). 2. Command word located in command register. 3. SYNC data word located in SW2/RMD register. Mode W/O Data INT 2 1. Indicates reception of mode commands without data that may require subsystem action. These are: SYNCHRONIZE (W/O DATA) RESET DYNAMIC BUS CONTROL ACCEPTANCE 2. Command word located in command register. Data Transmitted INT 3 1. Indicates reception of valid transmit command or vector mode command. 2. If issued for transmit command,then issued after DMA. 3. If issued for vector, data transmitted from CW2/AMD/VEC register. 4. Command word located in command register. Bus Controller Poll Operation Internal Triggers Trig A continues operation conditions Trig B Op Code XX24 - transaction -poll op enabled -BC mode begin again (from offset) conditions - transaction = last (TB6 = 0) - poll op enable - BC mode - valid trans interrupt SCDCT1611 Rev A 14 XX20 Summary of Registers Register Name General Function Op Code BC Command WD 1 Register 1. Contains the command word for all bus transactions (first for RT to RT transfers). (BC only) 2. Automatically loaded in polling operation. XX00 CW2 / AMD / VEC Register 1. Used in both RT and BC. 2. Contains second command word for RT to RT transfers. (BC only) 3. Contains associated mode data for mode command requiring transmitted data. (BC only) 4. Optionally automatically loaded in polling operation. (BC only) 5. Contains vector word. (RTU only) XX02 Transaction Word Register 1. Contains additional information required to fully define a bus transaction, i.e. bus selection, transfer type (normal/mode). (BC only) 2. Automatically loaded in polling operation. XX0C Transaction Address Register 1. Contains starting address for BC polling operation. XX0E Last Transaction Register 1. Contains address of last transaction. 2. Used to determine where in command stack, a failed transaction command is located. XX34 Operation Register 1. Sets operational mode i.e. Bus Controller Remote Terminal 2. Control of status word bits in RTU mode: a. BUSY b. SSERR c. SERVRQST XX0A Error Latch 1. Contains information on transactions occurring on 1553B bus. 2. Primarily used in bus controller mode. Useful in RTU mode especially during system debugging. XX32 RTU Command Word Register 1. Contains all commands received by RTU. (RTU only). Includes normal data and mode commands. XX36 RTU Receive Command Word Register 1. Contains only valid receive commands. (RTU only) 2. Loaded after data block validated. 3. Doubled buffered version of RTU command word register. XX38 Stat Word 1 Register 1. Contains returned status word. (BC only). 2. Contains first returned status word for RT to RT transfers. (BC only) XX3C Stat WD2 / RMD Register 1. Contains second returned status word for RT to RT transfers. (BC only). 2. Contains returned rode data for mode commands. (BC only). Sync word as RTV. XX3A SCDCT1611 Rev A 15 Operation Register MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 1. Power up and reset to busy RTU. 2. Used to define operating mode of 1553 interface, used for both BC and RTU modes 543210 3. Select Code = 00101X 001010 DS = 0 XX0AH Reg. Bit Name Definition 0 RT/BC Terminal Mode 0 = RTU Mode 1 = BC Mode 1 POE 2 CONT POLL 3 PFO Poll Operation Enable Enables Polling Operation in BC Mode 0 = Not Enabled 1 = Enabled Continuous Poll Operation Enable causes polling operation to continuously loop when enabled and active. 0 = Not Enabled If this bit is reset during an active polling loop, poll will end at completion of polling frame. 1 = Enabled Poll Fault Overide When not enabled, Poll Operation will halt immediately after a transaction failure. (Invalid Transfer Interrupt Generated). Note: Poll can be restarted, with last (failed transaction) or next transaction. When Enabled, poll will continue even if transaction failed. 0 = Not Enabled 1 = Enabled 4,5 REPEAT If an Error condition is detected in BC mode, the interface can RETRY the command sequence based on the following table: Bit 5 Bit 4 Repeat Count 0 0 None 0 1 1 1 0 2 1 1 3 The Interface will continue on to the next Transaction if the prescribed number of REPEAT attempts has transpired and the Error condition is still present. SCDCT1611 Rev A 16 Operation Register con’t Reg. Bit Name Definition 6,7 TEST FIFO Loop Tests A. 1553 Side Loop NO DMA occurs B. SUBYSTEM (Microprocessor) Side Loop 1553 Side Set BUSY FIFO Exercised via I/O Test Trigger Load Command and I/O Test Trigger Unload Command Bit 7 Bit 6 Test 0 0 RESET 1 1 Test A 1 0 Test B 0 1 Not Valid TEST A/B TEST ENABLE 8 NO OP NO OPERATION (Wait) when in poll mode (BC). 9 PACT POLL ACTIVE PACT = 1 indicates that a POLLING operation has been triggered. 10 DBCACC 11 SSERR Sets subsystem error flag in returned status word (RTU Mode Only). 12 BUSY Sets busy bit in returned status word, inhibits DMA (RTU Mode only). 13 TRANSACT 14-15 SERVRQ RTU Dynamic Bus Controll Acceptance when set in RTU Mode, Rtu will accept bus control request as per MIL-PRF-1553B 0 = Not Set 1 = Set TRANSFER ACTIVITY TRANSACT = 1 indicates a Transaction has been initiated and is in progress. Sets Service Request in returned status word (RTU Mode only). Bit 15 Bit 14 Flag 0 0 NOT Set 0 1 SET until reset 1 0 Set until VECTOR word is transmitted 1 1 Set until reset * * Bit 15 is ALWAYS RESET after VECTOR Word is transmitted. SCDCT1611 Rev A 17 Error Register MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 The error Register is reset by: - I/O reg reset command - I/O reset command - Power on reset (master reset) - Initiation of transfer in BC mode Bit Name 0* RTADER 1* PARER - Parity error in command or data word 2* ERROR - Any waveform encoding error in received data - Bad Manchester - Bad Parity - Bad Data Sync - Non Contiguity of data 3* LTFAIL - Encoding error in terminals transmission - Includes RT address parity 4 HSFAIL - Subsystem has not acknowledged DMA request in sufficient time. 5 TXTO 6 DMA TO * Additional information for interpretation of Register Bits 0-3. Bit Name 7 DBCACC 8 TRANS TO Indication (When Set) - RTU address Error (Parity) - Transmitter timeout error indicates 1553 transmitter has transmitted in excess of 680µsec and terminal fail safe timeout has turned off transmitter. NOTE: 1553B Max. is 800µs. If terminal timeout hardware (RT) fails self test mode command (Indicate self test), this bit will also be set. - DMA Time Out Indicates failure in data transfer between CT1611 and subsystem. If DMA takes longer than 80µsec this flag will be set and DMA will be initiated. Reg. Bits Indication 3 2 1 0 0 1 0 0 Waveform encoding error (Manchester) 0 1 1 0 Data parity error 1 X X 1 RTU address error Definition Dynamic Bus Control Acceptance Active only in RTU mode. Indicates RTU has accepted bus controller request. RTU must switch to BC mode. Transaction Time Out Active BC mode only Indicates BC transfer has failed due to loopmouthing RTU or non functioning transceive in BC. Occurs approximately 780µsec after transfer is triggered. SCDCT1611 Rev A 18 Error Register con’t Bit Name Indication (When Set) 9 GBR Good Block Received Active BC mode only Indicates valid message has been received by bus controller, set even if transaction is otherwise not valid. 10 RMD Received Mode Data Active only in BC mode Indicates valid mode data has been returned from RT. This bit is set even if transaction is otherwise not valid. 11 BIT SET Bit(s) set in returned status word(s). Active in BCC mode only. Indicates non masked bits in status word(s) are set. Masked bits are masked in Transaction Word Register. Bits include: Message error bit Instrumentation bit Service Request Reserved Bit(s) (3 bits) Broadcast Cmd Rcvd bit Busy bit Subsystem Flag Dynamic Bus Control Acceptance bit Terminal Flag 12 AD ERR Address in status word(s) error active only in BC mode. Indicates RTU address in returned status word(s) is incorrect. 13. 14 SW CNT Returned status word count. Active only in BC mode. Two bit non rollover counter for returned status words.. 15 BUS ACT ERR Bit 14 Bit 13 Count 0 0 None returned 0 1 One returned 1 0 Two returned 1 1 Three, or greater returned Bus Activity Error Active in BC mode only. This bit is set if the bus is active when should be quiet following: A. Returned mode data (indicates word count high) B. After status in normal receive, mode without data, and non broadcast RT to RT. SCDCT1611 Rev A 19 Transaction Word Register MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 Used only in BC mode Contains information not explicitly contained in command word. Defines: 1. Type of Transfer 2. Selection of bus - selects 1 of 4 Note: Most systems are only dual redundant 3. Continue, for continuous poll operation 4. Conditions for defining an invalid transfer via Bit masks for returned status words. 5. Continue/last control bit for framing poll operations. This register is loaded via I/O Command. It is also loaded during a Polling Operation, via DMA from the polling command stack. Reg. Bit Name 0-2 TRANS TYPE 3-4 5 BUS DMA3RD Definition Specifies Transaction Type Bit 2 Bit 1 Bit 0 Transaction 0 0 0 NORMAL Receive or Transmit 0 0 1 RT to RT 0 1 0 No Operation 0 1 1 Mode WITHOUT data 1 0 0 No Operation 1 0 1 Mode with RETURNED data 1 1 0 No Operation 1 1 1 Mode with associated data Selection of Bus Bit 4 Bit 3 Bus 0 0 "0" or "A" 0 1 "1" or "B" 1 0 "2" or "C" 1 1 "3" or "D" Polling Sequence Option (Polling Mode only) For use with RT to RT transfers and code with associated data transfers. When set, during polling sequence, the second command word (for RT to RT transfers) or the data word (for mode with associated data transfers) is loaded from the command stack. Otherwise the last entry in the second command/and register will be used in transfer. 0 = Not Set 1 = Set SCDCT1611 Rev A 20 Transaction Word Register con’t Reg. Bit Name Definition 6 POLL CONT Poll Operation Continue (Polling Mode only) When set polling operation will continue with next command in command stack. When Not Set, polling operation will terminate after transaction is complete. Last transfer in polling sequence must have this bit cleared. 0 = Not Set 1 = Set 7 - 15 MASK BITS Returned Status Word Bit Masks 1 = Masked 0 = Not Masked When a non masked bit in the returned status word(s) is set the transaction is declared not valid. Bit Status Bit 7 Terminal Flag 8 Dynamic Bus Control Acceptance 9 Subsystem Flag 10 Busy Bit * 11 Broadcast Command Received 12 Reserved Bits (any or all of 3) 13 Service Request Bit 14 Instrumentation Bit 15 Message Error Bit * Note: Setting the busy bit mask will not mask a busy response (i.e. declare it valid). When data is not returned, in response to a transmit command. SCDCT1611 Rev A 21 CT1611 – Pinouts vs Function Pin # FP DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin # Signal SSERR TRANSMIT/RECEIVE POLL/DATA DS R/W /RDSTB RDYD STRBD /WRSTB (OUT) STRBD /WRSTB (IN) ACK DMA REQ DMA ACK DB 0 DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 DB 8 DB 9 DB 10 DB 11 DB 12 DB 13 DB 14 DB 15 AD 0 AD 1 AD 2 AD 3 AD 4 AD 5 AD 6 AD 7 AD 8 AD 9 AD 10 INT 3 INT 1 INT 0 INT 2 MASTER RESET COMMON/CASE N/C SCDCT1611 Rev A 22 FP DIP 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 - 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 Signal +5V BUSY BITEN /RMDSTB LSTCMD /CWEN HSFAIL GBR H/L STATEN /STATSTB RT/BC DBCACC TXTO SERVREQ INCMD EOT DTRQ VECTEN /DWEN NBGT SYNC 16/8 MODE 1/MODE 0 IUSTB DTACK BCOP A BCOPSTB RTADER BCOP B PARER MANER LTFAIL DMA DATA ACK CLOCK IN (6MHZ) RTO REQBUS B REQBUS A IHDIR IHEN IH08 IH19 IH210 IH311 IH412 IH513 IH614 IH715 N/C Plug In Package Outline .225 MAX 2.400 MAX 1.600 MAX Lead 1 & ESD Designator .090 .135 Pin 1 .200 MIN 2.200 Pin 3 .050 TYP Pin 43 Pin 45 Pin 44 Pin 2 .018 DIA TYP 1.300 1.100 Pin 89 Pin 47 Pin 90 Pin 88 .135 .100 TYP Pin 48 Pin 46 2.100 Flat Package Outline 2.400 MAX .010 ±.002 .015 Pin 45 Pin 88 .225 MAX 1.600 MAX Lead 1 & ESD Designator .300 Min Pin 44 .115 TYP 2.150 .050 Lead Centers 44 Leads/Side SCDCT1611 Rev A 23 Date Code .080 REF Ordering Information Model No. Case CT1611 Plug In CT1611-FP Flat Pack PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused SCDCT1611 Rev A 24