PI3VDP411LS Features 07-0198 1 29 28 27 26 OE# 30 VCC3V 31 GND 32 SDA_SINK 33 SCL_SINK 34 HPD_SINK 35 DDC_EN 36 GND Pin Configuration VCC3V 25 24 GND 37 IN_D1- 38 23 OUT_D1- IN_D1+ 39 22 OUT_D1+ VCC3V GND VCC3V 40 21 IN_D2- 41 20 OUT_D2- 19 OUT_D2+ 18 GND IN_D2+ 42 GND 43 48-pin QFN Pinout 15 VCC3V 47 14 OUT_D4- IN_D4+ 48 13 12 OUT_D4+ 1 2 3 4 5 6 7 8 9 10 11 GND 46 IN_D4- OC_3 VCC3V VCC3V OUT_D3OUT_D3+ SCL_SOURCE 17 16 SDA_SOURCE 44 45 HPD_SOURCE IN_D3IN_D3+ OC_2(REXT ) • GND • • OC_1 • • EQ_1 • The PI3VDP411LS supports up to 2.5Gbps, which provides 12bits of color depth per channel, as indicated in HDMI rev 1.3. EQ_0 • OC_0 • Pericom Semiconductor’s PI3VDP411LS provides the ability to use a Dual-mode DP transmitter in HDMI mode. This flexibility provides the user a choice of how to connect to their favorite display. All signal paths accept AC coupled video signals. The PI3VDP411LS converts this AC coupled signal into an HDMI rev 1.3 compliant signal with proper signal swing. This converstion is automatic and transparent to the user. VCC3V • Description GND • Converts low-swing AC coupled differential input to HDMI rev 1.3 compliant open-drain current steering Rx terminated differential output HDMI level shifting operation up to 2.5Gbps per lane (250MHz pixel clock) Integrated 50-ohm termination resistors for AC-coupled differential inputs. Enable/Disable feature to turn off TMDS outputs to enter low-power state. Output slew rate control on TMDS outputs to minimize EMI. Transparent operation: no re-timing or configuration required. 3.3 Power supply required. Integrated ESD protection to 2kV Human Body on all I/O pins DDC level shifters Level shifter for HPD signal from HDMI/DVI connector Integrated pull-down on HPD_sink input guarantees "input low" when no display is plugged in GND • Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter PS8913A 08/29/07 PI3VDP411LS Display Port Redriver w/ Level Conversion feature for DVI/HDMI interoperability Block Diagram OE# OUT_D4+ OUT_D4- 0V IN_D4+ IN_D4- Rx OUT_D3+ OUT_D3- 0V IN_D3+ IN_D3- Rx OUT_D2+ OUT_D2- 0V IN_D2+ IN_D2- Rx OUT_D1+ OUT_D1- 0V IN_D1+ IN_D1- HPD_SOURCE 07-0198 2 Rx HPD_SINK HPD SCL_SOURCE SCL_SINK SDA_SOURCE SDA_SINK PS8913A 08/29/07 PI3VDP411LS Display Port Redriver w/ Level Conversion feature for DVI/HDMI interoperability Table 1: Package Pinout Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 07-0198 Pin Number 43 44 45 46 47 48 Pin Name GND VCC3V OC_0 OC_1 GND OC_2(REXT) HPD_SOURCE SDA_SOURCE SCL_SOURCE OC_3 VCC3V GND OUT_D4+ OUT_D4VCC3V OUIT_D3+ OUT_D3GND OUT_D2+ OUT_D2VCC3V OUT_D1+ OUT_D1GND OE# VCC3V GND SCL_SINK SDA_SINK HPD_SINK GND DDC_EN VCC3V EQ_0 EQ_1 GND GND IN_D1IN_D1+ VCC3V IN_D2IN_D2+ 3 Pin Name GND IN_D3IN_D3+ VCC3V IN_D4IN_D4+ PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature.....................................–65°C to +150°C Supply Voltage to Ground Potential.............–0.5V to +5V DC Input Voltage..........................................–0.5V to VDD DC Output Current.......................................120mA Power Dissipation.........................................1.0W Table 2: Signal Descriptions Pin Name Type OE# 5.5V tolerant low-voltage single-ended input IN_D4+ Differential input IN_D4– Differential input IN_D3+ Differential input IN_D3– Differential input IN_D2+ Differential input IN_D2– Differential input IN_D1+ Differential input IN_D1– Differential input OUT_D4+ TMDS Differential output OUT_D4– TMDS Differential output OUT_D3+ TMDS Differential output OUT_D3– TMDS Differential output 07-0198 Description Enable for level shifter path OE# IN_D Termination OUT_D Outputs 1 >100KΩ High-Z 0 50Ω Active Low-swing diff input from GMCH PCIE outputs. IN_D4+ makes a differential pair with IN_D4–. Low-swing diff input from GMCH PCIE outputs. IN_D4– makes a differential pair with IN_D4+. Low-swing diff input from GMCH PCIE outputs. IN_D3+ makes a differential pair with IN_D3–. Low-swing diff input from GMCH PCIE outputs. IN_D3– makes a differential pair with IN_D3+. Low-swing diff input from GMCH PCIE outputs. IN_D2+ makes a differential pair with IN_D2–. Low-swing diff input from GMCH PCIE outputs. IN_D2– makes a differential pair with IN_D2+. Low-swing diff input from GMCH PCIE outputs. IN_D1+ makes a differential pair with IN_D1–. Low-swing diff input from GMCH PCIE outputs. IN_D1– makes a differential pair with IN_D1+. HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4–. HDMI 1.3 compliant TMDS output. OUT_D4– makes a differential output signal with OUT_D4+. HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3–. HDMI 1.3 compliant TMDS output. OUT_D3– makes a differential output signal with OUT_D3+. 4 PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Pin Name OUT_D2+ Type TMDS Differential output OUT_D2– TMDS Differential output OUT_D1+ TMDS Differential output OUT_D1– TMDS Differential output HPD_SINK 5V tolerance single-ended input HPD_SOURCE SCL_SOURCE SDA_SOURCE SCL_SINK SDA_SINK DDC_EN VCC3V OC_2 (1) (REXT) Description HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2–. HDMI 1.3 compliant TMDS output. OUT_D2– makes a differential output signal with OUT_D2+. HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1–. HDMI 1.3 compliant TMDS output. OUT_D1– makes a differential output signal with OUT_D1+. Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the HDMI connector. Voltage High indicates "plugged" state; voltage low indicated "unplugged". HPD_SINK is pulled down by an integrated 100K ohm pulldown resistor. 3.3V single-ended output HPD_SOURCE: 0V to 3.3V (nominal) output signal. This is level-shiftedversion of the HPD_SINK signal. Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external terminaDDC I/O tion to 3.3V. Connected to SCL_SINK through voltage-limiting intergrated NMOS passgate. Single-ended 3.3V open-drain 3.3V DDC Data I/O. Pulled up by external termination DDC I/O to 3.3V. Connected to SDA_SINK through voltagelimiting intergrated NMOS passgate. Single-ended 5V open-drain 5V DDC Clock I/O. Pulled up by external termination DDC I/O to 5V. Connected to SCL_SOURCE through voltagelimiting integrated NMOS passgate. Single-ended 5V open-drain 5V DDC Data I/O. Pulled up by external termination DDC I/O to 5V. Connected to SDA_SOURCE through voltagelimiting integrated NMOS passgate. 5.0V tolerant Single-ended input Enables bias voltage to the DDC passgate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass gates themselves.) DDC_EN Passgate 0V Disabled 3.3V Enabled 3.3V DC Supply 3.3V single-ended control input 3.3V ± 10% Acceptable connections to OC_1 (REXT) pin are: Resistor to GND; Resistor to 3.3V; NC. (Resistor should be 0-ohm). Note: 1) internal 100Kohm pull-up 07-0198 5 PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Pin Name OC_3(1) Type Analog connection to external component or supply Output and Input jitter elimination control OC_0(1) OC_1(1) EQ_0(1) EQ_1(1) Description Acceptable connections to OC_3 pin are: short to 3.3V or to GND; NC. Control pins are to enable Jitter elimination features. For normal operation these pins are tied GND or to VCC3V. Please see the truth tables for more information. Notes: 1) internal 100Kohm pull-up Truth Table 1 OC_3 OC_2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Truth Table 2 EQ_0 EQ_1 0 0 1 1 0 1 0 1 07-0198 OC_1 OC_0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Vswing (mV) 500 600 750 1000 500 500 500 500 400 400 400 400 1000 1000 1000 1000 Pre/Deemphasis 0 0 0 0 0 1.5dB 3.5dB 6dB 0 3.5dB 6dB 9dB 0 -3.5dB -6dB -9dB Equalization (dB) 3 7.2 10 12 6 PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Electrical Characteristics Table 3: Power Supplies and Temperature Range Symbol Parameter Min Nom VCC3V 3.3V Power 3.0 3.3 Supply ICC Max Current TCASE Case temperature range for operation with spec. Table 4: OE Description OE# Asserted (low voltage) Unasserted (high voltage) -10 Max Units 3.6 V 100 mA 50 Celcius Device State Differential input buffers and output buffers enabled. Input impedance = 50Ω Low-power state. Differential input buffers and termination are disabled. Differential inputs are in a high-impedance state. OUT_D level-shifting outputs are disabled. OUT_D level-shifting outputs are in high-impedence state. Internal bias currents are turned off. 07-0198 7 Comments Total current from VCC 3.3V supply when de-emphasis/ pre-emphasis is set to 0dB. Comments Normal functioning state for IN_D to OUT_D level shifting function. Intended for lowest power condition when: • • No display is plugged in or The level shifted data path is disabled HPD_SINK input and HPD_SOURCE output are not affected by OE# SCL_ SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE# PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Table 5: Differential Input Characteristics for IN_D and RX_IN signals Symbol Parameter Min Nom Max Units Comments Tbit is determined by the display mode. NomTbit Unit Interval 360 ps inal bit rate ranges from 250Mbps to 2.5Gbps per lane. Nominal Tbit at 2.5 Gbps=400ps. 360ps=400ps-10% VRX-DIFFp-p Differential Input Peak 0.175 to Peak Voltage Minimum Eye Width at 0.8 TRX-EYE IN_D input pair VCM-AC-pp AC Peak Common Mode Input Voltage ZRX-DC 40 VRX-Bias 0 ZRX-HIGH-Z 100 07-0198 1.200 V Tbit 50 100 mV 60 Ω 2.0 V kΩ 8 VRX-DIFFp-p=2'|VRX-D+ x VRX-D-| Applies to IN_D and RX_IN signals The level shifter may add a maximum of 0.02UI jitter VCM-AC-pp = |VRX-D+ + VRX-D-|/2 - VRX-CM-DC. VRX-CM-DC = DC(avg) of|VRX-D+ + VRX-D-|/2 VCM-AC-pp includes all frequencies above 30 kHz. Required IN_D+ as well as IN_D- DC impedance (50Ω ± 20% tolerance). Intended to limit power-up stress on chipset's PCIE output buffers. Differential inputs must be in a high impedance state when OE# is HIGH. PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter TMDS Outputs The level shifter's TMDS outputs are required to meet HMDI 1.3 specifications. The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification. Table 6: Differential Output Characteristics for TMDS_OUT signals Symbol VH Parameter Min Single-ended AVCC-10mV high level output voltage Nom AVCC VL Single-ended AVCC-600mV low level output voltage Single-ended 450mV output swing voltage Single-ended current in high-Z state AVCC-500mV AVCC-400mV V 500mV 600mV V Swing down from TMDS termination voltage (3.3V ± 10%) 10 μA Measured with TMDS outputs pulled up to AVCC Max (3.6V)through 50Ω resistors. Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% This differential skew budget is in addition to the skew presented between D+ and D- paired input pins. HDMI revision 1.3 source allowable intra-pair skew is 0.15Tbit. This lane-to-lane skew budget is in addition to skew between differential input pairs VSWING IOFF Max AVCC+10mV Units Comments AVCC is the DC terminaV TR Rise time 125ps 0.4Tbit ps TF Fall time 125ps 0.4Tbit ps TSKEW-INTRA Intra-pair differential skew 30 ps TSKEW-INTER Inter-pair laneto-lane output skew 100 ps TJIT Jitter added to TMDS signals 25 ps 07-0198 9 tion voltage in the HDMI or DVI Sink. AVCC is nominally 3.3V The open-drain output pulls down from AVcc. Jitter budget for TMDS signals as they pass through the level shifter. 25ps = 0.056 Tbit at 2.25 Gb/s PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter Table 8: HPD Input Characteristics Symbol Parameter Min Input High Level 2.0 VIH-HPD VIL-HPD IIN-HPD VOH-HPDB VOL-HPDB THPD TRF-HPDB HPD_sink Input Low Level HPD_sink Input Leakage Current HPD_sink Output High-Level HPD_sink Output Low-Level HPD_sink to HPD_source propogation delay HPD_source rise/ fall time Table 9: OE Input and DDC_EN Symbol Parameter VIH Input High Level VIL IIN Input Low Level Input Leakage Current Table 10: Termination Resistors Symbol Parameter HPD_sink input pulldown resistor. RHPD 07-0198 Nom 5.0 Max 5.3 Units V 0.8 V 70 μA 2.5 VCC V 0 0.02 V 200 ns 20 ns 0 1 Min Nom Comments Low-speed input changes state on cable plug/unplug Measured with HPD_sink at VIH-HPD max and VIL-HPD min VCC = 3.3V ± 10% Time from HPD_sink changing state to HPD_source changing state. Includes HPD_source rise/fall time Time required to transition from VOHHPDB to VOL-HPDB or from VOL-HPDB to VOH-HPDB Max Units 2.0 VCC3V V 0 0.8 10 V μA Comments TMDS enable input changes state on cable plug/unplug Measured with input at VIH-EN max and VIL-EN min Min Nom Max Units Comments 80K 100k 120K Ω Guarantees HPD_sink is LOW when no display is plugged in. 10 PS8913A 08/29/07 PI3VDP411LS Digital Video Level Shifter from AC coupled digital video input to a DVI/HDMI transmitter ( "$ %&$!& ( ( ( ( "$ %&$!& Packaging Mechanical: 48-Pin, TQFN (ZD) ( ( ( !%##!$ ! $ ''!&$ .OTES !LLDIMENSIONSAREINMILLIMETERSANGLESINDEGREES 2EF*%$%#-/6++$ 4HERMAL6IA$IAMETER2ECOMMENDED^MM 4HERMAL6IA0ITCH2ECOMMENDEDMM DATE: 03/10/06 DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) "ILATERALCOPLANARITYZONEAPPLIESTOTHEEXPOSEDHEATSINKSLUG ASWELLASTHETERMINALS PACKAGE CODE: ZD (ZD48) REVISION: A DOCUMENT CONTROL #: PD-2045 Ordering Information Ordering Code Package Code PI3VDP411LSZDE ZD Package Description 48-pin Pb-free & Green, TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0198 11 PS8913A 08/29/07