PI3HDMI421AR

PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Description
• Supply voltage, VDD = 3.3V ±5%
• Compatible w/ DVI, HDMI 1.1, 1.2, and 1.3 signals
• HDMI revision 1.3 support up to 12-bits of color/channel
(2.5Gbps)
• Supports both AC-coupled and DC-coupled inputs
• 2:1 Mux
• Configurable output swing control (500mV, 750mV, 1000mV)
• Configurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, &
6.0dB)
• Configurable De-Emphasis (0dB, -1.5dB, -3.5dB, -6.0dB)
• Configurable Equalization (1dB,3.5dB, 6dB, or optimal
setting)
• Auto-FlexTM Equalization allws single setting for all cable
length support, 1meter to 20meters
• Max Data Rate = 2.5Gbps
• ESD protection = 6kV (typical)
• Inputs w/ built in termination
• Progogation delay = < 2ns input
• Uni-Directional
• Packaging (Pb-free & Green): 56-pad TQFN (ZB56)
Pericom Semiconductor’s PI3HDMI421AR 2:1 active mux circuit
is targeted for high-resolution video networks that are based
on DVI/HDMI standards, and TMDS signal processing. The
PI3HDMI421AR is an active 2 TMDS to 1 TMDS mux receiver
switch with Hi-Z outputs. The device receives differential signals
from selected video components and drives the video display unit.
It provides three controllable output swings that can be controlled
through a single bit. The allowable output swings are 500mV,
750mV and 1000mV. This solution also provides a unique
advanced pre-emphasis technique to increase rise and fall times
which are reduced during transmission across long distances.
The maximum DVI/HDMI Bandwidth of 2.5Gbps provides
1920x1080 resolution with 12-bit/channel color depths required
by the next Gen HDTV and PC graphics. For consumer video
networks, the device sits at the receiver’s side to switch between
multiple video components. PI3HDMI421AR is the industry’s
first active DVI/HDMI switch compatible with HDMI rev. 1.3,
which ensures transmitting high bandwidth video streams from
video components to the display unit.
The Optimized Equalization provides the user a single optimal
setting that can provide HDMI compliance for all cable lengths:
2meter, 10meter, 15meter, and 20 meter. Pericom also offers the
ability to fine tune the equalization settings in situations where
cable length is known.
Switch Block Diagram
Pin Configuration
D0+A
D0–A
VDD
CLK+A
CLK–A
GND
MS
OE
SEL_IN
S3 (port A)
S2 (port A)
AVDD
AGND
GND
Features
CLK+A
CLK-A
CLK+B
CLK-B
Pre-emphasis
and Output
Swing Control
Receiver Equalization
D0+B
D0-B
D1+B
D1-B
D2+B
D2-B
Receiver Equalization
D0+A
D0-A
D1+A
D1-A
D2+A
D2-A
Circuitry
GND
D1–A
D1+A
VDD
D2–A
D2+A
GND
CLK–B
CLK+B
VDD
D0–B
D0+B
GND
D1–B
D0+
D0D1+
D1D2+
D2CLK+
CLK-
07-0014
VDD
CLK–
CLK+
GND
D0–
D0+
VDD
GND
D1–
D1+
GND
D2–
D2+
VDD
A0/S4
A1/S5
A2/S6
A3/S7
GND
SDA/S2
SCL/S3
NC
NC
SEL_OUT
D2+B
D2–B
VDD
D1+B
Control
Logic
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
1
41
2
40
3
39
4
38
5
37
6
36
7
GND
35
8
34
9
33
10
32
11
31
12
30
13
29
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
PS8840e
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Function Block Description
VDD
50Ω
50Ω
Dx+z
Dx
TMDS
Receiver
with EQ
Dx-z
+y
TMDS
Driver
Dx
Note:
1. X = 0,1,2,3
2. Y = B,D
3. Z = A,C
-y
BYTE 1 (Address Assignment)
Address
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
A3
A2
A1
A0
R=1/W=0
Value
BYTE 2 (1st Data byte - Port A control and output control)
Port A and Output
Control
Swing Control
Pre-Emphasis
De-Emphasis
Output Port Select
Equalization (dB)
S7
S6
S5
S4
S3
S2
S1
S0
0
0
0
0
0
0
0
0
1
1
1
1
x
x
x
x
x
x
0
0
0
0
1
1
1
1
0
0
0
0
x
x
x
x
x
x
0
0
1
1
0
0
1
1
0
0
1
1
x
x
x
x
x
x
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
x
x
x
x
x
x
x
1
1
x
x
Swing
(mV)
500
750
1000
N/A
500
500
500
750
750
750
750
750
Result
Pre-emphasis (dB)
0
0
0
N/A
0
1.5
3.5
6.0
0
0
0
0
De-emphasis (dB)
0
0
0
N/A
0
0
0
0
0
-1.5
-3.5
-6.0
Port A is active
Port B is active
I/O's = Hi-Z
1
3.5
Optimized Equalization
8
BYTE 3 (2nd Data byte - Port B control)
Port B Control
Equalization (dB)
07-0014
S7
x
x
x
S6
x
x
x
S5
x
x
x
S4
x
x
x
S3
0
0
1
S2
0
1
0
S1
x
x
x
S0
x
x
x
Result
1
3.5
Optimized EQ Setting
x
x
x
x
1
1
x
x
8
2
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................................... –65°C to +150°C
Supply Voltage to Ground Potential...................................–0.5V to +5V
DC Input Voltage ...............................................................–0.5V to VDD
DC Output Current....................................................................... 120mA
Power Dissipation ........................................................................... 1.0W
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Pin Description
Pin #
Pin Name
Type
Description
4, 10, 16, 29, 36, 42, 45, 54
1, 7, 13, 24, 32, 35, 39, 43, 44, 51
VDD
GND
Power
Power
3.3V power supply
0V power supply
22
SCL
I
23
22, 23
SDA
S3, S2 (PortB)
I/O
I
48
SEL_IN
I
25, 26, 27, 28
A0 - A3
I
25, 26, 27, 28
S7, S6, S5, S4
I
50
MS
I
20, 21
NC
N/A
19
SEL_OUT
O
2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17,
18, 52, 53, 55, 56
30, 31, 33, 34, 37, 38, 40, 41
46, 47
Dxy ,CLKy
I
Dx, CLK
S2, S3 (Port A)
O
I
49
OE
I
07-0014
I2C Clock input Signal if and only if, MS = ‘HIGH’
I2C Date Input/Output Signal if and only if, MS = ‘HIGH’
If MS = ‘LOW’, then pins 22 and 23 are control bits S2 and S3 for
Port B only, as shown in the truth table on page 3.
Control pin used to choose which input signal is active, Port A or
Port B. If ‘LOW’, then Port A is active, if ‘HIGH’, then Port B is
active.
I2C address inputs if and only if MS = ‘HIGH’.
If MS = ‘LOW’, then pins 25-28 are control bits S7-S4, as shown
in truth table on page 3 of datasheet
Mode Select Pin. If MS = ‘HIGH’, then I2C control is active. Pins
25-28 are I2C address and pin 22 is SCL and pin 23 is SDA. If MS
= ‘LOW’, then I2C control is inactive and pin programmability is
active. Pins 25-28 are control pins S7-S4 and pin 23 is S2 and pin
22 is S3.
No Connect.
Output bit, that provides information to user as to which port is
active, if SEL_OUT = ‘LOW’, then Port A is active, if SEL_OUT
= ‘HIGH’, then Port B is active. Only used when MS pin is
‘HIGH’
High Speed TMDS input signals
High Speed TMDS output signals
If MS = ‘LOW’, then pins 22 and 23 are control bits S2 and S3 for
Port A only, as shown in the truth table on page 3.
Output is enabled and normal when OE = ‘HIGH’. If OE =
‘LOW’, output is disabled and at Hi-Z
3
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
TMDS Compliance Test Results
Item
HDMI 1.3 Spec
Pericom TMDS Product Spec
Termination Supply Voltage,
AVDD
3.3V ≤ 5%
3.30 ± 5%
Terminal Resistance
50-ohm ± 10%
45 to 55-ohm
Single-ended high level output
voltage, VH
AVDD ± 10mV
AVDD ±10mV
Single-ended low level output
voltage, VL
(AVDD - 600mV) ≤ VL ≤ (AVDD - 400mV)
(AVDD - 600mV) ≤ VL ≤ (AVDD - 400mV)
Operating Conditions
Source DC Characteristics at TP1
Single-ended output swing voltage, 400mV ≤ Vswing ≤ 600mV
Vswing
400mV ≤ Vswing ≤ 600mV
Single-ended standby (off) output
voltage, Voff
AVDD ± 10mV
AVDD ± 10mV
Single-ended standby (off) output
current, Ioff
| IOFF | < 10μA
| IOFF | < 10μA
Transmitter AC Characteristics at TP1
Risetime/Falltime (20%-80%)
75ps ≤ Risetime/Falltime ≤ 0.4 Tbit
(75ps ≤ tr/tf ≤ 242ps) @ 1.65Gbps
240ps
Intra-Pair Skew at Transmitter
Connector, max
0.15 Tbit
(90.9ps @ 1.65Gbps)
60ps max
Inter-Pair Skew at Transmitter
Connector, max
0.2 Tpixel
(1.2ns @ 1.65Gbps)
100ps max
Clock Jitter, max
0.25 Tbit
(151.5ps @ 1.65Gbps)
82ps max
Sink Operating DC Characteristics at TP2
Input Differential Voltage Level,
Vdiff
150 ≤ Vdiff ≤ 1200mV
150mV ≤ VDIFF ≤ 1200mV
Input Common Mode Voltage
Level, VICM
(AVDD - 300mV) ≤ Vicm ≤ (AVDD37.5mV)
Or AVDD ±10%
(AVDD - 300mV) ≤ Vicm ≤ (AVDD-37.5mV)
Or AVDD ±10%
Sink DC Characteristics When Source Disabled or Disconnected at TP2
Differential Voltage Level
07-0014
AVDD ± 10mV
AVDD ±10mV
4
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
DC Electrical Characteristics(2,3) (TA = –40°C to +85°C, unless otherwise noted. VDD = 3.3V ±0.3V)
Symbol
Parameter
Vidiff
Input Differential Voltage Level
Vicm
Test Condition(1)
Min.
Typ.(2)
Max.
Units
150
1200
mVp-p
Input Common Mode Voltage
1.8
VDD +10%
V
Vdiff
Differential Voltage Level
VDD – 10mV
VDD + 10mV
V
VOS
Offset Voltage
VDD – 250mV
V
VIH
Minimum Input High Voltage
VIL
Minimum Input Low Voltage
0.8
V
ICC
Power Supply Current
282
mA
VDD
1.8
V
AC Electrical Characteristics (TA = –40°C to +85°C, VDD = 3.3V ±0.3V)
Test Conditions(1)
Min.
Typ.(2)
Symbol
Paramter
VSEN
Differential Sensitivity (peak-to-peak)
VIN
Differential Input (peak-to-peak)
1560
mVp-p
Allowable Intra-Pair Skew at Sink Connector
50
ps
Allowable Inter-Pair Skew at Sink Connector
100
ps
150
Units
mVp-p
TMDS Clock Jitter
T20-80
Max.
50
ps
TDR Rise Time
200
ps
Through connection impedance
85
100
115
Ω
At Termination Impedance
90
100
110
Ω
tPHLD
Differential Propagation Delay High to Low
1
ns
tPLHD
Differenital Propagation Delay Low to High
1
ns
tSKD
Differential Skew | tPHLD - tPLHD |
25
ps
tPHZ
Disable Time High to Z
5
tPLZ
Disable Time Low to Z
5
tPZH
Enable Time Z to High
1
tPZL
Enable Time Z to Low
1
ns
μs
Power Supply Characteristics
Parameters
Description
ICCQ
Quiescent Power Supply Current
Test Conditions(1)
VDD = Max., VIN = VDD, OE = 'LOW'
Min.
Typ.(2)
Max.
1
Units
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VDD = 3.3V, TA = 25°C ambient and maximum loading.
07-0014
5
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Normalized Differential Amplitude
Normalized Eye Diagram Mask at TP1 for Source Requirements
0.65
0.50
0.25
0.0
-0.25
-0.50
-0.65
0.15 0.31666...
0.0
0.68333...
0.85
1.0
Normalized Time
Absolute Eye Diagram Mask at TP2 for Sink Requirements
Differential Amplitude (mV)
780
75
0
-75
0.70 0.75
0.25 0.30
0.0
07-0014
1.0
Normalized Time
6
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Application Information - Recommended layout for 2 HDMI Input System
07-0014
7
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Application Information
PI3HDMI421AR can be used to re-drive HDMI or DVI signals across internal cables or long FR4 trace
lengths.
If a DTV is designed with a side/front HDMI connector, a separate daughter card is needed for the side/front
HDMI connector and Pericom re-driver.
ATC compliance MUST only be maintained from the front/side connector to the PI3HDMI421AR IC. After
the PI3HDMI421AR signal integrity will be taken care of through the powerful pre-emphasis technique of
the Pericom solution.
DVI
Source
(OUT)
DVI Connector
Test Access Board
D0/D1/D2
Test Point
HDMI Cable
E2678A Differential
Socket probe head
E1132A/1134A
Probe Amplifier
HDMI411AD
Damping Resistors
Recovered
Clock
54854A/54855A Oscilloscope
SMA to BNC
Cable
07-0014
8
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Figure 3: 8bit deep color DVI/HDMI TX eye tested with 2 meter. 30 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
Figure 4: 8bit deep color DVI/HDMI TX eye tested with 10 meter. 24 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
07-0014
9
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Figure 5: 8bit deep color DVI/HDMI TX eye tested with 20 meter. 24 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
Figure 6: 8bit deep color DVI/HDMI TX eye tested with 25 meter. 24 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
07-0014
10
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
Figure 7: 12bit deep color DVI/HDMI TX eye tested with 1 meter. 30 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
Figure 8: 12bit deep color DVI/HDMI TX eye tested with 20 meter. 24 AWG HDMI cable.
Setting: Optimized equalization, 0dB output pre-emphasis and de-emphasis, and Swing
500mV.
07-0014
11
PS8840E
01/08/07
PI3HDMI421AR
2:1 Active HDMI 1.3 Compatible Mux with Advanced
Equalization for Enhanced Signal Integrity
.OTES
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Ordering Information
Ordering Code
PI3HDMI421ARZBE
Package Code
Package Description
ZB
56-pin, Pb-free & Green TQFN
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• Adding an X Suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
07-0014
12
PS8840E
01/08/07