PI6C5922504

PI6C5922504
2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Features
Description
ÎÎFMAX < 2.5GHz
The PI6C5922504 is a high-performance low-skew 1-to-4 LVDS
fanout buffer. The CLK inputs accept LVPECL, LVDS, CML and
SSTL signals. PI6C5922504 is ideal for clock distribution applications such as providing fanout for low noise Pericom oscillators.
ÎÎ4 pairs of differential LVDS outputs
ÎÎLow additive jitter, < 0.05ps (max)
ÎÎInput CLK accepts: LVDS, LVDS, CML, SSTL input level
ÎÎOutput to Output skew: <20ps
ÎÎOperating Temperature: -40oC to 85oC
ÎÎPower supply: 3.3V ±10% or 2.5V ±5%
ÎÎPackaging (Pb-free & Green)
TQFN available
Pin Configuration
Q0Q0+
VDD
GND
Block Diagram
Q0+
Q0Q1+
Q1REF_IN+
VTH
REF_IN-
Q1+
Q1Q2+
Q2-
Q2+
Q2EN
D
Q3+
Q3Q
Q3+
Q3VDD
LE
1
2
3
4
16 15 14 13
12
11
10
9
5 6 7 8
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1
REF_IN+
VTH
VREF-AC
REF_IN-
EN
ÎÎ16-pin
PI6C5922504 Rev A
08/14/2014
PI6C5922504
2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Pin Description(1)
Pin #
Name
Type
Description
1, 2
Q1+, Q1-
Output
Differential output pair, LVDS interface level.
3, 4
Q2+, Q2-
Output
Differential output pair, LVDS interface level.
5, 6
Q3+, Q3-
Output
Differential output pair, LVDS interface level.
7
VDD
Power
Core Power Supply
8
EN
Input
Synchronous Output Enable, with internal 25k-ohm pull-up resistor. Logic high selects
enable, and logic low selects disable.
9
REF_IN-
Input
Differential IN negative input, AC and DC coupled
10
VREF-AC
Output
Reference Voltage: Biased to VDD-1.4V. Used when AC coupling inputs
11
VTH
Output
Differential pair IN center-tap node. Tie to VREF-AC for AC Coupled inputs.
12
REF_IN+
Input
Differential IN positive input, AC and DC coupled
13
GND
Power
Ground
14
VDD
Power
Core Power Supply
15, 16
Q0+, Q0-
Output
Differential output pair, LVDS interface level.
Functional Description
REF_IN+
REF_IN-
EN
Q+
Q-
0
1
1
0
1
1
0
1
1
0
X
X
0
0
1
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PI6C5922504
2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Maximum Ratings (Over operating free-air temperature range)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Storage Temperature............................................... -65ºC to+155ºC
Ambient Temperature with Power Applied..........-40ºC to+85ºC
3.3V Core Supply Voltage.......................................... -0.5 to +4.6V
ESD Protection (HBM).......................................................... 2000V
DC Characteristics
Symbol
Parameter
Conditions
Min
VDD
Power Supply Voltage
TA
Ambient Temperature
IDD
Power Supply Current
R DIFF_IN
Differential Input Resistance
(IN+ to IN-)
90
VIH
Input High Voltage
VIL
Typ
Max
Units
3.0
3.6
V
2.375
2.625
V
-40
85
oC
@3.3V± 10%, loaded
88
105
@2.5V± 5% loaded
58
75
100
110
Ω
1.2
VDD - 0.9
V
Input Low Voltage
0.4
VIH-0.1
V
VIN
Input Voltage Swing
0.1
VDD
V
VDIFF_IN
Differential Input Swing
0.2
VREF-AC
Output Reference Voltage
VDD -1.5
mA
V
VDD -1.3
VDD -1.15
V
LVCMOS/LVTTL DC Characteristics (TA = -40oC to +85oC, VDD = 2.5V ±5% to 3.3V ±10%)
Symbol
Parameter
VIH
Input High Voltage
2.0
VDD
VIL
Input Low Voltage
0
0.8
IIH
Input High Current
-125
20
IIL
Input Low Current
-300
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Conditions
3
Min
Typ
Max
Units
V
μA
μA
PI6C5922504 Rev A
08/14/2014
PI6C5922504
2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
LVDS DC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, 2.5V ±5% )
Symbol
Parameter
VOUT
Min
Typ
Max
Units
Output Voltage Swing
250
325
400
mV
Differential Output Voltage Swing
500
650
800
mV
VOCM
Output Common Mode Voltage
1.15
1.35
V
Delta
VOCM
Change in Common mode Voltage
-100
100
mV
VDIFF_
OUT
Conditions
AC Characteristics (TA = -40oC to +85oC, VDD = 3.3V ±10%, 2.5V ±5%)
Symbol
Parameter
fmax
Output Frequency
tpd
Propagation Delay
Tsk
Conditions
Min
Typ
Max
Units
2.5
Output-to-output Skew(2)
GHz
VIN < 400mV
370
470
570
VIN ≥ 400mV
300
410
500
Device to Device skew
ps
20
ps
200
ps
Ts
Setup time
150
ps
Th
Hold time
150
ps
tr/tf
Output Rise/Fall time
todc
Output duty cycle
VPP
tj
20% - 80%
55
200
ps
f ≤ 1 GHz
48
52
%
1 GHz ≤ f < 2.5 GHz
40
60
%
Output Swing
LVDS outputs
250
800
mV
Buffer additive jitter RMS
156.25MHz with 12KHz
to 20MHz integration
range(3)
30
fs
Notes:
1. Measured from the differential input to the differential output crossing point
2. Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing point
3. Input source phase noise similar to phase noise plot in page 5
Thermal Information
Symbol
Description
ΘJA
Junction-to-ambient thermal resistance
ΘJC
Junction-to-case thermal resistance
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Condition
Still air
57.7 °C/W
32.2 °C/W
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Phase Noise Plots
Configuration Test Load Board Termination for LVDS Outputs
LVDS Buffer
VCC
Z o = 50
L = 0 ~ 10 in.
100
Z o = 50
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Output Swing vs Frequency
Propagation Delay vs Temperature
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Application information
Suggest for Unused Inputs and Outputs
LVCMOS Input Control Pins
Differential Clock Trace Routing
It is suggested to add pull-up=4.7k and pull-down=1k for LVCMOS pins even though they have internal pull-up/down but
with much higher value (>=50k) for higher design reliability.
Always route differential signals symmetrically, make sure
there is enough keep-out space to the adjacent trace (>20mil.). In
156.25MHz XO drives IC example, it is better routing differential trace on component side as the following Fig. 2.
REF_IN=/ REF_IN- Input Pins
They can be left floating if unused. For added reliability, connect
1kΩ to GND.
GND
Keep out board vias
VDD
150
2
3
4
GND
Outputs
All unused outputs are suggested to be left open and not connected to any trace. This can lower the IC power supply power.
156.25M XO
*100 is optional if IC has
VDD Pin Decoupling
As general design rule, each VDD pin must have a 0.1uF decoupling capacitor. For better decoupling, 1uF can be used. Locating the decoupling capacitor on the component side has better
decoupling filter result as shown in Fig. 1.
VDD
VDD
REF_INVDD
Clock IC Device
manual routing. Some good practices are to use minimum vias (total trace vias count <4), use independent layers with good reference
plane and keep other signal traces away from clock traces (>20mil.)
etc.
0.1uF
11 VDD
0.1uF
REF_IN+
Clock timing is the most important component in PCB design, so
its trace routing must be planned and routed as a first priority in
13
12
5
GND
Fig 2: IC routing for XO drive
14
GND
150
*100
6
Power Decoupling & Routing
GND
0.1uf
GND
10
9
8
Decouple cap.
on comp. side
Clock IC Device
Fig 1: Placement of Decoupling caps
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
LVPECL and LVDS Input Interface
LVPECL and LVDS DC Input
HCSL AC-Coupled Input
LVPECL and LVDS clock input to this IC is connected as shown
in the Fig. 3.
It is suggested to use AC coupling to buffer PCIe HCSL 100MHz
clock since its V_cm is relatively low at about 0.4V, as shown in
Fig. 6.
REF_IN+
50
*150
Zo =100
REF_IN-
*150
33
33
VTH
LVPECL Drive
VREF-AC
*150 removed for LVDS
REF_IN+
50
50
HCSL
50
0.01u
Zo =100
REF_IN-
0.01u
50
+ -
VDD
VTH
0.01uf
PCIe Ref_CLK
Device IC
Device IC
Fig 6: HCSL AC-Coupled Input Interface
LVPECL and LVDS AC Input
LVPECL and LVDS AC drive to this clock IC requires the use of
the VREF-AC output to recover the DC bias for the IC input as
shown in Fig. 4
0.01u
CMOS Clock DC Drive Input
LVCMOS clock has voltage Voh levels such as 3.3V, 2.5V, 1.8V.
CMOS drive requires a Vcm design at the input: Vcm= ½
(CMOS V) as shown in Fig. 7. Rs =22 ~33ohm typically.
REF_IN+
50
0.01u
+ -
VREF-AC
Fig 3: LVPECL/ LVDS Input
*150
50
Zo =100
REF_IN-
*150
VDD
LVPECL Drive
VTH
0.01uf
Rs
50
+ CMOS Driver
VREF-AC
*150 removed for LVDS
Zo
REF_IN+
Ro
VDD
3.3V
3.3V, 2.5V, 1.8V
Device IC
Fig 4: LVPECL/ LVDS AC Coupled Input
REF_INVcm
Rup
0.1u
Rdn
Diff. Input
VTH
Vcm design
CML AC-Coupled Input
CMOS V
CML AC-coupled drive requires a connection to VREF-AC as
shown in Fig. 5. The CML DC drive is not recommended as
different vendors have different CML DC voltage level. CML
is mostly used in AC coupled drive configuration for data and
clock signals.
Rup
Rdn
VREF-AC
Vcm
3.3V
1k
1k
1.65V
2.5V
1k
610
1.25V
1.8V
1k
380
0.9V
Fig 7: CMOS DC Input Vcm Design
REF_IN+
0.01u
50
CML
0.01u
Zo =100
REF_IN-
VDD
CML AC-Coupled
VTH
0.01uf
50
+ -
VREF-AC
Device IC
Fig 5: CML AC-Coupled Input Interface
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Device LVPECL Output Terminations
LVPECL Output Popular Termination
LVPECL Output AC Thevenin Termination
The most popular LVPECL termination is 150ohm pull-down
bias and 100ohm across at RX side. Please consult ASIC datasheet if it already has 100ohm or equivalent internal termination. If so, do not connect external 100ohm across as shown in
Fig. 8. This popular termination’s advantage is that it does not
allow any bias through from VDD. This prevents VDD system
noise coupling onto clock trace.
LVPECL AC Thevenin terminations require a 150ohm pulldown before the AC coupling capacitor at the source as shown
in Fig. 10. Note that pull-up/down resistor value is swapped
compared to Fig. 9. This circuit is good for short trace (<5in.)
application only.
Fig. 10 LVPECL Output AC Thenvenin Termination
Fig. 8 LVPECL Output Popular Termination
LVPECL Output Drive HCSL Input
LVPECL Output Thevenin Termination
Using the LVPECL output to drive a HCSL input can be done
using a typical LVPECL AC Thenvenin termination scheme.
Use pull-up/down 450/60ohm to generate Vcm=0.4V for the
HCSL input clock. This termination is equivalent to 50Ohm
load as shown in Fig. 11.
Fig. 9 shows LVPECL output Thevenin termination which is
used for shorter trace drive (<5in.), but it takes VDD bias current
and VDD noise can get onto clock trace. It also requires more
component count. So it is seldom used today.
Fig. 9 LVPECL Thevenin Output Termination
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Fig. 11 LVPECL Output Drive HCSL Termination
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
LVPECL Output V_swing Adjustment
It is suggested to add another cross 100ohm at TX side to tune
the LVPECL output V_swing without changing the optimal
150ohm pull-down bias in Fig. 12. This form of double termination can reduce the V_swing in ½ of the original at the RX side.
By fine tuning the 100ohm resistor at the TX side with larger
values like 150 to 200ohm, one can increase the V_swing by >
1/2 ratio.
Device Thermal Calculation
Fig. 13 shows the JEDEC thermal model in a 4-layer PCB.
Fig. 13 JEDEC IC Thermal Model
Important factors to influence device operating temperature are:
1) The power dissipation from the chip (P_chip) is after subtracting power dissipation from external loads. Generally it can be
the no-load device Idd
Fig. 12 LVPECL Output V_swing Adjustment
2) Package type and PCB stack-up structure, for example, 1oz
4 layer board. PCB with more layers and are thicker has better
heat dissipation
Clock Jitter Definitions
3) Chassis air flow and cooling mechanism. More air flow M/s
and adding heat sink on device can reduce device final die junction temperature Tj
Total jitter= RJ + DJ
Random Jitter (RJ) is unpredictable and unbounded timing noise
that can fit in a Gaussian math distribution in RMS. RJ test values are directly related with how long or how many test samples
are available. Deterministic Jitter (DJ) is timing jitter that is predictable and periodic in fixed interference frequency. Total Jitter
(TJ) is the combination of random jitter and deterministic jitter:
, where is a factor based on total test sample count. JEDEC std.
specifies digital clock TJ in 10k random samples.
The individual device thermal calculation formula:
Tj =Ta + Pchip x Ja
Tc = Tj - Pchip x Jc
Ja ___ Package thermal resistance from die to the ambient air
in C/W unit; This data is provided in JEDEC model simulation.
An air flow of 1m/s will reduce Ja (still air) by 20~30%
Jc ___ Package thermal resistance from die to the package case
in C/W unit
Phase Jitter
Phase noise is short-term random noise attached on the clock
carrier and it is a function of the clock offset from the carrier, for example dBc/Hz@10kHz which is phase noise power
in 1-Hz normalized bandwidth vs. the carrier power @10kHz
offset. Integration of phase noise in plot over a given frequency
band yields RMS phase jitter, for example, to specify phase jitter
<=1ps at 12k to 20MHz offset band as SONET standard specification.
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Tj ___ Die junction temperature in C (industry limit <125C
max.)
Ta ___ Ambiant air température in C
Tc ___ Package case temperature in C
Pchip___ IC actually consumes power through Iee/GND current
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Thermal calculation example
To calculate Tj and Tc of PI6CV304 in an SOIC-8 package:
Step 1: Go to Pericom web to find Ja=157 C/W, Jc=42 C/W
http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics/
Step 2: Go to device datasheet to find Idd=40mA max.
Step 3: P_total= 3.3Vx40mA=0.132W
Step 4: If Ta=85C
Tj= 85 + Ja xP_total= 85+25.9 = 105.7C
Tc= Tj + Jc xP_total= 105.7- 5.54 = 100.1C
Note:
The above calculation is directly using Idd current without subtracting the load power, so it is a conservative estimation. For
more precise thermal calculation, use P_unload or P_chip from
device Iee or GND current to calculate Tj, especially for LVPECL
buffer ICs that have a 150ohm pull-down and equivalent 100ohm
differential RX load.
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2.5 GHz 1:4 LVDS Fanout Buffer with Internal Termination
Packaging Mechanical: 16-pin TQFN (ZH)
Ordering Information(1,2,3)
Ordering Code
Package Code
Package Description
PI6C5922504ZHIE
ZH
Pb-free & Green, 16-pin QFN
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free & Green
3. X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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