ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS889832 is a high speed 1-to-4 DifferentialICS to-LVDS Fanout Buffer and is a member of the HiPerClockS™ HiPerClockS™ family of high performance clock solutions from IDT. The ICS889832 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF _AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889832 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in spaceconstrained applications. • Four differential LVDS outputs • IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, SSTL • 50Ω internal input termination to VT • Output frequency: >2GHz • Output skew: 25ps (maximum) • Part-to-part skew: 200ps (maximum) • Additive phase jitter, RMS: <0.2ps (typical) • Propagation delay: 510ps (maximum) • 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages 16 15 14 13 12 IN nQ0 nQ1 2 11 VT Q2 3 10 VREF_AC nQ2 4 Q2 EN 7 8 nIN ICS889832 nQ2 D 6 EN 50Ω nIN 9 5 VDD nQ1 nQ3 50Ω VREF_AC GND Q1 1 Q1 VT VDD Q0 Q3 IN Q0 PIN ASSIGNMENT nQ0 BLOCK DIAGRAM 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View Q Q3 nQ3 IDT ™ / ICS™ LVDS FANOUT BUFFER 1 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q1, nQ1 Type Description Output Differential output pair. LVDS interface levels. 3, 4 Q2, nQ2 Output Differential output pair. LVDS interface levels. 5, 6 Q3, nQ3 Output Differential output pair. LVDS interface levels. 7, 14 VDD Power 8 EN Input 9 nIN Input Positive supply pins. Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ outputs will go HIGH on the next LOW transition at IN inputs. Input threshold is VDD/2V. Includes a 37kΩ pull-up resistor. Default state is HIGH when left floating. The internal latch is clocked on the falling edge of the input signal IN. LVTTL / LVCMOS interface levels. Inver ting differential clock input. 50Ω internal input termination to VT. 10 VREF_AC Output Pullup Reference voltage for AC-coupled applications. 11 VT Input Termination input. 12 IN Input Non-inver ting differential clock input. 50Ω internal input termination to VT. 13 GND Power Power supply ground. 15, 16 Q0, nQ0 Output Differential output pair. LVDS interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLUP Input Pullup Resistor IDT ™ / ICS™ LVDS FANOUT BUFFER Test Conditions Minimum Typical 37 2 Maximum Units kΩ ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Input Outputs EN Q0:Q3 nQ0:nQ3 0 Disabled; LOW Disabled; HIGH 1 Enabled Enabled After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. EN VDD/2 VDD/2 tS tH nIN IN nQx VIN → ← tPD VOUT Swing Qx FIGURE 1. EN TIMING DIAGRAM TABLE 3B. TRUTH TABLE Inputs IN nI N Outputs EN Q0:Q3 nQ0:nQ3 0 1 1 0 1 1 0 1 1 0 X X 0 0(NOTE1) 1(NOTE1) NOTE 1: On next negative transition of the input signal (IN). IDT ™ / ICS™ LVDS FANOUT BUFFER 3 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute 4.6V Maximum Ratings may cause permanent damage to the Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA those listed in the DC Characteristics or AC Characteristics is not Input Current, IN, nIN ±50mA tended periods may affect product reliability. VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond implied. Exposure to absolute maximum rating conditions for ex- (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 120 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current EN VDD = VIN = 2.625V IIL Input Low Current EN VDD = 2.625V, VIN = 0V Minimum Typical Maximum Units 1.7 VDD + 0.3 V 0 0.7 V 5 µA -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter RIN Differential Input Resistance (IN, nIN) Test Conditions Minimum Typical Maximum Units IN-to-VT 40 50 60 Ω VIH Input High Voltage (IN, nIN) 1.2 VDD V VIL Input Low Voltage (IN, nIN) 0 VIH - 0.15 V VIN Input Voltage Swing 0.15 2.8 V VREF_AC Reference Voltage VDIFF_IN Differential Input Voltage Swing IIN Input Current; NOTE 1 VDD - 1.42 0.3 (IN, nIN) VDD - 1.37 VDD - 1.32 V 3.4 V 35 mA NOTE 1: Guaranteed by design. IDT ™ / ICS™ LVDS FANOUT BUFFER 4 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 0.3 0.4 0.5 mV 50 mV 1 1.25 1.5 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter fMAX Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 t PD t sk(o) t sk(pp) t jit Condition Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Minimum Typical >2 275 Integration Range: 12kHz - 20MHz 390 GHz 510 ps 25 ps 200 ps <0.2 ps tR/tF Output Rise/Fall Time tS Clock Enable Setup Time EN to IN, nIN 300 ps tH Clock Enable Hold Time EN to IN, nIN 300 ps 20% to 80% 70 150 235 ps All parameters are measured at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVDS FANOUT BUFFER 5 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz 0 -10 Additive Phase Jitter @ 200MHz (12kHz to 20MHz) = <0.2ps (typical) -20 -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT ™ / ICS™ LVDS FANOUT BUFFER meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 6 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD SCOPE Qx VDD 2.5V±5% POWER SUPPLY + Float GND – nIN LVDS V Cross Points IN V IH IN nQx V IL GND OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy t sk(pp) t sk(o) PART-TO-PART SKEW OUTPUT SKEW nIN 80% 80% IN VOD Clock Outputs 20% 20% tR nQ0:nQ3 tF Q0:Q3 tPD OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVDS FANOUT BUFFER PROPAGATION DELAY 7 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER nIN IN t HOLD EN VDIFF_IN, VDIFF_OUT 800mV (typical) t SET-UP SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING SETUP & HOLD TIME VDD VDD 100 out ➤ VOD/∆ VOD LVDS ➤ out DC Input ➤ LVDS ➤ out DC Input VIN, VOUT 400mV (typical) out ➤ VOS/∆ VOS ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS FANOUT BUFFER OFFSET VOLTAGE SETUP 8 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION Ω TERMINATIONS INTERFACE LVPECL INPUT WITH BUILT-IN 50Ω The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1f show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven by the most common 3.3V or 2.5V driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm LVDS Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 Ω FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER 2.5V VT Zo = 50 Ohm nIN Ω FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up Receiver With Built-In 50 Ohm Ω FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY A CML DRIVER WITH Ω FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR CML DRIVER Ω PULLUP BUILT-IN 50Ω 2.5V 2.5V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 3.3V CML with Built-In Pullup IN Zo = 50 Ohm C1 IN 50 Ohm 50 Ohm VT Zo = 50 Ohm C2 VT 50 Ohm Zo = 50 Ohm nIN R5 100 - 200 Ohm REF_AC Receiver with Built-In 50Ω Receiver with Built-In 50Ω Ω FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω IDT ™ / ICS™ LVDS FANOUT BUFFER 50 Ohm nIN REF_AC R5 100 - 200 Ohm C2 Ω FIGURE 1F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY A 3.3V CML DRIVER WITH BUILT-IN PULLUP 9 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS Output All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 2.5V LVDS DRIVER TERMINATION transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. Figure 2 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line Ω 100Ω Differential Transmission Line FIGURE 2. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ LVDS FANOUT BUFFER 10 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS889832. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS889832 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. • Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 120mA = 315mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow of and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.315W * 51.5°C/W = 101.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 16-PIN VFQFN, FORCED CONVECTION θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS FANOUT BUFFER 51.5°C/W 11 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS889832 is: 206 Pin compatible with SY89832U IDT ™ / ICS™ LVDS FANOUT BUFFER 12 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ LVDS FANOUT BUFFER 13 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS889832AK 832A 16 Lead VFQFN tube -40°C to 85°C ICS889832AKT 832A 16 Lead VFQFN 2500 tape & reel -40°C to 85°C ICS889832AK TBD 16 Lead "Lead-Free" VFQFN tube -40°C to 85°C ICS889832AKT TBD 16 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS FANOUT BUFFER 14 ICS889832AK REV A SEPTEMBER 19, 2006 ICS889832 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA