PI6C485352

PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential
LVPECL Clock Multiplexer
Features
Description
ÎÎPin-to-pin compatible to ICS85352I
The PI6C485352 is a high-performance low-skew LVPECL
fanout buffer. PI6C485352 features two selectable differential
inputs and translates to twelve LVPECL output pairs. The inputs
can also be configured to single-ended with external resistor
bias circuit. The CLK input accepts LVPECL, LVDS, LVHSTL,
SSTL or HCSL signals. The PI6C485352 is ideal for differential
to LVPECL translations and/or LVPECL clock distribution.
ÎÎFMAX ≤ 500 MHz
ÎÎPropagation Delay < 4ns
ÎÎOutput-to-output skew < 100ps
ÎÎ12 pairs of differential LVPECL outputs
ÎÎSelectable differential CLK and /CLK inputs
ÎÎCLK, /CLK pair accepts LVDS, LVPECL, LVHSTL, SSTL and
Typical clock translation and distribution applications are datacommunications and telecommunications.
ÎÎSelect input accept CMOS/LVTTL levels
Applications
ÎÎ2.5V/3.3V power supply
ÎÎNetworking systems including switches and Routers
ÎÎOperating Temperature: -40°C to +85°C
ÎÎHigh frequency backplane based computing and telecom
HCSL input level
platforms
ÎÎPackaging (Pb-free & Green):
— 48-pin TQFP (FA)
Block Diagram
Pin Configuration (48-Pin TQFP)
VCCO
CLK1
/CLK1
48 47 46 45 44 43 42 41 40 39 38 37
1
36
/Q0
2
35
/Q6
Q1
3
34
Q7
/Q1
4
33
/Q7
Q2
5
32
Q8
/Q2
6
31
/Q8
Q3
7
30
Q9
/Q3
8
29
/Q9
Q4
9
28
Q10
/Q4
10
27
/Q10
Q5
11
26
Q11
/Q5
12
25
13 14 15 16 17 18 19 20 21 22 23 24
/Q11
VEE
Rev. A
Q6
VCCO
VCC
PI6C485352
SEL11
SEL10
SEL9
SEL3
SEL4
SEL5
VCC
VCCO
1
SEL8
Q0
VEE
13-0003
SEL7
1
Q11
/Q11
SEL6
0
SEL0
1
SEL1
Q0
/Q0
SEL2
CLK1
/CLK1
0
CLK0
VCDD
CLK0
/CLK0
/CLK0
SEL [0:11]
12
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Pinout Table
Pin #
Pin Name
1, 2
Q0, /Q0
3, 4
Q1, /Q1
5, 6
Q2, /Q2
7, 8
Q3, /Q3
9, 10
Q4, /Q4
11, 12
Q5, /Q5
25, 26
/Q11, Q11
27, 28
/Q10, Q10
29, 30
/Q9,Q9
31, 32
/Q8,Q8
33, 34
/Q7,Q7
35, 36
/Q6,Q6
13, 24
Type
Description
Differential LVPECL Output pairs. LVPECL interface levels
Output
Output supply pins
VCCO
37, 48
14, 23
VEE
15, 22
VCC
16, 17
SEL5, SEL4,
18, 19
SEL3, SEL9,
20, 21
SEL10, SEL11,
40, 41
42, 43
SEL8, SEL7,
SEL6, SEL0,
44, 45
SEL1, SEL2
38
Power
Ground pins
Core supply pins
Pulldown
Clock select inputs. LVCMOS/LVTTL interface
levels
CLK1
Pulldown
Non-inverting differential clock input
39
/CLK1
Pullup/Pulldown
Inverting differential clock input
46
CLK0
Pulldown
Non-inverting differential clock input
47
/CLK0
Pullup/Pulldown
Inverting differential clock input
13-0003
2
PI6C485352
Rev. A
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Symbol
Parameter
Test Condition
VCC/ VCCo
Supply Voltage
Referenced to GND
VIN
Input voltage
Referenced to GND
Outputs, IO
Surge current
TSTG
Storage temperature
θjA
Package thermal impedence
Min.
Typ.
Max.
4.6
-0.5
VCC+0.5V
-65
Units
V
100
mA
150
°C
73
°C/W
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Pin Characteristics
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Units
CIN
Input Capacitance
4
pF
Rpullup
Input Pullup Resistance
50
kΩ
Rpulldown
Input Pulldown Resistance
50
kΩ
Control Input Function Table
SELX
Selected Clock Inputs
0
CLK0, /CLK0
1
CLK1, /CLK1
13-0003
3
PI6C485352
Rev. A
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Operating Conditions
Symbol
Parameter
VCC
Test Condition
Min.
Typ.
Max.
Units
Power Supply Voltage
3.0
3.3
3.6
V
VCCO
Output Power Supply Voltage
2.375
3.6
V
TA
Ambient Temperature
-40
85
°C
IEE
Power Supply Current
200
mA
LVCMOS/LVTTL DC Characteristics (TA = -40°C to +85°C, VCC = 3.3V ±10%, VCCO = 2.5V ±5%
to 3.3V ±10%)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
VIH
Input High voltage
SEL0:SEL11
2
VCC+0.3
VIL
Input Low voltage
SEL0:SEL11
-0.3
0.8
IIH
Input High current
SEL0:SEL11
VIN = VCC = 3.6V
IIL
Input Low current
SEL0:SEL11
VIN = 0V, VCC = 3.6V
150
-5
Units
V
μA
μA
Differential DC Characteristics (TA = -40°C to +85°C, VCC = 3.3V ±10%, VCCO = 2.5V ±5% to
3.3V ±10%)
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-peak Voltage
0.15
1.3
VCMR
Common Mode Input Voltage(1)
VEE+0.5
VCC-0.85V V
VOH
Output High Voltage
VCCO = 3.3V or 2.5V
VCCO -1.4
VCCO -0.9
V
VOL
Output Low Voltage(2)
VCCO = 3.3V or 2.5V
VCCO -2.0
VCCO -1.7
V
CLK0, CLK1
VIN = VCC = 3.6V
150
μA
/CLK0, /CLK1
VIN = VCC = 3.6V
150
μA
CLK0, CLK1
VCC = 3.6V, VIN = 0V
-5
μA
/CLK0, /CLK1
VCC = 3.6V, VIN = 0V
-150
μA
(2)
V
Note:
1. Outputs terminated with 50Ω to VCCO -2.0V
13-0003
4
PI6C485352
Rev. A
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
AC Characteristics (TA = -40°C to +85°C, VCC = 3.3V ±10%, VCCO = 2.5V ±5% to 3.3V ±10%)
Parameter
Description
Conditions
fmax
Output Frequency
tpd
Propagation Delay
Tsk
Min.
Typ.
Max.
Units
500
MHz
4
ns
Output-to-output Skew(2)
100
ps
Tskpp
Part-to-part Skew
500
ps
tr/tf
Output Rise/Fall time
150
700
ps
odc
Output duty cycle
45
55
%
Tj
Buffer additive jitter RMS
(1)
(3)
20% - 80%
0.05
ps
Note:
1.Measured from the differential input to the differential output crossing point
2 Defined as skew between outputs at the same supply voltage and with equal loads. Measured at the output differential crossing
point.
3. Defined as skew between outputs on different parts operating at the same supply voltage and with equal loads. Measured at the
outputs differential crossing point.
13-0003
5
PI6C485352
Rev. A
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Applications Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single-ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be placed as close as possible to the input pin. The ratio of R1 and
R2 should be adjusted to postion the V_REF at the center of the input voltage swing. For example, if the input clock swing is 2.5V
and VCC = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VCC
R1
1KΩ
Single Ended
Clock Input
CLK1
V_REF
C1
0.1μF
nCLK1
R2
1KΩ
Figure 1: Single-ended Signal Driving Differential Input
13-0003
6
PI6C485352
Rev. A
01/24/13
PI6C485352
2.5V/3.3V, 500 MHz Twelve 2-to-1 Differential LVPECL Clock Multiplexer
Packaging Mechanical: 48-Pin TQFP (FA)
1
DATE: 02/16/06
Notes:
1) All dimensions are in millimeters, Angles in Degrees
2) Ref JEDEC: MO-026D, variation ABC
3) Dimensions do not include mold protrusion
DESCRIPTION: 48-pin Thin Quad Flat Package (TQFP)
PACKAGE CODE: FA48
REVISION: - -
DOCUMENT CONTROL #: PD-2056
06-0182
Ordering Information
Ordering Number
Package Code
Package Description
PI6C485352FAE
FA
Pb-free & Green, 48-pin, 276-mil wide TQFP
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
13-0003
7
PI6C485352
Rev. A
01/24/13