PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Features Description ÎÎ25MHz crystal or reference clock input The PI6CFGL601B is a 6-output low-power 100MHz clock sythesizer for PCIe Gen 1-2-3. It runs from a 25MHz XTAL, provides spread spectrum capability, and has an SMBus for software control of the device. ÎÎ100MHz low power HCSL or LVDS compatible outputs ÎÎPCIe 3.0, 2.0 and 1.0 compliant ÎÎSelectable spread spectrum of -0.5% and no spread Application ÎÎProgrammable output amplitude ÎÎPCIe 3.0/2.0/1.0 clock generation ÎÎCycle-to-cycle jitter (typ.) ~ 30ps ÎÎSupply voltage of 3.3V+/-10% XTAL_OUT GND VDD NC GND 32-TQFN VDD ÎÎAvailable in lead-free package: NC ÎÎIndustrial ambient operating temperature XTAL_IN Pin Configuration ÎÎOutput supply voltage of 1.8V 32 31 30 29 28 27 26 25 NC 1 VDD 2 24 SDATA 23 SCLK NC 3 22 GND GND 4 21 CLK_5 GND 5 20 CLK_5# CLK_0 6 CLK_0# 7 18 CLK_4 17 CLK_4# CLK_3 CLK_3# VDDO1.8 GND CLK_2# CLK_2 CLK_1# 9 10 11 12 13 14 15 16 CLK_1 VDDO1.8 8 19 VDDO1.8 Block Diagram XTAL_IN or Ref CLK OSC XTAL_OUT - I+ + PROGRAMMABLE SPREAD PLL t STOP LOGIC 6 + CLK(5:0) 100MHz u CONTROL LOGIC SDATA SCLK All trademarks are property of their respective owners. 15-0018 1 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Pin Description Pin # Pin Name Type Description 1 NC N/A No Connection. 2 VDD Power Power supply, nominal 3.3V 3 NC N/A No Connection. 4 GND Power Ground pin. 5 GND Power Ground pin. 6 CLK_0 Output 0.7V differential true clock output, LOW when output is disabled. 7 CLK_0# Output 0.7V differential Complementary clock output, LOW when output is disabled. 8 VDDO1.8 Power Power supply for outputs, nominally 1.8V, range 1.05 to 3.3V 9 CLK_1 Output 0.7V differential true clock output, LOW when output is disabled. 10 CLK_1# Output 0.7V differential Complementary clock output, LOW when output is disabled. 11 CLK_2 Output 0.7V differential true clock output, LOW when output is disabled. 12 CLK_2# Output 0.7V differential Complementary clock output, LOW when output is disabled. 13 GND Power Ground pin. 14 VDDO1.8 Power Power supply for outputs, nominally 1.8V, range 1.05 to 3.3V 15 CLK_3# Output 0.7V differential Complementary clock output, LOW when output is disabled. 16 CLK_3 Output 0.7V differential true clock output, LOW when output is disabled. 17 CLK_4# Output 0.7V differential Complementary clock output, LOW when output is disabled. 18 CLK_4 Output 0.7V differential true clock output, LOW when output is disabled. 19 VDDO1.8 Power Power supply for outputs, nominally 1.8V, range 1.05 to 3.3V 20 CLK_5# Output 0.7V differential Complementary clock output, LOW when output is disabled. 21 CLK_5 Output 0.7V differential true clock output, LOW when output is disabled. 22 GND Power Ground pin. 23 SCLK Input Clock pin of SMBUS circuitry, 5V tolerant 24 SDATA Input/output Data pin of SMBUS circuitry, 5V tolerant 25 XTAL_OUT Output Crystal output, Nominally 25.00MHz. 26 XTAL_IN Input Crystal input or reference input clock, Nominally 25.00MHz. 27 GND Power Ground pin. 28 NC N/A No Connection. 29 VDD Power Power supply, nominal 3.3V 30 NC N/A No Connection. 31 GND Power Ground pin. 32 VDD Power Power supply, nominal 3.3V All trademarks are property of their respective owners. 15-0018 2 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Serial Data Interface (SMBus) This part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as shown below. Read and write block transfers can be stopped after any complete byte transfer by issuing STOP. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 0 1 0/1 Data Protocol (Write) 1 bit 8 bits 1 8 bits 1 Start bit Slave Addr: D2 Ack Register offset Ack 8 bits 1 8 bits 1 8 bits Byte Count=N Ack Data Byte 0 Ack … 1 1 bit Data Ack Stop bit Byte N-1 (Read) 1 bit Start bit 8 bits 1 8 bits 1 1 8 bits 1 8 bits 1 8 bits 1 Slave Register Repeat Slave Byte Data Ack Ack Ack Ack Ack … Addr: D2 offset start Addr: D3 Count=N Byte 0 8 bits 1 1 bit Data Byte N-1 NOT Ack Stop bit Note: 1.Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. All trademarks are property of their respective owners. 15-0018 3 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator SMBus Table: Device Control Register, READ/WRITE ADDRESS (D2/D3) BYTE 0 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Spread Enable 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 R/W Off -0.50% 1 SMBus Table: Output Enable Register BYTE 1 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 CLK_0 OE 5 Reserved 0 4 Reserved 0 3 CLK_1 OE 2 Reserved 0 1 Reserved 0 0 Reserved 0 Output Enable R/W Output Enable R/W Disable Disable Enable Enable 1 1 SMBus Table: Reserved Register BYTE 2 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 All trademarks are property of their respective owners. 15-0018 4 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator SMBus Table: Output Enable Register BYTE 3 Bit Pin# Name Control Function Type 0 1 Default 7 CLK_5 OE Output Enable R/W Disable Enable 1 6 CLK_4 OE Output Enable R/W Disable Enable 1 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 SMBus Table: Reserved Register BYTE 4 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 SMBus Table: Output amplitude adjustment BYTE 5 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 0 R/W CLK_0/1/2/3/4/5 Amplitude adjustment AMP All trademarks are property of their respective owners. 15-0018 R/W 5 00=700mV 01=800mV 10=900mV 11=1000mV 0 1 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator SMBus Table: Reserved Register BYTE 6 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 SMBus Table: Vendor & Revision ID Register BYTE 7 Bit Pin# Name 7 RID3 6 RID2 5 RID1 4 Control Function Type 0 1 Default R 0 R 0 R 0 RID0 R 0 3 VID3 R 0 2 VID2 R 0 1 VID1 R 0 0 VID0 R 0 REVISION ID VENDOR ID SMBus Table: Reserved Register BYTE 8 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 0 6 Reserved 0 5 Reserved 0 4 Reserved 0 3 Reserved 1 2 Reserved 1 1 Reserved 1 0 Reserved 1 All trademarks are property of their respective owners. 15-0018 6 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator SMBus Table: Output Enable Register BYTE 9 Bit Pin# Name Control Function Type 0 1 Default 7 Reserved 6 CLK_3 OE Output Enable R/W Disable Enable 1 5 CLK_2 OE Output Enable R/W Disable Enable 1 4 Reserved 0 3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 All trademarks are property of their respective owners. 0 15-0018 7 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential.......................................................4.6V All Inputs and Output....................................................-0.5V to VDD +0.5V Ambient Operating Temperature........................................-40°C to +85oC Storage Temperature........................................................... –65°C to +150°C Juction Temperature ............................................................................. 125°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Soldering Temperature.......................................................................... 260°C ESD Protection (Input).......................................................... 2000V (HBM) Electrical Characteristics–Current Consumption TA = -40~85oC; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for loading conditions Symbol Parameters Condition IDD3.3 Operating Supply Current 1 Min. VDD, All outputs active @100MHz Typ. Max. Units 50 65 mA Notes: 1. Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics TA = -40~85oC; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions Symbol Parameters tDC Duty Cycle1 tskew Skew, Output to Output tjcyc-cyc Jitter, Cycle to cycle 1 1,2 Condition Min. Measured differentially, PLL Mode 45 Typ. Max. Units 55 % VT = 50% 50 ps PLL mode 50 ps Notes: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Measured from differential waveform Electrical Characteristics–Input/Supply/Common Output Parameters TA = -40~85oC; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10% Symbol Parameters Condition Min. Typ. Max. Units VDD Supply Voltage1 Supply voltage for core, analog 3.0 3.3 3.6 V VDDO Supply Voltage1 Supply voltage outputs 1.65 1.8 2.0 V VIH Input High Voltage Single-ended inputs, except SMBus 0.65 VDD VDD +0.3 V VIL Input Low Voltage Single-ended inputs, except SMBus -0.3 0.35 VDD V VOH Output High Voltage1 Single-ended outputs, except SMBus. IOH = -2mA VDD -0.45 VOL Outputt Low Voltage1 Single-ended outputs, except SMBus. IOL = -2mA 1 1 All trademarks are property of their respective owners. 15-0018 8 V 0.45 V PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Symbol Parameters IIN Condition Min. Single-ended inputs, VIN = GND, VIN = VDD (exclude XTAL_IN pin) Typ. Max. Units -5 5 uA -200 200 uA -40 85 °C Single-ended inputs Input Current1 VIN = 0 V; Inputs with internal pull-up resistors IINP VIN = VDD; Inputs with internal pull-down resistors Tind Ambient Operating Temperature1 Fin Input Frequency1 Lpin Pin Inductance XTAL_IN 25.000 nH 5 pF Crystal inputs 6 pF Output pin capacitance 6 pF 1.8 ms 33 kHz Logic Inputs Capacitance 1 COUT MHz 7 1 CIN CINXTAL Industrial range 1.5 TSTAB Clk Stabilization1,2 From VDD Power-Up and after input clock stabilization to 1st clock f MODIN SS Modulation Frequency1 Allowable Frequency (Triangular Modulation) tF Tfall1,2 Fall time of control inputs 5 ns tR Trise Rise time of control inputs 5 ns VILSMB SMBus Input Low Voltage1 0.8 V VIHSMB SMBus Input High Voltage1 VDDSMB V VOLSMB SMBus Output Low Voltage1 @ IPULLUP 0.4 V IPULLUP SMBus Sink Current1 @ VOL 4 VDDSMB Nominal Bus Voltage1 3V to 5V +/- 10% 2.7 tRSMB SCLK/SDATA Rise Time1 tFSMB f MAXSMB 1,2 30 31.500 2.1 mA 5.5 V (Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns SCLK/SDATA Fall Time1 (Min VIH + 0.15) to (Max VIL - 0.15) 300 ns SMBus Operating Frequency1 Delay from assertion of first output enable register to first clock Maximum SMBus operating frequency 100 kHz Notes: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Control input must be monotonic from 20% to 80% of input swing. All trademarks are property of their respective owners. 15-0018 9 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Electrical Characteristics–CLK 0.7V Low Power Differential Outputs TA = -40~85oC; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for loading conditions Symbol Parameters Trf Slew rate1,2,3 ΔTrf Slew rate matching Slew rate matching, Scope averaging on VHigh Voltage High VLow Voltage Low1 Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Vmax Max Voltage1 Vmin Min Voltage1 Vswing Vswing1,2 Vcross_abs Δ-Vcross 1,2,4 1 Condition Min. Scope averaging on 1 Units 4 V/ns 20 % 850 -150 150 mV 1150 -300 Scope averaging off 300 Crossing Voltage (abs) Scope averaging off 300 Crossing Voltage (var) Scope averaging off 1,6 Max. 660 Measurement on single ended signal using absolute value. (Scope averaging off) 1,5 Typ. mV mV 550 mV 140 mV Notes: 1. Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential trace impedance). 2. Measured from differential waveform. 3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4. Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope uses for the edge rate calculations. 5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross abs. Electrical Characteristics–Phase Jitter Parameters TA = -40~85oC; Supply Voltage VDD = 3.3 V +/-10%; VDDO = 1.8V +/-10%, See Test Loads for Loading Conditions Symbol Parameters Condition tjphPCIeG1 Phase Jitter, PCI Express1,2,3,5 PCIe Gen 1 Min. PCIe Gen 2 Low Band tjphPCIeG2 Phase Jitter, PCI Express1,2,5 10kHz < f < 1.5MHz PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz) tjphPCIeG3 Phase Jitter, PCI Express1,2,4,5 PCIe Gen 3 (PLL BW of 2-4MHz, CDR = 10MHz) Typ. INDUSTRY LIMIT 27 86 0.5 3 2.1 3.1 0.5 1 Units ps (p-p) ps (rms) ps (rms) ps (rms) Notes: 1. Guaranteed by design and characterization, not 100% tested in production. 2. See http://www.pcisig.com for complete specs. 3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4. Calculated from Intel-supplied Clock Jitter Tool. 5. Applies to all different outputs. All trademarks are property of their respective owners. 15-0018 10 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs = 33Ω Zo=100Ω Rs = 33Ω 2pF 2pF Device RO Driving LVDS 3.3V Driving LVDS R7a R7b R8a R8b Cc Rs Rs Zo Cc Device LVDS Clock input R Driving LVDS inputs with the PI6CFGL601B Value Component Receiver has termination Receiver does not have termination R7a, R7b 10K Ω 140 Ω R8a, R8b 5.6K Ω 75 Ω Cc 0.1 uF 0.1 uF Vcm 1.2 V 1.2 V All trademarks are property of their respective owners. 15-0018 11 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Application Notes Crystal circuit connection The following diagram shows crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 27pF SaRonix-eCera FL2500047 Crystal�(CL�=�18pF) XTAL_OUT C2 27pF ASIC X1 CL= crystal spec. loading cap. X2 Cj Cj = chip in/output cap. (3~5pF) Cj Cb = PCB trace/via cap. (2~4pF) Cb Rf C1 Pseudo sine C1,2 = load cap. components Rd Cb Rd = drive level res. (100Ω) C2 Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF Recommended Crystal Specification Pericom recommends: a) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf All trademarks are property of their respective owners. 15-0018 12 PI6CFGL601BRevA 01/16/15 PI6CFGL601B 6-Output Low Power PCIE Gen 1-2-3 Clock Generator Packaging Mechanical: 32-Pin TQFN (ZH) Notes: 1. All dimensions are in mm. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area (mesh stencile design is recommended) DATE: 06/30/11 DESCRIPTION: 32-contact, Thin Quad Flat No-Lead (TQFN) PACKAGE CODE: ZH32 DOCUMENT CONTROL #: PD-2070 REVISION: B 11-0147 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information(1-3) Ordering Code PI6CFGL601BZHIE Package Code ZH Package Description 32-contact, Thin Quad Flat No-Lead (TQFN) Notes: 1. 1Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 All trademarks are property of their respective owners. 15-0018 13 PI6CFGL601BRevA 01/16/15