PI6C557-03

PI6C557-03
PCI Express Clock
Product Features
Description
ÎÎLVDS compatible outputs
The PI6C557-03 is a spread spectrum clock generator
supporting PCI Express and Ethernet requirements. The device
is used for PC or embedded systems to substantially reduce
Electromagnetic Interference (EMI).
ÎÎSupply voltage of 3.3V ±10%
ÎÎ25MHz input frequency
ÎÎHCSL outputs, 0.7V Current mode differential pair
The PI6C557-03 provides two differential (HCSL) spread spectrum
outputs. The PI6C557-03 is configured to select spread and clock
selection. Using Pericom's patented Phase-Locked Loop (PLL)
techniques, the device takes a 25MHz crystal input and produces
two pairs of differential outputs (HCSL) at 25MHz, 100MHz,
125MHz and 200MHz clock frequencies. It also provides spread
selection of ±0.25%, -0.5%, -0.75%, and no spread.
ÎÎJitter 60ps cycle-to-cycle (typ)
ÎÎSpread of ±0.25%, -0.5%, -0.75%, and no spread
ÎÎIndustrial temperature range
ÎÎPackaging: (Pb-free and Green)
àà 16-pin, 173 mils wide TSSOP
Block Diagram
VDD
2
SS1:SS0
S1:S0
CLK0
2
Control
Logic
2
CLK0
Phase Lock Loop
CLK1
X1/CLK
CLK1
Crystal
Driver
25 MHz
crystal or clock X2
2
Pulling
Capacitors
RR
GND
OE
Pin Configuration
12-0307
S0
1
16
VDDX
S1
2
15
CLK0
SS0
3
14
CLK0
X1/CLK
4
13
GNDA
X2
5
12
VDDA
OE
6
11
CLK1
GNDX
7
10
CLK1
SS1
8
9
IREF
1
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01/04/13
PI6C557-03
PCI Express Clock
Pin Description
Pin #
Pin Name
I/O Type
Description
1
S0
Input
Select pin 0 (Internal pull-up resistor). See Table 1.
2
S1
Input
Select pin 1 (Internal pull-up resistor). See Table 1.
3
SS0
Input
Spread Select pin 0 (Internal pull-up resistor). See Table 2.
4
X1/CLK
Input
Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
5
X2
Output
6
OE
Input
Output enable. Internal pull-up resistor.
7
GNDX
Power
Crystal ground pin.
8
SS1
Input
Spread Select pin 1 (Internal pull-up resistor). See Table 2.
9
IREF
Output
Precision resistor attached to this pin is connected to the internal current reference.
10
CLK1
Output
HCSL compliment clock output
11
CLK1
Output
HCSL clock output
12
VDDA
Power
Connect to a +3.3V source.
13
GNDA
Power
Output and analog circuit ground.
14
CLK0
Output
HCSL compliment clock output
15
CLK0
Output
HCSL clock output
16
VDDX
Power
Connect to a +3.3V source.
Crystal connection. Leave unconnected for clock input.
Table 2: Spread Selection Table
Table 1: Output Select Table
S1
S0
CLK(MHz)
SS1
SS0
Spread
0
0
25
0
0
Center ±0.25
0
1
100
0
1
Down -0.5
1
0
125
1
0
Down -0.75
1
1
200
1
1
No Spread
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01/04/13
PI6C557-03
PCI Express Clock
Output Structures
Application Information
Decoupling Capacitors
Decoupling capacitors of 0.01μF should be connected between
each VDD pin and the ground plane and placed as close to the
VDD pin as possible.
IREF =2.3mA
6*IREF
Crystal
Use a 25MHz fundamental mode parallel resonant crystal with
less than 300PPM of error across temperature.
Crystal Capacitors
CL = Crystals's load capacitance in pF
Crystal Capacitors (pF) = (CL - 8) *2
R R=475 Ω
See Output Termination
Sections
For example, for a crystal with 16pF load caps, the external effective crystal cap would be 16 pF. (16-8)*2=16.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance is 50Ω,
then R R = 475Ω providing an IREF of 2.32 mA. The output
current (IOH) is 6*IREF.
Output Termination
The PCI Express differential clock outputs of the PI6C557-03
are open source drivers and require an external series resistor
and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI Express Layout
Guidelines section.
The PI6C557-03 can be configured for LVDS compatible voltage
levels. See the LVDS Compatible Layout Guidelines section.
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PI6C557-03
PCI Express Clock
PCI Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, route as non-coupled 50Ω trace.
0.5 max
inch
L2 length, route as non-coupled 50Ω trace.
0.2 max
inch
L3 length, route as non-coupled 50Ω trace.
0.2 max
inch
RS
33
Ω
RT
49.9
Ω
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, route as coupled microstrip 100Ω differential trace.
2 min to 16 max
inch
L4 length, route as coupled stripline 100Ω differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express connector
Dimension or Value
Unit
L4 length, route as coupled microstrip 100Ω differential trace.
0.25 min to 14 max
inch
L4 length, route as coupled stripline 100Ω differential trace.
0.225 min to 12.6 max
inch
PCI Express Device Routing
L1
L2
RS
L1’
L4
L4’
L2’
RS
RT
PI6C557-03
Output
Clock
L3’
RT
PCI-Express
Load or
Connector
L3
Typical PCI Express (HCSL) Waveform
700 mV
0
tOR
0.52 V
0.175 V
12-0307
500 ps
500 ps
tOF
0.52 V
0.175 V
4
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01/04/13
PI6C557-03
PCI Express Clock
Application Information
LVDS Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, route as non-coupled 50Ω trace.
0.5 max
inch
L2 length, route as non-coupled 50Ω trace.
0.2 max
inch
RP
100
Ω
RQ
100
Ω
RT
150
Ω
L3 length, route as 100Ω differential trace.
L3 length, route as 100Ω differential trace.
LVDS Device Routing
L1
L3
RQ
L3’
L1’
RT
PI6C557-03
Clock
Output
RP
RT
L2’
L2
LVDS
Device
Load
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
1250 mV
1150 mV
12-0307
500 ps
tOF
1250 mV
1150 mV
5
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01/04/13
PI6C557-03
PCI Express Clock
Electrical Specifications
Maximum Ratings
Supply Voltage to Ground Potential............................................................5.5V
All Inputs and Outputs...................................................... -0.5V to VDD+0.5V
Ambient Operating Temperature..................................................-40 to +85°C
Storage Temperature......................................................................-65 to +150°C
Junction Temperature ............................................................................... 150°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Soldering Temperature .............................................................................. 260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Unit
Ambient Operating Temperature
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
DC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85°C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
3.0
3.3
3.60
V
VDD
Supply Voltage
VIH
Input High Voltage(1)
S0, S1, OE, CLK, SS0, SS1
2.0
VDD +0.3
V
VIL
Input Low Voltage(1)
S0, S1, OE, CLK, SS0, SS1
GND -0.3
0.8
V
With input pull-up
and pull-downs
-20
20
Without input pull-up
and pull-downs
-5
5
IIL
Input Leakage Current
IDD
R L = 50Ω, CL = 2pF
65
mA
IDDOE
Operating Supply
Current
OE = LOW
35
mA
CIN
Input Capacitance
Input pin capacitance
7
pF
COUT
Output Capacitance
Output pin capacitance
6
pF
LPIN
Pin Inductance
ROUT
Output Resistance
0 < Vin < VDD
µA
5
CLK Outputs
nH
3.0
kΩ
Notes:
1. Single edge is monotonic when transitioning through region.
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PI6C557-03
PCI Express Clock
AC Characteristics (VDD = 3.3V ±10%, TA = -40°C to +85oC)
Symbol
Parameter
Conditions
FIN
Input Frequency
VOUT
Output Frequency
VOH
Output High Voltage (1,2)
VOL
Output Low Voltage(1,2)
VCPA
Crossing Point Voltage(1,2)
Absolute
VCN
Crossing Point Voltage(1,2,4)
Variation over all edges
JCC
Jitter, Cycle-to-Cycle(1,3)
MF
tOR
Modulation Frequency
Spread Spectrum
Rise Time(1,2)
tOF
Fall Time(1,2)
∆TR /∆T
TSKEW
Rise/Fall Time Variation(1,2)
TDUTYCYCLE
Skew between outputs
Min.
Typ.
Max.
Unit
25
25
@VDD = 3.3V
660
700
-150
0
250
350
MHz
200
MHz
850
mV
mV
550
mV
140
mV
60
100
ps
30
31.5
33
kHz
From 0.175V to 0.525V
175
332
700
ps
From 0.525V to 0.175V
175
344
700
ps
125
ps
50
ps
55
%
VDD/2
Duty Cycle(1,3)
45
TOE
Output Enable Time(5)
All outputs
0.1
μs
TOT
Output Disable Time(5)
All outputs
0.1
μs
tSTABLE
From power-up to VDD=3.3V
3.0
ms
tSPREAD
Setting period after spread change
3.0
ms
Ferror
Synthesizer Error
0
ppm
1.6
PLL locked, xtal load is matched and
SSC off
Notes:
1. RL = 50Ω with CL = 2 pF and RR = 475Ω
2. Single-ended waveform
3. Differential waveform
4. Measured at the crossing point
5. CLK pins are tri-stated when OE is LOW
Thermal Characteristics
Symbol
Parameter
Conditions
θJA
Thermal Resistance Junction to Ambient
Still air
θJC
Thermal Resistance Junction to Case
Min.
Typ.
Max.
Unit
90
°C/W
24
°C/W
Recomended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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01/04/13
PI6C557-03
PCI Express Clock
Packaging Mechanical: 16-contact TSSOP (L)
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1-3)
Ordering Code
Package Code
PackageType
PI6C557-03LE
L
Pb-free & Green, 16-Pin TSSOP
Note:
1. Thermal characteristics and package top marking information can be found at http://www.pericom.com/packaging/
2. E = lead-free and green packaging
3. Adding an X suffix = tape/reel
Pericom Semiconductor Corporation • 1-800-435-2336 | All Trademarks Property of Respective Owners
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