PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Features Description ÎÎPCIe® 3.0, 2.0 and 1.0 compliant The PI6CFGL202B is a spread spectrum clock generator compliant to PCI Express® 3.0 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce Electromagnetic Interference (EMI). ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ25MHz crystal or clock input frequency ÎÎLow power consumption with independent output power The PI6CFGL202B provides two differential (HCSL) or LVDS spread spectrum outputs. The PI6CFGL202B is configured to select spread and clock selection. Using Pericom's patented PhaseLocked Loop (PLL) techniques, the device takes a 25MHz crystal input and produces two pairs of differential outputs (HCSL) at 25MHz, 100MHz, 125MHz and 200MHz clock frequencies. It also provides spread selection of -0.5%, -0.75%, and no spread. supply 1.05V to 3.3V ÎÎJitter 35ps cycle-to-cycle (typ) ÎÎSpread of -0.5%, -0.75%, and no spread ÎÎIndustrial temperature range ÎÎSpread Bypass option available ÎÎSpread and frequency selection via external pins ÎÎPackaging: (Pb-free and Green) àà 16-pin TSSOP (L16) Pin Configuration (16-Pin TSSOP) Block Diagram VDD 2 SS1:SS0 S1:S0 2 Control Logic Pulling Capacitors 1 16 VDDA3.3 CLK0 S1 2 15 CLK0 CLK0 SS0 3 14 CLK0# XTAL_IN 4 13 GNDA XTAL_OUT 5 12 VDDO OE 6 11 CLK1 GNDX 7 10 CLK1# SS1 8 9 Phase Lock Loop 2 XTAL_IN or Ref CLK 25 MHz crystal or clock XTAL_OUT S0 CLK1 CLK1 Crystal Driver 2 GND All trademarks are property of their respective owners. VDDDIG3.3 OE 15-0025 1 www.pericom.com03/03/15 3B 557-0 PI6C PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Pin Description Pin # Pin Name Type Description 1 S0 Input Select pin 0 (Internal pull-up resistor). See Table 1. 2 S1 Input Select pin 1 (Internal pull-up resistor). See Table 1. 3 SS0 Input Spread Select pin 0 (Internal pull-up resistor). See Table 2. 4 XTAL_IN Input Crystal or clock input. Connect to a 25MHz crystal or single ended clock. 5 XTAL_OUT Output Crystal connection. Leave unconnected for clock input. 6 OE Input Output enable. Internal pull-up resistor. 7 GNDX Power Crystal ground pin. 8 SS1 Input Spread Select pin 1 (Internal pull-up resistor). See Table 2. 9 VDDDIG3.3 Power 3.3V digital power. 10 CLK1# Output HCSL compliment clock output, LOW when output is disabled. 11 CLK1 Output HCSL clock output, LOW when output is disabled. 12 VDDO Power Power supply, nominal 1.8V, range1.05V~3.3V. 13 GNDA Power Output and analog circuit ground. 14 CLK0# Output HCSL compliment clock output, LOW when output is disabled. 15 CLK0 Output HCSL clock output, LOW when output is disabled. 16 VDDA3.3 Power 3.3V power supply for PLL core. Table 2: Spread Selection Table Table 1: Frequency Select Table S1 S0 CLK(MHz) SS1 SS0 Spread 0 0 25 0 0 No Spread 0 1 100 0 1 Down -0.5 1 0 125 1 0 Down -0.75 1 1 200 1 1 No Spread All trademarks are property of their respective owners. 15-0025 2 www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Test Loads Low-Power HCSL Differential Output Test Load 5 inches Rs Zo=100Ω Rs 2pF 2pF Device RO Driving LVDS 3.3V Driving LVDS R7a R7b R8a R8b Cc Rs Zo Cc Rs Device LVDS Clock input R Driving LVDS inputs with the PI6CFGL202B Value Component Receiver has termination Receiver does not have termination R7a, R7b 10K Ω 140 Ω R8a, R8b 5.6K Ω 75 Ω Cc 0.1 uF 0.1 uF 1.2 volts 1.2 volts Vcm All trademarks are property of their respective owners. 15-0025 3 www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Supply Voltage to Ground Potential.......................................................4.6V All Inputs and Output......................................................-0.5V toVDD+0.5V Ambient Operating Temperature............................................ -40 to +85°C Storage Temperature........................................................... –65°C to +150°C Junction Temperature........................................................................... 125°C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Soldering Temperature.......................................................................... 260°C ESD Protection (Input)............................................................2000V(HBM) Electrical Characteristics–Current Consumption (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters Condition Min. IDDOP Operating supply current1 Total power consumption, All outputs active @100MHz Typ. Max. Units 52 mA Notes: 1. Guaranteed by design and characterization, not 100% tested in production. Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating Conditions (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters Condition Min. Typ. Max. Units VDDX Supply Voltage1 Supply voltage for core, analog 3.0 3.3 3.6 V VDDO Supply Voltage Supply voltage outputs 1.65 1.8 2.0 V VIH Input High Voltage1 OE, S0, S1, SS0, SS1 0.65 VDD VDD + 0.3 V VIL Input Low Voltage1 OE, S0, S1, SS0, SS1 -0.3 0.35 VDD V Single-ended inputs, VIN = GND, VIN = VDD (exclude XTAL pin) -5 5 uA -200 200 uA 26 MHz 7 nH 1 IIN Single-ended inputs Input Current1 VIN = 0 V; Inputs with internal pull-up resistors IINP VIN = VDD; Inputs with internal pull-down resistors Fin Input Frequency Lpin Pin Inductance 1 CIN CINDIF_IN Capacitance 1,4 23 25 Logic Inputs, except DIF_IN 1.5 5 pF DIF_IN differential clock inputs 1.5 2.7 pF 6 pF 1 ms Output pin capacitance COUT TSTAB XTAL or X1 input 1 Clk Stabilization1,2 All trademarks are property of their respective owners. From VDD Power-Up and after input clock stabilization 15-0025 4 0.6 www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Symbol f MODIN Parameters Condition Input SS Modulation Allowable Frequency Frequency1 (Triangular Modulation) Min. Typ. Max. Units 30 31.500 33 kHz TOE Output Enable Time1 All output 10 μs tOT Output Disable Time All output 10 μs tSTABLE From Power-up to VDD =3.3V1 From Power-up VDD =3.3V 3.0 ms tSPREAD Setting period after spread change1 Setting period after spread change 3.0 ms 1 Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Control input must be monotonic from 20% to 80% of input swing. Input Frequency Capacitance 3. Time from deassertion until outputs are >200 mV 4. DIF_IN input Electrical Characteristics–CLK 0.7V Low Power HCSL Outputs (TA = -40~85oC; VDD = 3.3V+/10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters Condition Trf Slew rate VHIGH Voltage High VLOW Voltage Low1 Statistical measurement on single-ended signal using oscilloscope math function. (Scope averaging on) Vmax Max Voltage1 Measurement on single ended signal using Vmin Min Voltage absolute value. (Scope averaging off) -300 mV Vswing Vswing Scope averaging off 300 mV Vcross_abs Crossing Voltage (abs) Scope averaging off 250 Δ-Vcross Crossing Voltage (var) Scope averaging off tDC Duty Cycle tskew Skew, Output to Output tjcyc-cyc Jitter, Cycle to cycle 1,2,3 1 1 1,2 1,5 1,6 1 1,2 Typ. Max. Units 1.1 2 4.5 V/ns 660 950 mV -150 150 mV 1150 mV 550 mV 140 mV 55 % VT = 50% 50 ps PLL mode @100MHz output, SSC off 50 ps Measured differentially, PLL Mode 1 Min. 45 Note: 1. Guaranteed by design and characterization, not 100% tested in production. 2. Measured from differential waveform 3. Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around differential 0V. 4. Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5. Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6. The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. All trademarks are property of their respective owners. 15-0025 5 www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Electrical Characteristics–Phase Jitter Parameters (TA = -40~85oC; VDD = 3.3V+/-10%; VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions) Symbol Parameters tjphPCIeG1 Condition Min. PCIe Gen 11,2,3,5 PCIe Gen 2 Low Band tjphPCIeG2 Phase Jitter, PCI Express 10kHz < f < 1.5MHz1,2,5 PCIe Gen 2 High Band 1.5MHz < f < Nyquist (50MHz)1,2,5 PCIe Gen 3 tjphPCIeG3 (PLL BW of 2-4MHz, CDR = 10MHz) 1,2,4,5 Typ. Industry Limit 25 86 0.9 3 1.6 3.1 0.36 1 Units ps (p-p) ps (rms) ps (rms) ps (rms) Notes: 1. Guaranteed by design and characterization, not 100% tested in production. 2. See http://www.pcisig.com for complete specs. 3. Sample size of at least 100k cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 4. Calculated from Intel-supplied Clock Jitter Tool. 5. Applies to all different outputs. Thermal Characteristics Symbol Parameter Conditions θJA Thermal Resistance Junction to Ambient θJC Thermal Resistance Junction to Case All trademarks are property of their respective owners. 15-0025 Still air 6 Min. Typ. Max. Unit 90 °C/W 24 °C/W www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Application Notes Crystal circuit connection The following diagram shows crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggested to use C1= 27pF, C2= 27pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different board layouts. Crystal Oscillator Circuit XTAL_IN C1 27pF SaRonix-eCera FL2500047 Crystal�(CL�=�18pF) XTAL_OUT C2 27pF ASIC X1 CL= crystal spec. loading cap. X2 Cj Cj = chip in/output cap. (3~5pF) Cj Cb = PCB trace/via cap. (2~4pF) Cb Rf C1 Pseudo sine C1,2 = load cap. components Rd Cb Rd = drive level res. (100Ω) C2 Final choose/trim C1=C2=2 *CL - (Cb +Cj) for the target +/-ppm Example: C1=C2=2*(18pF) – (4pF+5pF)=27pF Recommended Crystal Specification a) FL2500047, SMD 3.2X2.5(4P), 25MHz, CL=18pF, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/FL.pdf b) FY2500091, SMD 5x3.2(4P), 25MHz, CL=18pF, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf All trademarks are property of their respective owners. 15-0025 7 www.pericom.com03/03/15 PI6CFGL202B Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs Packaging Mechanical: 16-Pin TSSOP (L) DATE: 05/03/12 Notes: 1. Refer JEDEC MO-153F/AB 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr DESCRIPTION: 16-Pin, 173mil Wide TSSOP PACKAGE CODE: L DOCUMENT CONTROL #: PD-1310 REVISION: F 12-0372 Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code PI6CFGL202BLIE L Description 16-pin, 173mil Wide (TSSOP) Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • "E" denotes Pb-free and Green • Adding an "X" at the end of the ordering code denotes tape and reel packaging Pericom Semiconductor Corporation • 1-800-435-2336 All trademarks are property of their respective owners. 15-0025 8 www.pericom.com03/03/15