PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer Features Description • High-speed, low-noise, non-inverting split 1-10 buffer The PI6C10810 is a 1.2V to 2.5V high-speed, low-noise 1-10 non-inverting clock buffer. The key goal in designing the PI6C10810 is to target networking applications that require lowskew, low-jitter, and high-frequency clock distribution. • Maximum Frequency up to 250 MHz • Low output skew < 60ps (Bank A, 2.5V) • Low duty cycle distortion < 200ps • Choice of 1.2V, 1.5V, 1.8V or 2.5V supply voltage on Bank A, Bank B, Bank C Providing output-to-output skew as low as 60ps, the PI6C10810 is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. • Industrial temperature range: –40°C to 85°C CLK0-4 operate from VDDA supply. • Low propagation delay < 2.0ns (2.5V) • Packages (Pb-free & Green): 20-pin, TSSOP (L20) 20-pin, SSOP (H20) 20-pin, QSOP (Q20) CLK5-6 operate from VDDC supply. CLK7-9 operate from VDDB supply. Block Diagram Pin Configuration VDDA CLK0 CLK1 BUF_IN CLK2 CLK3 CLK4 CLK5 BUF_IN 1 20 VDDB GND 2 19 CLK9 CLK0 3 18 CLK8 VDDA 4 17 GND CLK1 5 16 CLK7 GND 6 15 VDDC CLK2 7 14 CLK6 VDDA 8 13 GND CLK3 9 12 CLK5 GND 10 11 CLK4 CLK6 CLK7 Pin Description Pin Name BUF_IN CLK [0:9] GND VDDA, VDDB, VDDC CLK8 CLK9 VDDC VDDB 11-0015 1 Description Input Outputs Ground Power (1.2V, 1.5V, 1.8V, 2.5V) PS9014A 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 2.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature............................................................–65°C to +150°C VDD Voltage...........................................................................–0.5V to +3.6V Output Voltage (max. 3.6V)........................................... –0.5V to VDD+0.5V Input Voltage (max 3.6V)............................................... –0.5V to VDD+0.5V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2.5V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 2.5V ± 0.2V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Min. Typ. (2) Max. 2.3 2.5 2.7 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 1.7 3.6 VIL Input LOW Voltage Logic LOW level -0.3 0.7 II Input Current VDD = Max, Vin = VDD or GND Output High Voltage VOH Output LOW Voltage VOL VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 2.5V, +25°C ambient and maximum loading. I pin 15 IOH = -1mA 2.0 IOH = -2mA 1.7 IOH = -8mA 1.7 IOL = 1mA 0.1 IOL = 2mA 0.2 IOL = 8mA 0.2 Units V µA V 2.5V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 2.5V ± 0.2V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Input Frequency FIN (2) tPLH, tPHL tSK(O)(3) (3) tSK(P) tSK(T)(3)(5) Min. Typ 0 Units 250 MHz Propagation Delay BUF_IN to CLKn 1.0 Output to Output Skew between any two outputs of the same device @ same transition Bank A (CLK0 - CLK4) –60 60 Bank C (CLK5 - CLK6) –30 30 –150 150 Bank B (CLK7 - CLK9) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output Part to Part Skew between two identical outputs of different parts on the same board(4) RL = 500-Ohm, CL = 3pF, 125 MHz Outputs are measured @ VDD/2 1.5 Max. 100 2.0 200 300 tdc_in Duty Cycle In @ Ins edge rate 45 55 tdc_out Duty Cycle Out 40 57.5 tj(5) Additive Jitter tR(O) Output Rise Time 20%-80% CLKn tF(O) Output Fall Time 80%-20% CLKn 50 RL = 500-Ohm, CL = 3pF Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. 11-0015 2 ps 0.5 0.7 0.5 0.7 PS9014A % ps ns 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 1.8V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Storage Temperature............................................................–65°C to +150°C VDD Voltage...........................................................................–0.5V to +2.5V Output Voltage (max 2.5V) ........................................... –0.5V to VDD+0.5V Input Voltage (max 2.5V) . ............................................ –0.5V to VDD+0.5V 1.8V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.8V ± 0.15V, TA = -40° to 85°C) Parameters Test Conditions(1) Description Min. Typ. (2) Max. 1.65 1.8 1.95 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 1.1 2.7 VIL Input LOW Voltage Logic LOW level -0.3 0.35*VDD VDD = Max, Vin = VDD or GND Input Current(3) II VOH Output High Voltage VOL Output LOW Voltage I pin VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL 15 IOH = -2mA 1.35 IOH = -8mA 1.2 IOL = 2mA 0.1 IOL = 8mA 0.2 Notes: 1. For Max. or Min. conditions, use appropriate operating VDD and Ta values. 2. Typical values are at VDD = 1.8V, +25°C ambient and maximum loading. 3. This parameter is determined by device characterization but is not production tested. Units V µA V 1.8V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.8V ± 0.15V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Min. Input Frequency FIN (2) tPLH, tPHL tSK(O)(3) tSK(P)(3) tSK(T)(3)(5) Typ 0 Max. Units 200 MHz Propagation Delay BUF_IN to CLKn 1.0 Output to Output Bank A (CLK0 - CLK4) Skew between any Bank C (CLK5 - CLK6) two outputs of the same device @ same Bank B (CLK7 - CLK9) transition –60 60 30 30 –200 200 CL = 3pF, RL = 500-Ohm, 125 MHz Outputs are measured @ VDD/2 Pulse Skew between opposite transitions (tPHL-tPLH) of the same output Part to Part Skew between two identical outputs of different parts on the same board(4) 2.3 100 2.8 200 300 tdc_in Duty Cycle In @ 1 ns edge rate 45 55 tdc_out Duty Cycle Out 40 57.5 tj(5) Additive Jitter tR(o) Output Rise Time 20% - 80% CLKn 0.5 0.8 tF(o) Output Fall Time 80% - 20% CLKn 0.5 0.8 50 Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. 11-0015 ps 3 PS9014A % ps ns 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 1.5V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature............................................................–65°C to +150°C VDD Voltage...........................................................................–0.5V to +3.6V Output Voltage (max. 3.6V)........................................... –0.5V to VDD+0.5V Input Voltage (max 3.6V)............................................... –0.5V to VDD+0.5V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1.5V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.5V ± 0.1V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Min. Typ. (2) Max. 1.4 1.5 1.6 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 0.65×VDD VDD VIL Input LOW Voltage Logic LOW level -0.3 0.35×VDD II Input Current VOH Output High Voltage VOL Output LOW Voltage VDD = Max, Vin = VDD or GND VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 1.5V, +25°C ambient and maximum loading. I pin 15 IOH = -2mA 1.05 IOH = -8mA 1.75 IOL = 2mA 0.35 IOL = 8mA 0.65 Units V µA V 1.5V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.5V ± 0.1V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Input Frequency FIN tR/tF tPLH, tPHL tSK(O) (3) tSK(P)(3) tSK(T)(3)(5) tdc_in (5) tdc_out tj Typ Max. Units 200 MHz 1.0 ns 3.5 ns 0 CLKn Rise/Fall Time (2) Min. 20% to 80% Propagation Delay BUF_IN to CLKn 2.0 Output to Output Skew Bank A (CLK0 - CLK4) between any two outputs Bank C (CLK5 - CLK6) of the same device @ Bank B (CLK7 - CLK9) same transition Pulse Skew between opposite transitions (tPHL-tPLH) of the same output Part to Part Skew between two identical outputs of different parts on the same board(4) CL = 3pF, RL = 500-Ohms, 125 MHz Outputs are measured @ VDD/2 2.8 –100 100 –50 50 –200 200 100 200 300 Duty Cycle In @ Ins edge rate 45 55 Duty Cycle Out 40 60 Additive Jitter 50 tR(o) Output Rise Time 20% - 80% CLKn 0.6 0.9 tF(o) Output Fall Time 80% - 20% CLKn 0.6 0.9 Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. 11-0015 4 ps PS9014A % ps ns 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 1.2V Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature............................................................–65°C to +150°C VDD Voltage...........................................................................–0.5V to +3.6V Output Voltage (max. 3.6V)........................................... –0.5V to VDD+0.5V Input Voltage (max 3.6V)............................................... –0.5V to VDD+0.5V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1.2V DC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.2V ± 0.1V, TA = -40° to 85°C) Test Conditions(1) Parameters Description Min. Typ. (2) Max. 1.1 1.2 1.3 VDD Supply Voltage VIH Input HIGH Voltage Logic HIGH level 0.65×VDD VDD+0.3 VIL Input LOW Voltage Logic LOW level -0.3 0.35×VDD II Input Current VOH VOL Output High Voltage Output LOW Voltage VDD = Max, Vin = VDD or GND I pin VDD = Min., VIN = VIH or VIL VDD = Min., VIN - VIH or VIL Notes: 1. For Max. or Min. conditions, use appropriate operating range values. 2. Typical values are at VDD = 1.2V, +25°C ambient and maximum loading. 15 IOH = -2mA 1.05 IOH = -8mA 1.75 IOL = 2mA 0.35 IOL = 8mA 0.65 Units V µA V 1.2V AC Characteristics (Over Operating Range: VDDA, VDDB, VDDC = 1.2V ± 0.1V, TA = -40° to 85°C) Test Conditions(1) Parameters Description FIN tPLH, tPHL(2) tSK(O)(3) tSK(P)(3) tSK(T)(3)(5) tDC_IN tDC_OUT Min. Input Frequency 0 Propagation Delay BUF_IN to CLKn 4 Output to Output Skew between any two outputs of the same device @ same transition Bank A (CLK0 - CLK4) Bank C (CLK5 - CLK6) CL = 3pF, RL = 500-Ohm, 125 MHz Outputs are measured @ VDD/2 Bank B (CLK7 - CLK9) Pulse Skew between opposite transitions (tPHL-tPLH) of the same output Typ Max. Units 150 MHz 6 ns 5 –150 150 –50 50 –300 300 200 Part to Part Skew between two identical outputs of different parts on the same board(4) 300 300 Duty Cycle In @ 1ns edge rate 45 55 Duty Cycle Out 40 60 tj(5) Additive Jitter tR(o) Output Rise Time 20% - 80% CLKn 0.9 1 tF(o) Output Fall Time 80% - 20% CLKn 0.9 1 50 Notes: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew measured at worst case temperature (max. temp). 4. Identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 5. Guaranteed by design. 11-0015 ps 5 PS9014A % ps ns 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer Power Supply Characteristics Parameters Test Conditions(1) Description Min. VDDA = VDDB = VDDC = 2.7V Quiescent Power Supply Current IDDQ VDDA = VDDB = VDDC = 1.95V VDDA = VDDB = VDDC = 1.6V Short Circuit Current Max. Units 16 12 No Load. FIN = 40MHz (Bank A, Bank B, Bank C included) mA 8 VDDA = VDDB = VDDC = 1.2V IOS Typ. (2) 8 2.7V 1.95V 1.6V 1.2V VDDA = VDDB = VDDC ±80 ±50 ±35 ±15 Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics. 2. Typical values are at VDD = 1.2V, 1.5V, 1.8V or 2.5V, and +25°C ambient. 3. Per TTL driven input (VIN = VDD - 0.6V); all other inputs at VDD or GND. mA Capacitance (TA = 25°C, f = 1 MHz) Parameters(1) Description Test Conditions Typ Max. CIN Input Capacitance VIN = 0V 3.0 4 COUT Output Capacitance VOUT = 0V — 6 Note: 1. Units pF This parameter is determined by device characterization but is not production tested. Test Circuits for All Outputs VDD Pulse Generator f = 125MHz 50-Ohm D.U.T. CL 3pF 500-Ohm Definitions: CL = Load capacitance: includes jig and probe capacitance. 11-0015 6 PS9014A 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer Switching Waveforms Pulse Skew – tSK(P) Propagation Delay VDD VIH Input Input VDD/2 tPLH VIL tPHL tPLH VOH Output tF 0V tPHL VOH Output VDD/2 tR VDD/2 VDD/2 VOL VOL tSK(P) = | tPLH - tPLH | Output Skew – tSK(O) Package Skew – tSK(T) VDD VDD Input Input VDD/2 tPLHx 0V tPHLx tPLH1 VOH CLKx VOL tSK(O) = | tPLHy - tPLHx | 11-0015 tPHLy or tSK(T) Part #2 Output VDD/2 tPLHy VOH VDD/2 tSK(T) tSK(O) VOH CLKy 0V tPHL1 Part #1 Output VDD/2 tSK(O) VDD/2 VOL tSK(T) = | tPLH2 - tPLH1 | 7 VOH VDD/2 tPLH2 | tPHLy - tPHLx | VOL tPHL2 or VOL | tPHL2 - tPHL1 | PS9014A 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer DOCUMENT CONTROL NO. PD - 1311 20 REVISION: E DATE: 03/09/05 .169 .177 1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 1 .0256 BSC 0.65 4.3 4.5 .007 .012 0.19 0.30 0.45 0.75 SEATING PLANE .238 .269 6.1 6.7 .002 0.05 .006 0.15 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2336 • www.pericom.com Note: 1. Package Outline Exclusive of Mold Flash and Metal Burr 2. Controlling dimentions in millimeters 3. Ref: JEDEC MO-153F/AC 11-0015 .018 .030 DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP PACKAGE CODE: L 8 PS9014A 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer 1 DATE: 04/10/08 DESCRIPTION: 20-Pin, 209-Mil Wide, SSOP PACKAGE CODE: H20 DOCUMENT CONTROL #: PD-1240 REVISION: E 08-0140 11-0015 9 PS9014A 02/23/11 PI6C10810 1.2V-2.5V, 250MHz, 1:10 Networking Clock Buffer DOCUMENT CONTROL NO. PD - 1202 20 REVISION: H .008 0.20 MIN. .150 .157 3.81 3.99 Guage Plane .010 0.254 1 .041 1.04 REF .015 x 45˚ 0.38 .053 1.35 .069 1.75 Detail A 1 SEATING PLANE .025 BSC 0.635 0˚-6˚ .016 .035 0.41 0.89 Detail A .337 8.56 .344 8.74 .058 REF 1.47 DATE: 10/22/07 .008 .013 0.20 0.33 .004 0.101 .010 0.254 .008 0.203 .012 0.305 .007 .010 0.178 0.254 .228 .244 5.79 6.19 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Note: 1) Controlling dimensions in inches. 2) Ref: JEDEC MO-137B/AD 3) Dimensions do not include mold flash, protrusions or gate burrs DESCRIPTION: 20-Pin, 150-Mil Wide, QSOP PACKAGE CODE: Q Ordering Information(1-3) Ordering Code Package Code Package Type PI6C10810LE L Pb-free & Green, 20-pin 173-mil wide TSSOP PI6C10810HE H Pb-free & Green, 20-pin 209-mil wide SSOP PI6C10810QE Q Pb-free & Green, 20-pin 150-mil wide QSOP Notes: 1. Thermal Characteristics can be found on the web at www.pericom.com/packaging/ 2. E = Lead-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 11-0015 10 PS9014A 02/23/11