PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer Features Description ÎÎPCIe Gen2/ Gen3* compliant clock buffer/ZDB The PI6CEQ20200 is a high performance PCIe Gen2/ Gen3 zero delay buffer with two HCSL outputs. Pericom’s proprietary equalization technique used in this device improves signal integrity and makes this device suitable for PCIe Gen2/ Gen3 applications even when the input from the main clock has to travel a long distance. * Gen3 performance only available in Commercial temp ÎÎInternal equalization for better signal integrity ÎÎ2 HCSL outputs ÎÎDual PLL bandwidth for SSC tracking ÎÎCycle-to-Cycle Jitter : 40ps (typ) ÎÎOutput-to-Output Skew <10ps ÎÎ3.3V supply voltage ÎÎTSSOP-20 packages Applications ÎÎServers ÎÎEmbedded computing systems ÎÎNetworking systems Block Diagram Pin Configuration (20-Pin TSSOP & 20-Pin QSOP) OE0# CLK0 CLK0# SRCIN EQ SRCIN# PLL_BW_SEL SCLK SDATA PLL OE1# Control CLK1 CLK1# PLL_BW_SEL 1 20 VDDA SRCIN 2 19 GNDA SRCIN# 3 18 IRef OE_0# 4 17 OE_1# VDD 5 16 VDD GND 6 15 GND CLK0 7 14 CLK1 CLK0# 8 13 CLK1# VDD 9 12 VDD 10 11 SCLK SDATA 15-0058 1 www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Pin Description Pin # Pin Name Type Description 1 PLL_BW_SEL Input CMOS input to select the PLL Bandwidth 2, 3 SRCIN, SRCIN# Input HCSL inputs 4 OE_0# Input Output enable for CLK0 and CLK0#. “0” is “enabled”, “1” is “tri-stated. Internal pull-down 5, 9, 12, 16 VDD Power 3.3V Power Supply 6, 15 GND Power Ground 7, 8 CLK0, CLK0# Input HCSL output 10 SDATA Input/Output SMBus data 11 SCLK Input SMBus clock input 13, 14 CKL1#, CLK1 Output HCSL output 17 OE_1# Input Output enable for CLK1 and CLK1#. “0” is “enabled”, “1” is “tri-stated. Internal pull-down 18 IRef Input External resistor connection for internal current reference 19 GNDA Power Analog and PLL Ground 20 VDDA Power Analog and PLL power supply 15-0058 2 www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Storage temperature............................................... -65ºC to +155ºC Ambient Temperature with Power Applied.........-40ºC to +85ºC 3.3V Analog Supply Voltage...................................... -0.5 to +4.6V ESD Protection(HBM)........................................................... 2000V Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol Description Test Conditions VDD Power supply IDD Total Power Supply Current IDD_Output tri-stated Total power supply current with Outputs are tri-stated TA Operating temperature Min Type Max Unit - 3.135 - 3.465 V - - - 65 mA Outputs are tri-stated - - 30 mA Commercial temperature 0 +70 Industrial temperature -40 +85 ºC LVCMOS DC Electrical Characteristics (Over Operating Conditions) Symbol Parameter Conditions Min. Typ. Max. Unit VIH Input High Voltage - 2 - VDD+0.3 V VIL Input Low Voltage - -0.3 - 0.8 V IIH Input High Current VIN = VDD - - 45 µA IIL Input Low Current VIN = 0V -45 - - µA R PU Internal pull up resistance - - 120 - kOhm R DN Internal pull down resistance - - 120 - kOhm 15-0058 3 www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Differential DC Input Characteristics (Over Operating Conditions) Symbol Parameter Conditions Input High Current, IN- IIH VIN = VDD =3.465V Input High Current, IN+ Input Low Current, IN- IIL VIN = 0V Input Low Current, IN+ VIH Input High Voltage VIL Input Low Voltage Single-ended swing Min. Typ. Max. Unit - - 5 µA 45 µA -45 - - µA -5 - - µA 660 700 850 mV -150 0 mV HCSL DC Electrical Characteristics (Over Operating Conditions) Symbol Parameter Conditions Min. Typ. Max. Unit VOH Output High Voltage - 660 - 850 mV VOL Output Low Voltage - - - 150 mV VCROSS Absolute Crossing Point Voltages - 250 - 550 mV ΔVCROSS Total variation of VCROSS overall edges - - - 140 mV IOH Output High Current w/475-Ohm resistor. Connected between IREF pin and GND - - 14 - mA HCSL AC Switching Characteristics(*1, *2, *3) (Over Operating Conditions) Symbol Parameter Conditions Min. Typ. Max. Unit Fin Input Frequency - 90 100 110 MHz Tr /Tf Output Rise/Fall time Between 0.175V and 0.525V *2 175 - 700 ps ΔTr /ΔTf Rise and Fall Time Variation*2 - - - 125 ps TPD Propagation delay in PLL mode PLL is enabled 650 ps TPDBP Propagation delay in bypass mode PLL is bypassed 4.0 ns Tskew Output-to-Output Skew - - 10 ps TDC Output Duty Cycle*3 - 47 - 53 % JC-C Cycle to Cycle jitter Differential waveform 40 50 ps - 3.1 ps 0.61 1.0 ps - 3.0 ps - 3.0 ps JHF-RMS *3 Phase jitter, high frequency RMS jitter applying PCIE Gen2 jitter mask*3 RMS jitter applying PCIE Gen3 jitter mask*3 RMS jitter applying PCIE Gen2 jitter mask*3 Phase jitter, low frequency JLF-RMS 15-0058 - RMS jitter applying PCIE Gen3 jitter mask*3 , commercial temp range only 4 - www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization HCSL AC Switching Characteristics(*1, *2, *3) (Over Operating Conditions) Continued.. Symbol Parameter PLLLBW PLL Loop Bandwidth TOEN Conditions Min. PLL_BW_SEL=1 PLL_BW_SEL=0 Max. Unit 1.3 3 MHz 0.25 1 MHz OE enable time 100 ns TOEF OE disable time 100 ns TSQD Squelch detect time Input level is less than 150mV (single-ended) Typ. 50 ns Notes: 1. Test configuration is Rs=33Ω, Rp=49.9Ω, and 2pF 2. Measurement is taken from Single Ended waveform. 3. Measurement is taken from Differential waveform. HCSL Output Buffer Characteristics VDD (3.3V ± 5%) Slope ~ 1/Rs RO IOUT ROS Iout VOUT = 0.85V max 0V 0.85V Simplified diagram of current-mode output buffer HCSL Output Buffer Characteristics Symbol Minimum Maximum RO 3000Ω N/A ROS unspecified unspecified VOUT N/A 850mV 15-0058 5 www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Configuration Test Load Board Termination for HCSL Output Rs 33Ω 5% Clock Rs 33Ω 5% PI6CEQ20200 475Ω 1% Clock# Rp 49.9Ω 1% 2pF 5% Rp 49.9Ω 1% 2pF 5% Serial Data Interface This part is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit address and read/write bit as shown below. Address Assignment A6 A5 A4 A3 A2 A1 A0 W/R 1 1 0 1 0 1 0 0/1 Data Protocol (Write) 1 bit 8 bits Slave Start bit Addr: D4 1 8 bits 1 8 bits Ack Register Ack offset 1 Byte Ack Count=N 8 bits 1 Data Byte 0 Ack … 8 bits 1 1 bit Data Byte N-1 Ack Stop bit (Read) 1 bit Start bit 8 bits 1 Slave Addr: Ack D4 8 bits 1 Register Ack offset 1 8 bits 1 Slave Repeat Addr: Ack start D5 8 bits 1 Byte Count=N Ack 8 bits Data Byte 0 8 bits 1 Ack … Data Byte N-1 1 1 bit NOT Ack Stop bit Note: 1.Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0. 15-0058 6 www.pericom.com Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Data Byte 0: Control Register Bit Name Control function Type 0 1 PWD 7 SMB_EN SMBus enable RW Controlled by SMBus registers Controlled by device pins 1 6 RESERVED RW X 5 RESERVED RW X 4 RESERVED RW X 3 RESERVED RW X 2 RESERVED RW X 1 PLL_BW_SEL Select PLL Bandwidth RW Low BW High BW 1 0 PLL Bypass Select PLL bypass mode RW PLL bypass PLL enabled 1 Type 0 1 PWD Data Byte 1: Control Register Bit Name Control function 7 RESERVED RW X 6 RESERVED RW X 5 RESERVED RW X 4 RESERVED RW X 3 RESERVED RW X 2 RESERVED RW X 1 RESERVED RW X 0 RESERVED RW X Data Byte 2: Control Register Bit Name 7 RESERVED RW X 6 RESERVED RW X 5 RESERVED RW X 4 RESERVED RW X 3 RESERVED RW X 2 RESERVED RW X 1 RESERVED RW X 0 RESERVED RW X 15-0058 Control function Type 7 0 1 www.pericom.com PWD Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Data Byte 3: Control Register Bit Name Control function Type 7 RevID3 Revision ID R 0 6 RevID2 R 0 5 RevID1 R 0 4 RevID0 R 0 3 VENID3 R 0 2 VENID2 R 0 1 VENID1 R 0 0 VENID0 R 0 Vendor ID 0 1 PWD Data Byte 4: Control Register Bit Name 7 Devicde ID Control function Type 0 1 PWD R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 1 1 R 1 0 R 0 Data Byte 5: Control Register Bit Name Control function Type 7 B57 RW 0 6 B56 RW 0 5 B55 RW 0 4 B54 Write to this register will control how many bytes will be read back, default is 06=6 bytes. RW 0 3 B53 RW 0 2 B52 RW 1 1 B51 RW 1 0 B50 RW 0 15-0058 8 0 1 www.pericom.com PWD Rev B 05/05/15 PI6CEQ20200 PCIe® Gen2 / Gen3 Buffer with Equalization Packaging Mechanical: 20-Pin TSSOP (L) DATE: 05/03/12 DESCRIPTION: 20-pin, 173mil Wide TSSOP Notes: 1. Refer JEDEC MO-153F/AC 2. Controlling dimensions in millimeters 3. Package outline exclusive of mold flash and metal burr PACKAGE CODE: L DOCUMENT CONTROL #: PD-1311 REVISION: F 12-0373 Ordering Information Ordering Code Package Code Package Type Operating Temperature PI6CEQ20200LE L Pb-free & Green, 20-pin 173-mil TSSOP 0°C to 70°C PI6CEQ20200LEX L Pb-free & Green, 20-pin 173-mil TSSOP, Tape & Reel 0°C to 70°C PI6CEQ20200LIE L Pb-free & Green, 20-pin 173-mil TSSOP -40°C to 85°C PI6CEQ20200LIEX Notes: L Pb-free & Green, 20-pin 173-mil TSSOP, Tape & Reel -40°C to 85°C 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. E = Pb-free and Green 3. Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 15-0058 9 www.pericom.com Rev B 05/05/15