ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Features Description • Supply voltage, VCC = 3.3V ±5% • Each Port is compatible w/ DVI, HDMI 1.1, HDMI 1.2 or HDMI 1.3 signals • Supports both AC-coupled and DC-coupled inputs • Support for 8-bit, 10-bit, and 12-bit deep color per channel • High Performance, up to 2.5 Gbps per channel • Switching support for 3 side band signals (SCL, SDA and HPD) • 5V Tolerance on all side band signals • SCL, SDA, and HPD pins are the only pins that can support HOT INSERTION • Integrated 50-ohm (±10%) termination resistors at each high speed signal input • Configurable output swing control (500mV, 750mV, 1000mV) • Configurable Pre-Emphasis levels (0dB, 1.5dB, 3.5dB, & 6.0dB) • Configurable De-Emphasis (0dB, -3.5dB, -6.0dB, -9.5dB) • Optimized Equalization Single default setting will support all cable lengths • ESD protection = 8kV (typical) on high-speed data channels only • Propagation delay ≤ 2ns • High Impedance Outputs when disabled • Packaging (Pb-free & Green): 80-contact LQFP (FF80) Pericom Semiconductor’s PI3HDMI341ART 3:1 active switch circuit is targeted for high-resolution video networks that are based on DVI/HDMI standards and TMDS signal processing. The PI3HDMI341ART is an active 3 TMDS to 1 TMDS receiver switch with Hi-Z outputs. The device receives differential signals from selected video components and drives the video display unit. It provides three controllable output swings that can be controlled through a single bit. The allowable output swings are 500mV, 750mV and 1000mV. This solution also provides a unique advanced pre-emphasis technique to increase rise and fall times which are reduced during transmission across long distances. Each complete HDMI/DVI channel also has slower speed, side band signals, that are required to be switched. Pericom’s solution provides a complete solution by integrating the side band switch together with the high speed switch in a single solution. Using Equalization at the input of each of the high speed channels, Pericom can successfully eliminate deterministic jitter caused by long cables from the source to the sink. The elimination of the deterministic jitter allows the user to use much longer cables (up to 25 meters). The maximum DVI/HDMI Bandwidth of 2.5 Gbps provides 12bit deep color support, which is offered by HDMI revision 1.3. Due to its active uni-directional feature, this switch is designed for usage only for the video receiver’s side. For consumer video networks, the device sits at the receiver’s side to switch between multiple video components, such as PC, DVD, STB, D-VHS, etc. The PI3HDMI341ART is the industry’s first active DVI/ HDMI switch compatible with HDMI 1.1, 1.2, and 1.3 which ensures transmitting high-bandwidth video streams from video components to the display unit. The PI3HDMI341ART also provides enhanced robust ESD/EOS protection of 8kV, which is required by many consumer video networks today. The Optimized Equalization provides the user a single optimal setting that can provide HDMI compliance for all cable lengths: 1meter to 20meters and color depths of 8bit/ch, or 12bit/ch. Pericom also offers the abiility to fine tune the equalization settings in situations where cable length is known. For example, if 25meter cable length is required, Pericom's solution can be adjusted to 16dB EQ to accept 25metere cable length. 07-0016 1 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity EQ_S1 GND A34 B34 VCC A33 B33 GND A32 B32 VCC A31 B31 GND SCL3 SDA3 HPD3 VCC OE EQ_S0 Pin Configuration VCC HPD2 SDA2 SCL2 GND GND B21 A21 VCC B22 A22 GND B23 A23 VCC B24 A24 GND VCC HPD1 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 62 39 63 38 64 37 65 36 66 35 67 34 68 33 69 32 70 31 71 30 72 29 73 28 74 27 75 26 76 25 77 24 78 23 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 HPD_SINK SDA_SINK SCL_SINK GND GND Z1 Y1 VCC Z2 Y2 GND Z3 Y3 VCC Z4 Y4 GND S3 S2 S1 OC_S2 OC_S0 OC_S1 VCC GND A14 B14 VCC A13 B13 GND A12 B12 VCC A11 B11 GND SCL1 SDA1 OC_S3 07-0016 2 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Pin Description Pin # Pin Name I/O Description 6,9,12,15 68, 71, 74, 77 A11, A12, A13, A14 A21, A22, A23, A24 I I Port 1 TMDS Positive inputs Port 2 TMDS Positive inputs 49, 52, 55, 58 A31, A32, A33, A34 I Port 3 TMDS Positive inputs 5, 8, 11, 14 67, 70, 73, 76 B11, B12, B13, B14 B21, B22, B23, B24 I I Port 1 TMDS Negative inputs Port 2 TMDS Negative inputs 48, 51, 54, 57 B31, B32, B33, B34 I Port 3 TMDS Negative inputs 4, 10, 16 24, 30, 36, 37, 47, 53, 59, 65, 66, 72, 78 80 GND HPD1 O Port 1 HPD output 62 HPD2 O Port 2 HPD output 44 HPD3 O Port 3 HPD output 40 HPD_Sink I 42 OE I Sink side hot plug detector input. High: 5-V power signal asserted from source to sink and EDID is ready. Low: No 5-V power signal asserted from source to sink, or EDID is not ready. Output Enable, Active LOW 3 SCL1 I/O Port 1 DDC Clock 64 SCL2 I/O Port 2 DDC Clock 46 SCL3 I/O Port 3 DDC Clock 38 SCL_Sink I/O Sink Side DDC Data 2 SDA1 I/O Port 1 DDC Data 63 SDA2 I/O Port 2 DDC Data 45 SDA3 I/O Port 3 DDC Data 39 SDA_Sink I/O Sink Side DDC Data 21,22,23 S1, S2, S3 I Source Input Selector 7, 13, 17 27, 33, 43, 50, 56 61, 69, 75, 79 34, 31, 28, 25 VCC Y1, Y2, Y3, Y4 O TMDS positive outputs 35, 32, 29, 26 Z1, Z2, Z3, Z4 O TMDS negative outputs 41, 60 EQ_S0, EQ_S1 I Equalizer controls(1) 19, 18, 20, 1 OC_S0, OC_S1, OC_S2, OC_S3 I Output buffer controls Note: OC_S3 has an internal pull-up resistor. OC_S2 has an internal pull-down resistor. Ground 3.3V Power Supply Note: 1. EQ_S0 has an internal pull-down and EQ_S1 has an internal pull-up 07-0016 3 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Switch Block Diagram A14 B14 A13 B13 A12 B12 A11 B11 V CC RINT R e c e iv e r with E Q V CC RINT R e c e iv e r with E Q V CC RINT R e c e iv e r with E Q V CC RINT R e c e iv e r with E Q E2_S0 V CC ... E2_S1 RINT A24 R e c e iv e r with E Q OC_S0 OC_S1 OC_S2 OC_S3 B24 V CC RINT A23 3-to-1 R e c e iv e r with E Q Y4 TDMS Drive Z4 MUX B23 V CC RINT Z3 ... R e c e iv e r with E Q Y3 TDMS Drive A22 B22 A21 Y2 TDMS Drive V CC RINT Z2 R e c e iv e r with E Q Y1 B21 TDMS Drive Z1 V CC OE RINT A34 R e c e iv e r with E Q B34 V CC RINT A33 S1 R e c e iv e r with E Q S2 B33 S3 V CC RINT R e c e iv e r with E Q ... A32 B32 V CC A31 B31 RINT R e c e iv e r with E Q HPD1 HPD_SINK Control Logic HPD2 HPD3 SCL1 SDA1 SCL_SINK SDA_SINK SCL2 SDA2 SCL3 SDA3 07-0016 4 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Truth Table Control Pins I/O Selected S1 S2 S3 Y/Z H x x A1/B1 L H x A2/B2 L L H A3/B3 L L L None (Hi-Z) Hot Plug Detect Status SCL_Sink SDA_Sink SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 None (Hi-Z) HPD1 HPD2 HPD3 HPD_Sink L L L HPD_Sink L L L HPD_Sink L L L OC Setting Value Logic Table Input Control Pins Setting Value OC_S3 0 OC_S2 0 OC_S1 0 OC_S0 0 Vswing (mV) 500 Vos (V) 3.06 Pre-emphasis/De-emphasis (dB) none 0 0 0 1 750 2.95 none 0 0 0 0 1 1 0 1 1000 500 2.84 3.02 none none 0 1 0 0 500 3.06 0 0 1 0 1 500 3.05 1.5 0 1 1 0 500 2.97 3.5 0 1 1 1 500 2.9 6 1 0 0 0 500 3.08 0 1 0 0 1 340 3.08 -3.5 1 0 1 0 270 3.08 -6 1 0 1 1 160 3.08 -9.5 1 1 0 0 1000 2.85 0 1 1 0 1 830 2.85 -3.5 1 1 1 0 500 2.85 -6 1 1 1 1 330 2.85 -9.5 EQ Setting Value Logic Table EQ_S1 0 0 1 EQ_S0 0 1 0 1 1 07-0016 Setting Value 3dB on all high speed inputs 8dB on all high speed inputs Optimized Equalization enabled on all high speed inputs (default value if both EQ_S0 and EQ_S1 are left floating) 16dB on all high speed inputs 5 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................................... –65°C to +150°C Supply Voltage to Ground Potential................................–0.5V to +4.0V DC Input Voltage ...............................................................–0.5V to VCC DC Output Current....................................................................... 120mA Power Dissipation ........................................................................... 1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol VCC TA Parameter Min. Typ. Max. Units Supply Voltage 3.135 3.3 3.465 V 0 70 °C 150 1560 mVp-p 2 VCC + 0.01 V Operating free-air temperature TMDS Differential Pins (A/B) VID Receiver peak-to-peak differential input voltage VIC Input common mode voltage VCC TMDS output termination voltage RT 3.135 3.3 3.465 V Termination resistance 45 50 55 ohm Signaling rate 0 2.5 Gbps Control Pins (OC_Sx, EQ_Sx, S, OE) VIH LVTTL High-level input voltage 2 VCC VIL LVTTL Low-level input voltage GND 0.8 GND 5.5 V DDC Pins (SCL, SCL_SINK, SDA, SDA_SINK) VI(DDC) Input voltage V Status Pins (HPD_SINK) VIH LVTTL High-level input voltage 2 5.3 VIL LVTTL Low-level input voltage GND 0.8 07-0016 6 V P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity TMDS Compliance Test Results Item HDMI 1.3 Spec Pericom Product Spec Termination Supply Voltage, VCC 3.3V ≤ 5% 3.30 ± 5% Terminal Resistance 50-ohm ± 10% 45 to 55-ohm Single-ended high level output voltage, VH VCC ± 10mV VCC ±10mV Single-ended low level output voltage, VL ( VCC - 600mV) ≤ VL ≤ ( VCC- 400mV) ( VCC - 600mV) ≤ VL ≤ ( VCC 400mV) Single-ended output swing voltage, Vswing 400mV ≤ Vswing ≤ 600mV 400mV ≤ Vswing ≤ 600mV Single-ended standby (off) output voltage, Voff VCC ± 10mV VCC ± 10mV Risetime/Falltime (20%-80%) 75ps ≤ Risetime/Falltime ≤ 0.4 Tbit (75ps ≤ tr/tf ≤ 242ps) @ 1.65 Gbps 240ps Intra-Pair Skew at Transmitter Connector, max 0.15 Tbit (90.9ps @ 1.65 Gbps) 60ps max Inter-Pair Skew at Transmitter Connector, max 0.2 Tpixel (1.2ns @ 1.65 Gbps) 100ps max Clock Jitter, max 0.25 Tbit (151.5ps @ 1.65 Gbps) 82ps max Input Differential Voltage Level, Vdiff 150 ≤ Vdiff ≤ 1200mV 150mV ≤ VDIFF ≤ 1200mV Input Common Mode Voltage Level, VICM ( VCC - 300mV) ≤ Vicm ≤ ( VCC37.5mV) Or VCC ±10% ( VCC - 300mV) ≤ Vicm ≤ ( VCC37.5mV) Or VCC ±10% Operating Conditions Source DC Characteristics at TP1 Transmitter AC Characteristics at TP1 Sink Operating DC Characteristics at TP2 Sink DC Characteristics When Source Disabled or Disconnected at TP2 Differential Voltage Level 07-0016 VCC ± 10mV VCC ±10mV 7 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Electrical Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter ICC Supply Current PD Power Dissipation Test Conditions Min. VIH = VCC, VIL = VCC - 0.4V, RT = 50-ohm, VCC = 3.3V Am/Bm = 1.65 Gbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 165 MHz clock Typ.(1) Max. Units 190 230 mA 394 657 mW TMDS Differential Pins (A/B; Y/Z) VOH Single-ended high-level output voltage VCC10 VCC + 10 VOL Single-ended low-level output voltage VCC - 600 VCC - 400 400 600 Vswing Single-ended output swing voltage VOD(O) Overshoot of output differential voltage VOD(U) ΔVOC(SS) |I(OS)| VCC = 3.3V, RT = 50-ohm Pre-emphasis/De-emphasis = 0dB mV 6% 15% Undershoot of output differential voltage 12% 25% Change in steady-state common-mode output voltage between logic states 0.5 5 mV 12 mA Short circuit output current 2x Vswing VODE(SS) Steady state output differential voltage 560 840 VODE(PP) OC_S0 = VCC, Am/Bm = 250 Mbps HDMI data pattern, m = 2, Peak-to-peak output differential voltage 3, 4 A1/B1 = 25 MHz clock 800 1200 Single-ended input voltage under high impedance input or open input II = 10μA VCC - 10 VCC + 10 mV Input termination resistance VIN = 2.9V 50 55 ohm 2 μA VI(open) RINT 45 mVp-p DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| Input leakage current VI = 0.1VCC to 0.9VCC to isolated DDC ports 0.1 CIO Input/output capacitance VI = 0V 7.5 RON Switch resistance IO = 3mA, VO = 0.4V VPASS Switch output voltage VI = 3.3V, II = 100μA 1.5(2) pF 25 50 ohm 2.0 2.5(3) V Status Pins (HPD) VOH(TTL) TTL High-level output voltage IOH = -8mA VOL(TTL) TTL Low-level output voltage IOH = 8mA 2.4 V 0.4 V (Table Continued) 07-0016 8 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Electrical Characteristics (Continued) Symbol Parameter Typ.(1) Max. 0.1 2 0.1 2 VIH = 5.3V 23 100 VIH = 2.0V or VCC 0.1 2 VIL = GND or 0.8V 0.1 2 Test Conditions Min. Units Control Pins (OC_Sx, EQ_Sx, S, OE) |IIH| High-level digital input current |IIL| Low-level digital input current VIH= 2.0V or VCC VIL = GND or 0.8V μA Status Pins (HPD_SINK) |IIH| High-level digital input current |IIL| Low-level digital input current μA Notes: 1. All typical values are at 25°C and with a 3.3V supply. 2. The value is tested in full temperature range at 3.0V. 3. The value is tested in full temperature range at 3.6V. 07-0016 9 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity Switching Characteristics (over recommended operating conditions unless otherwise noted) Symbol Parameter Test Conditions Min. Typ.(1) Max. Units TMDS Differential Pins (Y/Z) tpd Propagation delay 2000 tr Differential output signal rise time (20% - 80%) tf Differential output signal fall time (20% - 80%) tsk(p) Pulse skew tsk(D) Intra-pair differential skew VCC = 3.3V, RT = 50-ohm, pre-emphasis/de-emphasis = 0dB 75 240 75 240 7 50 23 50 skew(2) tsk(o) Inter-pair differential tjit(pp) Peak-to-peak output jitter from Y/Z(1) residual jitter tjit(pp) Peak-to-peak output jitter from Y/Z(2:4) residual jitter 100 pre-emphasis/de-emphasis = 0dB, Am/Bm = 1.65 Gbps HDMI data pattern, m = 2 ,3, 4 A1/B1 = 165 MHz clock de-emphasis = -3.5dB, Am/Bm = 250 Mbps HDMI data pattern, m = 2, 3, 4 A1/B1 = 25 MHz clock 15 30 18 50 tDE De-emphasis duration tSX Select to switch output 6 10 ten Enable time 6 10 tdis Disable time 6 10 0.4 2.5 2 6.0 ps 240 ns DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) tpd(DDC) Propagation delay from SCLn to SCL_SINK or SDAn to SDA_SINK or SDA_SINK to SDAn CL = 10pF ns Control and Status Pins (OC_SX, EQ_SX, S, HPD_SINK, HPD) tpd(HPD) tsx(HPD) Propagation delay (from HPD_SINK to the active port of HPD) Switch time (from port select to the latest valid status of HPD) CL = 10pF ns 3 6.5 Notes: 1. All typical values are at 25°C and with a 3.3V supply. 2. tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of channel 2 to 4 of a device when inputs are tied together. Application Information Supply Voltage All VCC pins are recommended to have a 0.01uF capacitor tied from VCC to GND to filter supply noise TMDS inputs Standard TMDS terminations have already been integrated into Pericom’s PI3HDMI341ART device. Therefore, external terminations are not required. Any unused port must be left floating and not tied to GND. 07-0016 10 P-1.1 01/04/07 ADVANCE INFORMATION - COMPANY CONFIDENTIAL PI3HDMI341ART 3:1 Active HDMI 1.3 Compatible Switch with Optimized Equalization for Enhanced Signal Integrity '$7( 1RWHV $OOGLPHQVLRQVDUHLQPLOOLPHWHUVDQJOHVLQGHJUHHV 5HI-('(&06%'' 3DFNDJHRXWOLQHH[FOXVLYHRIPROGÀDVKDQGPHWDOEXUU '(6&5,37,21SLQ/RZ3UR¿OH4XDG)ODW3DFNDJH/4)3 3$&.$*(&2'()) '2&80(17&21752/3' 5(9,6,21 Ordering Information Ordering Code Package Code PI3HDMI341ARTFFE FF Package Description 80-pin, Pb-free & Green LQFP Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 07-0016 11 P-1.1 01/04/07