PI3WVR31212 DP/HDMI 1:2 De-multiplexer switches

PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Features
Description
ÎÎDP/HDMI 1:2 De-multiplexer switch with 4 high speed
PI3WVR31212 has one passive output port1, one active (DP to
HDMI) output port2. Passive output supports DP1.2 at 5.4Gbps
in I2C mode. Active port2 supports HDMI1.4b at 3.4Gbps.All
two output ports support auto port priority selection. Input port
accepts DP1.2 and HDMI2.0 (I2C control mode only) signals associated with output ports as described above.
differential channel and AUX/DDC, HPD and CAB_DET
signal channels
ÎÎOne passive output ports for DP1.2 at 5.4Gbps
ÎÎOne active output port with integrated DP to HDMI re-
driver (level shifter) supports HDMI 1.4 at 3.4Gbps
ÎÎPin control mode supports auto port priority selection only
ÎÎPin control mode supports port2 with DDC bi-direction
buffer switch only
ÎÎI2C control mode supports both auto and manual port
Application
priority selection
ÎÎNotebook
ÎÎI2C control mode supports port2 with 8 levels equalization
and 5 levels pre-emphasis
ÎÎI2C control mode supports port2 with either DDC bi-
direction buffer switch or DDC passive switch
ÎÎVery low operating power when passive port1 is selected
Pin Configuration: TQFN-60
AUXN
AUXP
SCL2
SDA2
GND
GND
NC
AUX1P/SCL1
AUX1N/SDA1
CAB_1
ÎÎ3.3V power supply
ÎÎ2KV HBM ESD protection for all I/O pins of port1 and all
control pins
ÎÎ8kV contact ESD (IEC61000-4-2) protection for all output
pins in port2
ÎÎPackaging:
60 pin TQFN package (5x9mm, 0.4mm pitch)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Center Pad
TQFN-60
5x9 mm
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VDD
D0P1
D0N1
D1P1
D1N1
D2P1
D2N1
D3P1
D3N1
GND
NC
NC
NC
GND
NC
NC
GND
CEXT
HPD1
MS
21 22 23 24 25 26 27 28 29 30
CLKN2
CLKP2
VDD
D0N2
D0P2
D1N2
D1P2
VDD
D2N2
D2P2
60 59 58 57 56 55 54 53 52 51
OEB
SCL
SDA
VDD
HPD_SRC
CAB_SRC
D0P
D0N
D1P
D1N
D2P
D2N
D3P
D3N
SDA_CTL/PRI_SEL
SCL_CTL/EQ
I2C_A1/PRE_EMP
I2C_A2/ROUT_SEL
HPD2
GND
14-0150
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Block Diagram
CEXT
CAB_SRC HPD_SRC
HPD1
120KΩ
VDD
LDO
HPD2
120KΩ
CAB_1
100KΩ pull High
AUXP
AUXN
AUX1P/SCL1
AUX1N/SDA1
SDA
SCL
SDA2
SCL2
D[0:3]P1
D[0:3]N1
VDD
0//VDD
D[0:3]P
D[0:3]N
RT
Port select
RT
ROUT
ROUT
D[0:3]P2
D[0:3]N2
Rpd
Rpd
GND
OEB
MS
PRI_SEL
EQ
PRE_EMP
ROUT_SEL
Control & Status
Register
I2C
Controller
SDA_CTL
SCL_CTL
(share pins)
I2C_A1, A2
(share pins)
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Pin Description
pin#
pin Name
7
D0P
9
D1P
11
D2P
13
D3P
8
D0N
10
D1N
12
D2N
14
D3N
49
D0P1
47
D1P1
45
D2P1
43
D3P1
48
D0N1
46
D1N1
44
D2N1
42
D3N1
25
D0P2
27
D1P2
30
D2P2
22
CLKP2
24
D0N2
26
D1N2
29
D2N2
21
CLKN2
52
AUX1N/SDA1
53
AUX1P/SCL1
57
SDA2
58
SCL2
60
AUXN
59
AUXP
3
SDA
2
SCL
32
HPD1
I
19
HPD2
I
5
HPD_SRC
O
14-0150
Signal Type
Description
IO
4 differential pair input (DP)
IO
4 differential pair output (DP) for port 1
IO
4 differential pair output (HDMI) for port 2
IO
AUX (DP) or DDC (HDMI) to three ports
IO
AUX to DP-source
IO
DDC to DP-source
HPD1-2 for port1-2;
HPD_SRC to DP-source.
3
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
pin#
pin Name
51
CAB_1
6
CAB_SRC
1
OEB
I
15
SDA_CTL/PRI_SE
I
16
SCL_CTL/EQ
17
I2C_A1/PRE_EMP
18
I2C_A2/ROUT_SEL
Signal Type
Description
CAB_1: CAB_DET to port1
IO
CAB_SRC: CAB_DET to DP-source
No CAB_DET for HDMI port2
IO
I
I
OEB=0, device active; OEB=1, device shut down
MS=0, PRI_SEL selects priority in pin control mode;
MS=1, SDA_CTL as SDA in I2C control mode
MS=0, EQ selects equalization in pin control mode;
MS=1, SCL_CTL as SCL in I2C control mode
MS=0, PRE_EMP selects Pre-emphasis in pin control mode;
MS=1, I2C_A1 as I2C address A1 in I2C control mode
MS=0, ROUT_SEL selects source termination in pin control
mode;
MS=1, I2C_A2 as I2C address A2 in I2C control mode
Mode Select:
31
MS
I
MS=0 for pin control mode
MS=1 for I2C control mode
33
CEXT
O
4,23,28,50
VDD
Power
GND
Ground
20,34,37,41,55,56,
Center Pad
35,36,38,39,40,54
14-0150
NC
Internal LDO bypass capacitance, 4.7uf to GND
3.3V VDD
Bottom GND EPAD
NC
Not Connected
4
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Pin mapping for dual mode DP source DEMUX to DP output
DP mode
HDMI/DVI mode
WVR31212 input pins WVR31212 port1 output
WVR31212 port2 output
ML_lan0(P)
TX2+
D0P
D0P1
D2P2
ML_lan0(N)
TX2-
D0N
D0N1
D2N2
ML_lan1(P)
TX1+
D1P
D1P1
D1P2
ML_lan1(N)
TX1-
D1N
D1N1
D1N2
ML_lan2(P)
TX0+
D2P
D2P1
D0P2
ML_lan2(N)
TX0-
D2N
D2N1
D0N2
ML_lan3(P)
TXC+
D3P
D3P1
CLKP2
ML_lan3(N)
TXC-
D3N
D3N1
CLKN2
Function Description
The MS pin selects I2C or pin control mode.
The default input is DP in pin control mode and can be switched between DP or HDMI in I2C control mode.
Pin control mode has only automatic port selection. I2C control mode has both automatic and manual port selection.
In auto port selection, when only one HPD high detected, the port with HPD high will be selected. When multiple HPD high detected,
the PRI_SEL pin (priority select) will determine the priority of the 2 ports. See priority selection table
When PRI_SEL=low or High, the port-priority will be port1-port2 from high to low; when PRI_SEL=M (open as not connected), the
port priority will be port2-por1 from high to low.
When port 1 is selected and CAB_1 is low as in DP mode, the AUX/DDC channels will work as AUX channels. AUXP shall have
100Kohm external resistor to GND and AUXN shall have 100Kohm external resistor to VDD. The data rate of AUX channels will be
>720Mbps.The internal DDC switch will be off.
When port 1 is selected and CAB_1 is high when DP to HDMI adapter plugged, the AUX/DDC channels will work as DDC channels.
The internal DDC channels are on and the AUX channels are off. The input of DDC channels can tolerate 5V input and voltage of
DDC to source will be limited about 3.3V or below.
When port 1 is selected (passive ports), port2 with HDMI re-driver will shut down.
When port 2 is selected, the internal DP to HDMI level shifter will be enabled. There will be 3 EQ and 3 Pre-emphasis settings in pin
control mode, 8 EQ and 5 Pre-emphasis settings in I2C control mode.
When port 2 is selected, HDMI output can be standard TMDS-open-drain source, as well to be selected with internal source termination as 50 ohm pull up to 3.3V VDD, using ROUT_SEL pin control or I2C control.
When port 2 is active as DP to HDMP level shifter, the DDC channel can be selected between bi-direction DDC buffer and passive
DDC switch in I2C mode.
HPD1, HPD2 are with internal CMOS buffers and can support 3.3V and 5V HPD inputs.
Squelch Mode
Squelch function will disable HDMI data output (as high impedance)when the voltage and frequency of input clock (TMDS) are
below squelch threshold, which will prevent random noise presenting in HDMI data output, thereby prevent noise on sink display.
Squelch function will enable-resume HDMI data output when input clock signals are above squelch threshold.
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Truth Table for TMDS port2
EQ – three level pin control PRE-EMP – three level pin control
EQ
Equalization value
PRE_SEL
TX pre-emphasis
0
1.5dB
0
0dB
open
4.0dB
open
1.5dB
1
6.5dB
1
2.5dB
ROUT_SEL
ROUT_SEL
Pull-Up Resistors on port2 D[0:2]P2/N2, CLKP2/N2
0
No Pull-up resistors
1
50Ω Pull-up resistors to VDD
1
6.5dB
Truth Table for AUX and DDC
PORT
When Port1 Selected
DP/HDMI
CAB_1
AUXP
AUXN
SCL
SDA
DP Mode
0
AUX1P
AUX1N
Hi-Z
Hi-Z
DP Mode
1
Hi-Z
Hi-Z
SCL1
SDA1
HDMI Mode
x
Hi-Z
Hi-Z
SCL1
SDA1
Priority Selection Table
PRI_SEL
(Priority order)
HPD1
HPD2
HPD_SRC
CAB_SRC
AUXP/AUXN
SDA/SCL
0 or 1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0 or 1
1
x
HPD1
CAB1
AUX1P/AUX1N
SDA1/SCL1
0 or 1
0
1
HPD2
High
Hi-Z
SDA2/SCL2
M
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
M
1
0
HPD1
CAB1
AUX1P/AUX1N
SDA1/SCL1
M
x
1
HPD2
High
Hi-Z
SDA2/SCL2
Note: M=internal half VDD when input=HiZ
PRI_SEL
(Priority order) HPD1
HPD2
D0P
D1P
D2P
D3P
D0N
D1N
D2N
D3N
0 or 1
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0 or 1
1
x
D0P1
D1P1
D2P1
D3P1
D0N1
D1N1
D2N1
D3N1
0 or 1
0
1
D2P2
D1P2
D0P2
CLKP2
D2N2
D1N2
D0N2
CLKN2
M
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
M
1
0
D0P1
D1P1
D2P1
D3P1
D0N1
D1N1
D2N1
D3N1
M
x
1
D2P2
D1P2
D0P2
CLKP2
D2N2
D1N2
D0N2
CLKN2
Note: M=internal half VDD when input=HiZ
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... –65°C to +150°C
Supply Voltage to Ground Potential ....................................–0.5V to +4.6V
High Speed Channel Input Voltage (DP Mode)........................–0.5V to 2V
High Speed Channel Input Voltage (HDMI Mode)................2.4V to 3.6V
DDC and HPD channels Input Voltage ....................................–0.5V to 6V
DC Output Current ..............................................................................180mA
Power Dissipation .................................................................................... 0.6W
Note: Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Electrical Characteristics
Recommended Operation Conditions
(VDD = 3.3V ±10%)
Parameter
Description
VDD
Operating Voltage
VDD supply current
(Port1 active)
IDD
VDD Supply Current
(Port2 active)
VDD Quiescent Supply Current
IDDQ
(port2 active w/o TMDS input)
Istb
Standby mode by I2C
Test Conditions
VDD=3.3V
Min.
Typ.
Max.
3.0
3.3
3.6
Unit
V
1
mA
Output Enable ( open drain 500mv
signal-end 0dB pre-emphasis, not
including 40mA current to source)
100
mA
Output Enable ( double termination,
500mv signal-end 0dB pre-emphasis, not including 40mA current to
source)
175
mA
TMDS Output Disable,
5.0
mA
VDD=3.6V, Port1selection, HPD_1
=0, MS=1, DP_HDMI=0
0.5
mA
VDD=3.6V, Port2 selection,
HPD_3=0,
2.0
mA
Isd1
Supply shut down current when
OEB disable (MS=0)
VDD=3.6V,OEB=high
50
uA
Isd2
Supply shut down current when
OEB disable (MS=1)
VDD=3.6V,OEB=high
0.5
mA
14-0150
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
DC Electrical Characteristics for Switching over Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
OEB,MS,ROUT_SEL
IIH
High level digital input current
VIH =VDD
-10
40
μA
IIL
Low level digital input current
VIL = GND
-10
10
μA
VIH
High level digital input voltage
2.0
VIL
Low level digital input voltage
0
V
0.8
V
0.4
V
HPD_SRC
VOL_HPD_SRC
Buffer Output Low Voltage
IOL = 4 mA
VOH_HPD_SRC
Buffer Output Low Voltage
IOH = 4 mA
2.4
V
HPD_sink
IIH
High level digital input current(1) VIH =VDD
-10
40
μA
IIL
Low level digital input current(1)
VIL = GND
-10
10
μA
VIH
High level digital input voltage
VDD=3.3V
2.0
VIL
Low level digital input voltage
V
0
0.8
V
-50
50
uA
CAB
ILK
Input leakage current
Switch is off, Vin=5.5v
CIO
Input/Output capacitance whenpassive switch on
RON
Passive Switch resistance
IO = 3mA, VO = 0.4V
Vpass
Switch Output voltage
VI=3.3V, II=100uA
CI(source)
Source side CAB capacitance
CI(sink)
Sink side CAB capacitance when
10
1.5
VI peak-peak = 1V, 100 KHz
pF
25
50
Ω
3.0
3.3
V
3.5
TBD
pF
6.5
TBD
pF
50
uA
SDA/SCL, SDA1/SCL1
ILK
Input leakage current
DDC switch is off, Vin=5.5V
CIO
Input/Output capacitance when
passive switch on
VI peak-peak = 1V, 100 KHz
8
RON
Passive Switch resistance
IO = 3mA, VO = 0.4V
25
50
Ω
Vpass
Switch Output voltage
3.0
3.6
V
CI(source)
Source side DDC capacitance (
passive switch off. )
CI(sink)
Sink side DDC capacitance ( pasVI peak-peak = 1V, 100 KHz
sive switch off. )
VI=5.0V, II=100uA
VDD=3.3V
-50
1.5
VI peak-peak = 1V, 100 KHz
pF
2.8
pF
5
pF
SDA2/SCL2 ( DDC buffer of port2 active)
VIH
High level input voltage
VIL
Low level input voltage
ILK
Input leakage current
14-0150
VDD=3.3V
DDC switch is off, Vin = 5.5V
8
2.0
V
0
0.8
V
-10
10
uA
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Parameter
Description
Test Conditions
IIL
Low level input current
VIL = 0.2V
VOL
Low level output voltage
ILOH
CIO
Min.
Typ.
-10
Max.
Unit
10
μA
IOL = 4mA
0.2
V
HIGH-level output leakage current
VO=3.6V
10
μA
Input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V or 0V
pF
SDA/SCL (DDC buffer of port2 active)
VIH
High level input voltage
VIL
Low level input voltage
ILK
Input leakage current
IIL
VDD=3.3V
2.0
V
0
0.4
V
DDC switch is off, Vin = 5.5V
-10
10
uA
Low level input current
VIL = 0.2V
-10
10
μA
VOL
Low level output voltage
IOL = 4mA
0.47
0.6
V
ILOH
HIGH-level output leakage current
VO=3.6V
10
μA
CIO
Input/output capacitance
VI = 3 V or 0 V; VCC = 3.3 V or 0V
0.52
5
8
pF
AUXP,AUXN, AUXnP/SCLn, AUXnN/SDAn
ILK
Input leakage current
DDC switch is off, Vin=5.5V
CIO
Input/Output capacitance when
passive switch on
VI peak-peak = 1V, 100 KHz
6
pF
RON
Passive Switch resistance
IO = 3mA, VO = 0.3V
5
Ω
IO = 3mA, VO = 3.0V
10
Ω
Vpass
Switch Output voltage
CI(source)
Source side capacitance ( passive
switch off. )
CI(sink)
Sink side capacitance ( passive
switch off. )
VI=5.5V, II=100uA
-50
50
uA
3.8
4
V
VI peak-peak = 1V, 100 KHz
2.5
TBD
pF
VI peak-peak = 1V, 100 KHz
3.5
TBD
pF
–1.6
–1.8
V
VDD=3.3V
High Speed Channel (D[0:3]P/N – D[0:3]P1N1)
VIK
Clamp Diode Voltage (HS Channel)
VDD = Max., IIN = –18mA
IIH
Input HIGH Current
VDD = Max., VIN = VDD
±10
IIL
Input LOW Current
VDD = Max., VIN = GND
±10
RON_HS
14-0150
On resistance between input to
out- put for high speed signals
µA
VINPUT,cm = 0V to 1.8V,
VINPUT,diff < 1.0Vp-p, diff, VDD =
3.0V, IINPUT =
8
Ohm
VINPUT,cm = 2.2V to 3.1V,
VINPUT,diff < 1.2Vp-p, diff, VDD =
3.0V, IINPUT = 20mA
8
Ohm
9
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
High Speed Channel (D[0:3]P/N – D[0:2]P2/N2; CLKP2/N2)
VI(open)
Single-ended input voltage under
high impedance input or open
input
IL=10uA
VDD-10
RT
Input termination resistance
VIN=2.9V
45
IOZ
Leakage current resistance
VDD=3.6V, OEB=High
Ioff
Power off leakage current
VDD=0, VIN=3.6V
VDD+10
mV
50
66
ohm
30
100
uA
50
uA
-50
Dynamic Electrical Characteristics over Operating Range
(TA = -40º to +105ºC, VDD = 3.3V ±10%)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
TMDS Differential Pins
Propagation delay
tpd
2000
Differential output signal rise time
tr
(20% - 80%)
Differential output signal fall time
tf
(20% - 80%)
VDD = 3.3V, Rout = 50Ω off, open
drain, 0dB pre-emphasis
120
tsk(p)
Pulse skew
50
tsk(D)
Intra-pair differential skew
120
50
tsk(o)
Inter-pair differential skew(2)
15
100
Tjit_clk(pp)
Peak-to-peak output jitter CLK
residual jitter
23
40
Tjit_dat(pp)
Peak-to-peak output jitter DATA
Residual Jitter
ten
Enable time
10
10
tdis
Disable time
25
50
Data Input = 3.4 Gbps HDMI data
pattern from signal generation,
short trace.
ps
50
CLK Input = 340 MHz clock
us
SCL,SDA channel, AUX channel , CAB channel : passive switches
tpd(DDC)
Propagation delay from SCLn/
SDAn to SCL/SDA or SCL/SDA to
SCLn/SDAn In passive SW on.
CL = 10pF, in passive switch
5
ns
SCL2,SDA2- SCL,SDA channel : buffers
tPLH
LOW-to-HIGH propagation delay
SCL/SDA to SCL2/SDA2
50
100
150
ns
tPHL
HIGH-to-LOW propagation delay
SCL/SDA to SCL2/SDA2
10
20
40
ns
tPLH
LOW-to-HIGH propagation delay
SCL2/SDA2 to SCL/SDA
50
100
150
ns
tPHL
HIGH-to-LOW propagation delay
SCL2/SDA2 to SCL/SDA
10
20
40
ns
14-0150
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Control and Status Pins (HPDn, HPD_SRC)
tpd(HPD)
Propagation delay (from HPDx to
the active port of HPD_SRC, high
to low)
tsx(HPD)
Switch time (from port select to
the latest HPD , manual selection
mode)
2
us
2
us
CL = 10pF
Dynamic Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
High Speed Channel (D[0:3]P/N – D[0:3]P1/N1)
XTALK
See Fig. 1 for
Crosstalk on High Speed Channels Measurement
Setup
f= 2.7 GHz
-32
-30
See Fig. 2 for
Measurement
Setup
f= 2.7 GHz
-19
-17
OFF Isolation on High Speed
Channels
OIRR
Differential Insertion Loss on
ILOSS
High Speed Channels
@2.7GHZ (see figure 3)
-1.8
-1.6
dB
dB
R loss
Differential Return Loss on High
Speed Channels
@ 2.7GHz (5.4Gbps)
BW_Dx±
Bandwidth -3dB for Main high
speed path (Dx±)
See figure 3
5.0
5.6
GHz
BW_AUX
Bandwidth -3dB for AUX
See figure 3
1.0
1.2
GHz
Tstartup
VDD valid to channel enable
10
us
Twakeup
Enabling output by changing OEB
from High to Low
10
us
Tpd
Propagation delay (input pin to
output pin) on all channels
80
tb-b
Bit-to-bit skew within the same
differential pair of Dx± channels
5
tch-ch
Channel-to-channel skew of Dx±
channels
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11
-18.0
-16.0
dB
ps
7
ps
35
ps
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
BALANCED
PORT1
BALANCED
PORT2
+
+
50
–
–
50
+
+
50
–
–
50
DUT
Fig 1. Crosstalk Setup
BALANCED
PORT1
+
+
50
–
–
50
+
–
BALANCED
PORT2
DUT
Fig 2. Off-isolation setup
BALANCED
PORT1
+
+
–
–
BALANCED
PORT2
DUT
Fig 3. Differential Insertion Loss
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
HPD auto selection timing waveform
HPDn
Sink HPD pulse duration<2ms
t1
HPD_SRC
Fig 4. HPD timing t1
Priority change
Priority changes from Low to High or from High to
Low and HPDn are high
HPD_SRC
Previous Channel Active
New Channel Active
All Channels Hi-Z
t1
t3
Fig 5. HPD timing t3
Other HPDs (Low)
HPDx
One of HPDn changes from Low
to High, others are Low
HPDx Channel Active
HPD_SRC
All Channels Hi-Z
t3
Fig 6. HPD timing t3
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
At least one of Other HPD Ports (High)
Active Port HPD
Active port changes form High to
Low, at least one of others is High
HPD_SRC
t2
t3
Previous Chan nel Active
New Channel Active
All Channels Hi-Z
t2 + t3
Fig 7. HPD timing
At least one of Other HPD Ports (High)
Priority Port HPD
t3
HPD_SRC
Previous Channel Active
t3
All Channels Hi-Z
New Channel Active
2 x t3
Fig 8. HPD timing
Other HPDs (Low)
HPDx
Active port changes form High to
Low, others are Low
HPD_SRC
HPDx Channel Active
HPDx Channel Active
All Channels Hi-Z
t4
Fig 9. HPD timing t4
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
2
ms
HPD auto switching timing
HPD pulse duration when treated as an IRQ –t1 (Figure 4)
Propagation delay of HPDx Desertion –t2 (Figure 7)
50
125
200
ms
HPD_SRC low duration when the outputs are switched –t3(Figure
5,6,7,8); Propagation delay of HPDx assertion (Figure 8)
100
250
400
ms
400
1000
1600
ms
Power down delay from HPDx de-assertion to chip power down –t4.
(Figure 9)
I2C Address Byte
Address Byte
b7(MSB)
b6
b5
b4
b3
b2
b1
b0 (R/W)
1
0
1
1
A2
A1
1
1/0*
* Read; 0:Write, A2 and A1 are two address bits setting
Data transmission format
Data is transmitted to the PI3WVR31212 registers using the Write mode as shown in Figure 1. Data is read from the PI3WVR31212
registers using the Read mode as shown in Figure 2.
Figure 1: I2C control register write condition
S
Slave Address
W A
DATA
A
...
A/A
DATA
P
From master to slave
A= acknowledge
A= not acknowledge
From slave to master
S= start condition
P= stop condition
Figure 2: I2c control register read condition
S
Slave Address
14-0150
R
A
DATA
A
...
DATA
15
A
P
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
I2C Control Register
The I2C control register uses index read or write for byte access.
Offset
Name
Description
Power Up Condition
Type
0x00
R/W
[7] Enable Standby
0: normal mode
1: standby mode
In standby mode, all ports are powered down.
[6:5] Port SEL1/SEL0 selection control
00 port 1
01all off
10 port 2
11 depends on priority selection
0x00
CONFIG[7:0]
[4:2]
PRI_SEL priority selection control by HPDx
00x port1/port2
010 port1/port2
011 port2/port1
1xx port2/port1
[1] DP_HDMI selection control
0=DP input,
1=Reserved
[0] Reserved
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
[7:5] EQ programmable setting
000: 1.5 dB
001:
4 dB
010: 6.5 dB
011:
9 dB
100: 11.5 dB
101:
14 dB
110: 16.5 dB
111:
0x01
RX_SET[7:5]
for port2; HPD
auto selection
time
19 dB
[4:3] HPD auto selection time source control
00: normal
0x00
01: -25%
R/W
10: +25%
11: test mode
[2] HPD auto selection time t3 setting
0: 256ms
1: 128ms
[1] HPD auto selection time t4 setting
0: 1024ms
1: 516ms
[0] HPD pulse duration treated as IRQ time t1 setting
0: 2ms
1: 4ms
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Output setting for HDMI re-driver/level shifter
[7] HDMI output control
0: open drain
1: double termination
[6:4] HDMI output Pre-emphasis settings
000: 0dB
001: 1.5dB
010: 2.5dB
011: 3.5dB
0x02
TX_SET[7:0]
for port2
100: 6dB
0x00
R/W
0x51
R
[3:2] TMDS output swing setting
00: 500mv as default
01: -10%
10: +10%
11: +20%
[1] TMDS output slow rate setting
0: as default
1: +10%
[0] Reserved to 0
Pericom Vendor Register ID (refer to PCIE clock buffer)
0x03
Pericom ID
[7:4] Vendor ID 0101
[3:0] device revision 0001
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
[7] HPD_SRC output logic function (buffer)
0: HPD_SRC=HPDx
1: HPD_SRC=/HPDx
[6] DDC function for port 2
0: Active buffer
1: passive switch
[5] Port switching in manual selection
0x04
HPDx/
CABx[6:0
Read only
1: disable T3 time pulse when port switching, Port
switch immediately
0: Enable T3 time pulse when port switching
0x00
R/W [7:4]
R [3:0]
[4] Reserved
[3] HPD2 status as read only
[2] Reserved
[1] HPD1 status as read only
[0] Reserved for HPD1B
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PI3WVR31212
DP/HDMI 1:2 De-multiplexer switches
Packaging Mechanical: ZL60
14-0044
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information
Ordering Code
Package Code
Package Description
PI3WVR31212ZLE
ZL
60-Pin, (TQFN) 5X9mm
Notes:
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• "E" denotes Pb-free and Green
• Adding an "X" at the end of the ordering code denotes tape and reel packaging
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