Datasheet

PI3HDMI621
2:1 Active HDMI™1.4 Sink-side Switch with Integrated
ARC and Fast Switching Support
Features
Description
ÎÎHDMI 1.4 compliant
PI3HDMI621 is 2:1 active switch that supports HDMI 1.4 specification with data rate up to 3.4 Gbps.
ÎÎOperation up to 3.4 Gbps per lane(340 MHz pixel clock) to
The I2C configuration function with multiple system control
signal integration of DDC channel MUX, Hot Plug Detection
DEMUX, cable plug-unplug detection and HDMI 1.4 ARC
transmitter help to save the extra requirement of GPIO control
pins or control chip and provide optimized trace routing and
component reduction.
support 4K x 2K @24Hz (297 MHz) and 3D video format
(1080p, 1080i and 720p)
ÎÎSupport up to 48-bit per pixel Deep Color TM
ÎÎIntegrated ARC(Audio Return Channel) and Rx Sense
function
ÎÎFast switching between two HDMI input ports
Programmable termination settings at TMDS input help to
avoid the compatibility issue caused by non standard HDMI
source to determine the connection status of TMDS channel
with proper termination voltage setting. The programmable
output termination setting supports double termination option
between PI3HDMI621 and the HDMI receiver chip to ease the
reflection effect caused by improper impedance matching design
and reducing jittery signals.
ÎÎProgrammable equalizer, emphasis and amplitude settings to
achieve optimized HDMI signal integrity
ÎÎEach input can be AC coupled or DC coupled, while the
output will maintain TMDS compliance DC coupled,
current steering signals
ÎÎIdle clock detection function for output squelch and auto
standby
PI3HDMI621 integrates ARC and supports video fast switching
among HDMI ports.
ÎÎIntegrated ESD protection on I/O pins to connector
àà 8 KV contact per IEC61000-4-2, level 4
àà 8 KV HBM
ÎÎIndustrial temperature coverage
The device is fully compatible with HDMI 1.4 and supports
backward compatibility to the DVI 1.0 standard.
ÎÎPackaging (Pb-free & Green): 48-contact LQFP (FB)
Pin Configuration
SCL_sink
SDA_sink
HPD_sink
SEL1
OEB
HPD2
SDA2
SCL2
CLKN2
CLNP2
D0N2
D0P2
48 47 46 45 44 43 42 41 40 39 38 37
VDD
D1N2
1
36
2
35
CLKN
CLKP
D1P2
3
34
GND
GND
4
D2N2
5
D2P2
6
33 D0N
32 D0P
CLKN1
CLKP1
7
8
29 D1N
GND
9
28 D1P
D0N1
10
27 D2N
D0P1
11
26 D2P
VDD
12
31 VDD
PI3HDMI621
LQFP- 48
30 VDD_REG
25 SPDIF_in
13 14 15 16 17 18 19 20 21 22 23 24
ARC_out
EQ_S0
OC_S0
Rout_S0
SCL1
SDA1
HPD1
GND
D2P1
1
D2N1
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D1P1
D1N1
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Functional Block Diagram
VDD_REG
VDD
HPD[1:2]
LDO
HPD_SINK
120KΩ
VDD
RX_SENSE
RT
RT
VDD
CLKP1/N1
D[0:2]P1/N1
2:1
Active
Mux
RT
Rout
Rout
CLKP/N
D[0:2]P/N
RT
CLKP2/N2
D[0:2]P2/N2
OEB
SEL1
SCL1
SDA1
SCL2
SDA2
Control Logic
SCL_SINK
2:1
Mux
SDA_SINK
ARC_OUT
SPDIF_IN
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Rout_S0
OC_S0
EQ_S0
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Pin Description
Pin #
Pin Name
Type 1
39
HPD_SINK
I
Sink side hot plug detector input; internal pull-down at 120K ohm.
18
HPD1
O
Port 1 HPD output
42
HPD2
O
Port 2 HPD output
7
8
10
11
13
14
15
16
CLKN1
CLKP1
D0N1
D0P1
D1N1
D1P1
D2N1
D2P1
I
Port 1 TMDS inputs. Rt=50 Ohm
45
46
47
48
2
3
5
6
CLKN2
CLKP2
D0N2
D0P2
D1N2
D1P2
D2N2
D2P2
I
Port 2 TMDS inputs. Rt=50 Ohm
36
35
33
32
29
28
27
26
CLKN
CLKP
D0N
D0P
D1N
D1P
D2N
D2P
O
TMDS outputs. Rout=50 Ohm when Rout_S0=High
20
SCL1
IO
Port 1 DDC Clock
44
SCL2
IO
Port 2 DDC Clock
19
SDA1
IO
Port 1 DDC Data
43
SDA2
IO
Port 2 DDC Data
37
SCL_SINK
IO
Sink side DDC Clock
38
SDA_SINK
IO
Sink side DDC Data
Description
TMDS output termination selection.
21
Rout_S0
I
41
OEB
I
22
OC_S0
I
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If HIGH or floating, then 50 Ohm is present on TMDS output pins. if LOW, then 50 Ohm is
not present on TMDS output pins. This pin has internal 100 KOhm pull-up
Output Enable control. Active low. Internal 100 KOhm pull-down. See truth table for functionality.
TMDS output pre-emphasis selection. See OC_S0 truth table for functionality.
This pin has internal 100 KOhm pull-up
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Pin Description
Pin #
Pin Name
Type 1
Description
TMDS input equalization selection.
If LOW or floating , EQ is set at 9 dB for all TMDS data inputs
23
EQ_S0
I
If HIGH, EQ is set at 15 dB for all TMDS data inputs (please note, TMDS clock inputs are
always set to 3 dB eq).
This pin has an internal 100 KOhm pull-low
PORT1 or PORT2 selection. Please see truth table for functionality
40
SEL1
I
25
SPDIF_IN
I
Single mode ARC signal input
24
ARC_OUT
O
Single mode ARC signal output
1, 12, 31
VDD
P
3.3V power supply
30
VDD_REG
P
LDO output for internal core power supplier. External capacitor 2.2 to 4.7 μF should be
added to GND.
4, 9, 17,
34
GND
G
Supply Ground
This pin has an internal 100K Ohm pull-up
Note
1. I = Input, O = Output, IO = Bidirectional, P = Power, G = Ground.
Description of Operation
Squelch function:
Squelch control is using low frequency clock signal detection method. When TMDS input clock frequency is less than 10 MHz or
less than 50 mV, power-down mode will initiate to save power.
Rx-SENSE detector:
This device searches for 50 Ohm termination present in the other side of HDMI Receiver. If the 50 Ohm is not present in the other
side, the device determine no valid HDMI receiver chip is connected. Then, this device will turn off 50 Ohm input termination
resistors for all TMDS data and clock pairs and enter into the power-down mode.
OC_S0 Truth Table (Swing setting 500 mV as default)
TMDS output pre-emphasis setting
Setting Value
Rout_S0 (internal pull-up)
OC_S0 (internal pull-up)
Single-end Vswing (mV)
Pre-emphasis (dB)
0
0
500
0 (open drain)
0
1
500
2.5 (open drain)
1
0
500
0 (double termination)
1
1
500
2.5 (double termination)
Note
1. open drain (Rout off); double termination (Rout on).
2. TMDS CLK pre-emphasis value is fixed to 0 dB.
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Port Selection Truth Table
OEB (Internal
pull-down)
SEL1
0
1
0
1
TMDS port
DDC port
HPD port
CLKN/P1, D0N/P1, D1N/P1,D2N/P1
SCL1/SDA1
HPD1
0
CLKN/P2, D0N/P2, D1N/P2,D2N/P2
SCL2/SDA2
HPD2
X
OFF
Follow SEL1
Follow SEL1
EQ_S0 Truth Table
EQ_S0 (Internal pull-down)
Operation
0
9 dB
1
15 dB
Note
1. For TMDS CLK channels, the EQ value is fixed to 3dB.
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Audio Return Channel(ARC):
There are two ARC input modes, common mode and single mode input. This device can supports "single mode input" only.
HDMI Source
To HDMI Source
HDMI Sink
12kohm
HEAC+
HEAC+
or NO
ARC_OUT
SPDIF_IN
From Scalar
Rest
Rest
9kohm
ARC single mode input and output
+Veh-swing
+Veh-swing
Veh
-Veh-swing
+Veh-swing
Veh = 0~5V
+Veh-swing = 250mV
-Veh-swing = 250mV
ARC single mode signal output waveform
RL
50Ω
SCl_SINK
SCL1
SDA1
SDA_SINK
SCL2
SDA2
Rup
Controller
Chip
2:1 Mux
DDC Channel Application Diagram
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Absolute Maximum Ratings
Item
Rating
Supply Voltage to Ground Potential
5.5V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature
260°C
Note: Stress beyond those lists under “Absolute Maximum Ratings” may cause permanent damage to the device
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Unit
Ambient Operating Temperature
-40
85
°C
Power Supply Voltage (measured in respect to GND)
3.0
3.6
V
DC Specification (VDD = 3.3 ± 10%)
Parameter
Parameter
VDD
Operating Voltage
IDD
Conditions
VDD Supply Current
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
Output Enable (open drain 500
mV single-ended 0 dB pre-emphasis)
120
150
mA
Output Enable ( double termination, 500 mV single-ended 0 dB
pre-emphasis)
190
230
mA
Idd_Squelch
Supply Current in squelch
mode
Input TMDS signal is not valid
11
13
mA
Idd_Rx sense
Supply current when no
50ohm detected in Rx
Input TMDS is valid, 50 Ohm Rx
is not detected
4
5
mA
Istb
Standby mode
VDD = 3.6V, HPD_x = 0, Arc_out
= 0, OEB = High
4
5
mA
VOL_HPD
Open Drain Output Low
Voltage
IOL = 4 mA
IOFF_HPD
Off leakage current
IOZ_HPD
Open drain Output leakage current
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12-0247
0
0.4
VDD = 0, VIN = 3.6V
20
VDD = 0, VIN = 5.5V
40
VDD = 3.6, VIN = 3.6V
20
VDD = 3.6, VIN = 5.5V
40
7
V
µA
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
HPD_SINK
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
High level digital input
current
VIH = VDD
25
40
µA
IIL
Low level digital input
current
VIL = GND
-10
10
µA
VIH
High level digital input
voltage
VDD = 3.3V
2.0
VIL
Low level digital input
voltage
V
0
0.8
V
Control Pin (OEB)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
High level digital input
current
VIH =VDD
30
45
µA
IIL
Low level digital input
current
VIL = GND
-10
10
µA
VIH
High level digital input
voltage
2.0
VIL
Low level digital input
voltage
0
V
0.8
V
DDC Channel Block
Symbol
Parameter
Conditions
ILK
Input leakage current
DDC switch is off
CIO
Input/Output capacitance
VI peak-peak = 1V, 100 KHz
10
RON
On resistance
IO = 3mA, VO = 0.4V
25
50
Ω
Vpass
Switch Output voltage
VI=3.3V, II=100uA
VDD=3.3V
2.0
2.5
V
VOH_DDC (source/
DDC Switch Output High
Voltage
VIN=3.3V.
External pull-up Rup to VDD
from 1.5 KΩ to 5 KΩ
sink)
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12-0247
Min.
8
Typ.
-10
Max.
40
1.5
VDD - 1
Units
µA
pF
V
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
SPDIF & ARC Pins, See ARC single mode waveform
Symbol
Parameter
Conditions
Min.
Typ.
IIH_SPDIF
High level input current
Vdd=3.6V, VIH =3.6V
500
µA
IIL_SPDIF
Low level input current
Vdd=3.6V, VIL = GND
-350
µA
Vel
Single mode input/output
Vel DC voltage level
0
5.0
V
Vel swing SPDIF
Single mode input swing
0.2
0.6
V
Vel swing ARC_
OUT
Single mode ARC output
swing
0.4
0.6
V
RO
Output resistance of ARC
output stage
tr
ARC output rise time (10%
< 0.4UI (fclock = 6.144MHz)
to 90%)
25
ns
tf
ARC output fall time (10%
< 0.4UI (fclock = 6.144MHz)
to 90%)
25
ns
TJpp
ARC signal peak to peak
jitter
3
ns
IOZ
Leakage current with Hi-Z
VDD = 3.6V
I/O
10
µA
0.5
Max.
Ω
55
< 0.4UI (fclock = 6.144MHz)
Units
TMDS Differential Pins
Symbol
Parameter
VOH
Single-ended high level output voltage
VDD-10
VOL
Single-ended low level output voltage
VDD-600
Vswing
Single-ended output swing voltage
VOD(O)
Conditions
Overshoot of output differential voltage (1)
VOD(U)
Undershoot of output differential voltage (2)
VOD(U)
Change in steady-state common-mode output voltage between logic
IOS
VDD = 3.3V,
Rout=50Ω
Min.
Typ.
Max.
VDD+10
Units
mV
VDD-400 mV
400
600
mV
180
mV
200
mV
5
mV
Short Circuit output current
-12
12
mA
Short Circuit output current at double termination mode
-24
24
mA
VDD-10
VDD+10
mV
VI(open)
Single-ended input voltage under high impedance input or open
II = 10uA
RT
Input termination resistance
VIN = 2.9V
45
50
55
Ω
Note:
1. Overshoot of output differential voltage VOD(O) = (VSWING(MAX) * 2) * 15%
2. Undershoot of output differential voltage VOD(O) = (VSWING(MIN) * 2) * 25%
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
AC Characteristics (Over recommended operating conditions unless otherwise noted)
TMDS Differential Pins
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
tpd
Propagation delay
2000
tr
Differential output signal
rise time (20% - 80%)
190
tf
Differential output signal
fall time (20% - 80%)
tsk(p)
Pulse skew
10
50
tsk(D)
Intra-pair differential skew
23
50
tsk(o)
Inter-pair differential skew
tjit(pp)
Peak-to-peak output jitter
CLK residual jitter
tjit(pp)
Peak-to-peak output jitter
DATA Residual Jitter
tSX
Select to switch output
ten
Enable time
1000
ns
tdis
Disable time
10
ns
190
VDD = 3.3V, Rout = 50 Ohm
ps
100
15
30
18
50
CLK Input = 165 MHz clock
10
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
Symbol
Parameter
Conditions
tpd(DDC)
Propagation Delay
CL = 10pF
Min.
Typ.
Max.
0.4
2.5
Typ.
Max.
Units
ns
Control and Status Pins (HPD_SINK, HPD)
Symbol
Parameter
Conditions
tpd(HPD)
Propagation Delay
CL = 10pF,
tsx(HPD)
Select to switch output
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12-0247
Min.
Pull-up resistor=1 KOhm
Open drain output
10
Units
10
ns
10
ns
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Packaging Mechanical: 48-Contact LQFP (FB)
1
DATE: 09/17/09
DESCRIPTION: 48-Contact, Low Profile Quad Flat Package (LQFP)
PACKAGE CODE: FB (FB48)
DOCUMENT CONTROL #: PD-2027
REVISION: C
09-0012
Please check for the latest package information on the Pericom web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
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Part Number
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Dual Mode DisplayPort to HDMI Level Shifter and Re-driver
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3.4Gbps HDMI 1.4 Re-driver for Source-side application, supporting Dual Mode DisplayPort
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3.4Gbps HDMI 1.4 Re-driver for Sink-side application, supporting Dual Mode DisplayPort
PI3VDP3212
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4-Lane DisplayPort 1.2 Compliant Switch
PI3HDMI412AD
1:2 Active 3.4Gbps HDMI 1.4 compliant Splitter/Re-driver
PI3HDMI521
2:1 Active 3.4Gbps HDMI 1.4 Switch with built-in ARC and Fast Switching support for Source-side Application
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3:1 Active 3.4Gbps HDMI 1.4 Switch/Re-driver with I2C control and ARC Transmitter
Reference Information
Document
Description
VESA DisplayPort Standard Version 1 Revision 2, Video Electronics Standards Association, January 5, 2010
VESA
VESA DisplayPort Dual-Mode Standard Version 1, Video Electronics Standards Association, February 10,
2012
VESA DisplayPort Interoperability Guideline Version 1.1a, Video Electronics Standards Association, February 5, 2009
HDMI
High-Definition Multimedia Interface Specification Version 1.4, HDMI Licensing, LLC, June 5, 2009
Ordering Information
Ordering Number
Package Code
Package Description
PI3HDMI621FBE
FB
Pb-free & Green 48-Contact LQFP
• Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
• E = Pb-free and Green
• X suffix = Tape/Reel
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PI3HDMI621
2:1 Active HDMI™1.4 Switch with Integrated
ARC and Fast Switching Support
Revision History
Date
Changes
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