Datasheet

PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with I2C Control & ARC Transmitter
Features
Description
ÎÎHDMI 1.4 compliant with fast video switch among each
PI3HDMI336 is an I2C configurable active switch using
Pericom’s new ActiveEyeTM technology to achieve optimized signal integrity for cable or on board transmission.
ports
ÎÎI2C control 3:1 HDMI
active switch Mux with DC coupled
or AC coupled Dual mode DisplayPort signals
Through I2C interface, system designer can easily program and
adjust equalization, emphasis and output swing settings.
àà Output will maintain its DC coupled, currentsteering
àà TMDS compliance input can be AC coupled video or
DC coupled
ÎÎ2.5Gbps data rate for TMDS clock up to 250MHz
ÎÎSupport up to 36-bits per pixel Deep ColorTM
With integrated DDC channel Mux, Hot Plug Detection
De-Mux, cable plug-unplug detection and HDMI 1.4 ARC
transmitter, PI3HDMI336 saves GPIO control pins, provides
optimized trace routing, and reduces BOM cost.
Programmable TMDS input termination settings helps designers
to avoid the compatibility issue caused by non standard HDMI
source.
modes
ÎÎProgrammable equalizer, emphasis and amplitude settings
to achieve optimized HDMI signal integrity
Programmable output termination setting supports double termination option between PI3HDMI336 and the HDMI receiver
chip. This feature minimizes the reflection caused by improper
impedance matching and reduces the signal jitter.
ÎÎIntegrated selectable DDC active/ passive switch to connect
DDC path
ÎÎIdle clock detection function for output squelch
ÎÎProgrammable TMDS termination control
àà TMDS input pull-up 50 Ohm termination, pull-down
>120K Ohm resistor when switch is deselected
àà Double terminated TMDS output
ÎÎIntegrated ESD protection on I/O pins to connector
àà 8KV contact per IEC61000-4-2, level 3
ÎÎPackaging
PI3HDMI336 is HDMI 1.4 compatible with backward compatibility to the DVI 1.0 standard and can be used for the DP++ application devices.
Block Diagram
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SCL_A
SDA_A
HPD_A
D3+B
D3-B
D2+B
D2-B
VDD
D1+B
D1-B
GND
CK+B
CK-B
SCL_B
SDA_B
HPD_B
àà 64 pin LQFP (FB), Pb-free and Green
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PI3HDMI336
LQFP- 64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D3+C
D3-C
D2+C
D2-C
VDD
D1+C
D1-C
GND
CK+C
CK-C
SCL_C
SDA_C
HPD_C
5V_portA
5V_portB
5V_portC
ARC_Out
SPDIF_IN
VDD
D3+
D3D2+
D2GND
D1+
D1CK+
CKVDD
SCL_sink
SDA_sink
HPD_sink
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CK-A
CK+A
D1-A
D1+A
VDD
D2-A
D2+A
GND
D3-A
D3+A
/OE
INT_ OUT
SVDD
SDA_CTL
SCL_CTL
I2C_ADR
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Block Diagram
VDD
EQ
Port A TMDS Input
CK+/-A,D1+/-[1..3]
RT=50 Ohm
Rpd = 200K Ohm
RT
VDD
Port A
RPD
Rout
D+/- [1..3]
CK+/-
MUX
VDD
RT
Port B TMDS Input
CK+/-B,D2+/-[1..3]
RT=50 Ohm
Rpd = 200K Ohm
/OE
Port B
VDD
RPD
RT
Port C TMDS Input
CK+/-C,D3+/-[1..3]
RT=50 Ohm
Rpd = 200K Ohm
Port C
I2C Controller
RPD
HPD_A
HPD_B
HPD_C
HPD
5V_PORT[A..C]
Control & Status
Register
SCL/SDA_CTL
HPD_SINK
INT_OUT
SCL_A, SDA_A
SCL_B, SDA_B
DDC Buffer or
Passive Switch
MUX
SCL/SDA_SINK
SCL_C, SDA_C
SPDIF_IN
ARC_OUT
Pin Description
Pin #
Pin Name
5, 19, 29, 44, 57
VDD
Power
3.3V power supply. When VDD is off, the TMDS channels and ARC will
be powered down.
13
SVDD
Power
3.3V standby power supply. SVDD is for side band signals (HPD, DDC
channel and the I2C control register unit).
8, 24, 41, 54
GND
Ground
32
HPD_SINK
I
Sink side hot plug detector input; internal pull-down at 120K W.
62
HPD_A
O
Port A HPD output
49
HPD_B
O
Port B HPD output
36
HPD_C
O
Port C HPD output
2
CK+A
1
CK-A
4
D1+A
I
Port A TMDS inputs. Rt=50ohm; Rpd=200kW.
3
D1-A
7
D2+A
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IO
Descriptions
Ground connection
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Pin Description Cont..
Pin #
Pin Name
6
D2-A
10
D3+A
9
D3-A
53
CK+B
52
CK-B
56
D1+B
55
D1-B
59
D2+B
58
D2-B
61
D3+B
60
D3-B
40
CK+C
39
CK-C
43
D1+C
42
D1-C
46
D2+C
45
D2-C
48
D3+C
47
D3-C
27
CK+
28
CK-
25
D+1
26
D-1
22
D+2
23
D-2
20
D+3
21
D-3
64
IO
Descriptions
I
Port A TMDS inputs. Rt=50ohm; Rpd=200kW.
I
Port B TMDS inputs. Rt=50ohm; Rpd=200kW.
I
Port C TMDS inputs. Rt=50ohm; Rpd=200kW.
O
TMDS outputs. Rout=50W.
SCL_A
IO
Port A DDC Clock
51
SCL_B
IO
Port B DDC Clock
38
SCL_C
IO
Port C DDC Clock
63
SDA_A
IO
Port A DDC Data
50
SDA_B
IO
Port B DDC Data
37
SDA_C
IO
Port C DDC Data
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Pin Description Cont..
Pin#
Name
IO Type
Descriptions
30
SCL_SINK
IO
Sink side DDC Clock
31
SDA_SINK
IO
Sink side DDC Data
15
SCL_CTL
IO
I2C Clock, compatible with I2C-bus specification, up to
400kb/s.
14
SDA_CTL
IO
I2C Data, compatible with I2C-bus specification, up to 400kb/s.
12
INT_OUT
O
Interrupt pin. Logic status output pin of INT Flag. Open drain
output, set INT_OUT to high by external pull to SVDD resistor.
11
/OE
I
Output Enable control. Active low. /OE only disables the high
speed TMDS channel but not the side band signals and I2C
circuitry supplied by SVDD. Internal pull-down at 100k ohm.
16
I2C_ADR
I
I2C Address LSB; internal pull-down at 100K W.
35, 34, 33
5V_PORTA, 5V_PORTB,
5V_PORTC
I
Connector 5V port. Internal pull down resistor at 100k when
VDD power on.
18
SPDIF_IN
I
Single mode ARC signal input. See page 11 in detail.
17
ARC_OUT
O
Single mode ARC signal output.
I2C Address Byte AddressByte
b7(MSB)
b6
b5
b4
b3
b2
b1
b0 (R/W)
1
0
1
0
1
0
I2C_ADR
1/0 *
I2C Control Register
Byte 0
Bit
7
Descriptions
Type
Power Up Condition
HDMI input port selection
R/W
0
Logic Settings
b[7:6] = 00 Port A
b[7:6] = 01 Port B
6
HDMI input port selection
R/W
0
b[7:6] = 10 Port C
b[7:6] = 11 no port active
See Port Selection truth table
0 = Output Disable
5
TMDS Output Enable
R/W
1
Disabled TMDS channel and enter standby
mode. Side band signals and I2C circuitry
are still alive.
1 = Output Enable
See Output Enable control table
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Bit
Descriptions
Type
Power Up Condition
Logic Settings
0 = HPD_SINK
4
HPD Input Selection
R/W
0
3
HPD Output Stage selection
R/W
0
1 = I2C Register Setting from B0b[0:3]
Under I2C register control mode,
HPD[A:C] can be individually control by
B0b[0:2] for HPD output.
0 = Open Drain
1 = Output Buffer
I. Byte0 b[4] = 1
When B0b[3] = 0 (open drain mode)
B0b[2]=0, set HPD [C] to Low
2
HPD Port C Logic Setting
R/W
0
B0b[2]=1, set HPD [C] to High by
external pull high resistor
When B0b[3] = 1 (output buffer mode)
B0b[2]=0, set HPD [C] to High
B0b[2]=1, set HPD [C] to Low
I. Byte0 b[4] = 1
When B0b[3] = 0 (open drain mode)
B0b[1]=0, set HPD [B] to Low
HPD Port B Logic Setting
R/W
0
B0b[1]=1, set HPD [B] to High by external pull high resistor
When B0b[3] = 1 (output buffer mode)
B0b[1]=0, set HPD [B] to High
B0b[1]=1, set HPD [B] to Low
I. Byte0 b[4] = 1
When B0b[3] = 0 (open drain mode)
B0b[0]=0, set HPD [A] to Low
0
HPD Port A Logic Setting
R/W
0
B0b[0]=1, set HPD [A] to High by external pull high resistor
When B0b[3] = 1 (output buffer mode)
B0b[0]=0, set HPD [A] to High
B0b[0]=1, set HPD [A] to Low
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Byte 1
Bit
Descriptions
Type
Power Up
Condition
7
Port A RT , Rpd on/off control
R/W
1
6
Port B RT , Rpd on/off control
R/W
1
5
Port C RT , Rpd on/off control
R/W
1
Logic Settings
0 = RT disconnected, Rpd connected
1 = RT connected, Rpd disconnected
0 = RT disconnected, Rpd connected
1 = RT connected, Rpd disconnected
0 = RT disconnected, Rpd connected
1 = RT connected, Rpd disconnected
0 = Disconnected
4
5V_PortC connect
R
0
1 = Connected
INT Flag B1b[1] is set by 5V_PortC edge signal when 5V_PortC
changes from 1 to 0, or from 0 to 1.
0 = Disconnected
3
5V_PortB connect
R
0
1 = Connected
INT Flag B1b[1] is set by 5V_PortB edge signal when 5V_PortB
changes from 1 to 0, or from 0 to 1.
0 = Disconnected
2
5V_PortA connect
R
0
1 = Connected
INT Flag B1b[1] is set by 5V_PortA edge signal when
5V_PortA changes from 1 to 0, or from 0 to 1
0 = INT Flag Clear
1 = INT Flag Set
1
INT Flag
R
0
INT Flag will be set from logic Low to High, when any 5V_Port has
detected plug or unplug transition action.
INT Flag is cleared to low after I2C bus reads the register byte 1.
See INT Flag flowchart.
0 = Passive switch
0
DDC channel selection
R/W
0
1 = Active switch buffer
For power saving operation, passive switch can be selected to further reduce the active power consumption.
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Byte 2
Bit
Descriptions
Type
Power Up
Condition
Logic Settings
7
TMDS AC swing for CML output
setting
R/W
6
TMDS AC swing for CML output
setting
R/W
0
5
TMDS output pull-up resistor
Rout control
R/W
0
4
Output squelch control
R/W
1
3
TMDS output pre-emphasis setting
R/W
0
See OCx truth table
2
TMDS output pre-emphasis setting
R/W
0
See OCx truth table
1
TMDS input equalization setting
R/W
1
See EQx truth table
0
TMDS input equalization setting
R/W
0
See EQx truth table
0
b[7:6] = 00 500mV *Note 1
0 = Disconnect Rout pull-up to VDD, open drain output
1 = Connect Rout pull-up to VDD (3.3V), double termination output
0 = Output squelch disable
1 = Output squelch enable
*Note 2, 3
Note:
1. B2[7:6] : internal use only
2. Output squelch control is used to control TMDS D+/-[0:3], which are set to ‘high impedance /or pull-up to VDD by internal 50W resistor’ when Output squelch is
enable if there is no TMDS input signal. When squelch is disable, TMDS D+/-[0:3] will be unknown if there is no TMDS input signal.
3. squelch control is using CLK channel signal detection. When TMDS input clock frequency is low or swing is small, it will show no input signal.
Equalizer (EQx) Truth Table
TMDS data channel only. TMDS clock channels is 3db fixed
B2b[1]
B2b[0]
0
0
3dB
0
1
6dB
1
0
12dB (default)
1
1
16dB
12-0237
EQ value on TMDS data channels
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
OCx truth table (Swing setting B2b[7:6]=00, 500mv as default)
TMDS output pre-emphasis setting
Setting Value
Note
B2b[5]
B2b[3]
B2b[2]
Single-end Vswing
(mV)
0
0
0
500
0
Open drain
0
0
1
500
1.5
Open drain
0
1
0
500
2.5
Open drain
0
1
1
500
3.5
Open drain
1
0
0
500
0
Double termination
1
0
1
500
1.5
Double termination
1
1
0
500
2.5
Double termination
1
1
1
500
3.5
Double termination
Pre-emphasis (dB)
Default Setting
Port selection truth table
B0b[7]
B0b[6]
TMDS port
DDC port
0
0
CK+/-A, D1+/-A,D2+/-A,D3+/-A
SCL_A/SDA_A
0
1
CK+/-B, D1+/-B,D2+/-B,D3+/-B
SCL_B/SDA_B
1
0
CK+/-C, D1+/-C,D2+/-C,D3+/-C
SCL_C/SDA_C
1
1
No port active
No port active
Data Channel TMDS input termination resistor RT, Rpd Control
Pull-down resistor Rpd active conditions:
1. The Data Channel RT is disconnected controlled by Byte 1 bit[7:5]
2. Output enable control /OE is disable(/OE=High), pull down all channels
3. No normal operation voltage input (but standby voltage SVDD is still On), pull down all channels
Output Enable Control
/OE
I2C B0b[5]
Operation
Low
High
Output Enable
X
Low
Output Disable
High
X
Output Disable
Note: Output disable condition: TMDS channel shut down, output high impedance.
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
INT-Flag flowchart
Power
On Reset
INT-Flag = 0
INT-OUT= 0 (pin)
Any 5V-portA/B/C
from high to low or
from low to high
INT-Flag = 1
INT-OUT=1 (pin)
I2C read out
INT-Flag =0 condition: after I2C read
out INT-Flag bit and Ack from master
is active.
I2C Bus transactions
Data transfers follow the format shown in Fig.1. After the START condition (S), a slave address is sent. This address is 7 bits long
followed by an eighth bit which is a data direction bit (R/W) - a ‘zero’ indicates a transmission (WRITE), a ‘one’ indicates a request
for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still
wishes to communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.
Figure 1: A complete data transfer
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Data is transmitted to the PI3HDMI336 registers using the Write mode as shown in Figure 2. Data is read from the PI3HDMI336
registers using the Read mode as shown in Figure 3
Figure 2 : Write to Control Register
Figure 3 : Read from Control Register
Audio Return channel
There are two ARC input modes. They’re ‘Common mode input’ and ‘single mode input’ but HDMI336 supports ‘single mode input’
only.
Figure 1: ARC single mode input and output
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Figure 2: ARC single mode signal output waveform
+Veh -swing
+Veh - swing
Veh
-Veh-swing
-Veh-swing
Veh = 0~5V
+Veh -swing = 250mV
-Veh-swing = 250mV
DDC Channel Application Diagram
Rup
SCL_SINK
SCL_A
SDA_A
SCL_B
SDA_SINK
SDA_B
SCL_C
SDA_C
3:1
Mux
DDC Source Side
Rup
Controller
Chip
Selectable
DDC Buffer or
Passive Switch
HDMI Sink Device
VOL = 0.7V/0.85V
VOL = External
VIH >= 2V
VIL =< 0.4V
I2C block uses "low VIL <= 0.4V and 0.7V <= 0.85V" to define the signal direction, exit from system lock
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
HPD[A:C] Output Diagram
From HPD_sink
or I2C byte0[2:0]
HPD
Output
Buffer
300K Ohm
Weak
Pull-down
No
Note:
1. HPD output block support by SVDD power.
2. During normal or standby mode, the HPD block is active. HPD signal output is programmed by the control register.
3. Open drain buffer is recommended with a 1Kohm pull-up resistor to 5V. If HPD output buffer is selected, external buffer transistor is required to avoid 5V to
3.3V leakage.
HPD[A:C] truth table:
B0b[4]=0, HPD_Sink input; B0b[3]=0, HPDx open drain output
HPD input select
Port selection
B0b[4]=0
HPD output select
B0b[3]=0
HPDA
HPDB
HPDC
Port A
HPD_Sink
Open drain
HPD_Sink
L
L
Port B
HPD_Sink
Open drain
L
HPD_sink
L
Port C
HPD_Sink
Open drain
L
L
HPD_sink
No port active
HPD_Sink
Open drain
L
L
L
B0b[4]=0, HPD_Sink input; B0b[3]=1, HPDx inverter output
HPD input select
HPD output select
Port selection
B0b[4]=0
B0b[3]=1
HPDA
HPDB
HPDC
Port A
HPD_Sink
Buffer
/HPD_Sink
H
H
Port B
HPD_Sink
Buffer
H
/HPD_sink
H
Port C
HPD_Sink
Buffer
H
H
/HPD_sink
No port active
HPD_Sink
Open drain
H
H
H
B0b[4]=1, I2C register input; B0b[3]=0, HPDx open drain output
HPD input select
HPD output select
Port selection
B0b[4]=1
B0b[3]=0
HPDA
B0b[3]=0
HPDA
HPDB
HPDC
Port [A:C]
B0b[2:0]
Open drain
No port active
B0b[2:0]
Open drain
12-0237
12
HPDB
HPDC
B0b[0]
B0b[1]
B0b[2]
B0b[0]
B0b[1]
B0b[2]
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
B0b[4]=1, I2C register input; B0b[3]=1, HPDx inverter output
HPD input select
HPD output select
Port selection
B0b[4]=1
B0b[3]=1
HPDA
HPDB
HPDC
Port [A:C]
B0b[2:0]
Buffer
/B0b[0]
/B0b[1]
/B0b[2]
No port active
B0b[2:0]
Buffer
/B0b[0]
/B0b[1]
/B0b[2]
Absolute Maximum Ratings
Supply Voltage to Ground Potential .................................................... 5.5V
All Inputs and Outputs .................................................-0.5V to VDD+0.5V
Ambient Operating Temperature ............................................ -20 to +85°C
Storage Temperature ............................................................. -65 to +150°C
Junction Temperature ........................................................................150°C
Soldering Temperature ......................................................................260°C
Note: Stresses greater than those listed under MAXI-
MUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Typ.
Max.
Unit
-20
+85
°C
+3.0
+3.6
V
DC Specification
VDD = 3.3V ±10%,
Symbol
Parameter
VDD
Operating Voltage
IDD
VDD Supply Current
Conditions
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
Output Enable ( open drain 500mv
signal-end 0dB pre-emphasis)
80
92
mA
Output Enable ( double termination,
500mv signal-end 0dB pre-emphasis)
170
210
mA
IDDQ
VDD Quiescent Supply Current
TMDS Output Disable, ARC_OUT=0
3
mA
Istb
Standby mode
VDD =0V, SVDD =3.6V, DDC passive
switch, HPD_x=0
1
mA
VIH_5V_A,
VIH_5V_B,
VIH_5V_C
Input High Voltage
of 5V ports
VIL_5V_A,
VIL_5V_B,
VIL_5V_C
Input Low Voltage of
5V ports
12-0237
V
0.7*SVDD
0.3*SVDD
13
V
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
DC Specification Cont..
Symbol
Parameter
Conditions
Min.
VOL_HPD
Buffer Output Low
Voltage
IOL = 4 mA
Open Drain Output
Low Voltage
IOL = 4 mA
0
VOH_HPD
Buffer Output High
Voltage
IOH = 1 mA
SVDD -1.1
IOFF_HPD
Off leakage current
IOZ_HPD
Open drain Output
leakage current
Typ.
Max.
Unit
0.4
V
0.4
V
V
VDD =0, SVDD =0, VIN=3.6V
10
VDD =0, SVDD =0, VIN=5.5V
20
SVDD =3.6, VIN=3.6V
25
SVDD =3.6, VIN=5.5V
35
uA
HPD_sink
IIH
High level digital
input current
VIH =VDD
-10
40
μA
IIL
Low level digital
input current
VIL = GND
-10
10
μA
VIH
High level digital
input voltage
VIL
Low level digital
input voltage
2.0
V
SVDD =3.3v
0
0.8
V
Control pin (/OE)
IIH
High level digital
input current
VIH =VDD
-10
40
μA
IIL
Low level digital
input current
VIL = GND
-10
10
μA
VIH
High level digital
input voltage
2.0
VIL
Low level digital
input voltage
0
V
0.8
V
0.4
V
INT_OUT
VOL_INT_OUT
Output open drain
Low Voltage
VOH_INT_OUT
High impedance,
depended on external External pull-up Rup to VDD from
pull high resistor and 1.5kΩ to 5kΩ
power supplier
IOFF_INT_OUT
Off leakage current
IOL = 4 mA
V
VDD -1
VDD =0, SVDD =0, VIN=3.6V
10
VDD =0, SVDD =0, VIN=5.5V
20
uA
12-0237
14
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
DDC Channel Block
Symbol
Parameter
VIH_DDC(source)
Source Side DDC Buffer Input
High Voltage
VIL_DDC(source)
Source Side DDC Buffer Input
Low Voltage
VOL_DDC(source)
Source Side DDC Buffer Output Low Voltage,
External pull-up Rup to VDD
from 1.5kΩ to 5kΩ
VOL_DDC(sink)
Sink Side DDC Buffer Output
Low Voltage,
External pull-up Rup to VDD
from 1.5kΩ to 5kΩ
VIH_DDC(sink)
Sink Side DDC Buffer Input
High Voltage,
VIL_DDC(sink)
Sink Side DDC Buffer Input
Low Voltage,
ILK
Input leakage current
DDC switch is off
CIO
Input/Output capacitance
when passive switch on
VI peak-peak = 1V, 100 KHz
10.5
RON
Passive Switch resistance
IO = 3mA, VO = 0.4V
30
50
Ω
Vpass
Switch Output voltage
2.0
2.8
V
CI(source)
Source side DDC capacitance
When active switch on or passive switch off.
VI peak-peak = 1V, 100 KHz
4.0
pF
CI(sink)
Sink side DDC capacitance
when active switch on or passive switch off.
VI peak-peak = 1V, 100 KHz
6.0
pF
VOH_DDC
(source/sink)
DDC Switch Output High
Voltage
12-0237
Conditions
Min.
Typ.
Max.
Unit
V
0.7*SVDD
0.3*SVDD V
0.7
0.4
V
0.85
V
2.0
VI=3.3V, II=100uA
SVDD =3.3V
V
-10
1.5
0.4
V
10
uA
pF
VIN=3.3V.
External pull-up Rup to VDD
from 1.5kΩ to 5kΩ
15
VDD - 1
V
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
AC Characteristics (over recommended operating conditions unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Units
TMDS Differential Pins
tpd
Propagation delay
2000
tr
Differential output signal rise
time (20% - 80%)
tf
Differential output signal fall
time (20% - 80%)
tsk(p)
Pulse skew
tsk(D)
Intra-pair differential skew
tsk(o)
Inter-pair differential skew
tjit(pp)
Peak-to-peak output jitter CLK
residual jitter
VDD = 3.3V, Rout = 50Ω
150
Residual Jitter
ps
10
50
23
50
100
(2)
Peak-to-peak output jitter DATA
tjit(pp)
150
Data Input = 1.65 Gbps HDMI
data pattern
CLK Input = 165 MHz clock
15
30
ps
18
50
ps
tSX
Select to switch output
10
ns
ten
Enable time
600
ns
tdis
Disable time
10
ns
DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK)
Propagation delay from SCLn
to SCL_SINK or SDAn to SDA_
SINK or SDA_SINK to SDAni in
passive or active SW.
tpd
CL = 10pF, in passive switch
1.5
CL = 10pF, in active switch,
SVDD=3.3v, Rup=2k
7.5
DDC I/O Pins (HPD_SINK, HPD inverter output)
tpd(HPD)
Propagation delay (from HPD_
SINK to the active port of HPD)
tsx(HPD)
Switch time (from port select to
the latest )
2.5
ns
*Note 1
CL = 10pF
2
6.0
3
6.5
ns
Note:
1. t plh time of HPD open drain output, depends on external pull high resistor and load capacitor.
12-0237
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PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
TMDS differential pins
Symbol
Parameter
VOH
Single-ended high level output voltage
VOL
Max.
Units
VDD+10
VDD -10
mV
Single-ended low level output voltage
VDD -600
VDD –400
mV
Vswing
Single-ended output swing voltage
400
600
mV
VOD(O)
Overshoot of output differential voltage
180 1
mV
VOD(U)
Undershoot of output differential voltage
200 2
mV
VOC(SS)
Change in steady-state common- mode
output voltage between logic states
5
mV
IOS
Test Conditions
Min.
Typ.
VDD = 3.3V, Rout=50Ω
Short Circuit output current
-12
12
mA
Short Circuit output current at double
termination mode
-24
24
mA
VDD+10
mV
55
Ohm
10
μA
VI(open)
Single-ended input voltage under high
impedance input or open input
II = 10uA
VDD -10
RT
Input termination resistance
VIN = 2.9V
45
IOZ
Leakage current with Hi-Z I/O
50
VDD = 3.6V,
SVDD = 3.6V
Note:
1. Overshoot of output differential voltage VOD(O) = (VSWING(MAX) * 2) * 15%,
2. Undershoot of output differential voltage VOD(O) = (VSWING(MIN) * 2) * 25%
SPDIF & ARC Pins, See ARC single mode waveform
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
IIH_SPDIF
High level input current
VDD=3.6V, VIH =3.6V
500
uA
IIL_SPDIF
Low level input current
VDD=3.6V, VIL = GND
350
uA
Vel
Single mode input/output Vel DC voltage level
0
5.0
V
Vel swing SPDIF Single mode input swing
0.2
0.6
V
Vel swing ARC_
Single mode ARC output swing
OUT
0.4
0.6
V
0.5
Ro
Output resistance of ARC output stage
tr
ARC output rise time (10% to 90%)
< 0.4UI (fclock = 6.144MHz) **
25
ns
tf
ARC output fall time (10% to 90%)
< 0.4UI (fclock = 6.144MHz) **
25
ns
TJpp
ARC signal peak to peak jitter
< 0.05UI (fclock = 6.144MHz)
3
ns
12-0237
55
17
Ohm
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Packaging Mechanical: 64-Pin LQFP (FB)
Notes:
1. JEDEC OUTLINE: MS-026 BBD
2. Dimensions D1 and E1 Do not include mold protrusion.
Allowable protrusion is 0.25mm per side. D1 and E1 are
maximum plastic body size dimensions including mold mismatch.
3. Dimension b does not include Dambar protrusion. Allowable Dambar
protrusion shall not cause the lead width to exceed the maximum b
dimension by more than 0.08mm.
DATE: 05/18/11
DESCRIPTION: 64-contact, Low Profile Quad Flat Package (LQFP)
PACKAGE CODE: FB (FB64)
DOCUMENT CONTROL #: PD-2099
REVISION: --
11-0064
1.
Pericom Semiconductor Corporation • 1-800-435-2336
12-0237
18
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Related Products
Part Number
Product Description
PI3HDMI1201
DisplayPort 1.2 Re-driver with built-in AUX listener
PI3VDP1430
Dual Mode DisplayPort to HDMI Level Shifter and Re-driver
PI3HDMI511
3.4G HDMI1.4 Re-driver for Source-side application, supporting Dual Mode DisplayPort
PI3HDMI611
3.4G HDMI1.4 Re-driver for Sink-side application, supporting Dual Mode DisplayPort
PI3VDP3212
2-Lane DisplayPort1.2 Compliant Switch
PI3VDP12412
4-Lane DisplayPort1.2 Compliant Switch
PI3HDMI412AD
1:2 Active 3.4Gbps HDMI1.4 compliant Splitter/Re-driver
PI3HDMI521
2:1 3.4Gbps HDMI1.4 Switch/Re-driver with built-in ARC and Fast Switching support for Sink Application
PI3HDMI621
2:1 3.4Gbps HDMI1.4 Switch/Re-driver with built-in ARC and Fast Switching support for Sink Application
PI3HDMI336
3:1 Active 3.4Gbps HDMI Switch/Re-driver with I2C control and ARC Transmitter
Reference Information
Document
Description
VESA DisplayPort Standard Version 1 Revision 2, Video Electronics Standards Association, January 5, 2010
VESA DisplayPort Dual-Mode Standard Version 1, Video Electronics Standards Association, February 10,
2012
VESA
VESA DisplayPort Interoperability Guideline Version 1.1a, Video Electronics Standards Association, February 5, 2009
HDMI
High-Definition Multimedia Interface Specification Version 1.4, HDMI Licensing, LLC, June 5, 2009
Ordering Information
Ordering Code
Package Code
Package Type
PI3HDMI336FBE
FB
Pb-free & Green, 64-pin LQFP
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
12-0237
19
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Revision History
Date
Changes
7/28/2012
Block diagram, Reference Schematic
12-0237
20
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Appendix: Eye Diagram at 1920x1080p
Input: Quantum Data + HDMI Cable
DUT Setting: Selected Port = Port C; HPD = Open Drain; TMDS = Open Drain/CML, RT connected, 500mV, 0dB Pre-emphasis
Output: HDMI-SMA Test Fixture + Agilent 54855A DSO
D1 Eye at 1920x1080p 12bit, 12dB EQ, 2m Cable, Open Drain
D1 Eye at 1920x1080p 12bit, 12dB EQ, 10m Cable, Open Drain
D1 Eye at 1920x1080p 8bit, 12dB EQ, 20m Cable, Open Drain
D1 Eye at 1920x1080p 8bit, 16dB EQ, 30m Cable, Open Drain
12-0237
21
www.pericom.com07/28/2012
PI3HDMI336
3:1 ActiveEye™ HDMI™ Switch with
I2C Control & ARC Transmitter
Appendix: Reference Schematic
5
4
3
2
1
HPD_C
D205
3
+3V3
2
1
Q201
MMBT3904
R210
SDA_A
SCL_A
4K7
C203
C204
C205
C206
0.1u
0.1u
3
C202
0.1u
2
C201
3
68K
2
1
4K7 2
3
4K7
R225
1K
1
2
3
R219
+5V_C
R226
68K
1
Q206
MMBT3904
2
HPD_sink
SDA_sink
SCL_sink
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
C207
1u
OUTPUT
C208
1u
SPDIF_IN
L1
1
2
ARC_OUT
CK+_D
D0-_D
FerriteBead_1206
D0+_D
D1-_D
J2
SPDIF_IN
RCA JACK
1
2
2
SDA_CTL
SCL_CTL
I2C_ADR
D2-_A
D2+_A
/OE
INT_OUT
D1-_A
D1+_A
CK-_A
CK+_A
D0-_A
D0+_A
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SDA_sink
SCL_sink
SPDIF_IN
CEC_D
CK-_D
J1
D2+_B
100K
HPD_sink
+5V_D
ARC_OUT
D1+_D
D2-_D
RCA JACK
D2+_D
HPD
+5V
PGND
SDA
SCL
HEAC+
CEC
CKCK SHIELD
CK+
D0D0 SHIELD
D0+
D1D1 SHIELD
D1+
D2D2 SHIELD
D2+
SDA_A
SCL_A
ARC_OUT
CEC_D
CK-_A
R216
4K7
4K7
C
A0
0xA8
0
0xAA
1
+3V3SB
1K
R214
R215
47K
R213
47K
R209
R207
+5V_A
R208
INPUT1
19
HPD
18
+5V
17
PGND
16
SDA
15
SCL
14
HEAC+
13
CEC
12
CK11
CK SHIELD
10
CK+
9
D08
D0 SHIELD
7
D0+
6
D15
D1 SHIELD
4
D1+
3
D22
D2 SHIELD
1
D2+
1K/ NC
CONN_HDMI-R
I2C_ADDRESS
SHELL3
SHELL4
R227
D1-_D
D1+_D
D2-_D
D2+_D
22
23
CK-_D
CK+_D
D0-_D
D0+_D
D0+_B
D1-_B
D1+_B
D2-_B
D
1
Q205
MMBT3904
LED_G
HPD_Sink
SDA_Sink
SCL_Sink
VDD
CKCK+
D1D1+
GND
D2D2+
D3D3+
VDD
SPDIF_IN
ARC_Out
PI3HDMI336
R224
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CK+_B
D0-_B
2
SHELL1
SHELL2
3
R206
CEC_D
CK-_B
3
2
1
JP212
1
20
21
D1-_B
D1+_B
D2-_B
D2+_B
HPD_A
HPD_B
SDA_B
SCL_B
CK-B
CK+B
GND
D1-B
D1+B
VDD
D2-B
D2+B
D3-B
D3+B
HPD_A
SDA_A
SCL_A
1K
55
D0-_B
D0+_B
47K
47K
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SDA_B
SCL_B
CK-_B
CK+_B
4K7
R223
R220
3
JP213
R211
1
Q202
MMBT3904
+5V_B
1K
R205
1
Q204
MMBT3904
D207
+3V3
+3V3SB
D208
/OE is pulled down at 100k ohm.
I2C_ADR is pulled up at 100k ohm.
R217
2INT_OUT
1K 1
LED_G
CK+_A
D0-_A
D0+_A
D1-_A
D1+_A
D2-_A
D2+_A
CONN_HDMI-R
B
POWER
D202
B0520LW
D203
B0520LW
8
7
6
5
A0 VCC
A1
WP
A2 SCL
GND SDA
8
7
6
5
+
1
ADJ/GND
R228
NP
+
C212
10K
0.1u
C211
10K
C210
0.1u
1
2
3
4
EDID_WPA
SCL_A
SDA_A
JP217 +3V3
U204
AT24C02B
1
2
3
4
EDID_WPB
SCL_B
SDA_B
A0 VCC
A1
WP
A2 SCL
GND SDA
8
7
6
5
R230
A0 VCC
A1
WP
A2 SCL
GND SDA
+3V3SB
U205 REG1117-3.3V
3
2
VIN VOUT
+5V_C
U203
AT24C02B
R231
1
2
3
4
R232
C209
0.1u
U202
AT24C02B
JP216 +5V
R229 0
USB 2.0 Mini B Female
1
2
D204
B0520LW
C213
JP211
+5V_USB
100u
EDID_WPC
JP210
1
2
3
4
5
4.7u
1
2
EDID_WPB
VBUS
DD+
ID
GND
+5V_B
10K
+5V_A
JP208
1
2
SDA_CTL
EDID_WPA
1
2
SDA_C
SCL_CTL
JP206
JP207
1
2
SCL_C
JP204
1
2
1
2
1
2
JP205
1
2
SDA_B
1
2
SDA_A
SCL_B
JP202
1
2
SCL_A
JP203
1
2
JP209
JP201
1u C214
+5V_C
1
2
+5V_B
+5V_D
1u C215
D201
B0520LW
22u C216
+5V_A
J0
A
68K
JP215 +5V
R218
3
2
1
CK-A
CK+A
D1-A
D1+A
VDD
D2-A
D2+A
GND
D3-A
D3+A
/OE
INT_OUT
SVDD
SDA_CTL
SCL_CTL
I2C_ADR
HPD_B
4K7
21
20
23
22
SHELL4
SHELL3
0.1u
1
2
3
+5V_A
+5V_B
+5V_C
CK+_C
CK-_C
SCL_C
SDA_C
D0+_C
D0-_C
D3+C
D3-C
D2+C
D2-C
VDD
D1+C
D1-C
GND
CK+C
CK-C
SCL_C
SDA_C
HPD_C
5V_portA
5V_portB
5V_portC
U201
D2+_C
SDA_B
SCL_B
R222
+5V_B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D1+_C
D2-_C
CONN_HDMI-R
SHELL2
SHELL1
+5V_A
LED_G
+3V3SB
2
21
20
23
22
SHELL4
SHELL3
SHELL2
SHELL1
D2+_C
D2-_C
D1+_C
D1-_C
+3V3
R204
2
D206
D0+_C
D1-_C
INPUT2
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
JP214
CK+_C
D0-_C
HPD
+5V
PGND
SDA
SCL
HEAC+
CEC
CKCK SHIELD
CK+
D0D0 SHIELD
D0+
D1D1 SHIELD
D1+
D2D2 SHIELD
D2+
1K
LED_G
+3V3
CEC_D
CK-_C
HPD_A
21
20
0.1u
47K
SDA_C
SCL_C
HPD_B
B
1
Q203
MMBT3904
1K
CONN_HDMI-R
C
JP212: 2-1
JP213: 2-1
JP214: 2-1
R221
+3V3SB
0.1u
47K
R203
R201
R202
23
22
SHELL4
SHELL3
SHELL2
SHELL1
D
INPUT3
19
HPD
18
+5V
17
PGND
16
SDA
15
SCL
14
HEAC+
13
CEC
12
CK11
CK SHIELD
10
CK+
9
D08
D0 SHIELD
7
D0+
6
D15
D1 SHIELD
4
D1+
3
D22
D2 SHIELD
1
D2+
Output Buffer
R212 4K7
Open Drain
JP212: 2-3
JP213: 2-3
JP214: 2-3
+5V_C
2
HPD Output
Connection
HPD_C
+3V3
A
EDID_WPC
SCL_C
SDA_C
Title
PI3HDMI336_Demoboard_Independent_EDID
Size
C
Date:
5
4
3
2
Document Number
<Doc>
Rev
A
Sheet
Thursday, January 13, 2011
1
of
1
1
Appendix: Evaluation Board Image
12-0237
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www.pericom.com07/28/2012