PI6C557-05B

PI6C557-05B
PCIe® 3.0 Clock Generator with 4 HCSL Outputs
Product Features
Description
• PCIe® 3.0 complaint
The PI6C557-05B is a spread spectrum clock generator compliant to PCI Express® 3.0 and Ethernet requirements. The device is used
for PC or embedded systems to substantially reduce Electromagnetic
Interference (EMI).
→PCIe 3.0 Phase jitter: 0.48ps RMS (High Freq. Typ.)
• LVDS compatible outputs
• Supply voltage of 3.3V ±5%
The PI6C557-05B provides four differential (HCSL) or LVDS
spread spectrum outputs. The PI6C557-05B is configured to select
spread and clock selection. Using Pericom's patented Phase-Locked
Loop (PLL) techniques, the device takes a 25MHz crystal input
and produces four pairs of differential outputs (HCSL) at 100MHz
and 200MHz clock frequencies. It also provides spread selection
of -0.5%, -1.0%, -1.5%, and no spread.
• 25MHz crystal or clock input frequency
• HCSL outputs, 0.7V Current mode differential pair
• Jitter 40ps cycle-to-cycle (typ)
• Spread of -0.5%, -1.0%, -1.5%, and no spread
• Industrial temperature range
• Spread Bypass option available
• Spread and frequency selection via external pins
• Packaging: (Pb-free and Green)
→20-pin, 173-mil wide TSSOP
Pin Configuration
Block Diagram
VDD
2
S[2:0]
3
Spread
Spectrum/
Output
clock
selection
OE
SS Circuitry
CLK0
CLK0
CLK1
CLK1
CLK2
CLK2
CLK3
CLK3
PLL
X1/CLK
25 MHz
Crystal
crystal
Driver
or clock X2
Pulling
Capacitors
PD
2
Rr(IREF)
GND
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VDDXD
1
20
CLK0
S0
2
19
CLK0
S1
3
18
CLK1
S2
4
17
CLK1
X1
5
16
GNDODA
X2
6
15
VDDODA
PD
7
14
CLK2
OE
8
13
CLK2
GNDXD
9
12
CLK3
10
11
CLK3
IREF
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Pin Description
Pin #
2
3
4
5
6
7
8
Pin Name
VDDXD
S0
S1
S2
X1
X2
PD
OE
I/O Type
Power
Input
Input
Input
Input
Output
Input
Input
9
10
11
GND
IREF
CLK3
Power
Output
Output
Description
Connect to a +3.3V source.
Spread Spectrum Select pin #0. See Spred Spectrum Selec table. Internal pull-up resistor.
Spread Spectrum Select pin #1. See Spred Spectrum Selec table. Internal pull-up resistor.
Spread Spectrum Select pin #2. See Spred Spectrum Selec table. Internal pull-up resistor.
Crystal connection.
Crystal connection.
Power down. Internal pull-up resistor.
Output enable. Tri-states output (High=enable outputs); Low=disable outputs). Internal
pull-up resister.
Connect to digital circuit ground.
Precision resistor attached to this pin is connected to the internal current reference.
Selectable 100/200 MHz Spread Spectrum differential compliment output clock 3.
12
13
14
15
16
17
18
19
20
CLK3
CLK2
CLK2
VDDODA
GND
CLK1
CLK1
CLK0
CLK0
Output
Output
Output
Power
Power
Output
Output
Output
Output
Selectable 100/200 MHz Spread Spectrum differential true output clock 3.
Selectable 100/200 MHz Spread Spectrum differential compliment output clock 2.
Selectable 100/200 MHz Spread Spectrum differential true output clock 2.
Connect to a +3.3V analog source.
Output and Analog circuit ground
Selectable 100/200 MHz Spread Spectrum differential compliment output clock 1.
Selectable 100/200 MHz Spread Spectrum differential true output clock 1.
Selectable 100/200 MHz Spread Spectrum differential compliment output clock 0.
Selectable 100/200 MHz Spread Spectrum differential true output clock 0.
1
Table 2: Spread Selection Table
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
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Spread %
-0.5
-1.0
-1.5
No Spread
-0.5
-1.0
-1.5
No Spread
Spread Type
Down
Down
Down
Not Applicable
Down
Down
Down
Not Applicable
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Output Frequency
100
100
100
100
200
200
200
200
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Output Structures
Application Information
Decoupling Capacitors
Decoupling capacitors of 0.01μF or 0.1μF must be connected
between each VDD pin and the PCB ground plane and placed as
close to the VDD pin as possible.
IREF =2.3mA
6*IREF
PI6C557-05B must be isolated from system power supply noise
to perform optimally.
Crystal
Use a 25MHz fundamental mode parallel resonant crystal with
less than 30PPM of error across temperature.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance is 50-Ohm, then RR = 475-Ohm providing an IREF of 2.32 mA. The output
current (IOH) is 6*IREF.
R R=475 Ω
See Output Termination
Sections
Output Termination
The PCI-Express differential clock outputs of the PI6C557-05B
are open source drivers and require an external series resistor
and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout
Guidelines section.
The PI6C557-05B can be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout Guidelines
section.
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
L1 length, route as non-coupled 50-Ohm trace.
L2 length, route as non-coupled 50-Ohm trace.
L3 length, route as non-coupled 50-Ohm trace.
RS
RT
Dimension or Value
0.5 max
0.2 max
0.2 max
33
49.9
Unit
inch
inch
inch
Ohm
Ohm
Differential Routing on a Single PCB
L4 length, route as coupled microstrip 100-Ohm differential trace.
L4 length, route as coupled stripline 100-Ohm differential trace.
Dimension or Value
2 min to 16 max
1.8 min to 14.4 max
Unit
inch
inch
Differential Routing to a PCI Express connector
L4 length, route as coupled microstrip 100-Ohm differential trace.
L4 length, route as coupled stripline 100-Ohm differential trace.
Dimension or Value
0.25 min to 14 max
0.225 min to 12.6 max
Unit
inch
inch
PCI-Express Device Routing
L1
RS
L1’
L2
L4
L4’
L2’
RS
PI6C557-05
Output
Clock
RT
L3’
RT
L3
PCI-Express
Load or
Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0
tOR
500 ps
500 ps
0.52 V
0.175 V
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tOF
0.52 V
0.175 V
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Application Information
LVDS Recommendations for Differential Routing
L1 length, route as non-coupled 50-Ohm trace.
L2 length, route as non-coupled 50-Ohm trace.
RP
RQ
RT
L3 length, route as 100Ω differential trace.
L3 length, route as 100Ω differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
Ohm
Ohm
Ohm
LVDS Device Routing
L1
L3
RQ
L3’
L1’
RT
PI6C557-05
Clock
Output
RP
RT
L2’
L2
LVDS
Device
Load
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
500 ps
1250 mV
1150 mV
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tOF
1250 mV
1150 mV
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P-0.1
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Electrical Specifications
Maximum Ratings
Supply Voltage to Ground Potential.......................................................... 5.5V
All Inputs and Outputs...................................................... -0.5V to VDD+0.5V
Ambient Operating Temperature................................................. -40 to +80°C
Storage Temperature.................................................................. -65 to +150°C
Junction Temperature . ...........................................................................150°C
Soldering Temperature . .........................................................................260°C
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ESD Protection (Input) .................................................... 2000 V min (HBM)
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
3.135
Typ.
Max.
+85
3.465
Unit
°C
V
Max.
3.465
VDD +0.3
0.8
Unit
V
V
V
5
µA
120
50
100
7
6
5
mA
mA
µA
pF
pF
nH
kΩ
DC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85oC)
Symbol
VDD
VIH
VIL
IIL
IDD
IDDOE
IDDPD
CIN
COUT
LPIN
ROUT
Parameter
Supply Voltage
Input High Voltage(1)
Input Low Voltage(1)
Conditions
Min.
3.135
2.0
GND -0.3
Without input pull-up
and pull-downs
RL = 50Ω, CL = 2pF @100MHz
Operating Supply Current
OE = LOW
No load PD = LOW
Input Capacitance
Input pin capacitance
Output Capacitance
Output pin capacitance
Pin Inductance
Output Resistance
CLK Outputs
Input Leakage Current
0 < Vin < VDD
Typ.
3.3
-5
105
40
60
3.0
Note:
1. Single edge is monotonic when transitioning through region.
AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85oC)
Symbol
FIN
Parameter
Input Frequency
VOUT
Output Frequency
VOH
VOL
VCPA
VCN
JCC
Output High Voltage (1,2)
Output Low Voltage(1,2)
Crossing Point Voltage(1,2)
Crossing Point Voltage(1,2,4)
Jitter, Cycle-to-Cycle(1,3)
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Conditions
HCSL terminal
LVDS terminal
@VDD = 3.3V
Absolute
Variation over all edges
Min.
660
-150
250
Typ.
25
700
0
350
40
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Max.
200
100
850
27
550
140
60
P-0.1
Unit
MHz
MHz
mV
mV
mV
mV
ps
04/29/11
PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Symbol
JRMS2.0
JRMS3.0
MF
tOR
tOF
TSKEW
TDUTY-CYCLE
TOE
TOT
tSTABLE
tSPREAD
Parameter
PCIe 2.0 RMS Jitter
Conditions
PCI-SIG jitter test method
PLL L-BW @ 2M & 5M 1st H3
PLL L-BW @ 2M & 4M 1st H3
PLL H-BW @ 2M & 5M 1st H3
PLL H-BW @ 2M & 4M 1st H3
Spread Spectrum
From 0.175V to 0.525V
From 0.525V to 0.175V
At Crossing Point Voltage
PCIe 3.0 RMS Jitter
Modulation Frequency
Rise Time(1,2)
Fall Time(1,2)
Skew between outputs
Duty Cycle(1,3)
Output Enable Time(5)
Output Disable Time(5)
From power-up to VDD=3.3V
Min.
Typ.
30
175
175
2.1
2.38
0.48
0.47
31.5
332
344
3.0
Unit
ps
ps
ps
ps
ps
kHz
ps
ps
ps
%
μs
μs
ms
3.0
ms
45
Setting period after spread change
All outputs
All outputs
From Power-up VDD=3.3V
Setting period after spread
change
Max.
3.1
3
3
1
1
33
700
700
50
55
10
10
Notes:
1. RL = 50-Ohm with CL = 2 pF and RR
2. Single-ended waveform
3. Differential waveform
4. Measured at the crossing point
5. CLK pins are tri-stated when OE is LOW
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Case
Conditions
Still air
Min.
Typ.
Max.
93
20
Unit
°C/W
°C/W
Recomended Crystal Specification
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500081, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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PI6C557-05B
PCIe 2.0/3.0 Clock Generator with 4 HCSL Outputs
Packaging Mechanical: 20-pin TSSOP (L)
DOCUMENT CONTROL NO.
PD - 1311
20
REVISION: E
DATE: 03/09/05
.169
.177
1
.252
.260
6.4
6.6
.004 0.09
.008 0.20
.047
1.20
Max
1
.0256
BSC
0.65
4.3
4.5
.007
.012
0.19
0.30
0.45
0.75
SEATING
PLANE
.018
.030
.238
.269
6.1
6.7
.002 0.05
.006 0.15
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2336 • www.pericom.com
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AC
DESCRIPTION: 20-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
Ordering Information(1-3)
Ordering Code
Package Code
PI6C557-05BLE
L
PackageType
Pb-free & Green, 20-Pin TSSOP
Note:
1. Thermal characteristics and package top marking information can be found at http://www.pericom.com/packaging/
2. E = lead-free and green packaging
3. Adding an X suffix = tape/reel
Pericom Semiconductor Corporation • www.pericom.com
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PCI®, PCI-X®, PCIe®, PCI Express® and PCI-SIG® are registered trademarks of
the PCI-SIG® (www.pcisig.org).
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