333 PI3EQX6801ZDE PI3EQX6801 SATA ReDriver Application Note Table of Contents General Introduction ............................................................................................................................. 2 How to Use Control Pins for Various Application .................................................................................. 3 External Component Requirement........................................................................................................ 4 Layout Design Guide ............................................................................................................................ 5 Power-Supply Bypass........................................................................................................................... 6 Power Supply Sequencing.................................................................................................................... 6 Equalization Setting .............................................................................................................................. 6 Output Swing Setting ............................................................................................................................ 8 Pre-emphasis Setting............................................................................................................................ 9 Typical Application Circuit................................................................................................................... 10 PCB Layout Sample............................................................................................................................ 12 Page 1 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 General Introduction PI3EQX6801 SATA ReDriverTM device is developed to redrive one full lane of SAS/SATA up to 6Gbps signal. The device has built-in continuous step output swing/pre-emphasis adjustment features, and delivers solid performance. Packaging: 20-contact TQFN (4x4mm) Main Application: Server Desktop Storage/Workstation Figure 1a: Example of Typical Application Figure 1b: Example of Typical Application Page 2 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 How to Use Control Pins for Various Application PI3EQX6801 device comes with control pins: EN, OOB, TDet_EN# AB/BB, and A_EQ/B_EQ. Table1 is the setting selection for various applications. Pins Function Description Setting Selection A_EN# B_EN# Channel Enable Function w/ internal 200k pull-down resistor High: Power-down mode Low: Normal Operation (default) DNC Do NOT connect Only for 3.3Vapplication For 3.3V application, it must be not connected. For 1.5V application, it must be connected to 1.5V. A_EM B_EM Output Emphasis Adjustment They allow analog resistive adjustment by the resistor to connect to GND. ( Note, recommend to use under 4.0dB Pre-emphasis) A_OS B_OS Output Swing Adjustment A_EQ B_EQ Input Equalizer Adjustment Tri-level control They allow analog resistive adjustment by the resistor to connect to GND. ( Note, recommend to use 600mV for SATA application, 1000mV for SAS application) Table 1: Setting Selection for Various Applications PI3EQX6801 can work with 1.5V or 3.3V power supply. Table 2 below lists the power consumption for reference. Power consumption (typical, mW) Slumber mode HDD unplug Power Supply Active (at 600mV Swing, 0db pre-emphasis) 1.5V Power 162 22.5 1.5 0.089 3.3V Power 356 50 3.3 1.82 Standby (Max.) Table 2: Power Consumption Page 3 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Note: PI3EQX6801 has the same pin-out and pin assignment as PI3EQX6701x. 1. If the customer currently uses PI3EQX6701x under +3.3V power application and intends to upgrade to PI3EQX6801, some changes MUST be taken care. Resistor values on x_EM and x_OS pins should be changed based on the 3rd page of PI3EQX6801 datasheet. The control on x_EQ pins of PI3EQX6801 is tri-level selection, Low/Open/High. A_EQ B_EQ PI3EQX6701C PI3EQX6701D PI3EQX6701E Low 1dB 7dB 1dB High 4dB 11dB 4dB Low 1dB 7dB 7dB High 4dB 11dB 11dB PI3EQX6801 2. If the customer currently uses PI3EQX6701x under +1.2V power application, PI3EQX6801 is not recommended because +1.5V power is required. External Component Requirement PI3EQX6801ZDE requires AC coupling capacitors for all redriver outputs. High-quality, low-ESR, X7R, 10nF, 0402sized capacitors are recommended Page 4 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Layout Design Guide Layout Considerations for Differential Pairs - The trace length miss-matching shall be less than 5 mils for the “+” and “–“ traces in the same pairs - Use wider trace width, with 100ohm differential impedance, to minimize the loss for long routes - Target differential Zo of 100ohm ±20% - More pair-to-pair spacing for minimal crosstalk coupling, it is recommended to have >3X gap spacing between differential pairs. - It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces - The use of vias should be avoided if possible, if vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. - Route the differential signals away from other signals and noise sources on the printed circuit board PCB Layout Trace Routings Figure 2: Layout Sample for Trace Routings Page 5 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Power-Supply Bypass Designers are advised to pay careful attention the details associated with high-speed design as well as providing a clean power supply; there are some approaches as recommendation. The supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The distance to plane should be <50mil. The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. Careful attention to supply bypassing through the proper use of bypass capacitors is required. A low-ESR 0.01uF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to PI3EQX6801ZDE. Smaller body size capacitors can help facilitate proper component placement. The distance of capacitors to IC body should be <100mil. One capacitor with capacitance in the range of 1uF to 10uF should be incorporated in the power supply bypassing design as well. It is can be either tantalum or an ultra-low ESR ceramic. Power Supply Sequencing Proper power supply sequencing is recommended for all devices. Always apply GND and VDD before applying signals, especially if the signal is not current limited. Caution: Do NOT exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Equalization Setting Various Input Trace and Eye Test with different EQ setting Figure 3 shows PI2EQX6811 test setup for different EQ setting, R in the figure represents PI2EQX6811. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB Input Trace EQ Setting Fixture 24inch SMA Cable Signal Generator R TP3 EM=0dB Tektronic Sampling Scope TP4 Figure 3: EQ Setting Test Setup for PI2EQX6811 Page 6 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Eye Diagram vs. EQ setting at 6Gb/s Input Trace Length SEL[2..0] Setting 6 inch FR4 Lab trace (-2dB loss at 3GHz) 4dB (A_EQ or B_EQ =Open) 18 inch FR4 Lab trace (-6dB loss at 3GHz) 8dB (A_EQ or B_EQ =Low) 30 inch FR4 Lab trace (-10dB at 3GHz) 16dB (A_EQ or B_EQ =High) 48 inch FR4 Lab trace (-16dB loss at 3GHz) 16dB (A_EQ or B_EQ =High) Input Eye at TP3 Output Eye at TP4 Table 3: Eye Diagram at TP4 vs. Input FR4 trace and EQ setting at 6Gb/s for PI2EQX6811 Input Trace Length 6 inch FR4 Lab trace (-1.2dB loss at 1.5GHz) 18 inch FR4 Lab trace (-3dB loss at 1.5GHz) 30 inch FR4 Lab trace (-5dB loss at 1.5GHz) 48 inch FR4 Lab trace (-9dB loss at 1.5GHz) Eye Diagram vs. EQ setting at 3Gb/s SEL[2..0] Setting Input Eye at TP3 Output Eye at TP4 4dB (A_EQ or B_EQ =Open) 8dB (A_EQ or B_EQ =Low) 16dB (A_EQ or B_EQ =High) 16dB (A_EQ or B_EQ =High) Table 4: Eye Diagram at TP4 vs. Input FR4 trace and EQ setting at 6Gb/s for PI2EQX6811 Page 7 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Output Swing Setting Figure 4 shows PI3EQX6801ZDE test setup for different output swing setting, R in the figure represents PI3EQX6801ZDE. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, Pre-emphasis is 0dB OS Setting Fixture 5cm 100ohm Trace MB R EM=Open EQ=Low Agilent Sampling Scope TP4 Figure 4: Output Swing Setting Test Setup for PI3EQX6801ZDE OS[1..0]=00 OS[1..0]=01 OS[1..0]=10 OS[1..0]=11 Output Swing at TP4 vs. OS setting at 3Gb/s Output Swing at TP4 vs. OS setting at 6Gb/s Table 5: Output Swing at TP4 vs. OS setting at 3Gb/s and 6Gb/s for PI3EQX6801ZDE Page 8 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Pre-emphasis Setting Figure 5 shows PI3EQX6801ZDE test setup for different Pre-emphasis setting, R in the figure represents PI3EQX6801ZDE. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 500mV, EQ setting is 0dB EM Setting Fixture 5cm 100ohm Trace MB R OS=3.9k EQ=Low Agilent Sampling Scope TP4 Figure 5: Pre-emphasis Setting Test Setup for PI3EQX6801ZDE A/B_ EM=15kohm A/B_ EM =10kohm A/B_ EM =5.6kohm Output Pre-emphasis at TP4 vs. EM setting at 3Gb/s Output Pre-emphasis at TP4 vs. EM setting at 6Gb/s Table 6: Pre-emphasis at TP4 vs. EM setting at 3Gb/s and 6Gb/s for PI3EQX6801ZDE Page 9 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Typical Application Circuit Figure 6 shows typical application circuit of PI3EQX6801ZDE. Reference Schematic for Power Supply = 3.3V +3.3V C3 C1 C2 1u_0805 10n_0402 10n_0402 A_OS R5 +3.3V U2 10n_0402 C7 10n_0402 TX C9 10n_0402 C11 10n_0402 1 2 3 4 5 6 7 8 9 10 RX AI+ AIA_EN# BOBO+ R8 0ohm or Open AO+ AOB_EN# BIBI+ DNC B_EQ B_EM B_OS VDD33 C5 0ohm or Open HGND VDD33 A_OS A_EM A_EQ DNC HOST Controller Open or Res v alue A_EQ R2 Device Connector 21 20 19 18 17 16 R7 0ohm or Open Res v alue A_EM R1 15 14 13 12 11 C6 10n_0402 C8 10n_0402 C10 10n_0402 C12 10n_0402 JP1 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SATA CONNECTOR PI3EQX6801ZDEZDE(3.3V)@TQFN20 B_OS R6 B_EM R3 Open or Res v alue B_EQ R4 0ohm or Open Res v alue PIN CONFIGURATION for CONTROL PIN NAME A_EN# B_EN# A_EQ B_EQ PIN FUNCTION DESCRIPTION Control Configuration With Internal 200k-ohm pull-down resistor Low: Normal Operation High: Power Down Mode Input Equalization Tri-level Input For real application, they could be OPEN. Equalization is controled by PIN7&PIN17 Input Equalization for Channel A&B Input [email protected]/s 8dB(A&B-CH) 16dB(A&B-CH) 4dB(A&B-CH) 0 1 Vdd/2 A_EM B_EM Output Emphasis Adjustment it is analog resistive adjustment. please refer to the next row table Emphasis is controlled by PIN4&13, PIN5&12 and PIN6&11 of SW1 for Channel A, PIN4&13, PIN5&12 and PIN6&11 of SW2 for Channel B, PIN4&13 PIN4&13 PIN5&12 PIN6&11 A_OS B_OS Output Swing Adjustment it is analog resistive adjustment. please refer to the next row table is is is is Open short(14k RES) short(10k RES) short(6k RES) Swing is controlled by PIN1&16, PIN2&15 and PIN3&14 of SW1 for Channel A, PIN1&16, PIN2&15 and PIN3&14 of SW2 for Channel B, PIN1&16 is short(5k RES) PIN2&15 is short(4k RES) PIN3&14 is short(2k RES) PIN6&16 PIN10&20 Voltage PIN Pre-emphasis for Channel A&B 0dB +2.0dB +3.0dB +4.0dB Swing Output for Channel A&B (mV, Vtx-diff-p at 6.0Gb/s) 660 820 1200 PI3EQX6801ZDE(3.3V)@TQFN20: PIN10&20=VDD33 (3.3V), PIN6&16=DNC Figure 6a: Typical Application Circuit of PI3EQX6801ZDE at Power=3.3V Page 10 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 Reference Schematic for Power Supply = 1.5V +1.5V C3 C1 C2 1u_0805 10n_0402 10n_0402 A_OS R5 +1.5V U1 10n_0402 C7 10n_0402 TX C9 10n_0402 C11 10n_0402 1 2 3 4 5 6 7 8 9 10 RX AI+ AIA_EN# BOBO+ R8 0ohm or Open AO+ AOB_EN# BIBI+ VDD15 B_EQ B_EM B_OS VDD15 C5 0ohm or Open HGND VDD15 A_OS A_EM A_EQ VDD15 HOST Controller Open or Res v alue A_EQ R2 Device Connector 21 20 19 18 17 16 R7 0ohm or Open Res v alue A_EM R1 15 14 13 12 11 C6 10n_0402 C8 10n_0402 C10 10n_0402 C12 10n_0402 JP1 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SATA CONNECTOR PI3EQX6801ZDE(1.5V)@TQFN20 B_OS R6 B_EM R3 Open or Res v alue B_EQ R4 0ohm or Open Res v alue PIN CONFIGURATION for CONTROL PIN NAME A_EN# B_EN# A_EQ B_EQ PIN FUNCTION DESCRIPTION Control Configuration With Internal 200k-ohm pull-down resistor Low: Normal Operation High: Power Down Mode Input Equalization Tri-level Input For real application, they could be OPEN. Equalization is controled by PIN7&PIN17 Input Equalization for Channel A&B Input [email protected]/s 8dB(A&B-CH) 16dB(A&B-CH) 4dB(A&B-CH) 0 1 Vdd/2 A_EM B_EM Output Emphasis Adjustment it is analog resistive adjustment. please refer to the next row table Emphasis is controlled by PIN4&13, PIN5&12 and PIN6&11 of SW1 for Channel A, PIN4&13, PIN5&12 and PIN6&11 of SW2 for Channel B, PIN4&13 PIN4&13 PIN5&12 PIN6&11 A_OS B_OS Output Swing Adjustment it is analog resistive adjustment. please refer to the next row table is is is is Open short(14k RES) short(10k RES) short(6k RES) Swing is controlled by PIN1&16, PIN2&15 and PIN3&14 of SW1 for Channel A, PIN1&16, PIN2&15 and PIN3&14 of SW2 for Channel B, PIN1&16 is short(5k RES) PIN2&15 is short(4k RES) PIN3&14 is short(2k RES) PIN6&16 PIN10&20 Voltage PIN Pre-emphasis for Channel A&B 0dB +2.0dB +3.0dB +4.0dB Swing Output for Channel A&B (mV, Vtx-diff-p at 6.0Gb/s) 660 820 1200 PI3EQX6801ZDE(1.5V)@TQFN20: PIN6&10&16&20=VDD15 (1.5V) Figure 6b: Typical Application Circuit of PI3EQX6801ZDE at Power=1.2V Page 11 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 PCB Layout Sample Figure 7 shows the typical layout routing of PI3EQX6801ZDE. Figure 7a: Typical Layout Routing of PI3EQX6801ZDE at Power=3.3V Figure 7b: Typical Layout Routing of PI3EQX6801ZDE at Power=1.5V Page 12 of 13 AN333 Pericom Semiconductor Corp. www.pericom.com 1/11/2012 333 History Version 1.0 Page 13 of 13 Original Version AN333 Pericom Semiconductor Corp. www.pericom.com Nov. 3, 2011 1/11/2012