www.fairchildsemi.com AN-9077 Motion SPM® 7 Series User’s Guide Table of Contents 1 2 3 4 Introduction................................................................. 2 Application Example ................................................. 14 1.1. Design Concept ...........................................................2 6.1. General Application Circuit Examples ..................... 14 1.2. Features .......................................................................2 6.2. Recommended Wiring of Shunt Resistor ................. 15 Product Selections ...................................................... 2 6.3. Snubber Capacitor .................................................... 15 2.1. Ordering Information ..................................................2 6.4. PCB Layout Guidance .............................................. 15 2.2. Product Line-Up .........................................................2 6.5. Thermal Characteristics ............................................ 16 Package ....................................................................... 3 6.6. Thermal Simulation .................................................. 16 6.6.1 6.6.2 6.6.3 Condition for RθJCB and RθJA .................................. 16 Simulation for RθJCB ............................................... 16 Simulation for RθJA................................................. 17 3.1. Internal Circuit Diagram .............................................3 3.2. Pin Description ...........................................................3 3.3. Package Structure .......................................................5 6.7. Evaluation Test ......................................................... 18 3.4. Package Outline ..........................................................5 6.8. System Performance ................................................. 20 3.5. Marking Specification .................................................5 7 Packing and Installation Guide.................................. 20 7.1. Integrated Functions and Protection Circuit ............... 6 Handling Precautions................................................ 20 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 Transportation ........................................................ 20 Storage ................................................................... 20 Environment .......................................................... 20 Electrical Shock ..................................................... 21 Circuit Board Coating ............................................ 21 4.1. Internal Structure of HVIC .........................................6 4.2. Circuit of Input Signal (VIN(H), VIN(L)).........................6 4.3. Functions vs. Control Supply Voltage ........................6 4.4. Under-Voltage Lockout Protection (ULVO) ..............7 8 Packing Specification ................................................ 22 4.5. Short-Circuit Protection ..............................................7 9 Related Resources ..................................................... 24 4.5.1 4.5.2 5 6 Timing of Short-Circuit Protection .......................... 7 Selecting Current Sensing Shunt Resistor ................ 8 Key Parameter Design Guidance ................................ 9 5.1. Thermal Sensing Unit (TSU) ......................................9 5.2. Bootstrap Circuit Design ........................................... 10 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 Operation of Bootstrap Circuit ............................... 10 Initial Charging of Bootstrap Capacitor ................. 11 Selection of Bootstrap Capacitor ........................... 12 Selection of Bootstrap Diode ................................. 12 Selection of Bootstrap Resistance .......................... 12 5.3. Minimum Pulse Width .............................................. 13 5.4. Interlock Function ..................................................... 13 5.5. Selection of CFOD.................................................... 13 5.6. Short Circuit Test ...................................................... 13 © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com AN-9077 APPLICATION NOTE 1 Introduction 1.2. Features This application note is about Motion SPM® 7 Series. It should be used in conjunction with the datasheet, the reference design, and other related application notes listed in the Related Resources section. The detailed features and integrated functions are: 250 V/ 500 V 3-phase FRFET Inverter Including HVIC Max. RDS(ON) - FSB70325; 1.4 , FSB70625; 0.8 , FSB70250; 3.4 , FSB70450; 2.2 , FSB70550; 1.85 Separate Open-Source Pins from Low-Side MOSFETs for Three-Phase Current-Sensing Active-HIGH Interface, Works with 3.3 / 5 V Logic Schmitt-Trigger Input Optimized for Low Electromagnetic Interference HVIC Temperature-Sensing Built-In for Temperature Monitoring HVIC for Gate Driving with Under-Voltage Protection Interlock Function Isolation Rating: 1500 VRMS / Minimum Moisture Sensitive Level (MSL) 3 RoHS Compliant 1.1. Design Concept The key design objective of Motion SPM 7 series is to provide a solution for compact and reliable inverter design when assembly space is constrained. It also can provide an energy-efficient solution for small power-motor drive applications, such as fans and pumps. SPM 7 series MOSFETs reduce the amount of body-diode reverse-recovery charge to minimize the switching loss and enable fast switching operations. Softness of the reverserecovery characteristics is managed through advanced MOSFET design processes and optimized gate resistor selection to contain Electromagnetic Interference (EMI) noise within a reasonable range. The SPM 7 series has six fast-recovery MOSFETs (FRFET®) and one three-phase HVIC. These MOSFETs and HVIC are not available as discrete parts. The FRFETbased power module has improved ruggedness and a larger Safe Operation Area (SOA) than IGBT-based module or Silicon-On-Insulator modules. 2 Product Selections 2.1. Ordering Information The FRFET-based power module has an advantage over an IGBT-based power module in light-load efficiency because the voltage drop across the transistor decreases linearly as current decreases; whereas IGBT VCE saturation voltage stays at the threshold level. Some applications require continuous operation at light load except short transients, and improving the efficiency in the light-load condition is the key to saving energy. Refrigerators, water circulation pumps, and some fans are good examples. The temperature-sensing function is implemented in the HVIC to enhance the system reliability. An analog voltage proportional to the temperature of the HVIC is provided for monitoring the module temperature and protection against over-temperature situations. Figure 1. Ordering Information 2.2. Product Line-Up Table 1 shows the basic line up without package variations. Table 1. Product Line-Up Part Number BVDSS FSB70325 Current Rating RƟJCB (Typ.) ID25 IDP RDS(ON) (Typ.) RDS(ON) (Max.) 250 4.1 8.2 1.1 1.4 2.0 FSB70625 250 6.9 13.9 0.7 0.8 1.2 FSB70250 500 3.3 6.7 2.5 3.4 1.2 FSB70450 500 4.8 9.7 1.9 2.2 0.9 FSB70550 550 5.3 10.6 1.6 1.85 0.9 An online loss and temperature simulation tool, Motion Control Design Tool (http://www.fairchildsemi.com/support/designtools/motion-control-design-tool/), is recommended to choose the right SPM product for the application. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 2 AN-9077 APPLICATION NOTE 3 Package 3.2. Pin Description 3.1. Internal Circuit Diagram Figure 3 shows the locations and the names of the pins. Figure 5 in the later section illustrates the internal layout of the module in more details. The internal circuit diagram is shown in Figure 2. The VTS pin from the HVIC gives the temperature-sensing signal. The detailed functional descriptions are provided in Table 2. ® Motion SPM 7 Series (19) VS(W) (23)(23a) VS(V) (24)(24a) VS(U) (22) PU (21) PV (20) PW (25) VB(U) VB(U) HO(U) (26) VB(V) VB(V) (27) VB(W) VS(U) VB(W) (5) VDD VDD (8)(8a) COM COM (6) IN(UH) UH (7) IN(VH) VH (9) IN(WH) WH (10) IN(UL) UL (11) IN(VL) VL (12) IN(WL) WL (1) /FO /FO (2) VTS VTS (3) Cfod CFOD (4) Csc CSC (14) U HO(V) VS(V) (16) V HO(W) VS(W) (17) W LO(U) (13) NU LO(V) (15) NV LO(W) (18) NW Figure 3. Figure 2. Circuit Diagram of Motion SPM 7 Series Pin Map (Top View) Table 2. Pin Description Pin # Name 1 2 3 4 5 6 7 8 (8a) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23(23a) 24(24a) 25 26 27 /FO VTS Cfod CSC VDD IN_UH IN_VH COM IN_WH IN_UL IN_VL IN_WL Nu U Nv V W Nw VS(W) PW PV PU VS(V) VS(U) VB(U) VB(V) VB(W) Pin Description Fault Output Voltage Output of HVIC Temperature Capacitor for Duration of Fault Output Capacitor (Low-Pass Filter) for Short-Circuit Current Detection Input Supply Bias Voltage for IC and MOSFETs Driving Signal Input for High-Side U Phase Signal Input for High-Side V Phase Common Supply Ground Signal Input for High-Side W Phase Signal Input for Low-Side U Phase Signal Input for Low-Side V Phase Signal Input for Low-Side W Phase Negative DC-Link Input for U Phase Output for U Phase Negative DC-Link Input for V Phase Output for V Phase Output for W Phase Negative DC-Link Input for W Phase High-Side Bias Voltage Ground for W Phase MOSFET Driving Positive DC-Link Input for W Phase Positive DC-Link Input for V Phase Positive DC-Link Input for U Phase High-Side Bias Voltage Ground for V Phase MOSFET Driving High-Side Bias Voltage Ground for U Phase MOSFET Driving High-Side Bias Voltage for U Phase MOSFET Driving High-Side Bias Voltage for V Phase MOSFET Driving High-Side Bias Voltage for W Phase MOSFET Driving © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 3 AN-9077 APPLICATION NOTE High-Side Bias Voltage Pins for Driving the High-Side MOSFET / High-Side Bias Voltage Ground Pins for Driving the High-Side MOSFET Pins: VB(U) – U,VS(U) , VB(V) – V,VS(V) , VB(W) – W,VS(W) These are drive power supply pins for providing gate drive power to the high-side MOSFETs. The advantage of boot-strap scheme is that no separate external power supplies are required to drive the highside MOSFETs. Each bootstrap capacitor is charged from the VDD supply during ON state of the corresponding low-side MOSFET. To prevent malfunctions caused by noise and ripple in supply voltage, a quality filter capacitor with low Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) should be mounted very close to these pins. Supply Bias Voltage for IC and MOSFETs Driving Pin: VDD This is a control supply pin for the internal ICs. This pin should be connected externally. To prevent malfunctions caused by noise and ripple in the supply voltage, a quality of filter capacitor with low ESR and ESL should be mounted very close to this pin. Low-Side Common Supply Ground Pin Pin: COM The common pin connects to the control ground for the internal ICs. Important! To prevent switching noises caused by parasitic inductance from influencing operations of the module, the main power current should not flow through this pin. Signal Input Pins Pins: IN(UL), IN(VL), IN(WL), IN(UH), IN(VH), IN(WH) These are pins to control operation of the MOSFETs. These terminals are activated by voltage input signals and internally connected to a Schmitt trigger circuit. The signal logic of these pins is active HIGH: the MOSFET turns ON when sufficient logic voltage is applied to the associated input pin. The wiring of each input needs to be short to protect the module against noise influences. The RC filter can be used to mitigate signal oscillations or noise picked up by the trace of the input signals. Analog Temperature Sensing Output Pin Pin: VTS This indicates the temperature of the HVIC with analog voltage. The HVIC itself creates some power loss, but mainly it is heat generated from the MOSFETs that increases the temperature of the HVIC VTS vs. temperature characteristics is illustrated in Figure 14. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 Positive DC-Link Pins Pins: PU, PV, PW These are the DC-link positive power supply pins of the inverter. These are connected to the collectors of the high-side MOSFETs. These pins should be connected externally. To suppress the surge voltage caused by the DC-link wiring or PCB pattern inductance, connect a smoothing filter capacitor close to this pin. Metal film capacitors are typically recommended. Negative DC-Link Pins Pins: NU, NV, NW These are the DC-link negative power supply pins (power ground) of the inverter. These pins are connected to the low-side MOSFET sources of the each phase. Inverter Power Output Pin Pins: U, V, W Inverter output pins to be connected to the inverter load, such as an electrical motor. Short-Current Detection Pin Pin: CSC A current-sensing shunt resistor should be connected between this pin and the low-side ground COM to detect short-circuit current (reference Figure 12). The shunt resistor should be selected to meet the detection levels matched for the specific application. An RC filter should be connected to CSC pin to eliminate noise. The connection length between the shunt resistor and CSC pin should be minimized. Fault Output Pin Pin: /FO This is the fault output alarm pin. An active-LOW output is given on this pin for a fault state condition in the SPM. The alarmed conditions are Short-Circuit (SC) or low-side bias Under-Voltage (UV) operation. It is an open-collector output and should be pulled up to the 5 V logic power supply with approximately 4.7 kresistance. Fault-Out Duration Time Selection Pin Pin: CFOD This is the pin for selecting the fault-out pulse length. An external capacitor should be connected between this pin and COM to set the fault-out pulse length. The fault-out pulse width, tFOD, depends on the capacitance of CFOD, as the following approximates: CFOD = 24 x 10-6 x tFOD [F] (1) www.fairchildsemi.com 4 AN-9077 APPLICATION NOTE 3.3. Package Structure 3.4. Package Outline Figure 4 shows the internal package structure, including the lead frame and bonding wires. This design has been revised to further improve the manufacturability and the reliability. For more detailed data regarding the package dimension and land pattern recommendation, refer to the datasheet. MOSFET - 3-phase Half Bride HVIC Figure 4. Package Structure Figure 5. Package Outline 3.5. Marking Specification The marking of the package is shown in Figure 6. Figure 6. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 Marking of Package www.fairchildsemi.com 5 AN-9077 APPLICATION NOTE The Motion SPM 7 series employ active-HIGH input logic. This removes the sequence restriction between the control supply and the input signal during startup or shutdown of power supply operation. In addition, pull-down resistors are internal to each input circuit. External pull-down resistors are not typically needed, and the number of external components is smaller as a result. The input noise filter inside the HVIC suppresses short-pulse noise and prevents the MOSFET from malfunction and excessive switching loss. Furthermore, by lowering the turn-on and turn-off threshold voltages of the input signal, as shown in Table 4, a direct connection to 3.3 V-class MCU or DSP is possible. 4 Integrated Functions and Protection Circuit 4.1. Internal Structure of HVIC HVIC of Motion SPM® 7 Series Input Level-Shift H/S Noise Circuit Restart Filter HIN 500k(typ) Common Mode Noise Canceller Gate Driver w/ Gate Resistors HO Gate Driver w/ Gate Resistors LO Inter Lock Input L/S Noise Restart Filter LIN 500k(typ) Matching Delay 450ns(typ) Figure 7. Internal Block Diagram of HVIC Table 4. Input Threshold Voltage Ratings (at VDD=15 V, TJ=25°C) Figure 7 shows the block diagram of structure of the HVIC inside the Motion SPM 7 series. Gate signal input pins have internal 500 kΩ pull-down resistors. The weak pull-down reduces standby power consumption. If there is concern about malfunction due to noise associated with layout, additional pull-down resistors of 4.7 kΩ, for example, can be placed close to the module input pins. RC filters can be used instead of pull-downs to eliminate noise and narrow pulses as well. Consider, however, that this filter introduces some distortion of PWM volt-second because the ON/OFF thresholds are not symmetrical within the supplied voltage. Figure 8 shows an example of PWM input interface circuit from the MCU to Motion SPM 7 series. The input logic is active HIGH and, because there are built-in pull-down resistors of 500 kΩ; external pull-down resistors are not typically needed. VIH On Threshold Voltage VIL Off Threshold Voltage IN(UH), IN(VH), IN(WH) – COM IN(UL), IN(VL), IN(WL) - COM Min. Max Unit . 2.4 0.8 V V Control and gate drive power for the Motion SPM 7 series is normally provided by a single 15 V DC supply connected to the module VDD and COM terminals. For proper operation, this voltage should be regulated to 15 V 10% and its current supply should be >260 µA for the SPM product only. Table 5 describes the behavior of the SPM parts for various control supply voltages. The control supply should be well filtered with a low-impedance electrolytic capacitor and a highfrequency decoupling capacitor connected at the pins. IN(UL), IN(VL), IN(WL) RF SPM CF COM Figure 8. Condition 4.3. Functions vs. Control Supply Voltage IN(UH), IN(VH), IN(WH) RPD Item As shown in Figure 7, the input signal integrates a 500 kΩ (typical) pull-down resistor. Therefore, when using an external filtering resistor between the MCU output and the Motion SPM® input, attention should be paid to the signal voltage drop at the SPM® input terminals to satisfy the turn-on threshold voltage requirement. For instance, R=100 Ω and C=1 nF can be used for the parts shown dotted in Figure 8. 4.2. Circuit of Input Signal (VIN(H), VIN(L)) MCU Symbol Recommended MCU I/O Interface Circuit High-frequency noise on the supply might cause the internal control IC to malfunction and generate erroneous fault signals. To avoid this, the maximum ripple on the supply should <±1 V/µs. In addition, it may be necessary to connect a 24 V/1 W Zener diode across the control supply to prevent surge destruction under severe conditions. The maximum rating voltages of input pins are shown in Table 3. The RC coupling at each input is shown as dotted in Figure 8 and may change depending on the PWM control scheme used in the application and the wiring impedance of the application PCB layout. Table 3. Maximum Ratings of Input Pins Symbol Item Condition Rating Unit VDD Control Supply Voltage Applied between VDD – COM 20 V It is crucial that all control circuits and power supplies be referred to COM terminal of the module; not to the N power terminal. In general, it is best practice to make the common reference (COM) a ground plane in the PCB layout. VIN Input Signal Voltage Applied between IN(xH) – COM, IN(xL) – COM V The main control power supply is also connected to the bootstrap circuits used to establish the floating supplies for the high-side gate drives. -0.3 ~ VDD + 0.3 When control supply voltage (VDD and VBS) falls below Under-Voltage Lockout (UVLO) level, HVIC turns off the MOSFETs while disregarding gate control input signals. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 6 AN-9077 APPLICATION NOTE Table 5. Control Voltage Range vs. Operations Control Voltage Range Input Signal Function Operations UV Protection Status Control IC does not operate. UVLO and fault output do not operate. dv/dt noise on main P-N supply can trigger MOSFETs. Control IC starts to operate. As the UVLO is set, gates of MOSFETs pull down regardless of control input signals. UVLO is cleared. MOSFETs operate in accordance with control gate input. Driving voltage is below recommended range; RDS(ON) and the switching loss are higher than under normal condition. Normal operation. This is the recommended operating condition. MOSFETs still operate. Because driving voltage is above the recommended range, MOSFETs switch faster. May increase system noise. Peak short-circuit current may increase. 0~5V 5 ~ 10 V 10 ~ 13.5 V 13.5 ~ 16.5 VDD 16.5~20 V for VDD 16.5~20 V for VBS Over 20 V RESET SET RESET b6 UVCCR b5 b1 Low-side Supply, Vcc UVCCD b2 b3 b4 MOSFET Current Figure 10. Timing Chart of UVLO [Low Side] 4.5. Short-Circuit Protection 4.5.1 Timing of Short-Circuit Protection The HVIC has a built-in short-circuit function. The IC monitors the voltage to the CSC pin and, if this voltage exceeds the VSC(ref), which is specified in the device datasheet, a fault signal is asserted and the six MOSFETs are turned off. The maximum short-circuit current magnitude is Typically gate-voltage dependant. A higher gate voltage results in a larger short-circuit current. To avoid this potential problem, the maximum short-circuit trip level is generally set to below 1.7 times the nominal rated collector current. The LVIC short-circuit protection-timing chart is shown in Figure 11 (with the external shunt resistance and RC connection). Module control circuit in can be damaged. 4.4. Under-Voltage Lockout Protection (ULVO) The three-phase HVIC has an under-voltage lockout function to protect MOSFETs from operation with insufficient gate driving voltage. A timing chart for this protection is shown in Figure 9 and Figure 10. c1: Normal operation: MOSFET ON and carrying current. a1: Control supply voltage rises: after the voltage reaches UVBSR, the circuit starts to operate immediately. a2: Normal operation: MOSFET turns on and carries current. a3: Under-Voltage detection (UVBSD). a4: MOSFET turns off regardless of control input condition, but there is no fault output signal. a5: Under-voltage lockout is cleared (UVBSR). a6: Normal operation: MOSFET turns on and carries current. b1: Control supply voltage rises: after the voltage rises UVDDR, the circuit starts when next input comes in. b2: Normal operation: MOSFET turns on and carries current. b3: Under-voltage detection (UVDDD). b4: MOSFET turns off regardless of control input condition and fault output signal goes LOW. b5: Under-voltage lockout is cleared (UVDDR). b6: Normal operation: MOSFET turns on and carries current. c4: MOSFET turns OFF. c2: Short-circuit current detection (SC trigger). c3: Hard MOSFET gate interrupt. c5: Fault output timer operation starts: the pulse width of the fault output signal is set by external capacitor CFO. c6: Input LOW: MOSFET OFF state. c7: Input HIGH: MOSFET ON state, but during the active period of fault output the MOSFET doesn’t turn ON. c8: MOSFET OFF state. Input Signal UV Protection Status RESET SET RESET a6 UVBSR High-side Supply, Vbs a5 a1 UVBSD a2 a3 a4 Figure 11. MOSFET Current Figure 9. Timing Chart of Short-Circuit Protection Timing Chart of UVLO [High Side] © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 7 AN-9077 APPLICATION NOTE 4.5.2 Selecting Current Sensing Shunt Resistor Figure 12 shows an example circuit of the SC protection using a 1-shunt resistor. The line current on the N side DClink is detected and the protective operation signal is passed through the RC filter. If the current exceeds the SC reference level, all the gates of the six MOSFETs are switched to OFF state and the FO fault signal is transmitted to the CPU. Since SC protection is non-repetitive, MOSFET operation should be immediately halted when the FO fault signal is given. Table 6. SC Protection Reference Level VSC(REF) Item Min. Typ. Max. Unit SC Trip Level VSC(REF) 0.45 0.50 0.55 V The three-shunt resistor circuit is more complicated and has more considerations than the one-shunt resistor circuit. The three-shunt circuit is popular because it permits sensing of individual phase currents. The circuit is very cost-effective and provides good current-sensing performance. Figure 13. Figure 12. Example of Short Circuit Protection Circuit with 1-Shunt Resistors Figure 13 shows a typical circuit for short-circuit detection using diodes. There are additional considerations when using this circuit. Note that this circuit is not adequate for the precise over-current detection due to dispersion and temperature dependency of VF. The internal protection circuit is triggered under shortcircuit condition by comparing the external shunt voltage to the reference SC trip voltage in the LVIC. The drive IC then interrupts low-side MOSFET gates to stop MOSFET operation. The value of current-sensing resistor is calculated by the following expression: RSHUNT VSC( REF ) I SC Example of Short Circuit Protection Circuit with 3-Shunt Resistors The short circuit sensing signal delay increases. A RF1 x CF1 time constant delay (t3) is added, so total delay becomes: TTOTAL t1 t2 t3 (2) (4) The added diode blocks the IC leakage current (approximately 500 nA) from the CSC pin. If this current is applied to the capacitor, C SC, VCSC increases to a somewhat higher value and causes SPM to stop gating even under normal conditions. To compensate for this corruption of SC current-sensing voltage, RCSC must be placed in parallel with C SC. The recommended value of RCSC is approximately 47 k. where VSC(REF) is the SC reference voltage of the HVIC. An RC filter (reference RF CSC above) is necessary to prevent noise related SC circuit malfunction. The RC time constant is determined by the applied noise time and the MOSFET withstand capability. It is recommended to be set in the range of 1.5 ~ 2 µs. When the external shunt resistor voltage drop exceeds the SC protection level, this voltage is applied to the C SC pin via the RC filter. The filter delay time (t1) is required for the CSC pin voltage to rise to the referenced SC protection level. Table 6 shows the specification of the SC protection level. The IC has an internal delay (t2) of 550 ns, including internal filtering time (Typical 400 ns). For the short circuit state, the diode drop voltage must be considered to set the short-circuit protection reference level. The equation is: VSEN VCSC VF (5) Therefore, the total time from the detection of the SC trip current to the gate off of the MOSFET becomes: TTOTAL t1 t2 © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 (3) www.fairchildsemi.com 8 AN-9077 APPLICATION NOTE Figure 15 shows the equivalent circuit diagram of the TSU inside the IC and a typical application diagram. The output voltage is clamped to 5.2 V by an internal Zener diode, but if the maximum input range of the analog-to-digital converter of the MCU is below 5.2 V, an external Zener diode should be inserted between an A/D input pin and the analog ground pin of the MCU. An amplifier can be used to change the range of voltage input to the analog-to-digital converter for better resolution of the temperature. It is recommended to add a ceramic capacitor of 1000 pF between VTS and COM (ground) to improve VTS stability. 5 Key Parameter Design Guidance 5.1. Thermal Sensing Unit (TSU) The junction temperature of power devices should not exceed the maximum junction temperature. Even though there is some margin between the T JMAX specified on the datasheet and the actual T JMAX at which power devices are destroyed, ensure the junction temperature stays well below the T JMAX. The Thermal Sensing Unit (TSU) uses the technology based on the temperature dependency of transistor Vbe; Vbe decrease 2 mV as temperature increases by 1ºC. VCC Vdd The TSU analog voltage output reflects the temperature of the HVIC in Motion SPM 7 series. The relationship between VTS voltage output and HVIC temperature is shown in Figure 14. It does not have any self-protection function and, therefore, should be used appropriately based on application requirement. There is a time lag from MOSFET temperature to HVIC temperature, making it difficult to respond quickly when temperature rises sharply in a transient condition, such as a shoot-through event. Even though the TSU has some limitations, it enhances system reliability. MCU Temperature Sensing Voltage 2.5Kohm VTS 2.5Kohm A/D 100Kohm 5.2V COM COM Figure 15. Internal Diagram, Interface Circuit of TSU Figure 16 and Figure 17 show the sourcing capability of the VTS pin at 25ºC and the test method. VTS voltage decreases as the sourcing current increases. Therefore, the load connected to VTS pin should be minimized to maintain the accurate voltage output level without degradation. 15V VCC VTS Current sweep ITS (0~ 140µA) SPM7 HVIC COM Figure 16. Test Method Figure 14. Temperature Sensing Voltage, Vts[V] 0.8 Temperature vs. VTS Figure 14 shows that the relationship between VTS voltage and V-phase HVIC temperature. It can be expressed as: VTS = 0.019 x THVIC + 0.2 [V] (6) The maximum variation of VTS, due to process variation, is ±0.095 V, which is equivalent to ±5ºC. This is regardless of temperature because the slopes of the three lines are identical. If the ambient temperature information is available, for example, through NTC in the system; VTS can be measured to adjust the offset before the motor starts. 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 20 40 60 80 100 120 140 ITS [uA] Figure 17. As temperature decrease further below 0°C, VTS decreases linearly until it reaches zero volts. If the temperature of HVIC increases above 150ºC, which is above the maximum operating temperature, VTS would increase theoretically up to 5.2 V until it gets clamped by the internal Zener diode. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 Vts at 25 C 0.7 Load Variation of VTS Figure 18 shows the test result representing the relationship between HVIC temperature and other measured temperature in a real application condition. The real junction temperature was measured with a special package and it is similar to case temperature and P pin (Pu, Pv, Pw) temperature. www.fairchildsemi.com 9 AN-9077 APPLICATION NOTE 5V line MCU R8 6.8K 1% R7 3K I/O Port R9 1.8K 1% Motion SPM® 7 Product Comparator VTS C14 104 R10 1.1K 1% C16 104 C17 102 Figure 20. Example of Over-Temperature Protection using TSU (Trip Level) When the temperature is below 80°C; VO, the open-collector output of the comparator, should stay HIGH. To make VO transition to LOW at 100°C, VREF needs to drop below 2.10 V, VTS voltage at 100°C. Figure 18. Load Current vs. Temperature (without Heat Sink) (7) The gap between MOSFET junction temperature and HVIC tempature gradually increases coresponding to load current. Judging from the experiment, MOSFET junction temperature can be estimated by calculated HVIC temperature, as shown in Figure 19. However, system conditions, such as heat dissipation, can change the curve. When the temperature is above 100°C, VO should stay LOW. To make VO transition to HIGH at 80°C, VREF must be higher than 1.724 V, VTS voltage at 80°C. (8) Therefore, it is necessary to make a profile according to set application conditions. As shown in Figure 18, real junction temperature has a similar values with measured case temperature or P pin (Pu, Pv, Pw) temperature if an external heatsink is not attached. There are four variables with two equations, so two variables need to be set. R7, the pull-up resistor for VO, can be chosen to be 3 kΩ. R2 can be 1.1 kΩ, considering VREF is below one half of the supply voltage (5 V in this example) and R9 needs to be bigger than R10. VCOMP 5V Set Voltage: VTS=2.10V(THVIC=100℃) Hysteresis voltage: ΔVTS=0.38V(THVIC=20℃) Reset Voltage: VTS=1.72V(THVIC=80℃) VTS 0V Figure 21. Comparator Output, Hysteresis using TSU 5.2. Bootstrap Circuit Design Figure 19. 5.2.1 Operation of Bootstrap Circuit The VBS voltage, which is the voltage difference between VB(U,V,W) and VS(U,V,W), provides the supply to the HVIC within the Motion SPM 7 series. This supply must be in the range of 13.5 V~16.5 V to ensure that the HVIC can fully drive the high-side MOSFET. The under-voltage lockout protection for the VBS ensures that the HVIC does not drive the high-side MOSFET if VBS drops below the specific voltage. This function prevents the MOSFET from operating in a high-dissipation mode. TJ vs. THVIC (without Heat Sink) Figure 20 is an example of the over-temperature protection circuit. A comparator with hysteresis is used to create a lowactive signal that can be read by a microprocessor. Based on this signal, the microprocessor can disable or enable PWM output. As an example, calculate the resistor values to set the upper threshold level at 100°C and the lower threshold level at 80°C so that the comparator output voltage VO matches the waveform in Figure 21. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 10 AN-9077 APPLICATION NOTE MOSFETs do not switch without creating any fault signal. This can lead to failure of motor start in some applications. VBS VCC VB VCC(H) IN(H) IN(L) CVCC COM CBS Motion SPM® VPN VB VCC 0V HO IN(H) HVIC VS VCC VDC 0V IN(L) LO VBS COM 0V ON Figure 22. VIN(L) Bootstrap Circuit for the Supply Voltage (VBS) of HVIC 0V The VBS floating supply can be generated in a number of ways, including the bootstrap method shown in Figure 22. This method has the advantage of being simple and inexpensive; however, the duty cycle and on-time are limited by the need to refresh the charge in the bootstrap capacitor. The bootstrap supply is formed by a combination of bootstrap diode, resistor, and capacitor, as shown in Figure 22. OFF 0V Figure 24. VB RBS DBS VCC(H) OFF CVCC ON IN(H) IN(L) COM Timing Chart of Initial Bootstrap Charging If the three phases are charged synchronously, initial charging current through a single shunt resistor may exceed the over-current protection level. Therefore, the initial charging time for the bootstrap capacitors should be separated, as shown in Figure 25. VDC VCC VBS ichg Bootstrap capacitor charging(U phase) CBS Motion SPM® VIN(UL) … HO IN(H) HVIC VS … Bootstrap capacitor charging(V phase) VB VCC Start PWM VIN(H) The current flow path of the bootstrap circuit is shown in Figure 23. When VS is pulled down to ground (either through the low-side power device or the load), the bootstrap capacitor (CBS) is charged through the bootstrap diode (DBS) and the resistor (RBS) from the VDD supply. VCC Section of charge pumping for VBS : Switching or Full Turn on … … VIN(VL) VDC Bootstrap capacitor charging(W phase) IN(L) LO … VIN(WL) COM System operating periode Bootstrap capacitor charging period Figure 25. Figure 23. Bootstrap Circuit Charging Path Recommended Initial Bootstrap Capacitor Charging Sequence Adequate on-time duration of the low-side MOSFET to fully charge the bootstrap capacitor is required for initial bootstrap charging. 5.2.2 Initial Charging of Bootstrap Capacitor Adequate on-time duration of the low-side MOSFET to fully charge the bootstrap capacitor is initially required before normal operation of the PWM starts. Figure 24 shows an example of the initial bootstrap charging sequence. Once VDD establishes, VBS needs to be charged by turning on the low-side MOSFETs. PWM signals are typically generated by an interrupt triggered by a timer with a fixed interval based on the switching carrier frequency. Therefore, it is desirable to maintain this structure without creating complimentary high-side PWM signals. In case of Motion SPM® 7 Series, the initial charging time (tcharge) can be calculated from the following equation: tch arg e CBS RBS 1 In VCC VCC g VBS (min) VF VLS (9) where: VF: forward voltage drop across the bootstrap diode; VBS(min): minimum value of the bootstrap capacitor; VLS: voltage drop across the low-side MOSFET or load; and δ: duty ratio of PWM. (0 – 1). The capacitance of VDD should be sufficient to supply necessary charge amount to VBS capacitance of all three phases. If normal PWM operations start before VBS reaches the under-voltage lockout reset level, the high-side © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 … www.fairchildsemi.com 11 AN-9077 APPLICATION NOTE 5.2.3 Selection of Bootstrap Capacitor The bootstrap capacitor of Motion SPM® 7 series can be calculated by: CBS QBS VBS (10) where: QBS = Total charge from CBS; ΔVBS = the allowable drop voltage of the CBS (voltage ripple). Figure 26. Capacitance of Bootstrap Capacitor on Variation of Switching Frequency Total gate charge, QBS, required by the bootstrap capacitor can be calculated by: QBS Qg ( I LK ,D I LK ,C IQBS ) tON QLS The bootstrap capacitor should always be placed as close to the pins of the SPM as possible. At least one low-ESR capacitor should be used to provide local de-coupling. For example, a separate ceramic capacitor close to the SPM is essential if an electrolytic capacitor is used for the bootstrap capacitor. If the bootstrap capacitor is either a ceramic or tantalum, it should be adequate for local decoupling. (11) where: Qg = Gate charge to turn on the high-side MOSFET; ILK,D = Bootstrap diode leakage current; ILK,C = Bootstrap capacitor leakage current, which can be ignored if it is not an electrolytic capacitor; IQBS = Quiescent current of gate driver IC; tON = Maximum on pulse width of high-side MOSFET; and QLS = Level-shift charge required per cycle. 5.2.4 Selection of Bootstrap Diode When a high-side MOSFET or body-diode conducts, the bootstrap diode (DBS) supports the entire bus voltage. A withstand voltage of more than 600 V is recommended. It is important that this diode be fast recovery (recovery time < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor into the VDD supply. Similarly, the highvoltage reverse leakage current is important if the capacitor must store a charge for long periods of time. In case of FSB70325, minimum CBS is calculated as: CBS _ min Q QLS ( I LK ,D I LK ,C I QBS ) tON QBS g VBS VBS 50nC (100A 0 70A) 200s 0.84 F 0.1V 5.2.5 Selection of Bootstrap Resistance A resistor, RBS, must be added in series with the bootstrap diode to slow down the dVBS/dt and this resistor determines the time to charge the bootstrap capacitor. If the minimum ON pulse width of the low-side MOSFET or the minimum OFF pulse width of high-side MOSFET is tO, the bootstrap capacitor must be charged ΔV during this period. Therefore, the value of bootstrap resistance can be calculated by: (12) → More than two times (2X) → 2.2 µF where: VDD = 15 V; Bootstrap Diode = US1J; Qg + QLS = Approximately 50 nC (designed value); ILG,D = 100 µA (maximum value from datasheet); ILK,C = 0 (ceramic capacitor); IQBS = 70 µA (maximum value from datasheet); tON = 200 µs (depends on system); and ΔVBS = 0.1 V (depends on system). RBS (VCC VBS ) tO CBS VBS The current flow path of the bootstrap circuit is shown in Figure 27. When VS is pulled down to ground (either through the low-side power device or the load), the bootstrap capacitor, CBS, is charged through the bootstrap diode, DBS, and the resistor, RBS, from the VDD supply. VBS Recommended CBS is normally two times CBS_min. VCC This capacitance value can be changed according to the switching frequency, the type of capacitor used, and the recommended VBS voltage of 13.5~16.5 V (from datasheet). The above result is a calculation example and can be changed according to the actual control method and lifetime of the selected components. CBS ichg VB RBS DBS CVCC VCC(H) OFF IN(H) ON IN(L) COM Figure 27. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 (13) Motion SPM® VB VCC HO IN(H) HVIC VS VDC IN(L) LO COM Charging Bootstrap Capacitor at Startup www.fairchildsemi.com 12 AN-9077 APPLICATION NOTE 5.3. Minimum Pulse Width HIN As shown in Figure 28, input noise filters with a 450 ns time constant screen out pulses narrower than the filter time constant. Additional propagation delay in the level-shifter and other circuits, plus gate charging time, prevent Motion SPM 7 series from responding to a narrow input pulse. LIN HO LO Figure 31. HVIC of Motion SPM® 7 Series Input Level-Shift H/S Noise Circuit Restart Filter HIN Common Mode Noise Canceller Gate Driver w/ Gate Resistors HO Gate Driver w/ Gate Resistors LO 5.5. Selection of CFOD Inter Lock 500k(typ) Input L/S Noise Restart Filter LIN 500k(typ) Matching Delay The external capacitor connected between the CFOD and COM pins determines the Time of the Fault Output Duration (tFOD). The tFOD can be calculated by the following approximate equation: 450ns(typ) Figure 28. Timing for the Input and Output of HVIC Internal Structure of Signal Input Pins tFOD = CFOD / (24 x 10-6) [s] (14) 5.6. Short Circuit Test Motion SPM 7 series has MOSFET and behaves much more ruggedly than IGBT-based modules when short circuit situations occur. Figure 32 is the test circuit used to measure short circuit withstanding time and the definitions of the terms used in the measurement. The low-side MOSFET is shorted with a wire and the high-side device is turned on. 15-V Line Figure 29. R1 Test Result for Short Pulse Input P D1 5.4. Interlock Function C1 The Motion SPM® 7 series interlock function prevents shoot-through phenomena when high- and low-side input, HIN and LIN, are placed in HIGH status at the same time. VCC VB HIN HO LIN VS COM LO C2 N 10F The first input signal has priority to prevent shoot-through. Table 7 and Figure 31 show the behavior of the interlock function based on one-leg diagram of SPM, Figure 30. 1F R2 One-Leg Diagram of SPM Example of bootstrap paramters: C1 = 0.1F ceramic capacitor, R1 = 20 Input RC filter : 100100pF Figure 32. Short Circuit Withstanding Time Test Circuit ® Figure 30. One-Leg Diagram of Motion SPM 7 Series Table 7. Logic Table for Inverter Output HIN LIN Output Status 0 0 Z Both MOSFETs OFF 0 1 0 Low-Side MOSFET ON 1 0 VDC High-Side MOSFET ON 1 1 Forbidden Interlock (refer to Figure 31) Open Open Z Same as (0,0) © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 TJ [°C] VDC [V] VDD [V] IMAX [A] IMIN [A] TSC [µs] 150.0 400.0 20.0 15.6 10.0 25.0 Figure 33. SCWT of FSB70250 at Worst Condition Figure 33 is a waveform of the FSB70250 at a short-circuit condition of VDC=400 V, VDD=VBS=20 V, TC=TJ=150°C. Even in this extreme condition, the FSB70250 demonstrates short-circuit withstand time (tSC) longer than IGBT modules. www.fairchildsemi.com 13 AN-9077 APPLICATION NOTE 6 Application Example 6.1. General Application Circuit Examples Motion SPM® 7 Series (19) VS(W) (22) Pu (23)(23a) VS(V) VDC (24)(24a) VS(U) 15V Line C1 104 C2 104 C3 104 R1 20R D1 US1J (25) VB(U) D2 US1J (26) VB(V) (27) VB(W) (5) VDD C14 105 R4 100R MICOM 5V Line R8 4.7K (7) IN(VH) Note1 (9) IN(WH) R5 100R (10) IN(UL) R6 100R (11) IN(VL) R7 100R (12) IN(WL) C4 C5 C6 C7 C8 C9 (1) /FO 102 102 102 102 102 102 VB(U) HO(U) VB(V) VS(U) (2) VTS (14) U VB(W) HO(V) VDD (8)(8a) COM (6) IN(UH) Note3 (16) V VS(V) COM UH (4) Csc Motor C21 104 600V HO(W) VH UL C22 220uF 600V (17) W VS(W) WH LO(U) VL (13) NU WL /FO LO(V) Note4 VTS (3) Cfod C13 102 15V Line ZD1 MMSZ5250B Note2 R3 100R Note4 (20) Pw D3 US1J R2 100R (21) Pv (15) NV Note4 R11 0R50 1/2W CFOD CSC LO(W) R9 0R50 1/2W (18) NW 5V Line R10 2K C15 102 C16 333 C17 102 C10 220uF/35V C11 220uF/35V Note5 Note6 C12 104 Figure 34. Example of Application Circuit Notes: 1. Shorter traces are desired between the microprocessor and the power module. If necessary, RC filters can be employed on gate signals to suppress noise coupled from power traces and remove very narrow pulses. RC values should be selected for input signals to be compatible with the turn-on and turn-off threshold voltages. Keep in mind that this RC filter may alter the timing of PWM and the resulted volt-second. 2. Each HVIC needs to have an 1 µF cermaic capacitor close to VDD pin and possibly to Com pin to supply instantaneous power. An electrolytic capacitor of 10 µF is required as well to supply stable VDD voltage to the module. A Zener diode can be used in parallel to make sure VDD does not increase beyond certain voltage at surge events. 3. A high frequency non-inductive capacitor of around 0.1~0.22 µF, C21, should be placed very close to the module and between P and the ground side of the shunt resistor R9 and R11. 4. PCB traces for the main power paths between DC bus capacitor C22 and the module should be as short as possible to minimize the noise associated with the parasitic inductance. These traces are colored in blue. 5. The current feedback trace should be connected directly from the shunt resistor (Kelvin connection) to get a clean and undistorted signal. 6. Power ground and signal ground need to be connected at a single point to prevent noise from the power to interfere with control signals. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 14 AN-9077 APPLICATION NOTE 6.2. Recommended Wiring of Shunt Resistor Incorrect position of Snubber Capacitor External current-sensing resistors are applied to detect phase current. A longer pattern between the shunt resistor and SPM pins causes large surge voltages that might damage the IC and distort the sensing signals. To decrease the pattern inductance, the wiring between the shunt resistor and SPM pins should be as short as possible. Parasitic impedance between the shunt resistor and the power module pins should be less than 10 nH, which results from a trace in 3 mm width, 20 mm length, and 1 oz thickness. P A Capacitor Bank B SPM Wiring Leakage Inductance Nu,Nv,Nw 6.3. Snubber Capacitor Please make the connection point as close as possible to the terminal of shunt resistor As shown in Figure 35, snubber capacitors should be located to suppress surge voltages effectively. Generally a 0.1～0.22 µF snubber capacitor is recommended. If the snubber capacitor is installed in location ‘A’ in Figure 35, it cannot suppress the surge voltage effectively because of parasitic impedance of the traces between the capacitor and the module. If the capacitor is installed in the location ‘B’, surge suppression is most effective because the snubber capacitor is connected right at the module power pins. However, in a single shunt resistor is used for phase current reconstruction or over-current protection, the voltage across the shunt resistor cannot correctly reflect the DC bus current information consumed by the module and, therefore, the current feedback signal is distorted. The ‘C’ position is a reasonable compromise with better suppression than in location ‘A’ without impacting the current sensing signal accuracy. For this reason, the location ‘C’ is generally used. Figure 36. Correct position of Snubber Capacitor Wiring inductance should be less than 10nH. width > 3mm, length < 20mm Figure 35. Recommended Wiring of Shunt Resistor and Snubber Capacitor 6.4. PCB Layout Guidance Figure 36 shows the PCB layout of the test board. Figure 37 shows the actual test board. The compact size of Motion SPM 7 series is the key to overcome the mechanical challenge in this type of design. More detailed guideline can be found in RD-356. PCB Layout Example © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 COM Shunt Resistor Figure 37. Test Board www.fairchildsemi.com 15 AN-9077 APPLICATION NOTE 6.5. Thermal Characteristics Figure 38 shows thermal equivalent circuit of an Motion SPM 7 series with heat sink placed on the bottom side of the PCB. Even though heat sink is absent, the PCB plays a role as a heat sink. In this case, TJ can be calculated as: TJ PD RJCB TCB (15) Figure 40. TJ TCB TH (Case Bottom) (Heat Sink = PCB) RΘJCB RΘCBH TA 6.6.2 Simulation for RθJCB The analysis model and boundary conditions for RθJCB are: RΘHA PD Three-dimensional model, steady-state analysis Flow, heat transfer, and radiation solution Simplified model Based on Mil Std 883C Method 1012.; Thermal Characteristics of Microelectronic Devices Figure 41 shows the modeling for RθJCB with ideal condition with infinite cooling. RΘCBA Figure 38. Vertical Structure of Trace Thermal Equivalent Circuit with Heat Sink on Bottom-Side 6.6. Thermal Simulation 6.6.1 Condition for RθJCB and RθJA To investigate thermal characteristics of the Motion SPM 7 series, variable conditions should be considered. The following simulation results for RθJCB and RθJA adopt variable factors with test board, solder void, and PCB pattern. SPM7 Package General description for the thermal test board specification is as shown in Table 8. TC: 25°C Infinite cooling block Table 8. Specification for Thermal Test Board Class Thermal Test Board Specification Overall Size 114.3 * 76.2 * 1.6 mm Trace Width 0.25 mm ±10% for ≥ 0.5 mm Pin Pitch; lead width for < 0.5 mm Pin Pitch Trace Thickness Signal: 2 oz (0.07 mm ±20%), Power/Ground: 1 oz (0.035 mm +0/-20%) Buried Plane Size 74 x 74 mm Trace Pitch (via spacing) 2.54 mm Fan Out Trace Length Remarks Figure 39. Figure 41. 3 Modeling for RθJCB Table 9 and Table 10 show analysis results for the simulation. The portion of the solder void is 0 ~ 20% of the chip size. 2 Table 9. Solder Void vs. RθJCB at 1 Chip Heating RθJCB at 1 Chip Heating [°C/W] Solder Void Low-Side High-Side HVIC Min. 25 mm Void Free 1.073 1.073 0.386 PKG Length <27 mm 2% 1.225 1.224 0.513 4% 1.358 1.354 0.617 6% 1.476 1.475 0.704 8% 1.596 1.592 0.804 10% 1.722 1.732 0.895 12% 1.826 1.824 0.979 14% 1.956 1.964 1.052 16% 2.044 2.036 1.149 18% 2.182 2.180 1.225 20% 2.316 2.312 Trace Array Pattern for Thermal Attachment © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 16 AN-9077 APPLICATION NOTE Table 10. Solder Void vs. RθJCB at Total Chip Heating RθJCB at Total Chip Heating [°C/W] Solder Void Low-Side High-Side HVIC Void Free 1.073 1.074 0.386 2% 1.225 1.226 0.513 4% 1.359 1.354 0.617 6% 1.476 1.477 0.702 8% 1.596 1.594 0.801 10% 1.722 1.736 0.895 12% 1.828 1.830 0.977 14% 1.958 1.970 1.049 16% 2.046 2.040 1.145 18% 2.184 2.184 1.220 20% 2.318 2.318 1.307 Figure 42. Based on JEDEC 51-2, integrated circuits thermal test method environment conditions - natural convection (still air) Various thermal test board options: 1s0p (one signal layer and zero power layer) with copper plane (minimum and 74mm2 land pattern per MOSFET, JESD51-3) 1s2p (one signal layer and two power layers) with copper plane (minimum and 74mm2 land pattern per MOSFET, JESD51-7) Figure 43 and Figure 44 show the dimensions of the thermal test board. Thermal Test Board (JESD51-3) Figure 44. Thermal Test Board (JESD51-7) Solder Void vs. RθJCB 6.6.3 Simulation for RθJA The SPM7 is mounted on the PCB specified in JEDEC to simulate RθJA. The Analysis model and boundary conditions for RθJA are: Figure 43. Three-dimensional model, steady-state analysis Flow, heat transfer, and radiation solution Simplified model Table 11. Solder Void vs. RθJA at 1s0p PCB 2 Solder Void RθJA at 1s0p PCB with Min. Cu Trace Pattern at Total Chip Heating (CASE1) [°C/W] RθJA at 1s0p PCB with 74 mm Cu Trace Pattern for MOSFET at Total Chip Heating (CASE2) [°C/W] Low-Side High-Side HVIC Low-Side High-Side HVIC Void Free 253.1 281.5 1441.7 183.9 199.0 1423.7 4% 253.1 281.7 1441.6 183.9 199.0 1423.7 10% 253.2 282.1 1441.6 183.9 199.3 1423.7 14% 253.4 282.3 1441.6 184.1 199.6 1423.6 20% 253.7 282.5 1441.6 184.4 199.8 1423.6 © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 17 AN-9077 APPLICATION NOTE Table 12. Solder Void vs. RθJA at 1s2p PCB 2 Solder Void RθJA at 1s2p PCB with Min. Cu Trace Pattern at Total Chip Heating (CASE3) [°C/W] RθJA at 1s2p PCB with 74 mm Cu Trace Pattern for MOSFET at Total Chip Heating (CASE4) [°C/W] Low-Side High-Side HVIC Low-Side High-Side HVIC Void Free 112.0 118.6 1390.8 92.8 96.8 1549.6 4% 112.3 118.8 1390.8 92.8 96.8 1549.6 10% 112.6 119.2 1390.8 93.2 97.1 1549.6 14% 112.8 119.4 1390.8 93.4 97.3 1549.6 20% 113.1 119.6 1390.8 93.7 97.5 1549.6 Figure 46. Figure 45. Top Side of the Test Board Solder Void vs. RθJA As shown in the simulation results, the epoxy void does not seem to be a significant risk factor for thermal performance of SPM 7 series. In simulation, the portion of increasing RθJA caused by epoxy solder void is smaller than total RθJA value. In real evaluation, the effect solder void is observed as shown in Figure 45. Additionally, it is observed that narrow width of the copper pattern leads to increasing RθJA. The RθJA difference between high- and low-side MOSFET is absorbed. Figure 48 shows the test bench of the evaluation test. 6.7. Evaluation Test The top of the case temperature was measured by an infrared camera to evaluate the effect of copper thickness and solder void. Figure 47. The condition of the evaluation test is the following: VDC = 300 V, VDD = VBS = 15 V, fSW = 16.6 kHz PWM method: SVPWM Output current = 0.3/0.4/0.5 Arms No heat sink Test board: FR4, 2 layer, 1 oz & 2 oz. Bottom Side of the Test Board As shown in the Table 13, increasing the thickness of the copper pattern can decrease the temperature of the case because it can reduce the thermal resistance. As shown in Table 14, increasing solder void can increase the temperature of the case slightly. Figure 46 and Figure 47 show the layout of the test board. Figure 48. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 Test Bench www.fairchildsemi.com 18 AN-9077 APPLICATION NOTE Table 13. Effect of Cu Thickness Copper Thickness 0.3 Arms 0.4 Arms 1 oz 69.2°C 91.5°C 2 oz 58.8°C 75.3°C 0.5 Arms 100°C Table 14. Effect of Solder Void at Irms = 400 mA, 1 oz, TA=21°C Small Void (<15%) Large Void (15~35%) Worst Case (>90%) 86°C 87.3°C 91.4°C As shown in Table 15, increasing the area of copper pattern for P (positive DC bus) decreases the temperature of the case because it reduces the thermal resistance. Table 15. Effect of Pattern width at Irms = 400 mA, 1 oz, TA=21°C Narrow Width (10 mm) Wide Width (20 mm) 83.5°C 74°C © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 19 AN-9077 APPLICATION NOTE 7 Packing and Installation Guide 6.8. System Performance A fan motor for an indoor air-conditioner unit has been tested to provide comparison data between the Motion SPM 7 Series and competition products. 7.1. Handling Precautions When using semiconductors, the incidence of thermal and/or mechanical stress to the devices due to improper handling may result in significant deterioration of electrical characteristics and/or reliability. Figure 49 illustrates the power loss of a single power device, such as MOSFET or IGBT. Under the same operating conditions, the FSB70550 shows the lowest conduction loss and switching loss compared to competitive products. Low power loss means better energy efficiency in the system. 7.1.1 Transportation Handle the device and packaging material with care. To avoid damage to the device, do not toss or drop. During transport, ensure that the device is not subjected to mechanical vibration or shock. Avoid getting devices wet. Moisture can also adversely affect the packaging (by nullifying the effect of the antistatic agent). Place the devices in conductive trays. When handling devices, hold the package and avoid touching the leads, especially the gate terminal. Put package boxes in the correct direction. Putting them upside down, leaning them, or giving them uneven stress can cause the electrode terminals to be deformed or the resin case to be damaged. Throwing or dropping the boxes can cause the devices to be damaged. Wetting the packaging boxes can cause breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or a snowy day. Figure 49. Single MOSFET/IGBT Power Loss Comparison (Simulation Condition: VDC=300 V, VDD=15 V, fSW=16.6 kHz, SVPWM, MI=0.8, PF=0.9, IO=500 mArms) Figure 50 shows the test bench set up and the case temperature comparison. Under the same operating conditions, the FSB70550 shows outstanding thermal performance compared to competitive parts. 7.1.2 Storage Avoid locations where devices may be exposed to moisture or direct sunlight. (Be especially careful during periods of rain or snow). Do not place the device cartons upside down. Stack the cartons on top of one another in an upright position only. Do not place cartons on their sides. The storage area temperature should be maintained within a range of 5°C to 35°C, with humidity kept within the range from 40% to 75%. Do not store devices in the presence of harmful (especially corrosive) gases or in dusty conditions. Ensure storage areas have minimal temperature fluctuation. Rapid temperature changes can cause moisture condensation on stored devices, resulting in lead oxidation or corrosion. As a result, lead solderability is degraded. When repacking devices, use antistatic containers. Unused devices should be stored no longer than one month. Do not allow external forces or loads to be applied to the devices while in storage. 7.1.3 Environment Be aware of the risk of moisture absorption by the products after unpacking from moisture-proof packaging. Figure 50. Case Temperature Comparison of Motion SPM 7 Series and Competitors (Test Conditions: VDC = 150 V, VDD = 15 V, fSW = 20 kHz, PWM Method = SVPWM, DT=2 µs, Servo Motor) © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 As humidity in the work environment decreases, the human body and other insulators become charged with electrostatic electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment. www.fairchildsemi.com 20 AN-9077 APPLICATION NOTE Be sure that all equipment, jigs, and tools in the working area are grounded to earth. When storing device-mounted circuit boards, use a board container or bag protected against static charge. To prevent static charge/discharge due to friction, keep them separated and do not stack them directly on top of one another. Place a conductive mat on the work area floor, or take other appropriate measures, so the floor surface is grounded to earth and protected against electrostatic electricity. Ensure that articles (such as clipboards) brought into static electricity control areas are constructed of antistatic materials as far as possible. Cover the workbench surface with a conductive mat, grounded to earth, to disperse electrostatic electricity on the surface through resistive components. Workbench surfaces must not be constructed of low-resistance metallic material that allows rapid static discharge when a charged device touches it directly. In cases where the human body comes into direct contact with a device, be sure to wear finger cots or gloves protected against static electricity. 7.1.4 Electrical Shock A device undergoing electrical measurement poses the danger of electrical shock. Do not touch a device unless sure that power to the measuring instrument is OFF. Ensure that work chairs are protected with an antistatic textile cover and are grounded to the floor surface with a grounding chain. Install antistatic mats on storage shelf surfaces. 7.1.5 Circuit Board Coating When using devices in equipment requiring high reliability or in extreme environments (where moisture, corrosive gas, or dust is present), circuit boards can be coated for protection. However, before doing so, carefully examine the possible effects of stress and contamination that may result. There are many and varied types of coating resins whose selection is, in most cases, based on experience. However, because device-mounted circuit boards are used in various ways, factors such as board size, board thickness, and the effects that components have on one another, makes it practically impossible to predict the thermal and mechanical stresses that semiconductor devices encounter. For transport and temporary storage of devices, use containers made of antistatic materials or materials that dissipate static electricity. Ensure that cart surfaces that come into contact with device packaging are made of materials that conduct static electricity and are grounded to the floor surface with a grounding chain. Operators must wear antistatic clothing and conductive shoes (or a leg or heel strap). Operators must wear a wrist strap grounded to earth through a resistor of about 1 MΩ. If tweezers are likely to touch the device terminals, use an antistatic type and avoid metallic tweezers. If a charged device touches such a low-resistance tool, a rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pad at the tip and connect it to a dedicated ground used expressly for antistatic purposes. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 21 AN-9077 APPLICATION NOTE 8 Packing Specification Motion SPM 7 series is shipped in tape. More detailed information can be found in Figure 51. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 22 AN-9077 APPLICATION NOTE Figure 51. Packing Information Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/PQ/PQFN27A.pdf For current packing container specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-PQFN27A.pdf © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 www.fairchildsemi.com 23 AN-9077 APPLICATION NOTE 9 Related Resources AN-9078 — Surface Mount Guidelines for Motion SPM® 7 Series RD-356 — Fairchild Motion SPM® 7 Series Reference Design FSB70325 — Motion SPM® 7 Series FSB70625 — Motion SPM® 7 Series FSB70250 — Motion SPM® 7 Series FSB70450 — Motion SPM® 7 Series FSB70550 — Motion SPM® 7 Series SPM® Module Design Guide Motion Control Design Tool DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. 2. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2014 Fairchild Semiconductor Corporation Rev. 1.0.2 • 8/22/14 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 24