318 PIxEQX6741Sx PIxEQX6741Sx SATA ReDriver Application Note Introduction PIxEQX6741Sx SATA ReDriver™ devices are developed to re-drive one full-lane of SAS/SATA signals up to 6Gbps. The devices’ features include lower power consumption and high performance. Figure1 shows typical application examples. PIxEQX6741Sx series devices support Termination Detect indication (TDet_A# or TDet_B#), which provides indication when load (HDD or Host) is connected. Also, HDD unplug condition feature can be used to control the device to go into power saving mode by the host. Packaging: 20-contact TQFN (4x4mm) Main Applications: - Server - Desktop - Storage/Workstation R=PIxEQX6741 SATA ReDriver Figure1a Typical Application Sample1 R=PIxEQX6741 SATA ReDriver Figure 1: Examples of Typical Application Page 1 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 PIxEQX6741Sx Part Selection for Various Applications PIxEQX6741Sx series devices include PI3EQX6741ST, PI3EQX6741STB and PI2EQX6741SL. These parts’ Applications Standards Recommended Device Package Low Power 1.05V VDD; NoteBook/Docking SATA 1.5G, 3.0G, 6.0G PI2EQX6741SL TQFN-20 3.3V VDD; NoteBook/Docking Desktop Sever/Storage SATA 1.5G, 3.0G, 6.0G SAS (G1-1.5g, G2-3.0g) PI3EQX6741ST PI3EQX6741STB, compatible with TI-SN75LVCP412CD TQFN-20 Table 1: Application Based Selection Table PI2EQX6741SLZDE supports +1.05V power supply, and the other two parts support from +3.3V power supply. Power consumption (mW) Comparison of Feature (Part Number) VDD (V) Max. Slumber Mode Standby PI2EQX6741SLZDE 1.05 104.5 15.4 PI3EQX6741S TZDE PI3EQX6741S TBZDE 3.3 342 50 Termination Detect Y/N Power Consumption(mW) When HDD is unplugged 1.1 √ 5.5 3.6 √ 18 Table 2: Power consumption at 1.2V and 2.5~3.3V Power Supply External Components Requirement PIxEQX6741SxZDE series devices require AC coupling capacitors for all redriver inputs and outputs. High-quality, low-ESR, X7R, 10nF, 0402-sized capacitors are recommended. Layout Design Guide Layout Considerations for Differential Pairs - The trace length miss-matching shall be less than 5 mils for the “+” and “–“ traces in the same pairs - Use wider trace width, with 100ohm differential impedance, to minimize the loss for long routes - Target differential Zo of 100ohm ±20% - More pair-to-pair spacing for minimal crosstalk coupling, it is recommended to have >3X gap spacing between differential pairs. - It is preferable to route differential lines exclusively on one layer of the board, particularly for the input traces - The use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be placed symmetrically for each side of a given differential pair. - Route the differential signals away from other signals and noise sources on the printed circuit board Page 2 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 PCB Layout Trace Routings Figure 2: Layout Sample for Trace Routings Power-Supply Bypass Designers must pay attention and be careful with the details associated with high-speed design as well as providing a clean power supply; there are some approaches that are recommended. - The supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers of the printed circuit board. The distance to plane should be <50mil. - The layer thickness of the dielectric should be minimized so that the VDD and GND planes create a low inductance supply with distributed capacitance. - Careful attention to supply bypassing through the proper use of bypass capacitors is required. A low-ESR 0.01uF bypass capacitor should be connected to each VDD pin such that the capacitor is placed as close as possible to PIxEQX6741SxZDE. Smaller body size capacitors can help facilitate proper component placement. - The distance of capacitors to IC body should be <100mil. - One capacitor with capacitance in the range of 1uF to 10uF should be incorporated in the power supply bypassing design as well. It is can be either tantalum or an ultra-low ESR ceramic. Page 3 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Power Supply Sequencing Proper power supply sequencing is recommended for all devices. Always apply GND and VDD before applying signals. especially if the signal is not current limited. Caution: Do NOT exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the device. Equalization and Pre-emphasis Setting Various Input Traces and Eye Tests with different EQ settings Figure 3 shows the test setup for testing PIxEQX6741SxZDE in different EQ setting. “R” in the figure represents PIxEQX6741SxZDE. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 600mV, Pre-emphasis is 0dB EQ Setting Input Trace Fixture 24inch SMA Cable Signal Generator Tektronic Sampling Scope R TP3 EM=0dB TP4 Figure 3: EQ Setting Test Setup for PIxEQX6741SxZDE Input Trace Length 6 inch FR4 Lab trace (-2dB loss at 3GHz) EQ Setting 3dB (A_EQ or B_EQ =Low) 18 inch FR4 Lab trace (-6dB loss at 3GHz) 3dB (A_EQ or B_EQ =Low) 30 inch FR4 Lab trace (-10dB at 3GHz) 6dB (A_EQ or B_EQ =Open) 48 inch FR4 Lab trace (-16dB loss at 3GHz) 9dB (A_EQ or B_EQ =High) Input Eye at TP3 Output Eye at TP4 Table 3: Eye Diagram vs. Input FR4 trace and EQ Setting at 6Gb/s Page 4 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Input Trace Length 6 inch FR4 Lab trace (-1.2dB loss at 1.5GHz) 18 inch FR4 Lab trace (-3dB loss at 1.5GHz) EQ Setting Input Eye at TP3 Output Eye at TP4 2.5dB (A_EQ or B_EQ =Low) 2.5dB (A_EQ or B_EQ =Low) 30 inch FR4 Lab trace (-5dB loss at 1.5GHz) 5dB (A_EQ or B_EQ =Open) 48 inch FR4 Lab trace (-9dB loss at 1.5GHz) 7.5dB (A_EQ or B_EQ =High) Table 4: Eye Diagram vs. Input FR4 trace and EQ Setting at 6Gb/s Various Input Traces and Eye Tests with different Pre-emphasis settings Figure 4 shows the test setup for testing PIxEQX6741SxZDE in different EM setting. “R” in the figure represents PIxEQX6741SxZDE. Signal Source: PRBS2^7-1 pattern, Differential Voltage is 600mV, Pre-emphasis is 0dB EM Setting Output Trace Fixture 24inch SMA Cable Signal Generator Tektronic Sampling Scope R TP1 EQ=Low TP2 Figure 4: EM Setting Test Setup for PIxEQX6741SxZDE Page 5 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 EM Setting Eye Test at TP2 for Various Output Trace 6 inch 12 inch FR4 Lab trace FR4 Lab trace (-2dB loss at (-4dB loss at No trace 3GHz) 3GHz) EM=low EM=High Table 5: Eye Diagram vs. Output FR4 Trace and EM setting at 6Gb/s EM Setting Eye Test at TP2 for Various Output Trace 6 inch 12 inch FR4 Lab trace FR4 Lab trace (-1.2dB loss at (-2.2dB loss at No trace 1.5GHz) 1.5GHz) EM=low EM=High Table 6: Eye Diagram vs. Output FR4 Trace and EM setting at 3Gb/s Termination Detect Feature Figure 5 shows the test setup for testing termination detect feature. “R” in the figure represents PIxEQX6741SxZDE. TDet_A# or TDet_B# MB HDD R TDet_EN =High TP6 Figure 5: PIxEQX6741SxZDE test setup for Termination Detect Feature Page 6 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Table7 shows the relationship between TDet_A#/TDet_B# and SATA signal at TP5/TP6 when HDD/HOST is plugged and unplugged at TDet_EN=HIGH HDD/HOST Plugged A/B_OS=2.7kohm A/B_OS =2.0kohm SATA Signal at TP5 SATA Signal at TP6 TDet_A# TDet_B# SATA Signal at TP5 SATA Signal at TP6 TDet_A# TDet_B# Unplugged Table 7: TDet_A#/TDet_B# and SATA signal at TP5/TP6 Page 7 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Typical Application Circuit Figure 6a and 6b show typical application circuits of PI3EQX6701xZDE. +3.3V C2 1u_0805 10n_0402 10n_0402 +3.3V R8 +3.3V R9 HOST Controller 10n_0402 AI_N C7 10n_0402 BO_N C9 10n_0402 BO_P C11 10n_0402 0ohm or Open 0ohm or Open A_EQ R6 0ohm or Open U1 1 2 3 4 5 GPIO Device Connector AI+ AITDet_B# BOBO+ AO+ AOTDet_A# BIBI+ 15 14 13 12 11 NC EN B_EM A_EM VDD C5 0ohm or Open TDet_EN R2 C6 10n_0402 AO_P C8 10n_0402 AO_N C10 10n_0402 BI_N C12 10n_0402 BI_P 1 2 3 4 5 6 7 JP1 1 2 3 4 5 6 7 SATA CONNECTOR PI3EQX6741STZDE@TQFN20 6 7 8 9 10 AI_P 0ohm or Open B_EQ R1 21 20 19 18 17 16 C1 HGND VDD B_EQ TDet_EN A_EQ NC C3 HDD Detect A_EM R3 R7 100kohm VDD_Host 0ohm or Open B_EM R4 0ohm or Open EN 0ohm or Open R10 Figure 6: Typical Application Circuit of PI3EQX6741STZDE +1.05V +1.05V C2 1u_0805 10n_0402 10n_0402 R8 +1.05V R9 HOST Controller 10n_0402 AI_N C7 10n_0402 BO_N C9 10n_0402 BO_P C11 10n_0402 0ohm or Open 0ohm or Open A_EQ R6 0ohm or Open U1 1 2 3 4 5 GPIO Device Connector AI+ AITDet_B# BOBO+ AO+ AOTDet_A# BIBI+ 15 14 13 12 11 VDD EN B_EM A_EM VDD C5 0ohm or Open TDet_EN R2 6 7 8 9 10 AI_P 0ohm or Open B_EQ R1 21 20 19 18 17 16 C1 HGND VDD B_EQ TDet_EN A_EQ VDD C3 C6 10n_0402 AO_P C8 10n_0402 AO_N C10 10n_0402 BI_N C12 10n_0402 BI_P JP1 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SATA CONNECTOR PI2EQX6741SLZDE@TQFN20 HDD Detect A_EM R3 VDD_Host R7 100kohm 0ohm or Open B_EM R4 0ohm or Open EN 0ohm or Open R10 Figure 7: Typical Application Circuit of PI2EQX6741SLZDE Page 8 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 +3.3V C3 C1 C2 1u_0805 10n_0402 10n_0402 +3.3V 0ohm or Open A_EQ R9 TDet_EN +3.3V R7 R6 0ohm or Open R1 0ohm or Open 100kohm Device Connector C5 10n_0402 AI_N C7 10n_0402 BO_N C9 10n_0402 BO_P C11 10n_0402 1 2 3 4 5 AI+ AINC BOBO+ HGND VDD TDet_EN TDet_A# EQ_A NC AI_P U1 21 20 19 18 17 16 HDD_Detect 6 7 8 9 10 GPIO VDD_Host NC EN B_EM A_EM VDD HOST Controller AO+ AONC BIBI+ 15 14 13 12 11 C6 10n_0402 AO_P C8 10n_0402 AO_N C10 10n_0402 BI_N C12 10n_0402 BI_P PI3EQX6741STBZDE@TQFN20 A_EM R3 JP1 1 2 3 4 5 6 7 SATA CONNECTOR 0ohm or Open B_EM R4 0ohm or Open EN 0ohm or Open R10 1 2 3 4 5 6 7 Figure 8: Typical Application Circuit of PI2EQX6741SLZDE Page 9 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Sample PCB Layout Figure 9 shows typical layout routing of PI3EQX6741STZDE. Figure 9: Typical Layout Routing of PI3EQX6741STZDE Figure 10 shows typical layout routing of PI3EQX6741SLZDE. Figure 10: Typical Layout Routing of PI3EQX6741SLZDE Page 10 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011 318 Figure 11 shows typical layout routing of PI3EQX6741STBZDE. Figure 11: Typical Layout Routing of PI3EQX6741STBZDE Page 11 of 11 AN318 Pericom Semiconductor Corp. www.pericom.com 11/2/2011