PT8A2651 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| PIR Sensor Light Switch Controller Features Description Operating voltage: 5V (Typical) Average supply current: 120µA (Typical) automatic PIR lamp control. The chip is equipped with On-chip regulator operational amplifiers, a comparator, timer, a zero Build-in noise rejection circuit crossing detector, control circuit, a voltage regulator, a 16KHz system oscillator system oscillator, and an output timing oscillator. Adjustable output duration Override function induced by the motion of a human body and transforms ON/AUTO/OFF selectable by MODE pin it to a voltage variation. If the PIR output voltage Auto-reset with ZC signal disappearing over 3 variation conforms to the criteria (refer to the functional seconds description), the lamp is turned on with an adjustable Output positive pulses to drive triac duration. The PT8A2651 offers three operating modes CDS to enable/disable output (ON, AUTO, OFF) which can be set through the MODE 40 second warm-up pin. While the chip is working in the AUTO mode the Quick check mode for installation user can override it and switch to the quickly install Low cost SOIC-16 package mode or manual ON mode or return to the AUTO mode The PT8A2651 is a CMOS LSI chip designed for Its PIR sensor detects infrared power variations by switching the power switch. The chip is enclosed in a 16 pin SOIC. Pin Configuration 12-07-0006 PT0219-1 1 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Description Pin No. Pin Name I/O Pin Description 1 VSS I Ground 2 TRIAC O TRIAC drive to output two pulses, active positive pulse. 3 OSCD I/O 4 OSCS I/O 5 ZC I 6 CDS I 7 MODE I/O 8 VDD I Output timing oscillator. with an external RC to adjust output duration. System oscillator. with an external RC to set the system frequency. The system frequency =16KHz for normal application. Schmitt input for AC zero crossing detection CDS is connected to a CDS voltage divider for daytime/night auto-detection. Low input to this pin can disable the PIR input. CDS is a schmitt trigger input with 5-second input debounce time. Operating mode selection input: VDD: TRIAC is always ON VSS: TRIAC is always OFF Open: Auto detection, outputs 31.25Hz square wave Positive power supply 9 VEE O Regulated voltage output The output voltage is about 3.6V with respect to VSS. 10 RSTB I Chip reset input, active low 11 OP1P I Non-inverting input of OP1 12 OP1N I Inverting input of OP1 13 OP1O O Output of OP1 14 OP2P I Non-inverting input of OP2, internal 1.8V default. 15 OP2N I Inverting input of OP2 16 OP2O O Output of OP2 Block Diagram Figure 1 Block Diagram 12-07-0006 PT0219-1 2 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings Storage Temperature ................................................................................... -40oC to +125oC Ambient Temperature with Power applied...............................................-20oC to +70oC Supply Voltage to Ground Potential (Input & VCC Only).....VSS-0.5V toVDD+0.5V Supply Voltage to Ground Potential (Onput & D/O Only)..VSS-0.5V toVDD+0.5V DC Input Voltage .............................................................................................-0.5V to +6.0V DC Output Current ...................................................................... 20mA Power Dissipation ......................................................................................................... 500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended operation conditions Sym Parameter VDD VIH VIL Operating Voltage “H” Input Voltage “L” Input Voltage VDD - FSYS System Oscillator Frequency 5V TA Operating temperature - Test Conditions Conditions ROSCS=430K COSCS=180P - Min Typ Max Unit 4.75 0.8 - 5.0 - 6.0 0.2 V VDD VDD 12.8 16 19.2 KHz -20 25 70 °C Min Typ Max Unit 3.0 0.9 2.6 1.1 2.7 0.8 2.7 0.8 3.3 1.2 2.9 1.4 3 1 3 1 3.6 1.5 3.2 1.7 3.3 1.2 3.3 1.2 V V V V V V V V Electrical Characteristics Test Conditions Conditions Sym Parameter VTH1 VTL1 VTH2 VTL2 VTH3 VTL3 VTH4 VTL4 CDS “H” Transfer Voltage CDS “L” Transfer Voltage ZC “H” Transfer Voltage ZC “L” Transfer Voltage OSCS “H” Transfer Voltage OSCS “L” Transfer Voltage OSCD “H” Transfer Voltage OSCD “L” Transfer Voltage VDD 5V 5V 5V 5V 5V 5V 5V 5V I IH High level leakage current (ZC,CDS) 5V VIH=4.5V -1 - 1 A I IL Low level leakage current (ZC,CDS) 5V VIL=0.5V -1 - 1 A I IHRSTB IOH IOL RSTB Input high level current Output source current( TRIAC) Output sink current(TRIAC) 5V 5V 5V VIH=4.5V VOH=4.0V VOL=0.5V -1 -18 3 - -5 - A mA mA Min Typ Max Unit 3.24 1.62 3.6 1.8 3.96 1.98 V V - 30 50 mV - 60 100 mV - Voltage regulation circuit Sym Parameter VEE OP2P Regulator Output Voltage Non-inverting input of OP2 VDD 5V 5V VO Line regulation - VLDR Load regulation 5V Test Conditions Conditions No load No load 4.5VDD5.5V, IL =1mA 0.5mA IL2mA 12-07-0006 PT0219-1 3 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Operational amplifier and windows comparator Parameter BW VH VL Description 3dB band width Threshold of windows comparator Test conditions VDD=5V VDD=5V Min 10 2.2 0.8 Typ 2.52 1.08 Max 2.8 1.3 Unit KHz V V Typ 31.25 1.45 62.5 Max 37.5 1.74 75 Unit Hz ms s Min Typ Max Unit - 120 200 A Frequency of oscillator and timing of ZC and trigger output Parameter FMODE TDZT TTPW Description Oscillator frequency/512 Delay time from ZC to TRIAC TRIAC Pulse Width Test conditions VDD=5V, RS=430K ,CS=180P Min 25 1.16 50 Power Dissipation Sym Description ICC Power supply current Test Conditions VDD=5V, RS=430K ,CS=180P, RD =2M, CD=104, other Input Pins=VSS, all outputs float. 12-07-0006 PT0219-1 4 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Functional Description VEE VEE supplies power to the analog front end circuit, it is about a stable 3.6V with respect to VSS normally. OSCS OSCS is a system oscillator input pin. System frequency of 16KHz can be generated when connecting to an external RC, see figure 2 (R=430K, C=180pf). TD=23552/FOSCD RS VTH3 + VTL3 + 430k OSCS CS + VTH4 RD OSCD + 180P CD PT8A2641/2/5/6/7/8 + VTL4 + + + PT8A2641/2/5/6/7/8 Figure 2 System oscillator Figure 3 Output timing oscillator OSCD OSCD is input pin of timing oscillator. It’s connected to an external RC to obtain the desired output timer. Variable output turn-on duration can be achieved by selecting various values of RC or using a variable resistor, see figure 3. Note: The minimum resistor should be low enough to 2K in order to provide adjustable range about 1000 times between min and max timer. Formula for timer calculation as below (VH=3/5VCC,VL=1/5VCC) Charging time of Capacitor: Tc =R*C*ln[(VCC-VL)/(VCC-VH)]=0.6931*R*C Ideal calculation formula: TD =23552*Tc. 5s 12minutes(720s) R (C=223) 15K 2000K Error compared to ideal formula ±15% ±5% 3s 5s 25s R (C=104) 2K 3K 15K Error compared to ideal formula ±100% ±80% ±15% Note: It is recommended that C is more than 103 in order to guarantee not too bad linearity. 5000s 3000K ±5% TRIAC TRIAC to drive (active positive pulse) TRIAC. The output active duration is controlled by the OSCD oscillating period. CDS With a schmitt trigger input structure, CDS is used to distinguish lighteness. Putting a cds component in a resistor divider, if light is weak enough, CDS is high the PIR input is active. Oppositely, the CDSO will be inactive when CDS is low. The input debounce time from inactive to active is 5 seconds. CDS should be pulled high without using this function. The input of CDS will be ignored once the output is active. CDS Status CDSO LOW Day Time inactive HIGH Night active RW CDS CDS CDS CDSO enable <5s >5s disable enable Figure CDS input interface and enable debounce Figure 44CDS input interface and enable debounce 12-07-0006 PT0219-1 5 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| RSTB RSTB is used to reset the chip. It is internal pull-high and active low. The use of CRST can extend the power-on initial time. If the RSTB pin is an open circuit (without CRST), the initial time is the default (40 secs). VCC REST Power on initial RSTB Because the band-pass filter and amplifier require a warm up period to reach a stable state after power-on so any inputs should be ignored during this period. CRST VSS In the AUTO mode within the first 10 seconds of power-on initialization, the system allows override control to access the quickly install mode. However, after FigureFig.5 5 RSTB example RSTBapplication application example 40 seconds of the initial time the system allows override control between ON and AUTO. It will remain in the warm up period if the total initial time has not elapsed after returning to AUTO. In case that the ZC signal disappears more than 3 seconds, the chip will restart the initialization operation. However, the restart initial time is always 40 seconds and cannot be extended by adding CRST to the RSTB pin as shown in Fig.5. MODE MODE is a tri-state input pin used to select the operating mode. MODE Operating Mode Description VDD Output always ON TRIAC outputs positive pulse train with synchronizing to ZC VSS Output always OFF TRIAC outputs low Outputs remain off state until activated by a valid PIR trigger signal. When working in Open AUTO the AUTO mode, the chip allows override control by switching the ZC signal. MODE outputs square wave with frequency of 31.25Hz. ZC ZC samples AC signal and generates zero crossing pulses to synchronize the TRIAC driver. With an effective ZC signal switching (switch OFF/ON 2 times within 3 seconds), the system provides the following additional functions: Quickly install mode: Within 10 seconds after power-on, effective ZC switching will force the chip to enter the quickly install mode. During the mode, the outputs will be active for a duration of 1.3 seconds each time a valid PIR trigger signal is received. If a time interval exceeds 32 seconds without a valid trigger input, the chip will enter the AUTO mode automatically. Figure 6 Test mode Override control When the chip is working in the AUTO mode (MODE= open), the output is activated by a valid PIR trigger signal and the active output duration is controlled by the OSCD oscillating period. The lamp can be switched always to “ON” from the AUTO mode by either switching the MODE pin to VDD or switching the ZC signal by an OFF/ON operation of the power switch (OFF/ON twice within 3 seconds). The term "override" refers to the change of operating mode by switching the power switch. The chip can be toggled from ON to AUTO by an override operation. Shows as Fig.7. If the chip is overridden to ON and there is no further override operation, it will return to AUTO automatically after an internal preset ON time duration has elapsed. This override ON time duration is set to 5 hours. During any operation (including override and the end of warm up as well as quick install mode), output will not flash. 12-07-0006 PT0219-1 6 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Figure 7 ZC override timing PIR amplifier Refer to the following diagram for details on the front end amplifier of PIR. In Fig.8 there are 2 op-amps with different applications. OP1 can be used independently as a first stage inverting or noninverting amplifier for the PIR. As the output of OP2 is directly connected to a comparator. The non-inverting input of OP2 is connected to the comparator’s window center point and can be used to check this voltage and provide a bias voltage that is equal to the center point voltage of the comparator. In Fig.8 the comparator can have window width VCP=VCN= (1/5) VEE. VEE Regulator OP1O OP1P OP1N + _ OP1 Comparator _ OP2O OP2P OP2N + OP2 VCP + + _ VCN COMPO + Second stage amplifier Usually the second stage PIR amplifier OP2 is a simple capacitively coupled inverting amplifier with a band pass configuration. The non-inverting input terminal is biased to the VSS center point of the comparator window and the output of OP2 is Figure 8 PIR amplifier directly coupled to the comparator center point. Fig.8 PIR amplifier In Fig.9, OP2P is directly connected to the comparator window center, and with the C3 filter it can act as the bias for OP2. For this configuration AV = R2/R1, low cutoff frequency fL = 1/2R1C1, high cutoff frequency fH = 1/2R2C2. By changing the value of R2 the sensitivity can be varied. C1 and C3 should be of low leakage types to prevent the DC operating point from change due to current leakage. Each op-amp current consumption is approximately 15A with the op-amps and comparator’s working voltage all provided by the regulator. Refer to the following diagrams for typical PIR front end circuit. VEE RW R2 1M R1 22K + _ first stage output OP2O Comparator C2 0.022 _ OP2N OP2 OP2P + C1 22U RW _ + COMPO + RW 10U C3 + RW Typical second amplifier Figure 9Fig.9 Typical second stagestage amplifier 12-07-0006 PT0219-1 7 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| First stage of PIR amplifier Fig.10 shows a typical first stage amplifier. C2 and R2 form a simple low pass filter with cut off frequency at 7Hz. The low frequency response is governed by R1 and C1 with cut-off frequency at 0.33Hz. The formula to calculate the gain shows as below. AV= (R1+R2)/R1 Fig.10 and Fig.11 are similar but in Fig.10 the input signal of amplifier is taken from the drain of the PIR. This has higher gain than that in Fig.10. Since OP1 is a PMOS input, VD has to be greater than 1.2V for adequate operation. VSS VSS VEE C1 22U VEE R1 22K C1 22U R2 1M R13 100k~180k VD R1 22K R2 1M PIR C2 D G S + C2 PIR 0.022 0.022 D G S OP1 OP1 OUT + R4 56K 56K VSS Typicalfirst firststage stageamplifier amplifier FigureFig.10 10 Typical OP1 C15 100U OP1 OUT VSS Fig.11 Figure 11 High gain gainfirst firststage stage COMPO COMPO is output from comparator, it can be output at pin 10 if needed. Signal from two-stage opamp outputs to a window comparator as pre-operation, COMPO outputs active positive pulses with various width once signal beyond window level. Whether an active PIR signal is detected, see figure 12 for detail. Trigger timing >Tmt <Tmt Figure 12 Trigger timing 12-07-0006 PT0219-1 8 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Referring to Figure 12 Note: 1. One measurable trigger width (Tmt) from comparator output is 24ms~ 32ms which varies with frequency of system oscillator (typical system frequency=16KHz ). 2. The output is activated if the trigger signal conforms to the following criteria: A trigger signal sustains duration: 0.34 seconds. 2 trigger signals within 2 seconds with one of the trigger signal sustain:0.16 seconds. More than 3 measurable triggers within 2 seconds. 3. The output duration is set by an external RC that is connected to the OSCD pin. Retrigger If another signal is attained in trigger hold time, the circuit will be retriggered, and the trigger hold time will be started from this time. Timing Diagram Figure 13 Timming diagram 12-07-0006 PT0219-1 9 07/06/12 PT8A2651 PIR Sensor Light Switch Controller ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information WE (SOIC-16) PKG. DIMENSIONS(MM) SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 A2 1.35 1.55 b 0.33 0.51 c 0.17 0.25 D 9.80 10.20 E 3.80 4.00 E1 5.80 6.20 e 1.27 BSC L 0.40 1.27 θ 0° 8° Note: 1) Controlling dimensions in millimeters. 2) Ref : JEDEC MS-012E/AC Ordering Information Ordering No. Package Code Package PT8A2651WE W Lead free SOIC-16 Note: E = Pb-free Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 12-07-0006 PT0219-1 10 07/06/12