PI6C22409

PI6C22409
2.5/3.3V 200MHz High-Speed, Low-Jitter, Low-Skew,
Zero-Delay Clock Buffer with 9 Outputs
Features
Description
•Phase-Lock Loop Clock Distribution
(Zero Input-to-Output Delay)
• Internal feedback connection
•Distributes one-to-two banks of four outputs
w/ one CLKOUT (9 - outputs total)
•High-Performance
• 30 MHz to 220 MHz operation frequency range
• <100ps output-to-output skew
• <100ps cycle-to-cycle jitter
• Low Power Configuration - 26mA (outputs unloaded)
•Spread-spectrum capable
•Power supply: +2.5V ±5% ; +3.3V ±10%
•Industrial temperature range parts available
• Packaging (Pb-free & Green):
— 16-pin TSSOP (L)
— 16-pin SOIC (W)
The PI6C22409 is a low-jitter, low-skew, high-speed Zero-Delay
Buffer with 9 outputs designed to address high-speed clock distribution applications.
The PI6C22409 features an internal patented Phase Lock Loop
(PLL) with high drive output capability and internal feedback. The PI6C22409 operates from a 2.5V ±5% or 3.3V ±10%
supply. All support documentation can be found on Pericom’s web
site at: www.pericom.com.
Pericom can customize these devices for specific requirements.
Block Diagram
Pin Configuration
PLL
MUX
CLKOUT
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
13
VDD
GND
5
12
GND
CLKB1
CLKB1
6
11
CLKB4
CLKB2
CLKB2
7
10
CLKB3
CLKB3
S2
8
9
CLKA1
REF
CLKA2
CLKA3
CLKA4
S1
Select Input
Decoding
S2
S1
CLKB4
Pin Description
Pin
Signal
Description
1
REF
Reference clock input with weak pull down.
2,3,6,7,
10,11,14,15
CLKA1, CLKA2, CLKB1, CLKB2, CLKB3,
CLKB4, CLKA3, CLKA4, CLKOUT
Clock output. Clock outputs with weak pull-down.
16
CLKOUT
Clock output. Internal feedback on this pin.
5,12
GND
Ground
4,13
VDD
Power
8,9
S2, S1
Select input with weak pull-ups.
13-0019
1
PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
Select Input Decoding
S2
0
0
1
1
S1
0
1
0
1
Clock A1 - A4
Tri-State
Driven
Driven
Driven
Clock B1 - B4
Tri-State
Tri-State
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Maximum Ratings(1)
Output Source
PLL
PLL
Reference
PLL
PLL shutdown
N
N
Y
N
Operation Ratings(2)
Supply voltage
VDD………………………….... ……..+3.0V to +3.6V
VDD…………………...…... ……+2.375V to +2.625V
Ambient Temperature (TA)….........…………..0°C to +70°C
Package Thermal Resistance(2)
θJA
Still-Air (SOIC-16)…...........…………………89°C/W
Still-Air (SOIC-16)...........................................90°C/W
θJB
Junction-to-Board (SOIC-16)............................... 26°C
Junction-to-Board (TSSOP-16)............................ 24°C
Supply Voltage
VDD............................................................-0.5V to +4.6V
REF…………………………………........-0.5V to +4.6V
Input Current ……………………………………....... .-50mA
Output Current....... …………………………………..±50mA
Lead Temperature (cap soldering, 10 sec.)..................+260°C
Storage Temperature (Ts)..............................-65°C to +150°C
Junction Temperature…...…….………………...........+150°C
Operating Temperature (cap industrial)…......-40°C to +85°C
Operating Temperature (cap commercial)…..... .0°C to +70°C
Notes:
1. Stresses greater then those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. θJA and θJB values are determined for a 4-layer board in still-air, unless otherwise stated.
13-0019
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PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
DC Electrical Characteristics
Parameter
VIL
Description
Input LOW Voltage
Test Conditions
Min.
Max.
VDD = 3.3V
0.8
VDD = 2.5V
0.7
VDD = 3.3V
2.0
VDD = 2.5V
1.7
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
50
IIH
Input HIGH Current
VIN = VDD
125
VOL
Output LOW Voltage
IOL = 12mA
VOH
Output HIGH Voltage
IDD
Supply Current
13-0019
VDD = 3.3V
0.4
VDD = 2.5V
0.5
VDD = 2.5V, IOH = –12mA
1.8
VDD = 3.3V, IOH = –12mA
2.4
Unloaded outputs 66 MHz
3
32
PS9002B
Units
V
µA
V
mA
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
AC Electrical Characteristics
Parameter
Description
Test Conditions
Output Frequency
FO
BW
Bandwidth for PLL
tDC
tR
Duty Cycle(4)
tsk(o)
Output to Output
skew(1)
Delay, REF Rising Edge to
CLKOUT Rising Edge(1)
t0
(2)(5)
tSK(D)
Device-to-device skew(1)
(3)
Cycle-to-Cycle Jitter
MHz
VDD = 3.3V
10
220
MHz
VDD = 2.5V
0.8
VDD = 3.3V
1.5
tLOCK
PLL Lock
50
55
1
For 2.5V: Measured between 0.6V and 1.8V; @10pF
1.8
For 3.3V: Measured between 0.8V and 2.0V; @10pF
1
For 2.5V: Measured between 0.6V and 1.8V; @10pF
1.8
All Outputs Equally Loaded
Measured at VDD/2, 66MHz
VDD = 3.3V
100
VDD = 2.5V
100
VDD = 3.3V
-100
VDD = 2.5V
-200
0
200
-300
0
+300
VDD = 3.3V
47
110
VDD = 2.5V
42
90
VDD = 3.3V
45
100
VDD = 2.5V
40
80
VDD = 3.3V
63
120
VDD = 2.5V
83
130
VDD = 3.3V
51
115
VDD = 2.5V
66
115
VDD = 3.3V
39
90
VDD = 2.5V
28
60
VDD = 3.3V
39
85
VDD = 2.5V
27
55
VDD = 3.3V
48
85
VDD = 2.5V
75
90
VDD = 3.3V
43
75
VDD = 2.5V
60
80
Measured at VDD/2 on CLKx pins of device
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
30pF load, >66MHz,
high drive
time (1)
45
MHz
For 3.3V: Measured between 0.8V and 2.0V; @10pF
15pF load, >66MHz,
standard drive
Period Jitter (Peak)
Units
200
30pF load, >66MHz,
high drive
tPJ
Max.
10
15pF load, >66MHz,
standard drive
tJIT
Typ.
VDD = 2.5V
Measured at VDD/2, 10 pF load
Rise Time(1)(4)
Fall Time(1)(4)
tF
Min.
Stable power supply, valid clocks presented on
CLKOUT pin
100
1
%
ns
ps
ps
ps
ms
Note:
1. See Switching Waveforms
2. All clock output should have the same loading to achieve zero delay between the input and outputs and zero output-to-output skew. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust to input-to-output delay. If input-to-output delay adjustments are needed, the CLKOUT load may be
changed to vary the delay between the REF input to the clock outputs. Output-to-output skew includes CLKA1-4 and CLKB1-4.
3. Specifications are guaranteed by design and not production tested.
4. Measured at 100MHz.
5. Measured with 16-Pin SOIC package
13-0019
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PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
Switching Waveforms
thigh
VDD/2
OUTPUT
OUTPUT
tlow
VDD/2
tDC =
VDD/2
thigh+ tlow
0V
tF
tR
thigh
VDD/2
VDD/2
OUTPUT
tSK(O)
VDD/2
VDD/2
tSK(D)
VDD/2
INPUT
VDD/2
OUTPUT
t0
0.1µf
0.1µF
VDD
VDD
CLKA,B
CLKA,B
0.1µf
GND
13-0019
CLOAD
VDD
1K
0.1µF
GND
GND
5
10pF
1K
VDD
GND
PS9002B
12/12/12
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
Packaging Mechanical: 16-Pin TSSOP (L)
DATE: 05/03/12
Notes:
1. Refer JEDEC MO-153F/AB
2. Controlling dimensions in millimeters
3. Package outline exclusive of mold flash and metal burr
DESCRIPTION: 16-Pin, 173mil Wide TSSOP
PACKAGE CODE: L
DOCUMENT CONTROL #: PD-1310
REVISION: F
12-0372
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
13-0019
6
PS9002B
12/12/12
DATE: 06/15
PI6C22409
2.5/3.3V 200MHz Zero-Delay Clock Buffer with Outputs
Packaging Mechanical: 16-Pin SOIC (W)
DATE: 06/15/12
DESCRIPTION: 16-Pin, 150mil Wide SOIC
PACKAGE CODE: W
DOCUMENT CONTROL #: PD-1004
REVISION: F
2012-0398
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1,2,3)
Ordering Code
Package Code
Package Type
PI6C22409LE
L
Pb-free & Green, 16-pin TSSOP
PI6C22409LIE
L
Pb-free & Green, 16-pin TSSOP, Industrial temp range
PI6C22409WE
W
Pb-free & Green, 16-pin SOIC
PI6C22409WIE
W
Pb-free & Green, 16-pin SOIC, Industrial temp range
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
13-0019
7
PS9002B
12/12/12