PI6C22405LIE

PI6C22405
2.5/3.3V 220MHz Zero-Delay
Clock Buffer with 5 Outputs
Features
Description
• Phase-Lock Loop Clock Distribution
(Zero Input-to-Output Delay)
• Internal feedback connection
• Distributes one to one bank of five outputs
• High-Performance
• 30 MHz to 220 MHz operation frequency range
• <100ps output-to-output skew
• <100ps cycle-to-cycle jitter
• Low Power Consumption - 25mA (outputs unloaded)
• Spread-spectrum capable
• Power supply
• +2.5V ±5%
• +3.3V ±10%
• Temperature range
• -40°C to +85°C Industrial temp range
• Packaging (Pb-free & Green):
—8-pin TSSOP (L8)
—8-pin SOIC (W8)
The PI6C22405 is a low-jitter, low-skew, high-speed Zero-Delay
Buffer with five outputs designed to address high-speed clock
distribution applications.
The PI6C22405 features an internal patented Phase Lock Loop
(PLL) with high drive output capability and internal feedback.
The PI6C22405 operates from a 2.5V±5% or 3.3V±10%
supply, guaranteed over the full industrial temperature range
of -40°C to +85°C. All support documentation can be found on
Pericom’s web site at: www.pericom.com.
Pericom can customize these devices for specific requirements.
Block Diagram
Pin Configuration
CLKOUT
PLL
REF
CLK 1
CLK 2
CLK 3
REF
1
8
CLKOUT
CLK 2
2
7
CLK 4
CLK 1
3
6
V DD
GND
4
5
CLK 3
CLK 4
Pin Description
Pin
Signal
Description
1
REF
Reference clock input with weak pull down.
2, 3,
5, 7
CLK2, CLK1,
CLK3, CLK4,
Clock output. Clock outputs contain a weak pull-down.
8
CLKOUT
Clock output. Internal feedback on this pin.
4
GND
Ground
6
VDD
Power
10-0136
1
PS9001A
03/17/10
PI6C22405
2.5/3.3V 220MHz Zero-Delay Clock Buffer with 5 Outputs
Maximum Ratings (1)
Operation Ratings(2)
Supply Voltage
VDD........................................................ -0.5V to +4.6V
REF…………………………………..... -0.5V to +4.6V
Input Current …………………………………….... .-50mA
Output Current.... …………………………………..±50mA
Lead Temperature (soldering, 10 sec.)......................+260°C
Storage Temperature (Ts)........................... -65°C to +150°C
Junction Temperature…...…….………………........+150°C
Operating Temperature (industrial)…......... .-40°C to +85°C
Supply Voltage
VDD………………………….. ……..+3.0V to +3.6V
VDD…………………...…. ……+2.375V to +2.625V
Ambient Temperature (TA)….......…………..0°C to +70°C
Package Thermal Resistance (2)
θJA
Still-Air….………………………………..…157°C/W
θJB
Junction-to-Board................................................ 42°C
Notes:
1.
Stresses greater then those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. θJA and θJB values are determined for a 4-layer board in still-air, unless otherwise stated.
DC Electrical Characteristics
Parameter
VIL
Description
Input LOW Voltage
Test Conditions
Min.
Max.
VDD = 3.3V
0.8
VDD = 2.5V
0.7
VDD = 3.3V
2.0
VDD = 2.5V
1.7
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
10
IIH
Input HIGH Current
VIN = VDD
100
VOL
Output LOW Voltage
IOL = 12mA
VOH
Output HIGH Voltage
IDD
Supply Current
10-0136
VDD = 3.3V
0.4
VDD = 2.5V
0.5
VDD = 2.5V, IOH = –12mA
1.8
VDD = 3.3V, IOH = –12mA
2.4
Unloaded outputs 66 MHz
2
25
PS9001A
Units
V
µA
V
mA
03/17/10
PI6C22405
2.5/3.3V 220MHz Zero-Delay Clock Buffer with 5 Outputs
AC Electrical Characteristics
Parameter
Description
FO
Output Frequency
BW
Bandwidth for PLL
tDC
Duty Cycle(1)(4)
tR
Rise Time(1)(4)
tF
Fall Time(1)(4)
Test Conditions
Min. Typ. Max.
VDD = 2.5V, CL = 15pF
10
200
MHz
VDD = 3.3V, CL = 15pF
10
220
MHz
VDD = 2.5V
0.8
VDD = 3.3V
1.5
Measured at VDD/2, 10pF load
1.8
For 3.3V: Measured between 0.8V and 2.0V @ 10pF
1
For 2.5V: Measured between 0.6V and 1.8V @ 10pF
1.8
VDD = 3.3V
90
VDD = 2.5V
90
t0
Delay, REF Rising Edge
to CLKOUT Rising
Edge(2)
Measured at VDD/2 @
66MHz
tSK(D)
Device-to-device Skew(3)
Measured at VDD/2 on CLKx pins of device
15pF load, >66MHz,
standard drive
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
30pF load, >66MHz,
high drive
15pF load, >66MHz,
standard drive
Period Jitter (Peak)
15pF load, >66MHz,
high drive
30pF load, >66MHz,
standard drive
30pF load, >66MHz,
high drive
tLOCK
PLL Lock Time (1)
55
For 2.5V: Measured between 0.6V and 1.8V @ 10pF
All outputs equally
loaded
tPJ
50
1
Output to Output Skew(2)
Cycle-to-Cycle Jitter
45
MHz
For 3.3V: Measured between 0.8V and 2.0V @ 10pF
tsk(o)
tJIT
Units
VDD = 3.3V
-100
100
VDD = 2.5V
-200
200
-300
+300
VDD = 3.3V
47
110
VDD = 2.5V
42
90
VDD = 3.3V
45
100
VDD = 2.5V
40
80
VDD = 3.3V
63
120
VDD = 2.5V
83
130
VDD = 3.3V
51
115
VDD = 2.5V
66
115
VDD = 3.3V
39
90
VDD = 2.5V
28
60
VDD = 3.3V
39
85
VDD = 2.5V
27
55
VDD = 3.3V
48
85
VDD = 2.5V
75
90
VDD = 3.3V
43
75
VDD = 2.5V
60
80
Stable power supply, valid clocks presented on REF pin
1.0
%
ns
ps
ps
ps
ms
Note:
1. See Switching Waveforms
2. All clock output should have the same loading to achieve zero delay between the input and outputs and zero output-to-output skew. Since the
CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-to-output delay. If input-to-output delay adjustments
are needed, the CLKOUT load may be changed to vary the delay between the REF input to the clock outputs. Output-to-output skew includes
CLK 1-4.
3. Specifications are guaranteed by design and not production tested.
4. Measured at 100MHz.
10-0136
3
PS9001A
03/17/10
PI6C22405
2.5/3.3V 220MHz Zero-Delay Clock Buffer with 5 Outputs
Switching Waveforms
thigh
Duty Cycle Timing
VDD/2
tlow
VDD/2
tDC =
VDD/2
All Outputs Rise/Fall Time
Output-Output Skew
OUTPUT
2.0V
0.8V
tR
OUTPUT
VDD/2
thigh
thigh tlow
3.3V
2.0V
0.8V
tF
0V
VDD/2
OUTPUT
tSK(O)
Device-Device Skew
OUTPUT Device 1
VDD/2
VDD/2
OUTPUT Device 2
tSK(D)
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
OUTPUT
t0
Test Circuit 1
0.1µF
0.1µF
VDD
OUTPUTS
0.1µF
CLK out
CLOAD
VDD
GND
Test Circuit 2
1kΩ
CLK out
OUTPUTS
0.1µF
10pF
1kΩ
VDD
GND
GND
Test Circuit for all parameters except tSLEW
10-0136
VDD
GND
Test Circuit for tSLEW ,Output slew
4
PS9001A
03/17/10
PI6C22405
2.5/3.3V 220MHz Zero-Delay Clock Buffer with 5 Outputs
Packaging Mechanical: 8-Pin SOIC (W)
DOCUMENT CONTROL NO.
PD - 1001
8
REVISION: F
.149
.157
DATE: 03/09/05
3.78
3.99
.0099
.0196
0.25
x 45˚
0.50
1
.189
.196
4.80
5.00
.0075
.0098
0-8˚
0.19
0.25
0.40 .016
1.27 .050
1
.016
.026
0.406
0.660
.2284
.2440
5.80
6.20
1.35
1.75
.053
.068
SEATING PLANE
REF
.050
BSC
1.27
.0040 0.10
.0098 0.25
.013 0.330
.020 0.508
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Notes:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012D/AA
DESCRIPTION: 8-Pin, 150-Mil Wide, SOIC
PACKAGE CODE: W
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
10-0136
5
PS9001A
03/17/10
PI6C22405
2.5/3.3V 220MHz Zero-Delay Clock Buffer with 5 Outputs
Packaging Mechanical: 8-Pin TSSOP (L)
DOCUMENT CONTROL NO.
PD - 1308
REVISION: E
DATE: 11/15/05
1
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
Note:
1. Package Outline Exclusive of Mold Flash and Metal Burr
2. Controlling dimentions in millimeters
3. Ref: JEDEC MO-153F/AA
DESCRIPTION: 8-Pin, 173-Mil Wide, TSSOP
PACKAGE CODE: L
Note:
• For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
Ordering Information(1,2,3)
Ordering Code
Package Code
Package Description
PI6C22405WE
W
Pb-free & Green, 8-pin SOIC
PI6C22405WIE
W
Pb-free & Green, 8-pin SOIC, Industrial temp range
PI6C22405LE
L
Pb-free & Green, 8-pin TSSOP
PI6C22405LIE
L
Pb-free & Green, 8-pin TSSOP, Industrial temp range
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free & Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
10-0136
6
PS9001A
03/17/10