STMICROELECTRONICS TDA7449L_04

TDA7449L
LOW COST
DIGITALLY CONTROLLED AUDIO PROCESSOR
1
■
FEATURES
Figure 1. Package
INPUT MULTIPLEXER
– 2 STEREO INPUTS
– SELECTABLE INPUT GAIN FOR OPTIMAL
ADAPTATION TO DIFFERENT SOURCES
■
ONE STEREO OUTPUT
■
VOLUME CONTROL IN 1.0dB STEPS
■
TWO SPEAKER ATTENUATORS:
DIP20
Table 1. Order Codes
Part Number
Package
TDA7449L
DIP20
– TWO INDEPENDENT SPEAKER CONTROL
IN 1.0dB STEPS FOR BALANCE FACILITY
Selectable input gain is provided. Control of all the
functions is accomplished by serial bus.
– INDEPENDENT MUTE FUNCTION
■
2
ALL FUNCTION ARE PROGRAMMABLE VIA
SERIAL BUS
The AC signal setting is obtained by resistor networks and switches combined with operational
amplifiers.
DESCRIPTION
Thanks to the used BIPOLAR/CMOS Technology,
Low Distortion, Low Noise and DC stepping are
obtained.
The TDA7449L is a volume control and balance
(Left/Right) processor for quality audio applications in TV systems.
Figure 2. Block Diagram
MUXOUTL
L-IN1
10
8
100K
L-IN2
9
100K
R-IN1
G
VOLUME
I2CBUS DECODER + LATCHES
6
100K
20
18
100K
R-IN2
5
19
0/30dB
2dB STEP
7
SPKR ATT
LEFT
G
VOLUME
SPKR ATT
RIGHT
4
LOUT
SCL
SDA
DIG_GND
ROUT
VREF
2
SUPPLY
INPUT MULTIPLEXER
+ GAIN
11
MUXOUTR
June 2004
3
VS
AGND
1
CREF
D98AU868
REV. 3
1/14
TDA7449L
Table 2. Absolute Maximum Ratings
Symbol
Parameter
VS
Operating Supply Voltage
Tamb
Operating Ambient Temperature
Tstg
Storage Temperature Range
Value
Unit
10.5
V
0 to 70
°C
-55 to 150
°C
Figure 3. Pin Connection
CREF
1
20
SDA
VS
2
19
SCL
PGND
3
18
DIG_GND
ROUT
4
17
N.C.
LOUT
5
16
N.C.
R_IN2
6
15
N.C.
R_IN1
7
14
N.C.
L_IN1
8
13
N.C.
L_IN2
9
12
N.C.
10
11
MUXOUT(R)
MUXOUT(L)
D98AU869
Table 3. Thermal Data
Symbol
Rth j-pin
Parameter
Thermal Resistance Junction- pins
Value
Unit
150
°C/W
Table 4. Quick Reference Data
Symbol
Parameter
Min.
Typ.
Max.
Unit
9
10.2
V
VS
Supply Voltage
6
VCL
Max Input Signal Handling
2
THD
Total Harmonic Distortion V = 0.1Vrms f = 1KHz
0.01
S/N
Signal to Noise Ratio Vout = 1Vrms (mode = OFF)
106
dB
SC
Channel Separation f = 1KHz
90
dB
Input Gain (2dB step)
0.1
%
0
30
dB
Volume Control (1dB step)
-47
0
dB
Balance Control 1dB step
-79
0
dB
Mute Attenuation
2/14
VRMS
100
dB
TDA7449L
Table 5. Electrical Characteristcs (refer to the test circuit Tamb = 25°C, VS = 9V, RL= 10KΩ, RG = 600Ω,
all controls flat (G = 0dB), unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
SUPPLY
VS
Supply Voltage
IS
Supply Current
SVR
6
Ripple Rejection
60
9
10.2
V
7
mA
90
dB
100
KΩ
INPUT STAGE
RIN
Input Resistance
VCL
Clipping Level
THD = 0.3%
2
2.5
Vrms
SIN
Input Separation
The selected input is grounded
through a 2.2µ capacitor
80
100
dB
-1
0
Ginmin
Minimum Input Gain
Ginman
Maximum Input Gain
30
dB
Step Resolution
2
dB
Gstep
1
dB
VOLUME CONTROL
Control Range
45
47
49
dB
AVMAX
Max. Attenuation
45
47
49
dB
ASTEP
Step Resolution
0.5
1
1.5
dB
AV = 0 to -24dB
-1.0
0
1.0
dB
AV = -24 to -47dB
-1.5
0
1.5
dB
AV = 0 to -24dB
0
1
dB
AV = -24 to -47dB
0
2
dB
adjacent attenuation steps
0
3
mV
CRANGE
EA
ET
VDC
Attenuation Set Error
Tracking Error
DC Step
from 0dB to AV max
Amute
Mute Attenuation
80
0.5
mV
100
dB
76
dB
SPEAKER ATTENUATORS
CRANGE
Control Range
SSTEP
Step Resolution
EA
Attenuation Set Error
AV = 0 to -20dB
AV = -20 to -56dB
VDC
DC Step
Amute
Mute Attenuation
0.5
1
1.5
dB
-1.5
0
1.5
dB
-2
0
2
dB
0
3
mV
adjacent attenuation steps
80
100
dB
3/14
TDA7449L
Table 5. Electrical Characteristcs (continued)
AUDIO OUTPUTS
Clipping Level
VCLIP
d = 0.3%
2.1
RL
Output Load Resistance
2
RO
Output Impedance
10
VDC
DC Voltage Level
2.6
VRMS
KΩ
40
70
W
3.8
V
GENERAL
ENO
Et
Output Noise
All gains = 0dB;
BW = 20Hz to 20KHz flat
5
15
µV
Total Tracking Error
AV = 0 to -24dB
0
1
dB
AV = -24 to -47dB
0
2
dB
S/N
Signal to Noise Ratio
SC
Channel Separation Left/Right
d
All gains 0dB; VO = 1VRMS ;
80
AV = 0; VI = 1VRMS ;
Distortion
106
dB
100
dB
0.01
0.08
%
1
V
BUS INPUT
VIL
Input Low Voltage
VIH
Input High Voltage
IIN
Input Current
VIN = 0.4V
VO
Output Voltage SDA
Acknowledge
IO = 1.6mA
3
V
5
µA
0.8
V
-5
0.4
Figure 4. Test Circuit
R2 2K
C9
5.6nF
150nF
J5
C7
MUXOUTL
IN1L
TREBLE(L)
10
J3
RCA
1
2
J4
3
4
5
330nF
16
C8
BIN(L)
BOUT(L)
15
14
GND
IN2L
GND
L-IN1
OUT_L
100K
C3 0.47µF
L-IN2
RB
8
5
9
C4 0.47µF
CON3
OUT_ R
LOUT
100K
G
VOLUME
TREBLE
SPKR ATT
LEFT
BASS
J2
RCA
0/30dB
2dB STEP
1
2
3
4
IN2R
GND
IN1R
GND
R-IN2
18
DIG_GND
19
SCL
20
SDA
G
VOLUME
TREBLE
BASS
SPKR ATT
RIGHT
C2 0.47µF
4
CON4
3
J6
4
ROUT
SUPPLY
GND
RB
11
MOUTL
MUXOUTR
TREBLE(R)
MOUTR
13
BOUT(R)
C5
150nF
R1
1
+9V
CREF
C6
330nF
2K
C12
22µF
+V8
1
GND
C10
5.6nF
C13
100nF
R3 30
AGND
VS
12
17
2
C11
10µF
D98AU849A
4/14
1
2
100K
BIN(R)
3
J10
4
4
7
INPUT MULTIPLEXER
+ GAIN
2
3
CON4
100K
3
J5
2
VREF
CON
1
JP1
JUMPER
6
C1 0.47µF
R-IN1
I2CBUS DECODER + LATCHES
1
CON4
+9 V
IN1R
J1
J9
OUT_L
GND
IN1L
J8
OUT_R
GND
2
CON2
J7
TDA7449L
3
APLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first
one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution.
The very high resolution allows the implementation of systems free from any noisy acoustical effect. The
TDA7449L audioprocessor provides 2 bands tones control.
3.1 CREF
The suggested 10µF reference capacitor (CREF) value can be reduced to 4.7µF if the application requires
faster power ON.
Figure 5. THD vs. frequency
Figure 7. Channel separation vs. frequency
Figure 6. THD vs. RLOAD
5/14
TDA7449L
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7449L and vice versa takes place through the 2 wires
I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
4.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The
stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
4.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge
bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
10). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this
clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the reception of
each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case
the master transmitter can generate the STOP information in order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission:
simply it waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 8. Data Validity on the I2CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 9. Timing Diagram of I2CBUS
SCL
I2CBUS
SDA
START
6/14
D99AU1032
STOP
TDA7449L
Figure 10. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA
MSB
START
5
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
SOFTWARE SPECIFICATION
5.1 Interface Protocol
The interface protocol comprises:
■
A start condition (S)
■
A chip address byte, containing the TDA7449L address
■
A subaddress bytes
■
A sequence of data (N byte + acknowledge)
■
A stop condition (P)
Figure 11.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
B
DATA
MSB
ACK
LSB
DATA
ACK
P
D96AU420
ACK = Acknowledge
S = Start
P = Stop
A = Address
B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus
The TDA7449L receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
Figure 12.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA
LSB
X
X
0 D3 D2 D1 D0 ACK
MSB
LSB
DATA
ACK
P
D96AU421
7/14
TDA7449L
6.2 Incremental Bus
The TDA7449L receive a start conditions, the correct chip address, a subaddress with the B = 1 incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from
"XXX1000" to "XXX1111" of DATA are ignored.
The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the
loop etc, and at the end it receivers the stop condition.
Figure 13.
CHIP ADDRESS
SUBADDRESS
MSB
S
1
LSB
0
0
0
1
0
0
0
MSB
ACK
X
DATA 1 to DATA n
LSB
X
X
MSB
1 D3 D2 D1 D0 ACK
LSB
DATA
ACK
P
D96AU422
Table 6. POWER ON RESET CONDITION
7
INPUT SELECTION
IN2
INPUT GAIN
28dB
VOLUME
MUTE
SPEAKER
MUTE
DATA BYTES
Address = 88 HEX (ADDR:OPEN).
Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB
LSB
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
B
0
0
0
0
INPUT SELECT
X
X
X
B
0
0
0
1
INPUT GAIN
X
X
X
B
0
0
1
0
VOLUME
X
X
X
B
0
0
1
1
NOT USED
X
X
X
B
0
1
0
0
BASS USED
X
X
X
B
0
1
0
1
TREBLE USED
X
X
X
B
0
1
1
0
SPEAKER ATTENUATE "R"
X
X
X
B
0
1
1
1
SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE
B = 0: NO INCREMENTAL BUS
X = DON’T CARE
In Incremental Bus Mode, the three "not used" functions must be addressed in any case. For example to
refresh "Volume = 0dB" and Speaker_R = -40dB", the following bytes must be sent:
8/14
TDA7449L
Table 8.
SUBADDRESS
XXX10010
VOLUME DATA
X0000000
NOT USED 1 DATA
XXXX1111
NOT USED 2 DATA
XXXX1111
NOT USED 3 DATA
XXXX1111
SPEAKER_R DATA
X0000010
Table 9. INPUT SELECTION
MSB
LSB
INPUT MULTIPLEXER
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
0
0
NOT ALLOWED
X
X
X
X
X
X
0
1
NOT ALLOWED
X
X
X
X
X
X
1
0
IN2
X
X
X
X
X
X
1
1
IN1
Table 10. INPUT GAIN SELECTION
MSB
D7
D6
D5
D4
LSB
INPUT GAIN
D3
D2
D1
D0
2dB STEPS
0
0
0
0
0dB
0
0
0
1
2dB
0
0
1
0
4dB
0
0
1
1
6dB
0
1
0
0
8dB
0
1
0
1
10dB
0
1
1
0
12dB
0
1
1
1
14dB
1
0
0
0
16dB
1
0
0
1
18dB
1
0
1
0
20dB
1
0
1
1
22dB
1
1
0
0
24dB
1
1
0
1
26dB
1
1
1
0
28dB
1
1
1
1
30dB
GAIN = 0 to 30dB
9/14
TDA7449L
Table 11. VOLUME SELECTION
MSB
D7
D6
D5
D4
D3
LSB
VOLUME
D2
D1
D0
1dB STEPS
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
X
1
1
1
-40dB
X
X
X
MUTE
VOLUME = 0 to 47dB/MUTE
Table 12. SPEAKER ATTENUATE SELECTION
MSB
D7
D6
D5
D4
SPEAKER ATTENUATION
D2
D1
D0
1dB
0
0
0
0dB
0
0
1
-1dB
0
1
0
-2dB
0
1
1
-3dB
1
0
0
-4dB
1
0
1
-5dB
1
1
0
-6dB
1
1
1
-7dB
0
0
0
0
0dB
0
0
0
1
-8dB
0
0
1
0
-16dB
0
0
1
1
-24dB
0
1
0
0
-32dB
0
1
0
1
-40dB
0
1
1
0
-48dB
0
1
1
1
-56dB
1
0
0
0
-64dB
1
0
0
1
-72dB
1
1
1
1
SPEAKER ATTENUATION = 0 to -79dB/MUTE
10/14
D3
LSB
X
X
X
MUTE
TDA7449L
Figure 14. PIN :1
Figure 17. PINS: 10, 11
VS
VS
VS
VS
20µA
20K
CREF
MUXOUT
20K
GND
D96AU430
D96AU491
Figure 18. PIN: 19,
Figure 15. PINS: 4, 5
VS
20µA
24
ROUT
LOUT
SCL
20µA
D96AU424
D96AU434
Figure 16. PINS: 6, 7, 8, 9
Figure 19. PIN: 20
VS
20µA
20µA
SDA
IN
100K
VREF
D96AU425
D96AU423
11/14
TDA7449L
Figure 20. DIP20 Mechanical Data & Package Dimensions
mm
DIM.
MIN.
a1
0.254
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
OUTLINE AND
MECHANICAL DATA
3.3
0.130
DIP20
Z
12/14
1.34
0.053
TDA7449L
Table 13. Revision History
Date
Revision
Description of Changes
April 1999
2
Second Issue
June 2004
3
Modified the style-sheet in compliance with the last revision of the
“Corporate Technical Pubblications Design Guide”.
13/14
TDA7449L
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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