ROHM BU1425AK

Multimedia ICs
NTSC / PAL digital RGB encoder
BU1425AK / BU1425AKV
The BU1425AK / BU1425AKV are ICs which convert digital RGB / YUV input to composite (NTSC / PAL / PAL60),
luminance (Y), and chrominance (C) signals, and outputs the results.
Applications
•Video
interfaces for VIDEO-CDs and CD-G decoders
•1)Features
Input clocks supported
27.0 / 13.5MHz
28.636 / 14.318MHz
28.375 / 14.1875MHz
35.4695 / 17.73475MHz
2) 24-bit RGB and 16-bit YUV input signals are supported.
3) Both master and slave systems are supported.
4) 9-bit high-speed DAC is used for DAC output of
composite VIDEO, Y, and C signals.
5) Internal 8-color OSD output function is provided.
6) FSC-TRAP on the Y channel can be turned on and
off.
7) C channel is equipped with an internal chrominance band-pass filter in addition to the U.V. lowpass filter.
8) 5V single power supply, low power consumption
(0.4W typ.)
9) Y and C output can be turned off (the power consumption with Y and C off is 0.25W typ.).
10) In the Master mode, applying 3.3V to the I / O VDD
and 5.0V to other VDDs produces HSY and VSY
output with an amplitude of 3.3V. This enables
direct connection to LSIs that use a power supply
voltage of 3.3V. (The clock output for the OSD has
a fixed amplitude of 5.0V.)
11) In the Slave mode, applying voltage to the I / O VDD
only, and applying 0V to other VDDs, enables a current consumption of 0 even when RGB DATA,
HSY, VSY, and OSD DATA are in the active state.
1
Multimedia ICs
BU1425AK / BU1425AKV
OSDSW
ROSD
GOSD
BOSD
•Block diagram
RGB 24BITS
OSD PALETTE
DAC
Y-FILTER
RD
GD / Y
LATCH
RGB
to
YUV
Y-LEVEL ADJ
UV
FILTER
BD / UV
CHROMA GEN
MIX SIG
and
sync
burst
C-FILTER
V
VOUT
Y
YOUT
C
COUT
VCLK
RSTB
PIXCLK
VIDEO TIMING CONTROL
SYNC BLANK
HSY
SUB CARRIER BURST GENERATOR
BURST
2
CLKSW
NTB
PAL60B
CDGSWB
YFILONB [1.0]
IM [0.1]
INT
ADDH
TEST12
MODE CONTROL FIELD / FLAME CONTROL
VSY
Multimedia ICs
BU1425AK / BU1425AKV
•Pin descriptions
Pin No. Pin name
Function
Function
Pin No. Pin name
1
BOSD
OSD BLUE DATA INPUT
33
SLABEB
2
GD0 / Y0
GREEN DATA Bit0 (LSB)
34
ADDH
+ 0.5 / – 0.5LINE at NON-INTER
3
GD1 / Y1
GREEN DATA Bit1
35
VREF-C
DAC BIAS
4
GD2 / Y2
GREEN DATA Bit2
36
CGND
CHROMA OUTPUT GROUND
5
GD3 / Y3
GREEN DATA Bit3
37
COUT
CHROMA OUTPUT
6
GD4 / Y4
GREEN DATA Bit4
38
VGND
Composite Output Ground
7
GD5 / Y5
GREEN DATA Bit5
39
VOUT
COMPOSITE OUTPUT
8
GD6 / Y6
GREEN DATA Bit6
40
AVSS
Analog Ground (DAC VREF)
9
GND
DIGITAL GROUND
41
P-VDD
POWER (DAC) VDD
10
GD7 / Y7
GREEN DATA Bit7 (MSB)
42
IR
11
BD0 / UV0
BLUE DATA Bit0 (LSB)
43
AVDD
12
BD1 / UV1
BLUE DATA Bit1
44
YGND
Luminance Output Ground
13
BD2 / UV2
BLUE DATA Bit2
45
YOUT
Luminance Output
14
BD3 / UV3
BLUE DATA Bit3
46
VDD
15
OSDSW
OSD ENABLE / DISABLE
47
YFILON2B
Y-FILSEL THROU / FILON2
16
CDGSWB
SELECT Video-CD / CD-G
48
YCOFF
DAC (YOUTCOUT) OFF
17
BD4 / UV4
BLUE DATA Bit4
49
YFILON1B
Y-FILSEL THROU / FILON1
18
BD5 / UV5
BLUE DATA Bit5
50
PAL60B
NORMAL / PAL60 at PALMODE
19
BD6 / UV6
BLUE DATA Bit6
51
VCLK
Video Clock Input
20
BD7 / UV7
BLUE DATA Bit7 (MSB)
52
RSTB
NORMAL / RESET
21
GND
DIGITAL GROUND
53
CLKSW
22
NTB
SELECT NTSC / PAL MODE
54
RD0
RED DATA Bit0 (LSB)
23
IM0
SELECT YUV / RGB
55
RD1
RED DATA Bit1
24
IM1
SELECT DAC / NORMAL
56
RD2
RED DATA Bit2
25
TEST1
Normally pull down to GND
57
ROSD
26
TEST2
SELECT U / V TIMING
58
RD3
RED DATA Bit3
SELECT MASTER / SLAVE
REFERENCE RESISTOR
ANALOG (VREF) VDD
DIGITAL VDD
SEL ×1CLK / ×2CLK
OSD RED DATA INPUT
27
VSY
V-SYNC INPUT or OUTPUT
59
RD4
RED DATA Bit4
28
HSY
H-SYNC INPUT or OUTPUT
60
RD5
RED DATA Bit5
29
PIXCLK
1 / 2freq. of BCLK
61
IOVDD
∗
VDD for I / O
30
VDD
DIGITAL VDD
62
RD6
RED DATA Bit6
31
IOVDD
VDD for I / O
63
RD7
RED DATA Bit7
32
INT
Interlace / Non-Interlace
64
GOSD
OSDGREEN DATA INPUT
∗ With pull-down resistor (approx. 30kΩ )
3
Multimedia ICs
BU1425AK / BU1425AKV
•Absolute maximum ratings (Ta = 25°C)
Parameter
Applied voltage
Symbol
Limits
Unit
VDD, AVDD
– 0.5 ~ + 7.0
V
Input voltage
– 0.3 ~ IOVDD + 0.3
V
Tstg
– 55 ~ + 150
°C
Pd
1350∗1
mW
VIN
Storage temperature
Power dissipation
∗1 Reduced by 11mW for each increase in Ta of 1°C over 25°C.
∗1 When mounted on 120mm × 140mm × 1.0mm glass epoxy board.
∗ Operation is not guaranteed at this value.
䊊 Not designed for radiation resistance.
•Recommended operating conditions
Symbol
Limits
Unit
Power supply voltage
Parameter
VDD = AVDD∗
4.50 ~ 5.50
V
Power supply voltage
IOVDD
3.30 ~ 5.50
V
Input high level voltage
VIH
2.1 ~ VDD
V
Input low level voltage
VIL
0 ~ + 0.8
V
Analog input voltage
VAIN
0 ~ AVDD
V
Operating temperature
Topr
°C
– 25 ~ + 60
∗ Should be used at VDD = AVDD.
•Electrical characteristics (unless otherwise noted, Ta = 25°C, V
DD
Parameter
= AVDD = 5.0V, GND = AVSS = VGND = CGND = YGND)
Symbol
Min.
Typ.
Max.
Unit
Burst frequency 1
fBST1
—
3.57954
—
MHz
Burst frequency 2
fBST2
—
4.43361
—
MHz
Burst cycle
Conditions
〈Digital block〉
CBST
—
9
—
CYC
Operating circuit current 1
Idd1
—
80
—
mA
27MHz color bar
Operating circuit current 2
Idd2
—
40
—
mA
27MHz color bar PD mode
Output high level voltage
VOH
4.0
4.5
—
V
IOH = – 2.0mA
Output low level voltage
VOL
—
0.5
1.0
V
IOH = 2.0mA
Input high level voltage
VIH
2.1
—
—
V
Input low level voltage
VIL
—
—
0.8
V
Input high level current
IIH
– 10
0.0
10.0
µA
Input low level current
IIL
– 10
0.0
10.0
µA
〈DAC block〉
—
BITS
± 3.0
LSB
25.14
—
mA
7.24
—
mA
0.0
10.0
µA
—
25.14
—
mA
IYB
—
7.24
—
mA
IYZ
– 10
0.0
10.0
µA
—
—
1.0
µA
RES
—
EL
—
Y white level current
IYW
—
Y black level current
IYB
—
Y zero level current
IYZ
– 10
V white level current
IYW
V black level current
V zero level current
Sleep mode current
Iddpd
DAC resolution
Linearity error
4
9
± 0.5
IR = 1.2kΩ
VIN Max. = IOVDD + 0.3V
VIN Min. = – 0.3V
25
26
27
28
29
30
31
32
SLABEB
ADDH
VREF
CGND
COUT
VGND
VOUT
AVSS
AVDD
IR
AVDD
YGND
YOUT
VDD
YFILON2B
YCOFF
35
36
37
38
39
40
41
42
43
44
45
46
47
48
BU1425AK / AKV
9
8
7
6
5
4
3
2
1
GND
GD6
GD5
GD4
GD3
GD2
GD1
GD0
BOSD
BD1
11
12
BD2
10
13
BD3
GD7
14
OSDSW
BD0
16
15
CDGSWB
GOSD
RD7
RD6
I / O VDD
RD5
RD4
RD3
ROSD
RD2
RD1
RD0
CLKSW
RSTB
VCLK
PAL GOB
YFILON1B
64
63
62
60
59
58
57
55
56
54
MAIN VDD 5.0 V
24
Pixel Clock in
Y-filter select
Reset [Low active] in
3
SLEEP MODE CTL
L: SLEEP
H: NORMAL
23
4
I / O VDD 5.0V or 3.3V
22
6 5
Luminance
21
34
7
75
20
Composite
1.2k
19
BD4
BD5
BD6
BD7
GND
NTB
IM0
IM1
TEST1
TEST2
VSY
HSY
PIXCLK
VDD
I / O VDD
INT
75
18
33
DIGITAL GND
INTERLACE / NON-INTER
PAL / NTSC
3
Chrominance
17
0.01µF
ANALOG GND
4
5
6
7
75
POWER GND
OSD CLOCK
Vsync out
Hsync out
B Data 0...7
G Data 0...7
R Data 0...7
OSD enable
OSD in [Blue]
OSD in [Green]
[Red]
OSD in
Video-CD / CD-G
Multimedia ICs
BU1425AK / BU1425AKV
example
•(1)Application
Example in Master mode: Doubled clock is input and 24-bit RGB input is used
2 1 0
2 1 0
7
6
61
5
4
3
2
1
0
53
52
51
50
49
ANALOG VDD
POWER VDD
DIGITAL VDD
Fig.1
5
27
28
29
30
31
32
0.01µF
Fig.2
SLABEB
ADDH
VREF
CGND
COUT
VGND
VOUT
AVSS
AVDD
IR
35
36
37
38
39
40
41
42
YGND
YOUT
VDD
YFILON2B
YCOFF
44
45
46
47
48
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CDGSWB
OSDSW
BD3
BD2
BD1
BD0
GD7
GND
GD6
GD5
GD4
GD3
GD2
GD1
GD0
BOSD
64
63
62
60
59
58
57
55
56
54
MAIN VDD 5.0V
26
BU1425AK / AKV
GOSD
RD7
RD6
I / O VDD
RD5
RD4
RD3
ROSD
RD2
RD1
RD0
CLKSW
RSTB
YCLK
PAL GOB
YFILON1B
SLEEP MODE CTL
L: SLEEP
H: NORMAL
25
Pixel Clock in
Y-filter select
Reset [Low active] in
3
I / 0 VDD 5.0V or 3.3V
24
4
Luminance
23
6 5
75
22
34
7
AVDD
21
1.2k
20
75
19
BD4
BD5
BD6
BD7
GND
NTB
IM0
IM1
TEST1
TEST2
VSY
HSY
PIXCLK
VDD
I / O VDD
INT
Composite
Chrominance
18
75
17
33
ANALOG GND
4
5
6
7
POWER GND
OSD CLOCK
DIGITAL GND
3
43
6
INTERLACE / NON-INTER
PAL / NTSC
Hsync in
Vsync in
U.V Data 0...7
Y Data 0...7
[Blue]
OSD in [Green]
OSD in [Red]
OSD in
OSD enable
Video-CD / CD-G
Multimedia ICs
BU1425AK / BU1425AKV
(2) Example in Slave mode: Doubled clock is input and 16-bit YUV input is used
2 1 0
2 1 0
7
6
61
5
4
3
2
1
0
53
52
51
50
49
ANALOG VDD
POWER VDD
DIGITAL VDD
Multimedia ICs
BU1425AK / BU1425AKV
•Equivalent circuits
Pin No.
Pin name
I/O
Equivalent circuit
Function
2~8
10
GD (7: 0)
I
G data input pin for 24-bit RGB input
Y data input pin for 16-bit YUV input
11 ~ 14
17 ~ 20
BD (0: 7)
I
B data input pin for 24-bit RGB input
U, V data input pins for 16-bit YUV
input
54 ~ 56
58 ~ 60
62.63
RD (0: 7)
I
R data input pin for 24-bit RGB input
1
57
64
15
ROSD
GOSD
BOSD
OSDSW
I
OSD data input pin when using the
OSD function.
When the OSDSW pin is HIGH, input
to the ROSD, GOSD, and BOSD pins
takes precedence over RGB, and the
data is converted.
23
24
IM0
IM1
I
Control pins used to select RGB (24bit), YUV (16-bit) or DAC Through as
the input mode.
16
CDGSWB
I
Switches the mode between VideoCD (HIGH) and CD-G (LOW).
22
NTB
I
Switches the mode between NTSC
(LOW) and PAL (HIGH).
7
Multimedia ICs
Pin No.
I/O
Equivalent circuit
Function
28
HSY
I/O
This is the horizontal synchronization
signal pin. Negative polarity Hsync
signals are input (when SLABEB =
LOW) or output (when SLABEB =
HIGH) here. This is also used as the
synchronization signal for fixing the
PIXCLK output phase.
27
VSY
I/O
Vertical synchronization signals (Vsync)
are input (when SLABEB = LOW) or
output (when SLABEB = HIGH) here.
O
The internal processing clock is divided in half and output. Data is read at
the point at which the edge of this
clock changes. This can also be used
as the clock for the OSD IC.
I
This pin switches between interlace
(when HIGH) and non-interlace (when
LOW) modes. This pin is effective in
both the VIDEO-CD and CD-G
modes.
I
I
This pin switches between the Master
(when HIGH) and Slave (when LOW)
modes. It is effective in the noninterlace mode, and it switches between – 0.5 lines (when LOW) and + 0.5
lines (when HIGH) for the number of
lines in an interlace field.
29
32
33
34
8
Pin name
BU1425AK / BU1425AKV
PIXCLK
INT
SLABEB
ADDH
35
VREF-C
I
This is the reference voltage generator
circuit monitoring pin which determines the output amplitude (output current for 1 LSB) of the DAC. A 0.01µF
capacitor should be attached between
this and pin 43 (AVDD).
37
COUT
O
This is the chrominance output pin for
the S pin.
Multimedia ICs
BU1425AK / BU1425AKV
Pin No.
Pin name
I/O
39
VOUT
O
Composite output pin
45
YOUT
O
Luminance output pin for the S pin
I
The output amplitude (output current
for 1 LSB) of the DAC is specified
using an external resistor, and this pin
controls the value of the current flowing per bit.
42
IR
Equivalent circuit
Function
48
YCOFF
I
When there is HIGH input at the signal
input pin which switches to and from
the low power consumption mode, this
turns off the output from the YOUT
and COUT pins.
51
VCLK
I
Input pin for the reference clock in the
Video-CD mode
52
RSTB
I
Reset input pin which initializes the
system. The system is reset when
this goes LOW.
49
YFILON1B
YFILON2B
I
Selects the F characteristic of the
Y-FILTER.
9
Multimedia ICs
Pin No.
50
PAL60B
53
CLKSW
25
26
TEST1
TEST2
31
46
61
41
43
10
Pin name
BU1425AK / BU1425AKV
I/O
Equivalent circuit
Function
I
Switches between the PAL and PAL60
modes. This is effective only when
the NTB pin is HIGH. (PAL mode
only)
I
This switches between dividing the
VCLK input in half and using it as an
internal clock (when LOW), and using
it as an internal clock without dividing
it in half (when HIGH).
I
Normally, this is connected to the
GND pin. However, when 16-bit YUV
input is used, the TEST2 pin can be
used as the U and V timing control
pins.
AVDD
IOVDD
Power supply pin for the digital, the
analog, and I / O blocks
9
21
36
38
40
44
GND
CGND
VGND
AVSS
YGND
Grounding pin for the digital and
analog blocks
30
VDD
Digital VDD. Equipped with pull-down
resistor.
Multimedia ICs
BU1425AK / BU1425AKV
operation
•(1)Circuit
Overview
chrominance data. At the same time, a clock with a frequency half that of the internal clock is output from the
PIXCLK pin. As a result, the PIXCLK pin can easily be
directly connected to the OSD IC clock input pin, and the
OSDSW pin can be directly connected to the BLK output
pin. Thus, the BU1425AK and the OSD IC can be synchronized, and OSD text with a burster trimmer stacker
feature can be used.
If the input data is in the RGB format, it is converted to
YUV. If it is in the YUV format, it is converted from the
CCIR-601 format to level-shifted YUV data. The YUV
data is then adjusted to the 100IRE level in the NTSC,
PAL, and PAL60 modes, and U and V data is phaseadjusted by a sub-carrier generated internally, and is
modulated to chrominance signals.
Ultimately, elements such as the necessary synchronization level, the color blanking level, and burst signals are
mixed, and pass through the 9-bit DAC to be output as
NTSC or PAL composite signals, luminance signals, and
chrominance signals (conforming to RS-170A). At this
point, the DAC is operating at twice the internal clock,
making it possible to reduce the number of attachments.
Furthermore, luminance signal output and chrominance
signal output can be turned off. At this point, it is possible
to reduce the level of power consumption.
The DAC output is current output. If a resistor of a specified value is connected to the IR pin, 2.0VP-P output can
be obtained by connecting 75Ω to the VOUT pin as an
external resistor. As a result, normally, when a video
input pin (75Ω terminus) is connected, the output is
approximately 1.0VP-P voltage output at a white 100%
level.
The BU1425AK / AKV converts digital images and video
data with an 8-bit configuration to 9-bit composite signals
(VOUT), luminance signals (YOUT), and chrominance signals (COUT) for the NTSC, PAL, and PAL60 formats,
and outputs the converted data as analog TV signals.
The user may select whether VOUT consists of chrominance signals that have passed through a chrominance
band pass and luminance signals that have been mixed,
or luminance signals that have passed through a chrominance trap and luminance signals that have not passed
through a chrominance trap. The F characteristic of this
chrominance trap may be selected from among three
available types. Since YOUT normally does not pass
through the trap, it is optimum for the S pin. COUT normally passes through the chrominance band pass, and is
thus highly resistance to dot interference. In addition,
when used in the doubled clock mode, it passes through
an interpolator filter, and for that reason is able to reproduce even cleaner image quality.
A correspondence can be set up between input digital
image data and Video-CD and CD-G decoder output.
Output TV signals, in addition to switching among the
NTSC, PAL, and PAL60 modes, can be switched
between the interlace and non-interlace modes.
The data clock input to the VCLK pin can also be input as
a doubled clock for the data rate (in doubled clock
modes). In doubled clock modes, data is read and
processed at the rising edge of an internal clock that has
been divided in half. In ordinary clock modes, data is
read and processed at the rising edge of the clock that
has the same phase as the input clock. Two input data
formats are supported: 24-bit RGB (4: 4: 4) and 16-bit
YUV (4: 2: 2). These are input to RD0 to 7, GD0 to 7, and
BD0 to 7, respectively. The selected input format can be
switched using the IM0 and IM1 pin input. When the
OSDSW pin is set to the "Enabled" (H) state, data input
to the ROSD, GOSD, and BOSD pins becomes effective,
making it possible to input 7-color (8 including black)
(2) Specifying the mode
1) Power saving mode
With the BU1425AK / AKV, setting the YCOFF pin to
HIGH turns off the output from the YOUT and COUT pins
of the DAC output, enabling use in the low power consumption mode.
Table 1: Low power consumption mode with the YCOFF pin
Pin No.
48
Output Mode and Power Consumption
Pin Name
YCOFF
VOUT pin
YOUT pin
COUT pin
Power consumption (typ.)
LOW
Composite signal
Luminance signal
Chrominance signal
0.45W
HIGH
Composite signal
No output (0V)
No output (0V)
0.25W
11
Multimedia ICs
BU1425AK / BU1425AKV
2) Output modes
The “Video-CD” and “CD-G” modes can be supported
by both digital image and video data, with the mode
being switched by the CDGSWB pin input. When the
CDGSWB pin input is LOW, the CD-G mode is set, and
when HIGH, the Video-CD mode is set. Also, the
“NTSC”, “PAL”, and “PAL60” modes may be selected
as the output TV modes. The output TV mode is
switched using the NTB and PAL60 pin input. Setting
the NTB pin input to LOW sets the NTSC mode, and
setting it HIGH with the PAL60 pin also HIGH sets the
PAL mode. Setting the NTB pin HIGH and the PAL60
pin LOW, sets the PAL60 mode.
Table 2: Specifying modes
Decoder mode
TV mode
0
CD-G
NTSC
1
Video-CD
NTSC
0
CD-G
PAL60
1
Video-CD
PAL60
0
CD-G
PAL
1
Video-CD
PAL
NTB
PAL60
CDGSWB
0
0
∗
∗
1
0
1
0
1
1
1
1
Also, INT pin input can be used to switch between
“interlace output” and “non-interlace output.”
Setting the input to LOW enables non-interlace output,
and setting it to HIGH enables interlace output. When
non-interlace output is used, the number of lines in one
field can be controlled using the ADDH pin. If the ADDH
pin is LOW, the number of lines in one field is set to the
number of interlace output lines minus 0.5 lines, and
when HIGH, the number of lines in one field is set to the
number of interlace output lines plus 0.5 lines.
Table 3: Pin settings for interlace / non-interlace modes
No. of Lines / Field
INT
ADDH
Scan Mode
0
0
Non-interlace
0
1
Non-interlace
263
313
1
∗
Interlace
262.5
312.5
NTSC / PAL60
PAL
262
312
3) Input formats
The digital data input format can be set as shown in the
table below, using the IM1 and IM0 pins. Both 24-bit
RGB (4: 4: 4) and 16-bit YUV (4: 2: 2) are supported. In
addition, digital RGB input can be output as analog
RGB output (RGB Through mode).
Table 4: Input format settings
12
IM1
IM0
Input format
Output signal
0
0
R (8 bits), G (8 bits), B (8 bits)
TV signals (9-bit resolution)
0
1
16-bit YUV (4: 2: 2)
TV signals (9-bit resolution)
1
0
—
—
1
1
ROSD, GOSD, BOSD expanded to RGB input
RGB analog signals (9 bits)
Multimedia ICs
BU1425AK / BU1425AKV
Table 5: Bit assignments in RGB Through mode
Output Pin
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
YOUT (45)
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
ROSD
VOUT (39)
GD7
GD6
GD5
GD4
GD3
GD2
GD1
GD0
GOSD
COUT (37)
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
BOSD
The BU1425AK / AKV has an internal OSD switch and
chrominance data generating function. Consequently,
joint usage of an OSD-IC with blanking and R, G, and B
output can be easily supported by the OSD. Moreover,
a clock with half the internal processing frequency of
the BU1425AK is output from the PIXCLK pin, and can
be connected to the OSD-IC clock input, enabling the
timing to be captured.
ROSD, GOSD, and BOSD pin input is effective as long
as the OSDSW pin input is HIGH. The relationship
between OSD data and chrominance data is as shown
in Table 6 below.
Table 6: Correspondence between OSD function, input data and chrominance output
OSDSW
ROSD
GOSD
BOSD
Output Chrominance Signal
1
0
0
0
Black (blanking)
1
0
0
1
Blue
1
0
1
0
Green
1
0
1
1
Cyan
1
1
0
0
Red
1
1
0
1
Magenta
1
1
1
0
Yellow
1
1
1
1
White
0
∗
∗
∗
Based on input specified by IM0 and IM1
4) Clock modes
With the BU1425AK / AKV, clock input is available at the
VCLK pin.
Clocks supplied from an external source should basically
be input at a frequency double that of clocks used internally (basic clock: BCLK) (when the CLKSW pin is LOW).
The phase relationship between the internal clock and
the external clock at this time is as shown in Fig. 3, with
the HSY pin input serving as a reference. In the Master
mode, in which data from the HSY pin is output and
used, HSY is output at the timing shown in Fig. 3. With
the BU1425AK, data (RD, GD, BD, etc.) is read at the rising edge of the internal clock (BCLK), so data should be
input to the BU1425AK / AKV as shown in Fig. 3.
HSY
VCLK
Internal clock (BCLK)
Input data
Fig. 3 Illustration of clock timing (CLKSW is LOW)
13
Multimedia ICs
BU1425AK / BU1425AKV
Also, setting the CLKSW pin to HIGH enables the frequency of the external clock to be used as BCLK, the
internal clock, just as it is. Since the data is read to the
BU1425AK / AKV at the rising edge of BCLK at this
time as well, data should be input as shown in Fig. 4.
The relationship with HSY is also as shown in Fig. 4.
HSY
VCLK
Internal clock (BCLK)
Input data
Fig. 4 Illustration of clock timing (CLKSW is HIGH)
With the BU1425AK / AKV, the sub-carrier (burst) frequency is generated using the internal clock. For this
reason, the frequencies used in the various modes are
limited, so those frequencies should be input (see Table
7 below).
Table 7: BU1425AK / AKV clock input frequency settings
CLKSW Pin
Video-CD Mode
NTSC
PAL / PAL60
0
27.000MHz
28.636MHz
28.3750MHz
1
13.500MHz
14.318MHz
14.1875MHz
5) Synchronization signals
The BU1425AK / AKV has an "Encoder Master" mode in
which synchronization signals are output, and an
"Encoder Slave" mode in which synchronization signals
are input from an external source and used to achieve
synchronization. These modes are switched at the
SLABEB pin. When the SLABEB pin is LOW, the Slave
mode is in effect, and when HIGH, the Master mode is in
effect.
In the Master mode, the HSY and VSY pins serve as output, with horizontal synchronization signals (HSYNC)
being output from the HSY pin and vertical synchronization signals (VSYNC) from the VSY pin. At this time, the
reference timing for synchronization signal output is
determined at the rising edge of the RSTB pin. Output is
obtained in accordance with the specified mode (NTSC,
PAL, or PAL60, interlace or non-interlace). Output in the
14
CD-G Mode
Same for NTSC / PAL / PAL60
non-interlace mode, however, is output only under "Odd"
field conditions (the falling edges of Hsy and Vsy are the
same).
In the Slave mode, the HSY and VSY pins serve as input,
and horizontal synchronization signals (HSYNC) should
be input to the HSY pin and vertical synchronization signals (VSYNC) to the VSY pin. The input synchronization
signals at this time should be input in accordance with
the specified mode. With the BU1425AK / AKV, field distinction between odd and even fields is made automatically for each field when interlace input is used. With the
BU1425AK, all synchronization signals are treated as
negative polarity signals (signals for which the sync interval goes LOW). When using the non-interlace mode,
operation is normally carried out under odd field conditions (the falling edges of Hsy and Vsy are simultaneous).
Multimedia ICs
BU1425AK / BU1425AKV
6) Y filter
With the BU1425AK / AKV, the frequency characteristic
of Y, which is mixed with the VOUT pin output, is set so
that it can be selected using the YFILON1B and 2B pins.
A through filter is normally used on the YOUT pin output,
so that it is not limited to this method.
Table 8: Frequency characteristic of the Y channel
YFILON2B
YFILON1B
Frequency characteristic of the Y channel
H
H
TRAP filter through
(same signal as YOUT pin output is mixed with VOUT)
L
H
chart1
H
L
chart2
L
L
chart3
5
180
0
135
0
135
–5
90
–5
90
– 10
45
– 10
45
– 15
0
– 20
– 45
– 25
– 90
– 30
– 135
– 35
– 180
– 40
100
1000
AMPLITUDE (dB)
180
PHASE (deg)
AMPLITUDE (dB)
5
– 15
0
– 20
– 45
– 25
– 90
– 30
– 135
– 180
– 35
– 40
100
10000 20000
PHASE (deg)
10
10
1000
10000 20000
FREQUENCY (kHz)
FREQUENCY (kHz)
Gain-Phase Graphic
Gain-Phase Graphic
Fig.5 chart1 (BCLK = 13.5MHz)
Fig.6 chart2 (BCLK = 13.5MHz)
5
180
0
135
–5
90
– 10
45
– 15
0
– 20
– 45
– 25
– 90
– 30
– 135
– 35
– 180
– 40
100
1000
PHASE (deg)
AMPLITUDE (dB)
10
10000 20000
FREQUENCY (kHz)
Gain-Phase Graphic
Fig.7 chart3 (BCLK = 14.318MHz)
15
Multimedia ICs
BU1425AK / BU1425AKV
(3) Output level
Figures 8 to 10 indicate the digital data values for the
DAC output when the color bars from the various pins
are reproduced.
WHITE
YELLOW
CYAN
GREEN
MAGEN
RED
BLUE
BLACK
BLACK LEVEL
= PEDESTAL LEVEL
SYNC TIP LEVEL
Fig. 8 YOUT output
W
H
I
T
E
BLACK LEVEL
Y
E
L
L
O
W
C
Y
A
N
G
R
E
E
N
M
A
G
E
N
T
A
R
E
D
B
L
U
E
B
L
A
C
K
COLOR
BURST
Fig. 9 COUT output
W
H
I
T
E
Y
E
L
L
O
W
C
Y
A
N
BLACK LEVEL
= PEDESTAL LEVEL
SYNC TIP LEVEL
Fig. 10 VOUT output
16
G
R
E
E
N
M
A
G
E
N
T
A
R
E
D
B
L
U
E
B
L
A
C
K
Multimedia ICs
BU1425AK / BU1425AKV
Table 9: BU1425AK color bar input / output data
Input (8-bit hexadecimal for each)
RGB24bit
Output (9-bit hexadecimal for each)
YUV (4: 2: 2)
NAME&COLOR
YOUT
COUT
VOUT
RD
GD
BD
YD
UD
VD
—
—
—
—
—
—
SYNC TIP
—
000
—
—
—
—
—
—
Color Burst NTSC
—
± 033
± 033
—
—
—
—
—
—
Color Burst PAL
—
± 038
± 038
—
—
—
—
—
—
BLANK LEVEL
—
100
—
00
00
00
10
80
80
BLACK (Pedestal)
072
000
072
00
00
FF
28
F1
6D
BLUE
092
± 072
± 072
00
FF
00
90
36
22
GREEN
117
± 096
± 096
00
FF
FF
A9
A5
10
CYAN
138
± 0A0
± 0A0
FF
00
00
51
5A
F0
RED
0C6
± 0A0
± 0A0
FF
00
FF
6A
C9
DD
MAGENTA
0E6
± 096
± 096
FF
FF
00
D2
0E
92
YELLOW
16C
± 072
± 072
FF
FF
FF
EB
80
80
WHITE
18C
000
000
000
∗ COUT and VOUT display the chrominance amplitude. COUT is C8H ± XXXH.
VOUT is YOUT ± XXXH.
(4) Timing
Table 10 below shows the input and output pins related
to timing.
Table 10: BU1425AK timing-related input / output pins
Pin No.
Pin name
I/O
Function
52
RSTB
I
System reset input pin
51
VCLK
I
Clock input pin
53
CLKSW
I
Clock input mode setting pin
27
VSY
I/O
Vertical synchronization signal I / O pin
28
HSY
I/O
Horizontal synchronization signal I / O pin
16
CDGSWB
I
Video-CD / CD-G mode switching pin
22
NTB
I
NTSC / PAL mode switching pin
50
PAL60B
I
PAL / PAL60 mode switching pin
32
INT
I
Interlace / Non-interlace mode switching pin
33
SLABEB
I
Master / Slave mode switching pin
34
ADDH
I
Pin which adds 1 line in non-interlace mode
29
PIXCLK
O
1 / 2 divider output for internal clock (OSD clock)
17
Multimedia ICs
BU1425AK / BU1425AKV
1) Input clocks and input data timings in the various
operation modes
There are slight differences in the input data and the clock
timing, depending on which mode is being used. What is
shared by all modes is that, with the BU1425AK / AKV,
data is read and discharged at the rising edge of the
internal clock. The illustration below shows the input conditions in the various modes.
1. Master mode, ∗1 clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (pin53)
Internal clock (BCLK)
Input data
Output data (HSY, VSY)
Tds1
Fig.11
∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 11
Parameter
Data setup time 1
18
Symbol
Min.
Typ.
Max.
Tds1
10
—
—
Multimedia ICs
BU1425AK / BU1425AKV
2. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = 2∗ input clock (pin 53 = H)
VCLK (pin53)
Internal clock
(BCLK)
Input data
Output data
(HSY, VSY)
Tds2
Fig.12
∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, following the rise of the RSTB pin (pin 52).
Table 12
Parameter
Data setup time 2
Symbol
Min.
Typ.
Max.
Tds2
10
—
—
3. Slave mode, ∗1 clock mode
Encoder slave (pin 33 = H)
Internal clock = input clock (pin 53 = H)
VCLK (pin53)
Internal clock
(BCLK)
Input data
Input data
(HSY, VSY)
Tds3S
Tsh1
Tds3H
Tsd1
Fig.13
19
Multimedia ICs
BU1425AK / BU1425AKV
∗ In this mode, the internal clock (BCLK) begins to operate at the same phase as the VCLK input, following the rise
of the RSTB pin (pin 52).
Table 13
Parameter
Symbol
Min.
Typ.
Max.
Data setup time 3S
Tds3S
5
—
—
Data hold time 3H
Tds3H
8
—
—
Sync signal setup time
Tsd1
5
—
—
Sync signal hold time
Tsh1
8
—
—
4. Slave mode, doubled clock mode
Encoder slave (pin 33 = L)
Internal clock = 2∗ input clock (pin 53 = L)
VCLK (pin53)
Internal clock
(BCLK)
Input data
Input data
(HSY, VSY)
Tds4
Tsh2
Tsd2
Fig.14
∗ In this mode, the internal clock (BCLK) begins to operate at a halved frequency at the rise of the VCLK input, following the rise of the RSTB pin (pin 52). When HSY is input, phase correction is carried out at the falling edge, as
shown in Fig. 14. (In other words, the phase of the internal clock (BCLK) is not determined until HSY is input.)
Table 14
Parameter
Symbol
Min.
Typ.
Max.
Data setup time 4
Tds4
10
—
—
Sync signal hold time 2
Tsh2
10
—
—
Sync signal setup time 2
Tsd2
10
—
—
20
Multimedia ICs
BU1425AK / BU1425AKV
2) Clock timing when the OSD function is used
Eight-color OSD color with a burster trimmer stacker feature can be used, simply by connecting an OSD with
external clock input. Output from the PIXCLK pin of the
BU1425AK should be input to the OSC-IN of the OSD IC.
The OSDSW input pin can be used as a signal for the
burster trimmer stacker feature called VBLK, or a similar
name. (See page 13 for a table showing the correspondence between input data and color output.)
Internal clock (BCLK)
HSY (IN / OUT)
PIXCLK
OSDSW
ROSD.GOSD
V.Y.C.OUT
VIDEO-DATA
BLACK
YELLOW
VIDEO-DATA
Fig. 15 Clock timing with the OSD function
∗ The frequency of the PIXCLK pin output is one-half that of the internal clock. This phase is determined at the rising
edge of HSY, as shown in Fig.15. (In the Encoder Master mode, phase correction is implemented using the HSY
output of the BU1425AK itself.) The OSD function is effective only during the time that video output is enabled.
(See the TV signal timing diagram on page 27.)
21
Multimedia ICs
BU1425AK / BU1425AKV
3) Output timing
1. Master mode, doubled clock mode
Encoder master (pin 33 = H)
Internal clock = input clock∗ 1 / 2 (pin 53 = L)
VCLK
Internal clock (BCLK)
Thdr
HSY (OUT)
Thdf
VSY (OUT)
Tvdf
PIXCLK (OUT)
Tpdr
Tvdr
Fig. 16 Output timing with a doubled clock
Table 15
Parameter
Symbol
Min.
Typ.
Max.
HSY output delay
Thdr Thdf
—
14
—
VSY output delay
Tvdr Tvdf
—
14
—
PIXCLK output delay
Tpdr Tpdf
—
14
—
22
Multimedia ICs
BU1425AK / BU1425AKV
2. Master mode, regular clock mode
Encoder master (pin 33 = H)
Internal clock = input clock (pin 53 = L)
VCLK
Internal clock (BCLK)
HSY (OUT)
Thdf
VSY (OUT)
Tvdf
PIXCLK (OUT)
Tpdr
Thdr
Tvdr
Fig. 17 Output timing with a clock at the regular frequency
Table 16
Parameter
Symbol
Min.
Typ.
Max.
HSY output delay
Thdr Thdf
—
10
—
VSY output delay
Tvdr Tvdf
—
10
—
PIXCLK output delay
Tpdr Tpdf
—
10
—
23
Multimedia ICs
BU1425AK / BU1425AKV
4) Odd / even recognition timing in Slave mode
1. Timing based on recognition of odd conditions
The BU1425AK / AKV distinguishes whether the conditions of each field (each time that VSY is input) are odd
or otherwise, and internal operation is carried out based
on that recognition after the data is input. As a result,
HSY and VSY are input under input conditions appropriate to the specified mode, enabling regulated output for
the first time. Odd input conditions are indicated below.
Timing that does not match these conditions is recognized as an even field.
HSY
VSY
Tvl
Expanded view
HSY
VSY
Thvdiff
Fig. 18 Odd recognition conditions
Table 17: Odd recognition conditions
Parameter
VSY input L interval
VSY Delay from HSY
Symbol
Unit
Min.
Typ.
Max.
Tvl
BCLK
128
—
—
Thvdiff
BCLK
HSY falling edge
– 1clk
—
HSY Rising edge
– 2clk
∗ BCLK = One cycle of internal clock
24
Multimedia ICs
BU1425AK / BU1425AKV
2. Even timing
The BU1425AK / AKV distinguishes whether the conditions of each field (each time that VSY is input) are odd
or otherwise, and internal operation is carried out based
on that recognition after the data is input. As a result,
HSY and VSY are input under input conditions appropri-
ate to the specified mode, enabling regulated output for
the first time. Timing that does not match the odd field
conditions is recognized as an even field. In order to prevent malfunctioning of the internal HSY counter, however, there are regulations which apply to the timing at
which VSYNC is input in even fields.
HSY
VSY
Tvl
Expanded view
T = 1 / Fhsync
The middle of HSY
HSY
T = 1 / Fhsync∗1 / 2
T = 1 / Fhsync∗1 / 2
VSY
Thvdiff
Fig. 19 Even conditions
Table 18: Even conditions
Symbol
Unit
Min.
Typ.
Max.
VSY input L interval
Parameter
Tvl
BCLK
128
—
—
VSY Delay from The
middle of HSY
Thvdiff
BCLK
The middle of HYS
– 128clk
—
HSY Falling edge
– 128clk
∗ BCLK = One cycle of internal clock
25
Multimedia ICs
BU1425AK / BU1425AKV
VOUT
(39)
BURST
BURST
BURST
BURST
YOUT
(45)
COUT
(37)
Td1
Td2
Td3
Td4
Td5
Fig. 20 TV signal timing diagram
Table 19
NTSC
Parameter
Symbol
Unit
SYNC rise
Td1
Burst start
Td2
Burst end
Data start
1-line interval
26
PAL60
PAL
V-CD
CD-G
V-CD
CDG1
V-CD
CDG1
BCLK
64
67
64
67
64
67
BCLK
71
76
71
75
71
75
Td3
BCLK
106
112
106
112
106
112
Td4
BCLK
128
135
142
149
128
135
Td5
BCLK
858
910
864
908
858
902
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
259
260
523
261
524
262
525
263
1
265
Even_Field
264
Odd_Field
2
3
266
4
267
∗ Indicates a line interval during which video data is output
522
5
268
6
269
7
270
8
271
9
272
10
273
11
274
12
∗
18
281
19
282
20
Multimedia ICs
BU1425AK / BU1425AKV
Frame timing in Video-CD mode
(NTSC / PAL60: Interlace)
Fig. 21
27
28
Fig.22
VOUT (39pin)
Vsync (27pin)
Hsync (28pin)
VOUT (39pin)
Vsync (27pin)
Hsync (28pin)
310
623
312
625
2
313
315
3
Even_Field∗4
314
Odd_Field∗4
1
316
4
317
5
318
6
319
7
320
8
321
9
322
10
∗3 Indicates a line interval during which video data is output
∗4 First and second have been added to aid in explanation, but there is no actual distinction.
311
624
323
11
324
12
335
23
336
∗3
24
337
25
Multimedia ICs
BU1425AK / BU1425AKV
Frame timing in Video-CD mode
(PAL: Interlace)
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
259
521
261
523
262
524
2
3
265
Second_Field∗4
264
First_Field∗4
263
1
266
4
267
5
268
6
269
7
270
8
271
9
272
10
∗3 Indicates a line interval during which video data is output
∗4 First and second have been added to aid in explanation, but there is no actual distinction.
260
522
273
11
274
12
281
∗3
18
282
19
20
Multimedia ICs
BU1425AK / BU1425AKV
Frame timing in CD-G mode
(NTSC / PAL60: Non-interlace)
Fig.23
29
30
Fig.24
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
VOUT
(39pin)
Vsync (27pin)
Hsync (28pin)
310
622
312
624
2
3
315
Second_Field∗4
314
First_Field∗4
313
1
316
4
317
5
318
6
319
7
320
8
321
9
322
10
∗3 Indicates a line interval during which video data is output
∗4 First and second have been added to aid in explanation, but there is no actual distinction.
311
623
323
11
324
12
335
23
336
∗3
24
337
25
Multimedia ICs
BU1425AK / BU1425AKV
Frame timing in CD-G mode
(PAL: Non-interlace)
Multimedia ICs
BU1425AK / BU1425AKV
(5) Adjustment of the DAC output level
The voltage level of the DAC output is determined by the
DAC internal output current and the DAC output external
resistor. The output current per 1 DAC bit is determined
by the external resistor of the IR pin (pin 42), as shown
below.
the following results:
I (1LSB) = VVREF/RIR ∗1 / 16 [A] ... (equation 6-1)
VVREF ... Voltage generated by the regulator circuit in
the BU1425AK
[V]
RIR ... External resistor for the IR pin 1200[Ω]
(6) YUV input mode
With the BU1425AK, setting the IM0 pin (pin 23) to
HIGH enables a 16-bit YUV input format to be supported. At that time, the timing of U and V can be reversed
when data is input, using the H / L state of the Test2
pin.
The input conditions for this mode are shown below.
Consequently, when VVREF = 1.3V and RIR = 1200Ω,
a current of 67.71µA per 1LSB is output. Because the
white level of Y is a digital value of 396 (decimal value),
0
1
V (Y white) = 0.0677 × 396 = 26.81mA
At this point, if the DAC output external resistance is
37.5Ω, an amplitude of 1.005VP-P is obtained.
2
2n 2n + 1
Internal clock (BCLK)
HSY
Y-Data
U.V-Data
Y1
Y2
Y3
Y4
Y5
U1
V1
U3
V3
U5
Y1
Y2
Y3
Y4
Y5
U1
V1
U3
V3
U5
Fig. 25 YUV input timing when TEST[2] = L
0
1
2
2n 2n + 1
Internal clock (BCLK)
HSY
Y-Data
U.V-Data
Fig. 26 YUV input timing when TEST[2] = H
31
Multimedia ICs
BU1425AK / BU1425AKV
∗ Reversal of the U and V timing using the H / L state of TEST[2] can be controlled regardless of whether CLKSW is
HIGH or LOW (the input clock is a doubled clock or not).
∗ When using the RGB input mode, TEST[2] should be fixed at LOW.
∗ In the Master mode, HSYNC is output at the timing shown in Fig. 26. For that reason, the timing of U and V should
be determined by counting from that falling edge. In the Slave mode, the HSY, U, and V data should be input at the
timing shown in Fig. 26.
Table 20
TEST2
(pin26)
CLKSW
(pin53)
0
0
0
1
In a doubled clock mode, the timing of U and V is as shown in Fig. 7-1.
In a regular clock mode, the timing of U and V is as shown in Fig. 7-1.
1
1
0
1
In a doubled clock mode, the timing of U and V is as shown in Fig. 7-2.
In a regular clock mode, the timing of U and V is as shown in Fig. 7-2.
•External dimensions (Units: mm)
BU1425AK
BU1425AKV
48
16
0.8
0.35 ± 0.1
0.15 ± 0.1
0.15
QFP-A64
32
17
64
0.5
16
0.5
12.0 ± 0.3
10.0 ± 0.2
33
32
49
1
1.4 ± 0.1
1
0.5
17
64
0.10
2.7 ± 0.1
12.0 ± 0.3
10.0 ± 0.2
32
49
0.05
16.4 ± 0.3
14.0 ± 0.2
16.4 ± 0.3
14.0 ± 0.2
48
33
0.125 ± 0.1
0.2 ± 0.1
0.1
VQFP64