RENESAS M34282E2GP

4282 Group
REJ03B0084-0133Z
Rev.1.33
2004.03.18
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
• Timer
Timer 1 ................................................................... 8-bit timer
(This has a reload register and carrier wave output auto-control
function)
Timer 2 ................................................................... 8-bit timer
(This has two reload registers and carrier wave output function)
• Logic operation function (XOR, OR, AND)
• RAM back-up function
• Key-on wakeup function (ports D4–D7, E0–E2, G0–G3) .... 11
• I/O port (ports D, E, G, CARR) .......................................... 16
• Oscillation circuit ..................................... Ceramic resonance
• Watchdog timer
• Power-on reset circuit
• Voltage drop detection circuit ......................... Typical:1.50 V
(system reset)
The 4282 Group enables fabrication of 8 × 7 key matrix and has
the followin timers;
• an 8-bit timer which can be used to set each carrier wave and
has two reload register
• an 8-bit timer which can be used to auto-control and has a
reload register.
FEATURES
• Number of basic instructions ............................................. 68
• Minimum instruction execution time ............................ 8.0 µs
(at f(XIN) = 4.0 MHz, system clock = f(XIN)/8)
• Supply voltage ................................................. 1.8 V to 3.6 V
• Subroutine nesting ..................................................... 4 levels
APPLICATION
Various remote control transmitters
Part number
ROM (PROM) size
(× 9 bits)
1024 words
M34282M1-XXXGP
M34282M2-XXXGP
2048 words
M34282E2GP
2048 words
RAM size
(× 4 bits)
Package
ROM type
48 words
20P2E/F-A
Mask ROM
64 words
64 words
20P2E/F-A
Mask ROM
20P2E/F-A
One Time PROM
PIN CONFIGURATION (TOP VIEW)
1
20
VDD
E2
2
19
CARR
E1
3
18
D0
XIN
4
17
D1
XOUT
5
16
D2
E0
6
15
D3
G0
7
14
D4
G1
8
13
D5
G2
9
12
D6
G3
10
11
D7
M34282Mx-XXXGP
VSS
Outline 20P2E/F-A
Rev.1.33
Mar 18, 2004
page 1 of 67
Rev.1.33
Mar 18, 2004
Port E
2
page 2 of 67
Register A (4 bits)
Register B (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack register SK (4 levels)
ALU(4 bits)
720 series
CPU core
Port G
4
4
(48,64 words ✕ 4 bits)
RAM
(1024,2048 words ✕ 9 bits)
ROM
Memory (Note)
Reset (voltage drop detection circuit)
XIN -XOUT
System clock generation circuit
Port D
4
Note: PROM 2048 words ✕ 9 bits, RAM 64 words ✕ 4 bits for built-in PROM version.
Watchdog timer (14 bits)
Timer 2 (8 bits, carrier wave generation)
Timer 1 (8 bits, carrier wave output control)
Timer/Remote-control carrier-wave output
Internal peripheral function
I/O port
1
4282 Group
BLOCK DIAGRAM
4282 Group
PERFORMANCE OVERVIEW
Parameter
Number of basic instructions
Function
68
Minimum instruction execution time 8.0 µs (f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V)
Memory sizes ROM M34282M2/E2 2048 words ✕ 9 bits
RAM
Input/Output
ports
1024 words ✕ 9 bits
M34282M1
M34282M2/E2 64 words ✕ 4 bits
48 words ✕ 4 bits
M34282M1
D0–D3 Output
D4–D7 I/O
E0–E2 Input
Four independent output ports
E0, E1 Output
G0–G3 I/O
CARR Output
2-bit output port (E0, E1)
Timer
Four independent I/O ports with the pull-down function
3-bit input port with the pull-down function
4-bit I/O port with the pull-down function
1-bit output port; CMOS output
Timer 1
Timer 2
Subroutine nesting
Device structure
8-bit timer with a reload register
Package
20-pin plastic molded SSOP (20P2E/F-A)
–20 °C to 85 °C
8-bit timer with two reload registers
4 levels (However, only 3 levels can be used when the TABP p instruction is executed)
CMOS silicon gate
Operating temperature range
Supply voltage
1.8 V to 3.6 V
Active mode
400 µA
dissipation
(f(XIN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V)
(typical value) RAM back-up mode 0.1 µA (at room temperature, VDD = 3 V)
Power
PIN DESCRIPTION
VDD
Pin
Name
Power supply
VSS
Ground
XIN
System clock input
XOUT
System clock output
Output
D0–D3
Output port D
Output
Each pin of port D has an independent 1-bit wide output function. The output
structure is P-channel open-drain.
D4–D7
I/O port D
I/O
1-bit I/O port. For input use, set the latch of the specified bit to “0.” When the built-
Input/Output
Function
—
Connected to a plus power supply.
—
Input
Connected to a 0 V power supply.
I/O pins of the system clock generating circuit. Connect a ceramic resonator
between pins XIN and XOUT. The feedback resistor is built-in between pins XIN
and XOUT.
in pull-down transistor is turned on, the key-on wakeup function using “H” level
sense and the pull-down transistor become valid. The output structure is P-channel
open-drain.
E0–E2
I/O port E
Output
Input
2-bit (E0, E1) output port. The output structure is P-channel open-drain.
3-bit input port. For input use (E0, E1), set the latch of the specified bit to “0.”
When the built-in pull-down transistor is turned on, the key-on wakeup function
using “H” level sense and the pull-down transistor become valid. Port E2 has an
input-only port and has a key-on wakeup function using “H” level sense and pulldown transistor.
G0–G3
I/O port G
CARR
Carrier wave output
I/O
4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output structure
is P-channel open-drain. When the built-in pull-down transistor is turned on, the keyon wakeup function using “H” level sense and pull-down transistor become valid.
Output
for remote control
Rev.1.33
Mar 18, 2004
page 3 of 67
Carrier wave output pin for remote control. The output structure is CMOS circuit.
4282 Group
CONNECTIONS OF UNUSED PINS
Connection
Pin
Open or connect to VDD pin (Note 1).
Set the output latch to “1” and open, or
D0–D7
E 0, E 1
connect to VDD pin (Note 2).
Open or connect to VSS pin.
Set the output latch to “1” and open, or
E2
G0–G3
connect to VDD pin (Note 2).
Notes 1: Ports D4–D7: Set the bit 2 (PU02) of the pull-down control register PU1 to “0” by software and turn the pull-down transistor
OFF.
2: Set the corresponding bits of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.
(Note in order to set the output latch to “1” to make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “1” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note when connecting to VSS and VDD)
• Connect the unused pins to VSS or VDD at the shortest distance and use the thick wire against noise.
PORT FUNCTION
Port
Input/
Output
Pin
Port D
Output structure
Output P-channel open-drain
(4)
D0–D3
D4–D7
Control
Control
Control
bits
1 bit
instructions
SD
registers
RD
I/O
CLD
SD
(4)
RD
PU1
I/O
(2)
E0
E1
Input
(1)
E2
Port G
P-channel open-drain
I/O
G0–G3
P-channel open-drain
Output: OEA
2 bits
Input:
IAE
3 bits
IAE
4 bits
OGA
(4)
Port CARR
1 bit
• System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.
When using
Rev.1.33
System clock
Instruction clock
f(XIN)/8
f(XIN)/32
f(XIN)
f(XIN)/4
Mar 18, 2004
page 4 of 67
Pull-down function and
key-on wakeup function
PU0
Pull-down function and
key-on wakeup function
(programmable)
SCAR
RCAR
DEFINITION OF CLOCK AND CYCLE
CCK instruction
When not using
PU0
(programmable)
IAG
Output CMOS
(1)
CARR
Pull-down function and
key-on wakeup function
(programmable)
CLD
SZD
Port E
Remark
• Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.
• Machine cycle
The machine cycle is the cycle required to execute the
instruction.
4282 Group
PORT BLOCK DIAGRAMS
Decoder
Register Y
(Note 1)
S
SD instruction
Q
Ports D 0–D3
R
RD instruction
CLD instruction
Register Y
Decoder
(Note 1)
SD instruction
S Q
RD instruction
R
Ports D 4–D7 (Note 5)
CLD instruction
Skip decision (SZD instruction)
Key-on wakeup
Pull-down transistor
(Note 2) PU1i
Register A
Aj
(Note 3)
(Note 1)
D Q
OEA
instruction
IAE instruction
Ports E 0, E1 (Note 5)
T
Aj
Pull-down
transistor
Key-on wakeup input
(Note 3) PU0j
IAE instruction
Register A
A2
Port E 2 (Note 5)
Key-on wakeup input
Pull-down
transistor
(Note 1)
Register A
(Note 1)
D Q
Aj
(Note 3)
OGA
instruction
T
Ports G 0, G1 (Note 5)
IAG instruction
Aj
Key-on wakeup input
Pull-down transistor
PU02
Register A
(Note 1)
D Q
Ak
(Note 4)
OGA
instruction
T
Ports G 2, G3 (Note 5)
IAG instruction
Ak
Key-on wakeup input
Pull-down transistor
PU03
CAR flag
SCAR instruction
S Q
RCAR instruction
R
CARRY
(to timer 1)
CARRYD
(from timer 2)
Timer 1 underflow signal
Port CARR
D Q
V12
(Note 1)
T R
Carrier wave output control signal
V10
Notes 1:
This symbol represents a parasitic diode.
2: i represents bits 0 to 3.
3: j represents bits 0, 1.
4: k represents bits 2, 3.
5: Applied voltage must be less than VDD.
Rev.1.33
Mar 18, 2004
page 5 of 67
4282 Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(M(DP))
Addition
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
ALU
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
TAB instruction
Register B
B3 B2 B1 B0
Register A
A3 A2 A1 A0
TEAB instruction
Register E ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
TBA instruction Register A
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
4
8
Specifying address
0
Low-order 4 bits
p3
PCH
p2 p1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents
of register D
The contents
of register A
Most significant 1 bit
Carry flag CY (1)
URS flag (1)
URSC instruction
Fig. 4 TABP p instruction execution example
Rev.1.33
Mar 18, 2004
page 6 of 67
4282 Group
(5) Most significant ROM code reference enable flag (URS)
URS flag controls whether to refer to the contents of the most
significant 1 bit (bit 8) of ROM code when executing the TABP
p instruction. If URS flag is “0,” the contents of the most
significant 1 bit of ROM code is not referred even when
executing the TABP p instruction. However, if URS flag is “1,”
the contents of the most significant 1 bit of ROM code is set to
flag CY when executing the TABP p instruction (Figure 4).
URS flag is “0” after system is released from reset and returned
from RAM back-up mode. It can be set to “1” with the URSC
instruction, but cannot be cleared to “0.”
(6) Stack registers (SKs) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contents of registers SKs are destroyed when 4 levels are
exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions.
Note : The 4282 Group just invalidates the next instruction
when a skip is performed. The contents of program
counter is not increased by 2. Accordingly, the number
of cycles does not change even if skip is not performed.
However, the cycle count becomes “1” if the TABP p,
RT, or RTS instruction is skipped.
Program counter (PC)
Executing BM
instruction
Executing RT
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Subroutine
Main program
Address
SUB1 :
000016 NOP
NOP
·
·
·
RT
000116 BM SUB1
000216 NOP
(PC) ← (SK0)
(SP) ← 3
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
Rev.1.33
Mar 18, 2004
page 7 of 67
4282 Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not exceed after the last page of
the built-in ROM.
Program counter (PC)
p3 p2 p1 p0
PCH
Specifying
page
a6 a5 a4 a3 a2 a1 a0
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers X and Y. Register X specifies a file and
register Y specifies a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
9).
Register Y (4)
Specifying
RAM digit
Specifying RAM file
Register X (2)
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D7
0
1 0 1
Register Y (4)
D5
1
Port D output latch
Fig. 9 SD instruction execution example
Rev.1.33
Mar 18, 2004
page 8 of 67
D0
4282 Group
PROGRAM MEMORY (ROM)
Table 1 ROM size and pages
Part number
M34282M2/E2
ROM size (✕ 9 bits)
2048 words
Pages
16 (0 to 15)
M34282M1
1024 words
8 (0 to 7)
Page 2 (addresses 010016 to 017F16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern of all addresses can be used as data areas with
the TABP p instruction.
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers X and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 11 shows the RAM map.
Table 2 RAM size
Part number
M34282M2/E2
M34282M1
RAM size
64 words ✕ 4 bits (256 bits)
48 words ✕ 4 bits (192 bits)
8
000016
007 F16
008016
00FF16
010016
017 F16
018016
7
6
5
4
3
2
1 0
Page 0
Page 1
Subroutine special page
Page 2
Page 3
Page 15
07FF16
Fig. 10 ROM map of M34282M2/E2
RAM 64 words ✕ 4 bits (256 bits)
Register X
Register Y
The program memory is a mask ROM. 1 word of ROM is
composed of 9 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127).
0 1
2 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48 words
M34282M1
64 words
M34282M2/E2
Fig. 11 RAM map
Rev.1.33
Mar 18, 2004
page 9 of 67
4282 Group
TIMERS
The 4282 Group has the programmable timer.
• Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer 1
underflow flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
FF16
n: Counter initial value
Count starts
Reload
Reload
n
The contents of counter
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 underflow flag “1”
“0”
A skip instruction is executed
Fig. 12 Auto-reload function
The 4282 Group timer consists of the following circuit.
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
These timers can be controlled with the timer control registers
V1 and V2.
Each timer function is described below.
Table 3 Function related timer
Timer 1
8-bit programmable
Frequency
Use of output signal
dividing ratio
• Carrier wave output control
• Carrier wave output (CARRY) 1 to 256
Timer 2
binary down counter
8-bit programmable
• Bit 5 of watchdog timer
• f(XIN)
binary down counter
• f(XIN)/2
Circuit
Structure
14-bit timer
Count source
14-bit fixed frequency • Instruction clock
1 to 256
• Carrier wave output
16384
• Watchdog timer
• Timer 1 count source
Rev.1.33
Mar 18, 2004
page 10 of 67
Control
register
V1
V2
4282 Group
SNZT1 instruction
V10 (Note 1)
V11
0
0
CARRY
T1F
Timer 1 (8)
1
1
Timer 1 underflow signal
(to port CARR)
Reload register R1 (8)
(T1AB)(Note 2)
(TAB1)
Register B
Register A
(TAB1)
Register B
Register A
(T2HAB)
Reload register R2H (8)
XIN
0
0
1/2
Timer 2(8)
1
1
Reload control circuit
V23
V20 (Note 1)
V21
T
Q
R
SNZT2
instruction
(Note 3) (T2R2L)
(T2AB)
V22
Reload register R2L (8)
T2F
T2F
(T2AB)
(TAB2)
CARRYD
(to port CARR)
Register B
(TAB2)
Register A
CAR flag
SCAR instruction
S Q
RCAR instruction
R
CARRY
(to timer 1)
Port CARR
Timer 1 underflow signal
D Q
V12
T R
Frequency divider
(divided by 4)
XIN
CCK instruction
S Q
R
V10
STCK (System clock)
Frequency divider
(divided by 8)
Initializing signal
(Note 3)
Carrier wave output control signal
INSTCK
(Instruction clock)
Synchronous
circuit
Initializing signal (Note 4)
System reset
14-bit timer (WDT)
INSTCK
0
5
13
WDF1 WDF2
WRST instruction
Initializing signal
(Note 4)
Notes 1: Counting is stopped by clearing to “0.”
2: When the T1AB instruction is executed after V1 0 is set to “1,”
writing is performed only to reload register R1.
3: The data of reload register R2L set with the T2AB instruction
can be also written to timer 2 with the T2R2L instruction.
4: The initializing signal is output at reset or RAM back-up mode.
Fig. 13 Timers structure
Rev.1.33
Mar 18, 2004
page 11 of 67
4282 Group
Table 4 Control registers related to timer
Timer control register V1
V12
Carrier wave output auto-control bit
V11
Timer 1 count source selection bit
V10
Timer 1 control bit
at reset : 0002
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
0
1
Carrier wave output (CARRY)
Bit 5 of watchdog timer (WDT)
0
Stop (Timer 1 state retained)
1
Operating
Timer control register V2
V23
Carrier wave “H” interval expansion bit
V22
Carrier wave generation function control bit
V21
Timer 2 count source selection bit
V20
Timer 2 control bit
at reset : 00002
To expand “H” interval is invalid
To expand “H” interval is valid (when V22=1 selected)
0
Carrier wave generation function invalid
1
0
Carrier wave generation function valid
f(XIN)
1
f(XIN)/2
0
1
Stop (Timer 2 state retained)
Operating
(1) Control registers related to timer
• Timer control register V1
Register V1 controls the timer 1 count source and autocontrol function of carrier wave output from port CARR by
timer 1. Set the contents of this register through register A
with the TV1A instruction.
• Timer control register V2
Register V2 controls the timer 2 count source and the carrier
wave generation function by timer. Set the contents of this
register through register A with the TV2A instruction.
(2) Precautions
Note the following for the use of timers.
• Count source
Stop timer 1 or timer 2 counting to change its count source.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 256 µs
(at the minimum instruction execution time : 8 µs) is
generated from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
• Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
Mar 18, 2004
page 12 of 67
at RAM back-up : 00002
0
1
Note: “W” represents write enabled.
Rev.1.33
at RAM back-up : 0002
W
W
4282 Group
(3) Timer 1
Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1).
When timer is stopped, data can be set simultaneously in timer
1 and the reload register (R1) with the T1AB instruction.
When timer is operating, data can be set to only reload register
R1 with the T1AB instruction.
When setting the next count data to reload register R1 at
operating, set data before timer 1 underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with the bit 1 of register V1, and
➂ set the bit 0 of register V1 to “1.”
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 underflow flag (T1F) is set to “1,” new data is loaded
from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
When the bit 2 of register V1 is set to “1,” the carrier wave
output enable/disable interval of port CARR is alternately
generated each timer 1 underflows (Figure 14).
Data can be read from timer 1 to registers A and B. When
reading the data, stop the counter and then execute the TAB1
instruction.
(4) Timer 2
Timer 2 is an 8-bit binary down counter with the timer 2 reload
registers (R2H and R2L).
Data can be set simultaneously in timer 2 and the reload
register (R2L) with the T2AB instruction.
The contents of reload register (R2L) set with the T2AB
instruction can be set again to timer 2 with the T2R2L
instruction. Data can be set to reload register (R2H) with the
T2HAB instruction.
Timer 2 starts counting after the following process;
➀ set data in timer 2,
➁ select the count source with the bit 1 of register V2, and
➂ select the valid/invalid of the carrier wave generation
function by bit 2 of register V1 (when this function is valid,
select the valid/invalid of the carrier wave “H” interval
expansion by bit 3), and
➃ set the bit 0 of register V1 to “1.”
When the carrier wave generation function is invalid (V22=“0”),
the following operation is performed;
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the
timer 2 underflow flag (T2F) is set to “1,” new data is loaded
from reload register R2L, and count continues (auto-reload
function).
When a value set in reload register R2L is n, timer 2 divides
the count source signal by n + 1 (n = 0 to 255).
When the carrier wave generation function is valid (V22=“1”),
the carrier wave which has the “L” interval set to the reload
register R2L and “H” interval set to the reload register R2H
can be output (Figure 15).
After the count of the “L” interval of carrier wave is started,
timer 2 underflows and the timer 2 underflow flag (T2F) is set
Rev.1.33
Mar 18, 2004
page 13 of 67
to “1”. Then, the “H” interval data of carrier wave is reloaded
from the reload register R2H, and count continues.
When timer underflows again after auto-reload, the T2F flag
is set to “1”. And then, the “L” interval data of carrier wave is
reloaded from the reload register R2L, and count continues.
After that, each timer underflows, data is reloaded from reload
register R2H and R2L alternately.
When a value set in reload register R2H is n, “H” interval of
carrier wave is as follows;
➀ When to expand “H” interval is invalid (V23 = “0”),
Count source ✕ (n+1), n = 0 to 255
➁ When to expand “H” interval is valid (V23 = “1”),
Count source ✕ (n+1.5), n = 1 to 255
When a value set in reload register R2L is m, “L” interval of
carrier wave is as follows;
Count source ✕ (m+1), m = 0 to 255
Data can be read from timer 2 to registers A and B. When
reading the data, stop the counter and then execute the TAB2
instruction.
(5) Timer underflow flags (T1F, T2F)
Timer 1 underflow flag or timer 2 underflow flag is set to “1”
when the timer 1 or timer 2 underflows. The state of flags T1F
and T2F can be examined with the skip instruction (SNZT1,
SNZT2).
Flags T1F and T2F are cleared to “0” when the next instruction
is skipped with a skip instruction.
4282 Group
Timer 1 starts
Timer 1 underflow
(V10)←1
“1”
“0”
“H”
Port CARR output “L”
a
b
c
▲
▲
▲
Set the interval “a” to timer 1. Set the interval “b”
Set the interval “c”
to reload register R1. to reload register R1.
Count source CARRY selected
▲
Set the interval “d”
to reload register R1.
d
(V11)←0
Auto-control valid
Carrier wave output start
(V12)←1
Timer 1 stop
(V10)←0
Timer 1 underflow
“1”
“0”
“H”
CARRY “L”
(Note)
“H”
Port CARR output “L”
Register V12 “1”
“0”
Auto-control invalid
Carrier wave output start
Auto-control invalid
Carrier wave output stop
Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1.
Fig. 14 Port CARR output control by timer 1
● In this case, the following is set;
• Timer 2 carrier wave generation function is valid (V22=“1”),
• “L” interval (0316) of carrier wave is set to reload register R2L
• “H” interval (0216) of carrier wave is set to reload register R2H
To expand “H” interval of carrier wave is invalid (V23=“0”)
[Count source: 4.0 MHz, Resolution: 250 ns]
Timer 2 count source
Timer 2 count value 0316
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R2L)
(R2H)
(R2L)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
3 clocks
interval
CARRYD
3 clocks
interval
Carrier wave period:
7 clocks
Timer 2 starts
Carrier wave period:
7 clocks
To expand “H” interval of carrier wave is valid (V23=“1”)
(When count source is 4.0 MHz, carrier wave is expanded for 125 ns]
Timer 2 count source
Timer 2 count value 0316
(Reload register) (R2L)
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
(R2H)
(R2L)
0216
0116 0016 0316 0216 0116 0016
(R2H)
(R2L)
Timer 2 underflow signal
CARRYD
3.5 clocks
interval
Timer 2 starts
Carrier wave period:
7.5 clocks
3.5 clocks
interval
Carrier wave period:
7.5 clocks
Note: When to expand “H” interval of the carrier wave is valid, set “0116” or more to reload register R2H.
Fig. 15 Carrier wave generation example by timer 2
Rev.1.33
Mar 18, 2004
page 14 of 67
0216
(R2H)
4282 Group
● In this case, the following is set;
• To expand “H” interval of carrier wave is invalid (V23 = “0”),
• Timer 2 carrier wave generation function is valid (V22=“1”),
• Count source XIN/2 selected (V21=“1”),
• “L” interval (0316) of carrier wave is set to reload register R2L
• “H” interval (0216) of carrier wave is set to reload register R2H
Timer 2 count start timing
Machine cycle Mi
Mi + 1
Mi + 2
TV2A instruction execution cycle (V20) ←1
Instruction clock
=f(XIN)/8
XIN
XIN/2
(Count source selected)
Register V2 0
0316
Timer 2 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216
(R2L)
(R2H)
(R2L)
Timer 2 underflow signal
CARRYD
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle Mi
Mi + 1
Mi + 2
TV2A instruction execution cycle (V20)←0
Instruction clock
=f(XIN)/8
XIN
XIN/2
(Count source selected)
Register V2 0
Timer 2 count value
(Reload register)
0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R2L)
(R2H)
(R2L)
0216
(R2H)
Timer 2 underflow signal
(Note 1)
CARRYD
Timer 2 count stop timing
Notes 1: When the carrier wave generation function is vaild (V22=“1”), avoid a timing
when timer 2 underflows to stop timer 2. When the timer 2 count stop occurs
at the same timing with the timer 2 underflows, hazard may occur in the carrier
wave output waveform.
2: When the timer 2 is stopped during “H” output of carrier wave while the carrier
wave generation function is valid, it is stopped after the “H” interval set by
reload register R2H is output.
Fig. 16 Timer 2 count start/stop timing
Rev.1.33
Mar 18, 2004
page 15 of 67
4282 Group
WATCHDOG TIMER
Watchdog timer provides a method to reset and restart the system
when a program runs wild. Watchdog timer consists of 14-bit
timer (WDT) and watchdog timer flags (WDF1, WDF2).
Watchdog timer downcounts the instruction clock (INSTCK) as
the count source immediately after system is released from reset.
When the timer WDT count value becomes 000016 and underflow
occurs, the WDF1 flag is set to “1.” Then, when the WRST
instruction is not executed before the timer WDT counts 16383,
WDF2 flag is set to “1” and internal reset signal is generated and
system reset is performed.
Execute the WRST instruction at period of 16383 machine cycle
or less to keep the microcomputer operation normal.
Timer WDT is also used for generation of oscillation stabilization
time. When system is returned from reset and from RAM backup mode by key-input, software starts after the stabilization
oscillation time until timer WDT downcounts to 3E0016 elapses.
Software start
Software start
Software start
3FFF16
3E0016
Value of timer WDT
0000 16
“1”
“0”
WDF1 flag
“1”
“0”
WDF2 flag
Internal reset signal
“H”
“L”
System
reset
POF
instruction
execution
Return
WRST
instruction
execution
System
reset
Fig. 17 Watchdog timer function
LOGIC OPERATION FUNCTION
The 4282 Group has the 4-bit logic operation function. The logic
operation between the contents of register A and the low-order
4 bits of register E is performed and its result is stored in register
A.
Each logic operation can be selected by setting logic operation
selection register LO.
Set the contents of this register through register A with the TLOA
instruction. The logic operation selected by register LO is
executed with the LGOP instruction.
Table 5 shows the logic operation selection register LO.
Table 5 Logic operation selection register LO
Logic operation selection register LO
at reset : 002
LO1 LO0
LO1
Logic operation selection bits
LO0
Note: “W” represents write enabled.
Rev.1.33
Mar 18, 2004
page 16 of 67
at RAM back-up : 002
1
Logic operation function
0 Exclusive logic OR operation (XOR)
1 OR operation (OR)
0 AND operation (AND)
1
1 Not available
0
0
W
4282 Group
RESET FUNCTION
In order to make the built-in power-on reset circuit operate
efficiently, set the voltage rising time until VDD = 0 to 2.2 V is
obtained at power-on 1ms or less.
The 4282 Group has the power-on reset circuit, though it does
not have RESET pin. System reset is performed automatically
at power-on, and software starts program from address 0 in page
0.
f(XIN)
Internal reset signal “H”
“L”
f(X IN) 16384 pulses
Software operation starts
(address 0 in page 0)
Fig. 18 Reset release timing
VDD
Power-on reset circuit
output voltage
Internal reset signal
Power-on reset circuit
Reset state
Voltage drop detection circuit
Watchdog timer output
Internal reset signal
Reset released
Power-on
Fig. 19 Power-on reset circuit example
(1) Internal state at reset
Table 6 shows port state at reset, and Figure 20 shows internal
state at reset (they are retained after system is released from
reset).
The contents of timers, registers, flags and RAM except shown
in Figure 20 are undefined, so set the initial value to them.
(2) Note on power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
- when the supply voltage (VDD) rises from 0 V to 2.2 V, within 1 ms.
Also, note that system reset does not occur under the following
conditions;
- when the supply voltage (VDD) rises from the voltage higher
than 0V, or
- when it takes more than 1 ms for the supply voltage (VDD) to
rise from 0 V to 2.2 V.
Rev.1.33
Mar 18, 2004
page 17 of 67
Table 6 Port state at reset
Name
State at reset
D0–D3 High impedance state
D4–D7
High impedance state (Pull-down transistor OFF)
G0–G3
High impedance state (Pull-down transistor OFF)
High impedance state (Pull-down transistor OFF)
E 0 , E1
CARR
“L” output
4282 Group
• Program counter (PC) .............................................................. 0
0
0
0
• Timer 2 underflow flag (T2F) ................................................... 0
• Timer control register V1 .......................................................... 0
• Timer control register V2 .......................................................... 0
0
0
0
0
0
• Port CARR output flag (CAR) .................................................. 0
• Pull-down control register PU0 ................................................ 0
• Pull-down control register PU1 ................................................ 0
0
0
0
0
0
0
0
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
• Power down flag (P) ................................................................. 0
• Timer 1 underflow flag (T1F) ................................................... 0
• Logic operation selection register LO ...................................... 0
• Most significant ROM code reference enable flag (URS)
0
• Carry flag (CY) ......................................................................... 0
0
• Register A ................................................................................. 1
• Register B ................................................................................. 1
• Register X ................................................................................. 0
1
1
1
1
0
1
1
• Register Y ................................................................................. 0
• Stack pointer (SP) .................................................................... 1
0
0
0
1
Fig. 20 Internal state at reset
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage at operating and to reset the microcomputer if
the supply voltage drops below the specified value (Typ. 1.50 V)
or less.
VDD
The voltage drop detection circuit is stopped and power
dissipation is reduced in the RAM back-up mode with the
initialized CPU stopped.
(Note)
Reset voltage
TYP 1.5V
Microcomputer starts operation
after f(X IN) is counted to 16384 times.
Internal reset signal
Note: The voltage drop detection circuit does not have
the hysteresis characteristics in the detected voltage.
Fig. 21 Voltage drop detection circuit operation waveform
Note on voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
A battery exchange of an application product is explained as
an example.
The supply voltage falls below to the recommended operating
voltage while CPU keeps active. Then, an unexpected
oscillation-stop, which does not happen by POF instruction
occurs before the supply voltage falls below to the detection
voltage. In this time, even if the supply voltage re-goes up to
the recommended operating voltage, since reset does not
occur, MCU may not operate correctly.
Please confirm the oscillator you use and the frequency of
system clock, and test the operation of your system sufficiently.
VDD
Recommended operatng
condition min.value
Oscillation is stopped
incorrectly.
VDET
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VDET
Reset
Fig. 22 VDD and VDET
Rev.1.33
Mar 18, 2004
page 18 of 67
4282 Group
RAM BACK-UP MODE
Table 7 Functions and states retained at RAM back-up
RAM back-up
Function
The 4282 Group has the RAM back-up mode.
When the POF instruction is executed, system enters the RAM
back-up state.
As oscillation stops retaining RAM, the functions and states of
reset circuit at RAM back-up mode, power dissipation can be
reduced without losing the contents of RAM. Table 7 shows the
function and states retained at RAM back-up. Figure 23 shows
the state transition.
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port CARR
O
O
Port G
O
✕
Logic operation selection register LO
✕
Timer 1 function, Timer 2 function
Timer underflow flags (T1F, T2F)
✕
✕
Watchdog timer (WDT)
Watchdog timer flags (WDF1, WDF2)
MostsignificantROMcodereferenceenableflag(URS)
✕
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2:The stack pointer (SP) points the level of the stack
register and is initialized to “112” at RAM back-up.
(3) Identification of the start condition
Warm start (return from the RAM back-up state) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
POF instruction
is executed
A
B
f(XIN) stop
(Stabilizing time a )
Reset
✕
Timer control registers V1, V2
Pull-down control registers PU0, PU1
(2) Cold start condition
The CPU starts executing the software from address 0 in page
0 when any of the following conditions is satisfied .
• reset by power-on reset circuit is performed
• reset by watchdog timer is performed
• reset by voltage drop detection circuit is performed
In this case, the P flag is “0.”
O
✕
O
Ports D0–D7
Ports E0, E1
(1) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up state by executing the POF
instruction, the CPU starts executing the software from address
0 in page 0. In this case, the P flag is “1.”
✕
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : Microcomputer starts its operation after f(XIN) is counted to16384 times.
Fig. 23 State transition
Power down flag P
POF instruction
S
Reset input
R
Q
Software start
P = “1”
?
Yes
No
● Set source
● Clear source
POF instruction is executed
Reset input
Fig. 24 Set source and clear source of the P flag
Rev.1.33
Mar 18, 2004
page 19 of 67
Cold start
Warm start
Fig. 25 Start condition identified example using the SNZP
instruction
4282 Group
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode. Table 8 shows the return condition for each
return source.
Table 8 Return source and return condition
Return source
Ports D4–D7
Return condition
Remarks
Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is
input.
turned ON by register PU1 is valid.
Ports E0, E1, G
Return by an external “H” level Only key-on wakeup function of the port whose pull-down transistor is
input.
turned ON by register PU0 is valid.
Ports E2
Return by an external “H” level Key-on wakeup function is always valid.
input.
(5) Pull-down control register
Registers PU0 and PU1 are 4-bit registers and control the
ON/OFF of pull-down transistor and key-on wakeup function
for ports E0, E1, G and ports D4–D7.
Set the contents of register PU0 or PU1 through register A
with the TPU0A or TPU1A instruction, respectively.
Table 9 Pull-down control registers
Pull-down control register PU0
PU03
Ports G2, G3 pull-down transistor control
bit
PU02
Ports G0, G1 pull-down transistor control
bit
PU01
Port E1 pull-down transistor control bit
PU00
Port E0 pull-down transistor control bit
at reset : 00002
0
1
0
1
0
1
0
1
Pull-down control register PU1
PU13
Port D7 pull-down transistor control bit
PU12
Port D6 pull-down transistor control bit
PU11
Port D5 pull-down transistor control bit
PU10
Port D4 pull-down transistor control bit
Note: “W” represents write enabled.
Rev.1.33
Mar 18, 2004
page 20 of 67
at RAM back-up : state retained
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
at reset : 00002
at RAM back-up : state retained
0
Pull-down transistor OFF, key-on wakeup invalid
1
0
Pull-down transistor ON, key-on wakeup valid
1
0
1
W
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
0
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
1
Pull-down transistor ON, key-on wakeup valid
W
4282 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits.
• System clock generating circuit
• Control circuit to stop the clock oscillation
• Control circuit to return from the RAM back-up state
CCK instruction
XIN
OSC
XOUT
Frequency
divider
(divided by 8)
Internal clock
generation circuit
(divided by 4)
Multiplexer
INSTCK
STCK
Internal power-on reset circuit
POF instruction
R
S
Q
Pull-down control
register PU0
Ports E0,E1,G0–G3
Pull-down control
register 1
Ports D4–D7
Port E2
Fig. 26 Clock control circuit structure
System clock signal f(XIN) is obtained by externally connecting a
ceramic resonator. Connect this external circuit to pins XIN and
XOUT at the shortest distance as shown Figure 27.
A feedback resistor is built-in between XIN pin and XOUT pin.
4282
XIN
4
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) Mask ROM Order Confirmation Form*
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical
copies) or one floppy disk.
CIN
Use the resonator
manufacturer’s
recommended value
because constants
such as capacitance
depend on the
resonator.
XOUT
5
COUT
Fig. 27 Ceramic resonator external circuit
* For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
Rev.1.33
Mar 18, 2004
page 21 of 67
4282 Group
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.01 µF) between pins
VDD and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the One Time PROM version, port E2 is also used as VPP
pin. Connect this pin to VSS through the resistor about 5 kΩ
which is assigned to E2/V PP pin as close as possible at the
shortest distance.
➁ Notes on unused pins
(Note in order to set the output latch to “0” to make pins open)
• After system is released from reset, a port is in a highimpedance state until the output latch of the port is set to
“0” by software.
Accordingly, the voltage level of pins is undefined and the
excess of the supply current may occur.
• To set the output latch periodically is recommended
because the value of output latch may change by noise or
a program run away (caused by noise).
(Note when connecting to VSS and VDD)
• Connect the unused pins to V SS and VDD at the shortest
distance and use the thick wire against noise.
➂ Timer
• Count source
Stop timer 1 or timer 2 counting to change its count source.
• Watchdog timer
Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.
• Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
• Timer 1 count operation
When the bit 5 of the watchdog timer (WDT) is selected as
the timer 1 count source, the error of maximum ± 256 µs
(at the minimum instruction execution time : 8 µs) is
generated from timer 1 start until timer 1 underflow. When
programming, be careful about this error.
• Stop of timer 2
Avoid a timing when timer 2 underflows to stop timer 2.
• Writing to reload register R2H
When writing data to reload register R2H while timer 2 is
operating, avoid a timing when timer underflows.
• Timer 2 carrier wave output function
When to expand “H” interval of carrier wave is valid, set “1”
or more to reload register R2H.
➃ Program counter
Make sure that the program counter does not specify after the
last page of the built-in ROM.
Rev.1.33
Mar 18, 2004
page 22 of 67
➄ Power-on reset
Under the following condition, the system reset occurs by the
built-in the power-on reset circuit of this product;
- when the supply voltage (VDD) rises from 0 V to 2.2 V, within 1 ms.
Also, note that system reset does not occur under the following
conditions;
- when the supply voltage (VDD) rises from the voltage higher
than 0V, or
- when it takes more than 1 ms for the supply voltage (VDD) to
rise from 0 V to 2.2 V.
➅ Voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
A battery exchange of an application product is explained as
an example.
The supply voltage falls below to the recommended operating
voltage while CPU keeps active. Then, an unexpected
oscillation-stop, which does not happen by POF instruction
occurs before the supply voltage falls below to the detection
voltage. In this time, even if the supply voltage re-goes up to
the recommended operating voltage, since reset does not
occur, MCU may not operate correctly.
Please confirm the oscillator you use and the frequency of
system clock, and test the operation of your system sufficiently.
VDD
Recommended operatng
condition min.value
Oscillation is stopped
incorrectly.
VDET
Even if the voltage re-goes up to
the recommended operating voltage,
MCU may not operate correctly.
→ Normal operation
VDD
Recommended
operatng condition
min.value
VDET
Reset
Fig. 28 VDD and VDET
4282 Group
INSTRUCTIONS
The 4282 Group has the 68 instructions. Each instruction is
described as follows;
(1) List of instruction function
(2) Machine instructions (index by alphabet)
(3) Machine instructions (index by function)
(4) Instruction code table
SYMBOL
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Contents
Symbol
Contents
Symbol
A
B
Register A (4 bits)
D
Port D (8 bits)
Register B (4 bits)
E
Port E (3 bits)
DR
Register D (3 bits)
Register E (8 bits)
G
CARR
Port G (4 bits)
Port CARR (1 bit)
Timer control register V1 (3 bits)
CAR
CAR flag (1 bit)
Timer control register V2 (4 bits)
Pull-down control register PU0 (4 bits)
x
Hexadecimal variable
Pull-down control register PU1 (4 bits)
y
Hexadecimal variable
LO
Logic operation selection register LO (2 bits)
p
n
Hexadecimal variable
Hexadecimal constant which represents the
X
Register X (2 bits)
Y
j
DP
Register Y (4 bits)
Data pointer (6 bits)
Hexadecimal constant which represents the
immediate value
A3A2A1A0
PC
(It consists of registers X and Y)
Program counter (11 bits)
Binary notation of hexadecimal variable A
(same for others)
←
Direction of data movement
Data exchange between a register and memory
ER
V1
V2
PU0
PU1
PCH
PCL
SK
SP
CY
R1
T1
T1F
R2H
R2L
T2
T2F
WDT
WDF1
WDF2
URS
P
immediate value
High-order 4 bits of program counter
Low-order 7 bits of program counter
Stack register (11 bits ✕ 4)
Stack pointer (2 bits)
Carry flag
Timer 1 reload register
↔
?
( )
—
Timer 1
Decision of state shown before “?”
Contents of registers and memories
Negate, Flag unchanged after executing
instruction
Timer 1 underflow flag
Timer 2 reload register
Timer 2 reload register
Timer 2
Timer 2 underflow flag
Watchdog timer
Watchdog timer flag 1
Watchdog timer flag 2
M(DP)
a
p, a
C
+
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p3 p2 p1 p0
Hex. number C + Hex. number x (also same for
others)
x
Most significant ROM code reference enable flag
STCK
Power down flag
System clock
INSTCK
Instruction clock
Note : The 4282 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
Rev.1.33
Mar 18, 2004
page 23 of 67
4282 Group
LIST OF INSTRUCTION FUNCTION
Grouping Mnemonic
Function
Page
Function
Grouping Mnemonic
(A) ← n
TAB
(A) ← (B)
38
TBA
(B) ← (A)
40
TAY
(A) ← (Y)
40
(SK(SP)) ← (PC)
(PCH) ← p p=0 to 15
(PCL) ← (DR2–DR0, A3–A0)
LA n
Page
31
n = 0 to 15
Register to register transfer
TABP p
TYA
(Y) ← (A)
42
TEAB
(ER7–ER4) ← (B)
41
(SP) ← (SP) + 1
39
When URS=0
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(ER3–ER0) ← (A)
When URS=1
TABE
(B) ← (ER7–ER4)
(CY) ← (ROM(PC))8
(B) ← (ROM(PC))7 to 4
39
(A) ← (ER3–ER0)
(DR2–DR0) ← (A2–A0)
40
LXY x, y
(X) ← x, x = 0 to 3
31
(Y) ← y, y = 0 to 15
INY
(Y) ← (Y) + 1
31
DEY
(Y) ← (Y) – 1
30
TAM j
(A) ← (M(DP))
40
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Arithmetic operation
RAM addresses
(A) ← (ROM(PC))3 to 0
TDA
(X) ← (X) EXOR(j)
j = 0 to 3
XAM j
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
43
j = 0 to 3
RAM to register transfer
XAMD j
(A) ←→ (M(DP))
43
AM
AMC
(A) ← (A) + (M(DP))
27
(A) ← (A) + (M(DP)) + (CY)
27
(CY) ← Carry
An
(A) ← (A) + n
27
n = 0 to 15
SC
(CY) ← 1
35
RC
(CY) ← 0
33
SZC
(CY) = 0 ?
37
CMA
(A) ← (A)
30
RAR
→ CY → A3A2A1A0
33
LGOP
Logic operation
instruction
31
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
43
XOR, OR, AND
j = 0 to 3
(Y) ← (Y) + 1
SB j
(Mj(DP)) ← 1
34
Bit operation
j = 0 to 3
RB j
(Mj(DP)) ← 0
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
Rev.1.33
Mar 18, 2004
page 24 of 67
33
j = 0 to 3
37
4282 Group
Function
Comparison
operation
Grouping Mnemonic
Page
Grouping Mnemonic
SEAM
(A) = (M(DP)) ?
36
TV1A
SEA n
(A) = n ?
35
TAB1
Function
Page
(V12–V10) ← (A2–A0)
42
(B) ← (T17–T14)
39
(A) ← (T13–T10)
n = 0 to 15
Ba
(PCL) ← a6–a0
27
BL p, a
(PCH) ← p
(PCL) ← a6–a0
28
BA a
(PCL) ← (a6–a4, A3–A0)
28
at timer 1 operating (V10=1):
(R17–R14) ← (B)
(PCH) ← p
28
(R13–R10) ← (A)
T1AB
at timer 1 stop (V10=0):
37
Branch operation
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
BLA p, a
(PCL) ← (a6–a4, A3–A0)
SNZT1
BM a
(SP) ← (SP) + 1
28
(T1F) = 1 ?
36
After skipping
(SK(SP)) ← (PC)
(PCH) ← 2
the next instruction
(T1F) ← 0
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p p= 0 to 15
(PCL) ← a6–a0
BMLA p, (SP) ← (SP) + 1
(SK(SP)) ← (PC)
a
TV2A
(V23–V20) ← (A3–A0)
42
TAB2
(B) ← (T27–T24)
39
29
29
Timer operation
Subroutine operation
(PCL) ← a6–a0
(A) ← (T23–T20)
T2AB
(R2L7–R2L4) ← (B)
38
(T27–T24) ← (B)
(R2L3–R2L0) ← (A)
(PCH) ← p p= 0 to 15
(T23–T20) ← (A)
(PCL) ← (a6–a4, A3–A0)
Return operation
T2HAB
(PC) ← (SK(SP))
RT
(R2H7–R2H4) ← (B)
38
(R2H3–R2H0) ← (A)
34
(SP) ← (SP) – 1
T2R2L
RTS
(PC) ← (SK(SP))
(T27–T24) ← (R2L7–R2L4)
(SP) ← (SP) – 1
SNZT2
(T2F) = 1 ?
After skipping
the next instruction
(T2F) ← 0
Rev.1.33
38
(T27–T24) ← (R2L3–R2L0)
34
Mar 18, 2004
page 25 of 67
36
4282 Group
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Other operation
Carrier wave
control operation
Input/Output operation
Grouping Mnemonic
Function
Page
CLD
(D) ← 0
29
RD
(D(Y)) ← 0
(Y) = 0 to 7
34
SD
(D(Y)) ← 1
(Y) = 0 to 7
35
SZD
(D(Y)) = 0 ?
(Y) = 4 to 7
37
OEA
(E1, E0) ← (A1, A0)
32
IAE
(A2–A0) ← (E2–E0)
30
OGA
(G) ← (A)
32
IAG
(A) ← (G)
30
SCAR
(CAR) ← 1
35
RCAR
(CAR) ← 0
33
NOP
(PC) ← (PC) + 1
32
POF
RAM back-up
32
SNZP
(P) = 1 ?
36
CCK
STCK changes to f(XIN)
29
TLOA
(LO1, LO0) ← (A1, A0)
41
URSC
(URS) ← 1
42
TPU0A
(PU03–PU00) ← (A3–A0)
41
TPU1A
(PU13–PU10) ← (A3–A0)
41
WRST
(WDF1) ← 0
43
Rev.1.33
Mar 18, 2004
page 26 of 67
4282 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instrunction
code
D8
0
D0
1
0
1
0
n3 n2 n1 n0
2
0
A
n
16
(A) ← (A) + n
n = 0 to 15
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Overflow = 0
Grouping:
Arithmetic operation
Description: Adds the value n in the immediate field to
register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no
overflow as the result of operation.
AM (Add accumulator and Memory)
Instrunction
code
D0
D8
0
0
0
0
0
1
0
1
0
2
0
0
A
16
(A) ← (A) + (M(DP))
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents
of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instrunction
code
D8
0
D0
0
0
0
0
1
0
1
1
2
0
0
B
16
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Adds the contents of M(DP) and carry flag
CY to register A. Stores the result in register A and carry flag CY.
B a (Branch to address a)
Instrunction
code
Operation:
Rev.1.33
D8
1
D0
1
a6 a5 a4 a3 a2 a1 a0
(PCL) ← a6–a0
Mar 18, 2004
page 27 of 67
2
1
8
+a
a
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
a in the identical page.
4282 Group
BA a (Branch to address a + Accumulator)
Instrunction
code
D8
D0
0
0
0
0
0
0
0
0
1
1
1
a6 a5 a4 a3 a2 a1 a0
2
2
0
0
1 16
1
8
+a
a
16
(PCL) ← a6–a4, A3–A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
(a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in
the identical page with register A.
BL p, a (Branch Long to address a in page p)
Instrunction
code
D8
0
1
D0
0
1
0
1
1
p3 p2 p1 p0
2
a6 a5 a4 a3 a2 a1 a0 2
0
3
p
1
8
+a
a 16
16
(PCH) ← (P)
(PCL) ← a6–a0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch out of a page : Branches to address
a in page p.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
BLA p, a (Branch Long to address a in page p)
Instrunction
code
D8
0
1
D0
0
1
0
0
1
0
0
0
0
2
a6 a5 a4 p3 p2 p1 p0 2
0
1
0
1
8
+a
p 16
16
(PCH) ← (P)
(PCL) ← (a6–a4, A3–A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Branch operation
Description: Branch within a page : Branches to address
(a6 a5 a4 A3 A2 A1 A0) determined by replacing the low-order 4 bits of the address a in
page p with register A.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
BM a (Branch and Mark to address a in page 2)
Instrunction
code
Operation:
Rev.1.33
D8
1
D0
0
a6 a5 a4 a3 a2 a1 a0
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← 2
(PCL) ← a6–a0
Mar 18, 2004
page 28 of 67
2
1
a
a
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine in page 2 : Calls the
subroutine at address a in page 2.
4282 Group
BML p, a (Branch and Mark Long to address a in page p)
Instrunction
code
D8
D0
0
0
1
1
1
p3 p2 p1 p0
1
0
a6 a5 a4 a3 a2 a1 a0 2
2
0
7
p
1
a
a 16
16
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
(PCL) ← a6–a0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address a in page p.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
BMLA p, a (Branch and Mark Long to address a in page p)
Instrunction
code
D0
D8
0
0
1
0
1
0
0
0
0
1
0
a6 a5 a4 p3 p2 p1 p0 2
2
0
5
0
1
a
p 16
16
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
–
Grouping:
Subroutine call operation
Description: Call the subroutine : Calls the subroutine at
address (a6 a5 a4 A3 A2 A1 A0) determined
by replacing the low-order 4 bits of address
a in page p with register A.
Note:
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
CCK (Change system Clock to f(XIN))
Instrunction
code
Operation:
D8
0
D0
0
1
0
1
1
0
0
1
2
0
5
9
16
Change to STCK = f(XIN)
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Changes system clock (STCK) from f(XIN)/8
to f(XIN). Execute this instruction at address
0 in page 0.
CLD (CLear port D)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
0
0
1
0
0
(D) ← 1
Mar 18, 2004
0
1
2
0
1
1
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to port D (high-impedance state).
page 29 of 67
4282 Group
CMA (CoMplement of Accumulator)
Instrunction
code
D8
0
D0
0
0
0
1
1
1
0
0 2
0
1
C 16
(A) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Stores the one’s complement for register
A’s contents in register A.
DEY (DEcrement register Y)
Instrunction
code
D8
0
D0
0
0
0
1
0
1
1
1
2
0
1
7
16
(Y) ← (Y) – 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped.
IAE (Input Accumulator from port E)
Instrunction
code
D8
0
D0
0
1
0
1
0
1
1
0
2
0
5
6
16
(A2–A0) ← (E2–E0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of port E to register
A.
IAG (Input Accumulator from port G)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
0
1
0
1
0
(A) ← (G)
Mar 18, 2004
0
0
2
0
2
8
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Transfers the contents of port G to register
A.
page 30 of 67
4282 Group
INY (INcrement register Y)
Instrunction
code
D8
0
D0
0
0
0
1
0
0
1
1
2
0
1
3
16
(Y) ← (Y) + 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped.
LA n (Load n in Accumulator)
Instrunction
code
D0
D8
0
1
0
1
1
n3 n2 n1 n0
2
0
B
n
16
(A) ← n
n = 0 to 15
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
Arithmetic operation
Description: Loads the value n in the immediate field to
register A.
When the LA instructions are continuously
coded and executed, only the first LA instruction is executed and other LA
instructions coded continuously are
skipped.
LGOP (LoGic OPeration between accumulator and register E)
Instrunction
code
Operation:
D8
0
D0
0
1
0
0
0
0
0
1
2
0
4
1
16
Logic operation XOR, OR, AND
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Arithmetic operation
Description: Executes the logic operation selected by
logic operation selection register LO between the contents of register A and
register E, and stores the result in register
A.
LXY x, y (Load register X and Y with x and y)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
1
1
x1 x0 y3 y2 y1 y0
(X) ← x, x = 0 to 3
(Y) ← y, y = 0 to 15
Mar 18, 2004
page 31 of 67
2
0
C
+x
y
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
Continuous
description
Grouping:
RAM addresses
Description: Loads the value x in the immediate field to
register X, and the value y in the immediate
field to register Y. When the LXY instructions are continuously coded and executed,
only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
4282 Group
NOP (No OPeration)
Instrunction
code
D8
0
D0
0
0
0
0
0
0
0
0 2
0
0
0 16
(PC) ← (PC) + 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: No operation
OEA (Output port E from Accumulator)
Instrunction
code
D8
0
D0
1
0
0
0
0
1
0
0 2
0
8
4 16
(E1, E0) ← (A1, A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port E.
OGA (Output port G from Accumulator)
Instrunction
code
D8
0
D0
1
0
0
0
0
0
0
0
2
0
8
0 16
(G) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Outputs the contents of register A to port G.
POF (Power OFf1)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
0
0
0
1
1
RAM back-up
Mar 18, 2004
0
1
2
0
0
D
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Puts the system in RAM back-up state.
page 32 of 67
4282 Group
RAR (Rotate Accumulator Right)
Instrunction
code
D8
D0
0
0
0
0
1
1
1
0
1
2
0
1
D
16
→ CY → A3A2A1A0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0/1
–
Grouping:
Arithmetic operation
Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the
right.
RB j (Reset Bit)
Instrunction
code
D0
D8
0
0
1
0
0
1
1
j1
j0
2
0
4
C
+j 16
(Mj(DP)) ← 0
j = 0 to 3
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Clears (0) the contents of bit j (bit specified
by the value j in the immediate field) of
M(DP).
RC (Reset Carry flag)
Instrunction
code
D8
0
D0
0
0
0
0
0
1
1
0
2
0
0
6
16
(CY) ← 0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
0
–
Grouping:
Arithmetic operation
Description: Clears (0) to carry flag CY.
RCAR (Reset CAR flag)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
1
0
0
0
0
1
(CAR) ← 0
Mar 18, 2004
1
0
2
0
8
6
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Carrier wave control operation
Description: Clears (0) to port CARR output flag.
page 33 of 67
4282 Group
RD (Reset port D specified by register Y)
Instrunction
code
D8
0
D0
0
0
0
1
0
1
0
0
2
0
1
4
16
(D(Y)) ← 0
However,
(Y) = 0 to 7
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y (high-impedance state).
RT (ReTurn from subroutine)
Instrunction
code
D8
0
D0
0
1
0
0
0
1
0
0
2
0
4
4
16
(SP) ← (SP) – 1
(PC) ← (SK(SP))
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
–
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine.
RTS (ReTurn form subroutine and Skip)
Instrunction
code
D8
0
D0
0
1
0
0
0
1
0
1
2
0
4
5
16
(SP) ← (SP) – 1
(PC) ← (SK(SP))
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
2
–
Skip at uncondition
Grouping:
Return operation
Description: Returns from subroutine to the routine
called the subroutine, and skips the next instruction at uncondition.
SB j (Set Bit)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
1
0
1
1
1
(Mj(DP)) ← 0
j = 0 to 3
Mar 18, 2004
j1
j0
2
0
5
C
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Bit operation
Description: Sets (1) the contents of bit j (bit specified by
the value j in the immediate field) of M(DP).
page 34 of 67
4282 Group
SC (Set Carry flag)
Instrunction
code
D8
0
D0
0
0
0
0
0
1
1
1
2
0
0
7 16
(CY) ← 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
1
–
Grouping:
Arithmetic operation
Description: Sets (1) to carry flag CY.
SCAR (Set CAR flag)
Instrunction
code
D0
D8
0
1
0
0
0
0
1
1
1
2
0
8
7
16
(CAR) ← 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Carrier wave control operation
Description: Sets (1) to port CARR output flag (CAR).
SD (Set port D specified by register Y)
Instrunction
code
D8
0
D0
0
0
0
1
0
1
0
1
2
0
1
5
16
(D(Y)) ← 1
(Y) = 0 to 7
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instrunction
code
D8
0
0
Operation:
Rev.1.33
D0
0
1
0
0
1
1
0
1
0
1
1
2
n3 n2 n1 n0 2
(A) = n ?
n = 0 to 15
Mar 18, 2004
0
page 35 of 67
0
0
2
B
5
16
Number of
words
Number of
cycles
Flag CY
Skip condition
2
2
–
(A) = n, n = 0 to 15
n 16
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the value n in
the immediate field.
4282 Group
SEAM (Skip Equal, Accumulator with Memory)
Instrunction
code
Operation:
D8
0
D0
0
0
1
0
0
1
1
0
2
0
2
6
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(A) = (M(DP))
16
(A) = (M(DP)) ?
Grouping:
Comparison operation
Description: Skips the next instruction when the contents of register A is equal to the contents of
M(DP).
SNZP (Skip if Non Zero condition of Power down flag)
Instrunction
code
Operation:
D8
0
D0
0
0
0
0
0
0
1
1
2
0
0
3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(P) = 1
16
(P) = 1 ?
Grouping:
Other operation
Description: Skips the next instruction when P flag is “1”.
After skipping, P flag remains unchanged.
SNZT1 (Skip if Non Zero condition of Timer 1 underflow flag)
Instrunction
code
Operation:
D8
0
D0
0
1
0
0
0
0
1
0
2
0
4
2
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(T1F) = 1
16
(T1F) = 1 ?
After skipping, (T1F) ← 0
Grouping:
Timer operation
Description: Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears (0) to T1F flag.
SNZT2 (Skip if Non Zero condition of Timer 2 inerrupt request flag)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
1
0
1
0
0
(T2F) = 1 ?
After skipping, (T2F) ← 0
Mar 18, 2004
page 36 of 67
1
0
2
0
5
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(T2F) = 1
Grouping:
Timer operation
Description: Skips the next instruction when the contents of T2F flag is “1.”
After skipping, clears (0) to T2F flag.
4282 Group
SZB j (Skip if Zero, Bit)
Instrunction
code
Operation:
D8
0
D0
0
0
1
0
0
0
j1
j0
2
0
2
j
16
(Mj(DP)) = 0 ?
j = 0 to 3
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Mj(DP)) = 0
j = 0 to 3
Grouping:
Bit operation
Description: Skips the next instruction when the contents of bit j (bit specified by the value j in
the immediate field) of M(DP) is “0.”
SZC (Skip if Zero, Carry flag)
Instrunction
code
Operation:
D0
D8
0
0
0
1
0
1
1
1
1
2
0
2
F
16
(CY) = 0 ?
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(CY) = 0
Grouping:
Arithmetic operation
Description: Skips the next instruction when the contents of carry flag CY is “0.”
SZD (Skip if Zero, port D specified by register Y)
Instrunction
code
Operation:
D8
D0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
1
1 2
2
0
2
4
0
2
B 16
16
(D(Y)) = 0 ?
(Y) = 4 to 7
Number of
words
Number of
cycles
Flag CY
2
2
–
Skip condition
(D(Y)) = 0
(Y) = 4 to 7
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.”
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
1
0
0
0
1
1
at timer 1 stop (V10=0)
(R17–R14) ← (B), (R13–R10) ← (A)
(T17–T14) ← (B), (T13–T10) ← (A)
at timer 1 operating (V10=1)
(R17–R14) ← (B), (R13–R10) ← (A)
Mar 18, 2004
page 37 of 67
1
2
0
4
7
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1
and reload register R1.
At timer 1 operating (V10 = 1), transfers the
contents of register A and register B to reload register R1.
4282 Group
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instrunction
code
D8
0
D0
1
0
0
0
1
0
0
0
2
0
8
8 16
(R2L7–R2L4) ← (B)
(R2L3–R2L0) ← (A)
(T27–T24) ← (B)
(T23–T20) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of registers A and B
to timer 2 and timer 2 reload register R2L.
T2HAB (Transfer data to register R2H Accumulator from register B)
Instrunction
code
D8
0
D0
1
0
0
0
1
0
0
1
2
0
8
9
16
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A and
register B to reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instrunction
code
D8
0
D0
0
1
0
1
0
0
1
1
2
0
5
3
16
(T27–T24) ← (R2L7–R2L4)
(T23–T20) ← (R2L3–R2L0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of reload register
R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
0
0
1
1
1
(A) ← (B)
Mar 18, 2004
1
0
2
0
1
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register B to register A.
page 38 of 67
4282 Group
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instrunction
code
D8
0
D0
0
1
0
1
0
1
1
1
2
0
5
7
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T17–T14)
(A) ← (T13–T10)
Operation:
Number of
words
Grouping:
Timer operation
Description: Transfers the contents of timer 1 to registers A and B.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instrunction
code
D0
D8
0
0
1
0
0
0
0
0
0
2
0
4
0
Number of
cycles
Flag CY
Skip condition
1
1
–
–
16
(B) ← (T27–T24)
(A) ← (T23–T20)
Operation:
Number of
words
Grouping:
Timer operation
Description: Transfers the contents of timer 2 to registers A and B.
TABE (Transfer data to Accumulator and register B from register E)
Instrunction
code
D8
0
D0
0
0
1
0
1
0
1
0
2
0
2
A
16
(B) ← (ER7–ER4)
(A) ← (ER3–ER0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register E to registers A and B.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instrunction
code
Operation:
Note:
Rev.1.33
D8
0
Number of
words
D0
1
0
0
1
p3 p2 p1 p0
2
0
SK(SP)) ← (PC) , (SP) ← (SP) + 1
(PCH) ← p, p = 0 to 7, (PCL) ← (DR2–DR0, A3–A0)
When URS = 0,
(B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
When URS = 1,
(CY) ← (ROM(PC))8
(B) ← (ROM(PC))7 to 4, (A) ← (ROM(PC))3 to 0
(SP) ← (SP) – 1, (PC) ← (SK(SP))
p is 0 to 7 for M34282M1,
p is 0 to 15 for M34282M2/E2.
Mar 18, 2004
page 39 of 67
9
p
16
1
Number of
cycles
Flag CY
–
0/1
Arithmetic operation
3
Skip condition
–
Grouping:
Description:
Transfers bits 7 to 4 to register B and bits 3 to 0 to register
A when URS flag is cleared to “0.” These bits 7 to 0 are the
ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0) specified by registers A and D in page p.
Transfers bit 8 of ROM pattern is transferred to flag CY when
URS flag is set to “1” (after the URSC instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
4282 Group
TAM j (Transfer data to Accumulator from Memory)
Instrunction
code
D8
0
D0
0
1
1
0
0
1
j1
j0
2
0
6
4
j
+j
16
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 3
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After transferring the contents of M(DP) to
register A, an exclusive OR operation is
performed between register X and the value
j in the immediate field, and stores the result in register X.
TAY (Transfer data to Accumulator from register Y)
Instrunction
code
D8
0
D0
0
0
0
1
1
1
1
1
2
0
1
F
16
(A) ← (Y)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register Y to register A.
TBA (Transfer data to register B from Accumulator)
Instrunction
code
D8
0
D0
0
0
0
0
1
1
1
0
2
0
0
E
16
(B) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register B.
TDA (Transfer data to register D from Accumulator)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
0
1
0
1
0
(DR2–DR0) ← (A2–A0)
Mar 18, 2004
page 40 of 67
0
1
2
0
2
9
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register D.
4282 Group
TEAB (Transfer data to register E from Accumulator and register B)
Instrunction
code
D8
0
D0
0
0
0
1
1
0
1
0
2
0
1
A
16
(ER7–ER4) ← (B)
(ER3–ER0) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A and
register B to register E.
TLOA (Transfer data to register LO from Accumulator)
Instrunction
code
D0
D8
0
0
1
0
1
1
0
0
0
2
0
5
8
16
(LO1, LO0) ← (A1, A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to logic
operation selection register LO.
TPU0A (Transfer data to register PU0 from Accumulator)
Instrunction
code
D8
0
D0
1
0
0
0
1
1
1
1
2
0
8
F
16
(PU03–PU00) ← (A3–A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
1
0
0
0
1
1
(PU13–PU10) ← (A3–A0)
Mar 18, 2004
page 41 of 67
1
0
2
0
8
E
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Transfers the contents of register A to pullup control register PU1.
4282 Group
TV1A (Transfer data to register V1 from Accumulator)
Instrunction
code
D8
0
D0
0
1
0
1
0
1
1
1
2
0
5
B
16
(V12–V10) ← (A2–A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instrunction
code
D8
0
D0
0
1
0
1
1
0
1
0 2
0
5
A 16
(V23–V20) ← (A3–A0)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Timer operation
Description: Transfers the contents of register A to register V2.
TYA (Transfer data to regiser Y from Accumulator)
Instrunction
code
D8
0
D0
0
0
0
0
1
1
0
0
2
0
0
C 16
(Y) ← (A)
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Register to register transfer
Description: Transfers the contents of register A to register Y.
URSC (Sets Upper ROM Code reference enable flag)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
1
0
0
0
0
0
(URS) ← 1
Mar 18, 2004
1
0
2
0
8
2
16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Sets the most significant ROM code reference enable flag (URS) to “1.”
page 42 of 67
4282 Group
WRST (Watchdog timer ReSeT)
Instrunction
code
D8
0
D0
0
0
0
0
1
1
1
1
2
0
0
F
16
(WDF1) ← 0
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
Other operation
Description: Initializes the watchdog timer flag (WDF1).
XAM j (eXchange Accumulator and Memory data)
Instrunction
code
D0
D8
0
0
1
1
0
0
0
j1
j0
2
0
6
j
16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 3
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
–
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instrunction
code
D8
0
D0
0
1
1
0
1
1
j1
j0
2
0
6
C
+j 16
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 3
(Y) ← (Y) – 1
Operation:
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 15
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y is 15, the next instruction
is skipped.
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instrunction
code
Operation:
Rev.1.33
D8
0
D0
0
1
1
0
1
0
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
Mar 18, 2004
page 43 of 67
j1
j0
2
0
6
8
+j 16
Number of
words
Number of
cycles
Flag CY
Skip condition
1
1
–
(Y) = 0
Grouping:
RAM to register transfer
Description: After exchanging the contents of M(DP)
with the contents of register A, an exclusive
OR operation is performed between register X and the value j in the immediate field,
and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of
register Y is 0, the next instruction is
skipped.
4282 Group
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (INDEX BY FUNCTION)
TAB
0
0
0
0
1
1
1
1
0
0 1
E
1
1
(A) ← (B)
TBA
0
0
0
0
0
1
1
1
0
0 0
E
1
1
(B) ← (A)
TAY
0
0
0
0
1
1
1
1
1
0 1
F
1
1
(A) ← (Y)
TYA
0
0
0
0
0
1
1
0
0
0 0
C
1
1
(Y) ← (A)
TEAB
0
0
0
0
1
1
0
1
0
0 1
A
1
1
(ER7–ER4) ← (B) (ER3–ER0) ← (A)
TABE
0
0
0
1
0
1
0
1
0
0 2
A
1
1
(B) ← (ER7–ER4) (A) ← (ER3–ER0)
TDA
0
0
0
1
0
1
0
0
1
0 2
9
1
1
(DR2–DR0) ← (A2–A0)
LXY x, y
0
1
1
x1 x0 y3 y2 y1 y0
0 C y
+x
1
1
(X) ← x, x = 0 to 3
1
1
(Y) ← (Y) + 1
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
RAM addresses
Register to register transfer
Type of
instructions
Hexadecimal
notation
Function
(Y) ← y, y = 0 to 15
INY
0
0
0
0
1
0
0
1
1
0 1
DEY
0
0
0
0
1
0
1
1
1
0 1 7
1
1
(Y) ← (Y) – 1
TAM j
0
0
1
1
0
0
1
j1
j0
0 6
1
1
(A) ← (M(DP))
3
4
(X) ← (X) EXOR(j)
+j
j = 0 to 3
RAM to register transfer
XAM j
0
0
1
1
0
0
0
j1
j0
0 6
j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
XAMD j
0
0
1
1
0
1
1
j1
j0
0 6
C
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
+j
j = 0 to 3
(Y) ← (Y) – 1
XAMI j
0
0
1
1
0
1
0
j1
j0
0 6
8
+j
1
1
(A) ←→ (M(DP))
(X) ← (X) EXOR(j)
j = 0 to 3
(Y) ← (Y) + 1
Rev.1.33
Mar 18, 2004
page 44 of 67
Skip condition
Carry flag CY
4282 Group
–
–
Transfers the contents of register B to register A.
–
–
Transfers the contents of register A to register B.
–
–
Transfers the contents of register Y to register A.
–
–
Transfers the contents of register A to register Y.
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
–
–
Transfers the contents of register A to register D.
Continuous
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
Detailed description
Y.
description
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
Rev.1.33
Mar 18, 2004
page 45 of 67
4282 Group
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
LA n
0
1
0
1
1
n3 n2 n1 n0
Hexadecimal
notation
0 B n
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(A) ← n
n = 0 to 15
TABP p
0
1
0
0
1
p3 p2 p1 p0
0 9
p
1
3
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p, p=0 to 7 (Note)
(PCL) ← (DR2–DR0, A3–A0)
When URS=0,
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
When URS=1,
(CY) ← (ROM(PC))8
(B) ← (ROM(PC))7 to 4
(A) ← (ROM(PC))3 to 0
(SP) ← (SP) – 1
Arithmetic operation
(PC) ← (SK(SP))
AM
0
0
0
0
0
1
0
1
0
0 0
A
1
1
(A) ← (A) + (M(DP))
AMC
0
0
0
0
0
1
0
1
1
0 0
B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
An
0
1
0
1
0
n3 n2 n1 n0
0 A n
1
1
(A) ← (A) + n
n = 0 to 15
SC
0
0
0
0
0
0
1
1
1
0 0
7
1
1
(CY) ← 1
RC
0
0
0
0
0
0
1
1
0
0 0
6
1
1
(CY) ← 0
SZC
0
0
0
1
0
1
1
1
1
0 2
F
1
1
(CY) = 0 ?
CMA
0
0
0
0
1
1
1
0
0
0 1
C
1
1
(A) ← (A)
RAR
0
0
0
0
1
1
1
0
1
0 1
D
1
1
→ CY → A3A2A1A0
LGOP
0
0
1
0
0
0
0
0
1
0 4
1
1
1
Logic operation instruction XOR, OR, AND
Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2.
Rev.1.33
Mar 18, 2004
page 46 of 67
Skip condition
Carry flag CY
4282 Group
Continuous
–
description
–
Detailed description
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
and other LA instructions coded continuously are skipped.
–
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A when URS flag is cleared to “0.” These bits
7 to 0 are the ROM pattern in address (DR2 DR 1 DR0 A3 A2 A1 A0) specified by registers A and D in
page p.
0/1 Transfers bit 8 of ROM pattern is transferred to flag CY when URS flag is set to “1” (after the URSC
instruction is executed).
(One of stack is used when the TABP p instruction is executed.)
–
–
–
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
Overflow = 0
–
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
–
1
Sets (1) to carry flag CY.
–
0
Clears (0) to carry flag CY.
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
–
–
Stores the one‘s complement for register A‘s contents in register A.
–
–
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
–
Executes the logic operation selected by logic operation selection register LO between the contents of
register A and register E, and stores the result in register A.
Rev.1.33
Mar 18, 2004
page 47 of 67
4282 Group
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Type of
instructions
SB j
0
0
1
0
1
1
1
j1
j0
Hexadecimal
notation
0 5
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
C
Bit operation
+j
RB j
0
0
1
0
0
1
1
j1
j0
0 4
C
0
0
0
1
0
0
0
j1
j0
0 2
j
(Mj(DP)) ← 1
j = 0 to 3
1
1
+j
SZB j
Function
(Mj(DP)) ← 0
j = 0 to 3
1
1
(Mj(DP)) = 0 ?
Comparison
operation
j = 0 to 3
SEAM
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
SEA n
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
0
1
0
1
1
n3 n2 n1 n0
1
1
a6 a5 a4 a3 a2 a1 a0
n = 0 to 15
Ba
0 B n
1
8
a
1
1
(PCL) ← a6–a0
2
2
(PCH) ← p
(PCL) ← a6–a0
+a
BL p, a
0
0
0
1
1
p3 p2 p1 p0
0 3
p
1
1
a6 a5 a4 a3 a2 a1 a0
1 8
a
Branch operation
(Note)
+a
BA a
BLA p, a
0
0
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
0
0
0
0 1
1
1
0
0
0
1
0
0
0
0
0
0
1
0
a6 a5 a4 p3 p2 p1 p0
0 0
1 8
1
0
p
+a
Note: p is 0 to 7 for M34282M1, p is 0 to 15 for M34282M2/E2.
Rev.1.33
Mar 18, 2004
page 48 of 67
2
2
2
2
(PCL) ← (a6–a4, A3–A0)
(PCH) ← p
(PCL) ← (a6–a4, A3–A0)
(Note)
Skip condition
Carry flag CY
4282 Group
–
–
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
–
–
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
j = 0 to 3
Detailed description
of M(DP) is “0.”
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
(A) = n
n = 0 to 15
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
–
–
Branch within a page : Branches to address a in the identical page.
–
–
Branch out of a page : Branches to address a in page p.
–
–
Branch within a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in the identical page with register A.
–
Rev.1.33
–
Mar 18, 2004
Branch out of a page : Branches to address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the loworder 4 bits of the address a in page p with register A.
page 49 of 67
4282 Group
Mnemonic
Type of
instructions
BM a
D8 D7 D6 D5 D4 D3 D2 D1 D0
Hexadecimal
notation
1
1
0
a6 a5 a4 a3 a2 a1 a0
a
a
Number of
cycles
Instruction code
Parameter
Number of
words
MACHINE INSTRUCTIONS (CONTINUED)
1
1
Function
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
1
1
p3 p2 p1 p0
0 7
p
0
0
1
1
0
a6 a5 a4 a3 a2 a1 a0
1 a a
BMLA p, a 0
0
1
0 5
0
1
0
a6 a5 a4 p3 p2 p1 p0
1 a
p
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
0
1
0
0
0
0
(PCL) ← a6–a0
(Note)
2
2
(SK(SP)) ← (PC)
(SP) ← (SP) + 1
(PCH) ← p
Return operation
(PCL) ← (a6–a4, A3–A0)
(Note)
RT
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(SP) ← (SP) – 1
(PC) ← (SK(SP))
RTS
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(SP) ← (SP) – 1
(PC) ← (SK(SP))
T1AB
0
0
1
0
0
0
1
1
1
0 4 7
1
1
at timer 1 stop (V10=0)
(R17–R14) ← (B), (R13–R10) ← (A)
(T17–T14) ← (B), (T13–T10) ← (A)
Timer operation
at timer 1 operating (V10=1)
(R17–R14) ← (B), (R13–R10) ← (A)
TAB1
0
0
1
0
1
0
1
1
1
0 5 7
1
1
(B) ← (T17–T14)
(A) ← (T13–T10)
TV1A
0
0
1
0
1
1
0
1
1
0 5 B
1
1
(V12–V10) ← (A2–A0)
SNZT1
0
0
1
0
0
0
0
1
0
0 4 2
1
1
(T1F) = 1 ?
After skipping the next instruction
(T1F) ← 0
T2AB
0
1
0
0
0
1
0
0
0
0 8 8
1
1
(R2L7–R2L4) ← (B)
(R2L3–R2L0) ← (A)
(T27–T24) ← (B),
(T23–T20) ← (A)
Note : p is 0 to 7 for M34282M1, and p is 0 to 15 for M34282M2/E2.
Rev.1.33
Mar 18, 2004
page 50 of 67
Skip condition
Carry flag CY
4282 Group
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (a6 a5 a4 A3 A2 A1 A0) determined by replacing the
low-order 4 bits of address a in page p with register A.
–
–
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
–
–
At timer 1 stop (V10 = 0), transfers the contents of register A and register B to timer 1 and reload
register R1.
Detailed description
At timer 1 operating (V10 = 1), transfers the contents of register A and register B to reload register R1.
–
–
Transfers the contents of timer 1 to registers A and B.
–
–
(T1F) = 1
–
Transfers the contents of register A to registers V1.
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears (0) to T1F flag.
–
–
Transfers the contents of register A and register B to timer 2 and reload register R2L.
Rev.1.33
Mar 18, 2004
page 51 of 67
4282 Group
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
TAB2
0
0
1
0
0
0
0
0
0
0 4 0
1
1
(B) ← (T27–T24), (A) ← (T23–T20)
TV2A
0
0
1
0
1
1
0
1
0
0 5 A
1
1
(V23–V20) ← (A3–A0)
SNZT2
0
0
1
0
1
0
0
1
0
0 5 2
1
1
(T2F) = 1 ?
After skipping the next instruction
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Timer operation
Type of
instructions
Hexadecimal
notation
Function
(T2F) ← 0
T2HAB
0
1
0
0
0
1
0
0
1
0 8 9
1
1
(R2H7–R2H4) ← (B)
(R2H3–R2H0) ← (A)
T2R2L
0
0
1
0
1
0
0
1
1
0 5 3
1
1
(T27–T24) ← (R2L7–R2L4)
Input/Output operation
Carrier wave
control operation
(T23–T20) ← (R2L3–R2L0)
Rev.1.33
SCAR
0
1
0
0
0
0
1
1
1
0 8 7
1
1
(CAR) ← 1
RCAR
0
1
0
0
0
0
1
1
0
0 8 6
1
1
(CAR) ← 0
CLD
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 0
RD
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 7
SZD
0
0
0
1
0
0
1
0
0
0 2 4
2
2
(D(Y)) = 0 ?
(Y) = 4 to 7
0
0
0
1
0
1
0
1
1
0 2 B
OEA
0
1
0
0
0
0
1
0
0
0 8 4
1
1
(E1, E0) ← (A1, A0)
IAE
0
0
1
0
1
0
1
1
0
0 5 6
1
1
(A2–A0) ← (E2–E0)
OGA
0
1
0
0
0
0
0
0
0
0 8 0
1
1
(G) ← (A)
IAG
0
0
0
1
0
1
0
0
0
0 2 8
1
1
(A) ← (G)
Mar 18, 2004
page 52 of 67
Skip condition
Carry flag CY
4282 Group
–
–
Transfers the contents of timer 2 to registers A and B.
–
–
Transfers the contents of register A to registers V2.
(T2F) = 1
–
Skips the next instruction when the contents of T2F flag is “1.”
After skipping, clears (0) to T2F flag.
–
–
Transfers the contents of register A and register B to reload register R2H.
–
–
Transfers the contents of reload register R2L to timer 2.
–
–
Sets (1) to port CARR output flag (CAR).
–
–
Clears (0) to port CARR output flag (CAR).
–
–
Clears (0) to port D (high-impedance state).
–
–
Clears (0) to a bit of port D specified by register Y (high-impedance state).
–
–
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
(Y) = 4 to 7
–
Skips the next instruction when a bit of port D specified by register Y is “0.”
–
–
Outputs the contents of register A to port E.
–
–
Transfers the contents of port E to register A.
–
–
Outputs the contents of register A to port G.
–
–
Transfers the contents of port G to register A.
Rev.1.33
Mar 18, 2004
Detailed description
page 53 of 67
Number of
words
Number of
cycles
4282 Group
NOP
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
POF
0
0
0
0
0
1
1
0
1
0 0
D
1
1
RAM back-up
SNZP
0
0
0
0
0
0
0
1
1
0 0
3
1
1
(P) = 1 ?
CCK
0
0
1
0
1
1
0
0
1
0 5
9
1
1
STCK changes to f(XIN)
TLOA
0
0
1
0
1
1
0
0
0
0 5
8
1
1
(LO1, LO0) ← (A1, A0)
URSC
0
1
0
0
0
0
0
1
0
0 8
2
1
1
(URS) ← 1
TPU0A
0
1
0
0
0
1
1
1
1
0 8
F
1
1
(PU03–PU00) ← (A3–A0)
TPU1A
0
1
0
0
0
1
1
1
0
0 8
E
1
1
(PU13–PU10) ← (A3–A0)
WRST
0
0
0
0
0
1
1
1
1
0 0
F
1
1
(WDF1) ← 0
Instruction code
Parameter
Mnemonic
D8 D7 D6 D5 D4 D3 D2 D1 D0
Other operation
Type of
instructions
Rev.1.33
Mar 18, 2004
page 54 of 67
Hexadecimal
notation
Function
Skip condition
Carry flag CY
4282 Group
–
–
No operation
–
–
Puts the system in RAM back-up state.
(P) = 1
–
Skips the next instruction when P flag is “1.”
After skipping, P flag remains unchanged.
–
–
System clock (STCK) changes to f(XIN) from f(XIN)/8. Execute this CCK instruction at address 0 in page
0.
–
–
Transfers the contents of register A to the logic operation selection register LO.
–
–
Sets the most significant ROM code reference enable flag (URS) to “1.”
–
–
Transfers the contents of register A to register PU0.
–
–
Transfers the contents of register A to register PU1.
–
–
Initializes the watchdog timer flag (WDF1).
Rev.1.33
Mar 18, 2004
Detailed description
page 55 of 67
4282 Group
INSTRUCTION CODE TABLE
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111
D8–D4
D 3–
D0
Hex.
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10000 11000
10111 11111
10–17 18–1F
notation
0000
0
NOP
BLA
SZB
0
BL
TAB2 BMLA
XAM
0
BML
OGA TABP
0
A
0
LA
0
LXY
0,0
LXY
1,0
LXY
2,0
LXY
3,0
BM
B
0001
1
BA
CLD
SZB
1
BL
LGOP
XAM
1
BML
TABP
1
A
1
LA
1
LXY
0,1
LXY
1,1
LXY
2,1
LXY
3,1
BM
B
0010
2
SZB
2
BL
SNZT1 SNZT2
XAM
2
BML
URSC TABP
2
A
2
LA
2
LXY
0,2
LXY
1,2
LXY
2,2
LXY
3,2
BM
B
0011
3
INY
SZB
3
BL
T2R2L XAM
BML
TABP
3
A
3
LA
3
LXY
0,3
LXY
1,3
LXY
2,3
LXY
3,3
BM
B
0100
4
RD
SZD
BL
RT
TAM
0
BML
OEA TABP
4
A
4
LA
4
LXY
0,4
LXY
1,4
LXY
2,4
LXY
3,4
BM
B
0101
5
SD
SEAn
BL
RTS
TAM
1
BML
TABP
5
A
5
LA
5
LXY
0,5
LXY
1,5
LXY
2,5
LXY
3,5
BM
B
0110
6
RC
SEAM
BL
TAM
2
BML RCAR
TABP
6
A
6
LA
6
LXY
0,6
LXY
1,6
LXY
2,6
LXY
3,6
BM
B
0111
7
SC
T1AB TAB1
TAM
3
BML SCAR
TABP
7
A
7
LA
7
LXY
0,7
LXY
1,7
LXY
2,7
LXY
3,7
BM
B
1000
8
IAG
BL*
TLOA
XAMI
0
BML* T2AB
TABP
8*
A
8
LA
8
LXY
0,8
LXY
1,8
LXY
2,8
LXY
3,8
BM
B
1001
9
TDA
BL*
CCK
XAMI
1
BML* T2HAB
TABP
9*
A
9
LA
9
LXY
0,9
LXY
1,9
LXY
2,9
LXY
3,9
BM
B
1010
A
AM
BL*
TV2A
XAMI
2
BML*
TABP
10*
A
10
LA
10
LXY
0,10
LXY
1,10
LXY
2,10
LXY
3,10
BM
B
1011
B
AMC
BL*
TV1A
XAMI
3
BML*
TABP
11*
A
11
LA
11
LXY
011
LXY
1,11
LXY
2,11
LXY
3,11
BM
B
1100
C
TYA
CMA
BL*
RB
0
SB
0
XAMD
BML*
0
TABP
12*
A
12
LA
12
LXY
0,12
LXY
1,12
LXY
2,12
LXY
3,12
BM
B
1101
D
POF
RAR
BL*
RB
1
SB
1
XAMD
BML*
1
TABP
13*
A
13
LA
13
LXY
0,13
LXY
1,13
LXY
2,13
LXY
3,13
BM
B
1110
E
TBA
TAB
BL*
RB
2
SB
2
XAMD BML* TPU1A TABP
2
14*
A
14
LA
14
LXY
0,14
LXY
1,14
LXY
2,14
LXY
3,14
BM
B
1111
F
BL*
RB
3
SB
3
TABP
XAMD
BML* TPU0A
15*
3
A
15
LA
15
LXY
0,15
LXY
1,15
LXY
2,15
LXY
3,15
BM
B
SNZP
DEY
BL
TEAB TABE
WRST TAY
SZC
3
IAE
The above table shows the relationship between machine language codes and machine language instructions. D3–D0
show the low-order 4 bits of the machine language code, and D8–D4 show the high-order 5 bits of the machine language
code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word
instructions, but only the first word of each instruction is shown. Do not use the code marked “–.”
The codes for the second word of a two-word instruction are described below.
BL
BML
BA
BLA
BMLA
SEA
SZD
Rev.1.33
The second word
1 1aaa aaaa
1 0aaa aaaa
1 1aaa aaaa
1 1aaa pppp
1 0aaa pppp
0 1011 nnnn
0 0010 1011
Mar 18, 2004
page 56 of 67
* cannot be used in the M34282M1.
4282 Group
REGISTER STRUCTURE
Timer control register V1
V12
at reset : 0002
Carrier wave output auto-control bit
V11
Timer 1 count source selection bit
V10
Timer 1 control bit
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
0
1
Carrier wave output (CARRY)
Bit 5 of watchdog timer (WDT)
0
Stop (Timer 1 state retained)
1
Operating
Timer control register V2
V23
Carrier wave “H” interval expansion bit
V22
Carrier wave generation function control bit
V21
Timer 2 count source selection bit
at reset : 00002
Timer 2 control bit
V20
Logic operation selection bits
To expand “H” interval is invalid
To expand “H” interval is valid (when V22=1 selected)
0
Carrier wave generation function invalid
1
0
Carrier wave generation function valid
f(XIN)
1
f(XIN)/2
0
1
Stop (Timer 2 state retained)
Operating
at reset : 002
PU02
at reset : 00002
Ports G2, G3 pull-down transistor control
0
bit
Ports G0, G1 pull-down transistor control
1
bit
PU01
Port E1 pull-down transistor control bit
PU00
Port E0 pull-down transistor control bit
0
1
0
1
0
1
Pull-down control register PU1
PU13
Port D7 pull-down transistor control bit
PU12
Port D6 pull-down transistor control bit
PU11
Port D5 pull-down transistor control bit
PU10
Port D4 pull-down transistor control bit
Rev.1.33
Mar 18, 2004
page 57 of 67
W
W
0 AND operation (AND)
1 Not available
Pull-down control register PU0
PU03
at RAM back-up : 002
W
LO1 LO0
Logic operation function
0
0 Exclusive logic OR operation (XOR)
0
1 OR operation (OR)
1
1
LO0
at RAM back-up : 00002
0
1
Logic operation selection register LO
LO1
at RAM back-up : 0002
0
1
0
1
0
1
W
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
at reset : 00002
0
1
at RAM back-up : state retained
at RAM back-up : state retained
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
Pull-down transistor OFF, key-on wakeup invalid
Pull-down transistor ON, key-on wakeup valid
W
4282 Group
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
VI
VO
Pd
Conditions
Parameter
Unit
V
Ratings
Supply voltage
Input voltage
–0.3 to 5
–0.3 to VDD+0.3
V
Output voltage
–0.3 to VDD+0.3
300
V
mW
–20 to 85
°C
–40 to 125
°C
Topr
Power dissipation
Operating temperature range
Tstg
Storage temperature range
Ta = 25 °C
RECOMMENDED OPERATING CONDITIONS
(Ta = –20 °C to 85 °C, VDD = 1.8 V to 3.6 V, unless otherwise noted)
Symbol
VDD
VRAM
VSS
VIH
VIH
VIL
Parameter
Conditions
Limits
Min.
Typ.
1.8
1.1
Supply voltage
RAM back-up voltage (at RAM back-up mode)
“H” level input voltage Ports D4–D7, E, G
“H” level input voltage XIN
“L” level input voltage Ports D4–D7, E, G
“L” level input voltage XIN
IOH(peak) “H” level peak output current Ports D, E1, G
IOH(peak) “H” level peak output current Port E0
IOH(peak) “H” level peak output current CARR
IOL(peak) “L” level peak output current CARR
IOH(avg) “H” level average output current Ports D, E1, G
IOH(avg) “H” level average output current Port E0
IOH(avg) “H” level average output current CARR
VDD = 3.0 V
0.7VDD
0.8VDD
TPON
V
V
V
V
VDD = 3.0 V
–4
mA
VDD = 3.0 V
VDD = 3.0 V
–24
–20
mA
mA
VDD = 3.0 V
4
VDD = 3.0 V
VDD = 3.0 V
–2
–12
mA
mA
VDD = 3.0 V
–10
VDD = 3.0 V
System clock frequency when STCK = f(XIN)/8 selected Ceramic resonance
when STCK = f(XIN) selected Ceramic resonance
Voltage drop detection circuit detection voltage
Voltage drop detection circuit low voltage
When supply voltage passes
determination time
the detected voltage at ±50V/s.
Power-on reset circuit valid power source rising time
VDD = 0 to 2.2 V
Mar 18, 2004
VDD
V
Note: The average output current ratings are the average current value during 100 ms.
Rev.1.33
V
VDD
VDD = 3.0 V
VDD = 3.0 V
Ta=25 °C
TDET
page 58 of 67
V
0.2VDD
0.2VDD
VDD = 3.0 V
0
0
IOL(avg) “L” level average output current CARR
VDET
Unit
3.6
0
Supply voltage
VIL
f(XIN)
Max.
3.6
2
4
500
1.10
1.40
1.50
0.2
1.80
1.56
mA
mA
mA
MHz
kHz
V
1.2
ms
1
ms
4282 Group
ELECTRICAL CHARACTERISTICS
(Ta = –20 °C to 85 °C, VDD = 3 V, unless otherwise noted)
Symbol
Parameter
Test conditions
VOL
VOL
“L” level output voltage Port CARR
“L” level output voltage XOUT
VOH
“H” level output voltage Ports D, E1, G
VOH
VOH
“H” level output voltage Port E0
“H” level output voltage CARR
VOH
“H” level output voltage XOUT
IIL
IIH
“L” level input current Ports D4–D7, E, G
“H” level input current Ports E0, E1
IOZ
IDD
Output current at off-state Ports D, E0, E1, G VO = VSS
Supply current (when operating)
f(XIN) = 4.0 MHz
f(XIN) = 500 kHz
Limits
Min.
IOL = 2 mA
Pull-down resistor value Ports D4–D7, E, G
ROSC
Feedback resistor value between XIN–XOUT
0.9
0.9
Machine cycle
Pin name
System clock
STCK
Ports D, E, G output
D0–D7,E0,E1
G0–G3
Ports D, E, G input
Rev.1.33
Mar 18, 2004
D4–D7
E0–E2
G0–G3
page 59 of 67
Unit
V
2.1
V
V
IOH = –12 mA
1.5
V
IOH = –10 mA
IOH = –0.2 mA
1.0
2.1
V
V
VI = VSS
VI = VDD
Pull-down transistor in off-state
400
250
1
Ta = 25 °C
VDD = 3 V, VI = 3 V
75
700
BASIC TIMING DIAGRAM
Parameter
Max.
IOL = 0.2 mA
IOH = –2 mA
Supply current (at RAM back-up)
RPH
Typ.
Mi
Mi+1
0.1
150
–1
1
µA
µA
–1
800
µA
µA
µA
µA
µA
kΩ
kΩ
500
3
0.5
300
3200
4282 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4282 Group has the
One Time PROM versions whose PROMs can only be written to
and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM versions, but it has PROM mode that enables writing
to built-in PROM.
Table 10 Product of built-in PROM version
PROM size
Part number
(✕ 9 bits)
M34282E2GP
2048 words
Table 10 shows the product of built-in PROM version. Figure 29
and 30 show the pin configurations of built-in PROM versions.
The One Time PROM version has pin-compatibility with the mask
ROM version.
RAM size
(✕ 4 bits)
Package
64 words
20P2E/F-A
ROM type
One Time PROM [shipped in blank]
PIN CONFIGURATION (TOP VIEW)
1
20
VDD
E2
2
19
CARR
E1
3
18
D0
XIN
4
17
D1
XOUT
5
16
D2
E0
6
15
D3
G0
7
14
D4
G1
8
13
D5
G2
9
12
D6
G3
10
11
D7
M34282E2GP
VSS
Outline 20P2E/F-A
Fig. 29 Pin configuration of built-in PROM version
Rev.1.33
Mar 18, 2004
page 60 of 67
4282 Group
(1) PROM mode (serial input/output)
The M34282E2GP has a PROM mode in addition to a normal
operation mode. It has a function to serially input/output the
command codes, addresses, and data required for operation
(e.g., read and program) on the built-in PROM using only a
few pins. This mode can be selected by setting pins SDA (serial
data input/output), SCLK (serial clock input), PGM and VPP to
“H” after connecting wires as shown in Figure 30 and powering
on the VDD pin, and then applying 12.5V to the VPP pin.
In the PROM mode, three types of software commands (read,
program, and program verify) can be used. Clock-synchronous
serial I/O is used, beginning from the LSB (LSB first).
As for the Development tools, refer to the Developer Tools
(http://www.renesas.com/en/tools) of “Renesas Technology
Corp.” Homepage.
PIN CONFIGURATION (TOP VIEW)
Vss
VSS
Vpp
20 VDD
19 CARR
E1 3
18 D0
4
XOUT 5
M34282E2GP
E2 2
XIN
*
1
VDD
17 D1
16 D2
SCLK
E0 6
SDA
G0 7
PGM
G1 8
13 D5
G2 9
12 D6
G3 10
11 D7
15 D3
14 D4
Outline 20P2E/F-A
* : connected to the ceramic resonance circuit.
Note: The state of disconnected pins are the same as that at reset.
Fig. 30 Pin configuration of built-in PROM version (continued)
Rev.1.33
Mar 18, 2004
page 61 of 67
4282 Group
In the first transfer, the command code is input. Then, address
input or data input/output is performed according to the
contents of the command code. Table 11 shows the software
command used in the PROM mode. The following explains
each software command.
(2) Functional outline
In the PROM mode, data is transferred with the clocksynchronous serial input/output. The input data is read through
the SDA pin into the internal circuit synchronously with the
rising edge of the serial clock pulse. The output data is output
from the SDA pin synchronously with the falling edge of the
serial clock pulse. Data is transferred in units of 8 bits.
Table 11 Software command
Number of transfer
First command
Command
Read
Third
Fourth
Read address L (input)
Read address H (input)
Program address L (input)
Program address H (input)
Read data L (output)
Program data L (input)
Program address H (input)
Program data L (input)
2516
3516
Program address L (input)
Program
Program verify
Number of transfer
Fifth
Command
Read
Second
code input
1516
Sixth
Seventh
Verify data L (output)
Verify data H (output)
Read data H (output)
Program
Program verify
Program data H (input)
Program data H (input)
(3) Read
Input the command code 1516 in the first transfer. Proceed
and input the low-order 8 bits and the high-order 8 bits of the
address and pull the PGM pin to “L.” When this is done, the
contents of input address is read and stored into the internal
data latch.
tCH
When the PGM pin is released back to “H” and serial clock is
input to the SCLK pin, the low-order 8 bits and high-order 8
bits of read data which have been stored into the data latch,
are serially output from the SDA pin.
tCH
tCH
SCLK
A0
SDA
A7
Command code input (1516)
D0
A8A9 A10
D7
0 0 0 0 0
1 0 1 0 1 0 0 0
Read address input (L)
Read address input (H)
tCR
D8
0 0 0 0 0 0 0
tWR
tRC
Read data output (L)
Read data output (H)
PGM
Read
Note: When outputting the read data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).
Fig. 31 Timing at reading
Rev.1.33
Mar 18, 2004
page 62 of 67
4282 Group
(4) Program
Input command code 2516 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
tCH
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address.
tCH
tCH
tCH
SCLK
A0
SDA
D0
A8A9 A10
A7
D8
D7
0 0 0 0 0 0 0
0 0 0 0 0
1 0 1 0 0 1 0 0
Commanf code input (2516 )Program address input (L) Program address input (H)
Program data input (L) Program data input (H)
tCP
tWP
PGM
Program
Fig. 32 Timing at programming
and verified and stored into the internal data latch. When the
PGM pin is released back to “H” and serial clock is input to the
SCLK pin, the verify data that has been stored into the data
latch is serially output from the SDA pin.
(5) Program verify
Input command code 3516 in the first transfer. Proceed and
input the low-order 8 bits and high-order 8 bits of the address
and the low-order 8 bits and high-order 8 bits of program data,
and pull the PGM pin to “L.” When this is done, the program
data is programmed to the specified address. Then, when the
PGM pin is pulled to “L” again after it is released back to “H,”
the address programmed with the program command is read
tCH
tCH
tCH
tCH
SCLK
A0
SDA
A8 A9 A10
A7
D0
D7
0 0 0 0 0
1 0 1 0 1 1 0 0
Command code input (3516)
Program address input (L)
Program address input (H)
D8
0 0 0 0 0 0 0
Program data input (L)
Program data input (H)
tCP
tWP
PGM
Program
tCH
SCLK
D0
D7
SDA
D8
0 0 0 0 0 0 0
tCR
tWR
tRC
Verify data output (L)
Verify data output (H)
PGM
Verify
Note: When outputting the verify data, the SDA pin is switched for output at the first falling of the serial clock. The SDA pin is
placed in the high-impedance state during the th(C–E) period after the last rising edge of the serial clock (at the 16th bit).
Fig. 33 Timing at program verifying
Rev.1.33
Mar 18, 2004
page 63 of 67
4282 Group
PROGRAM ALGORITHM FLOW CHART
START
VDD = 4V,VPP = 4V
VDD = 4V,VPP = 12.5V
ADRS = first location
X=0
WRITE PROGRAM-VERIFY
COMMAND
3516
WRITE PROGRAM
DATA
DIN
PROGRAM ONE PULSE
OF 0.2ms
X=X+1
X = 25?
YES
NO
FAIL
VERIFY
BYTE?
PASS
PASS
WRITE PROGRAM
COMMAND
2516
WRITE PROGRAM
DATA
DIN
VERIFY
BYTE?
FAIL
PROGRAM PULSE OF
0.2Xms DURATION
INC ADRS
NO
LAST
ADRS?
YES
READ COMMAND
VERIFY
ALL BYTE?
PASS
DEVICE
PASSED
Rev.1.33
Mar 18, 2004
page 64 of 67
FAIL
1516
DEVICE
FAILED
4282 Group
TIMING REQUIREMENT CONDITION AND SWITCHING CHARACTERISTICS
(Ta = 25 °C, VDD = 4.0 V, VPP = 12.5 V)
Symbol
Limits
Min. Max.
Parameter
tCH
Serial transfer width time
2.0
tCR
tWR
Read wait time after transfer
Read pulse width
2.0
500
tRC
Transfer wait time after read
2.0
tCP
tWP
Program wait time after transfer
Program pulse width
2.0
0.19
0.21
tOWP
Added program pulse width
0.19
5.25
tC(CK)
tW(CKH)
SCLK input cycle time
SCLK “H” pulse width
1.0
450
tW(CKL)
SCLK “L” pulse width
450
SCLK rising time
SCLK falling time
40
40
td(C–Q)
SDA output delay time
0
th(C–Q)
th(C–E)
SDA output hold time
SDA output hold time (only for 16th bit)
tsu(D–C)
SDA input set-up time
60
th(C–D)
SDA input hold time
180
tr(CK)
tf(CK)
Unit
µs
µs
ns
µs
µs
ms
ms
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
180
0
100
TIMING DIAGRAM
tf(CK)
tC(CK)
tW(CKL)
tW(CKH)
tr(CK)
SCLK
td(C-Q)
th(C-E)
th(C-Q)
SDA output
tsu(D-C) th(C-D)
SDA input
Measurement condition
Output timing voltage: VOL = 0.8 V, VOH = 2.0 V
Input timing voltage: VIL = 0.2 VDD, VIH = 0.8 VDD
Rev.1.33
Mar 18, 2004
page 65 of 67
4282 Group
(6) Notes on handling
➀ A high-voltage is used for writing. Take care that overvoltage
is not applied. Take care especially at turning on the power.
➁ For the One Time PROM version, Renesas corp. does not
perform PROM writing test and screening in the assembly
process and following processes. In order to improve
reliability after writing, performing writing and test according
to the flow shown in Figure 34 before using is
recommended.
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 34 Flow of writing and test of the product shipped in
blank
Rev.1.33
Mar 18, 2004
page 66 of 67
4282 Group
PACKAGE OUTLINE
20P2E/F-A
Plastic 20pin 225mil SSOP
EIAJ Package Code
SSOP20-P-225-0.65
Weight(g)
0.08
JEDEC Code
–
e
b2
11
E
HE
e1
I2
20
Lead Material
Alloy 42/Cu Alloy
F
Recommended Mount Pad
Symbol
1
10
A
D
G
b
e
x
A2
M
A1
L
L1
y
c
z
Z1
Rev.1.33
Mar 18, 2004
Detail G
page 67 of 67
Detail F
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
x
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
1.45
–
–
0.2
0.1
0
–
1.15
–
0.32
0.22
0.17
0.2
0.15
0.13
6.6
6.5
6.4
4.5
4.4
4.3
–
0.65
–
6.6
6.4
6.2
0.7
0.5
0.3
–
1.0
–
–
0.325
–
–
–
0.475
–
–
0.13
0.1
–
–
0°
–
10°
–
0.35
–
–
5.8
–
–
1.0
–
4282 Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Jul. 23, 2003
–
1.10 Jul. 25, 2000
12
13
22
1.20 Aug. 23, 2000
7
8
14
18
21
1.30 Jul. 03, 2001 All pages
1
9
21
61
1.31 Feb. 12, 2003
1.32 Feb. 20, 2004
1.33 Mar. 18, 2004
17
18
21
22
61
12
18
22
57
18
22
First edition issued
(2) Precautions revised.
(3) Timer 1, (4) Timer 2 revised.
➂ Timer revised
Character fonts errors revised.
Character fonts errors revised.
Character fonts errors revised.
Character fonts errors revised.
Character fonts errors revised.
“PRELIMINARY Notice: This is not a final specification. Some parametric limits are
subject to change.” eliminated.
Product name table; “Under development” eliminated.
48 words ✕ 4 bits (128 bits) → 48 words ✕ 4 bits (192 bits)
ROM ORDERING METHOD revised.
“Mitsubishi Microcomputer Development Support Tools” Hompage
(http://www.tool-spt.mesc.co.jp/index_e.htm)
→ (http://www.tool-spt.maec.co.jp/index_e.htm)
(2) Note on power-on reset added.
Note on voltage drop detection circuit added.
ROM ORDERING METHOD revised.
Note on power-on reset and Note on voltage drop detection circuit added.
Introducing development tools revised.
Register V2 revised.
Fig.22 revised.
Fig.28 revised.
Register V2 revised.
Note on voltage drop detection circuit revised.
Note on voltage drop detection circuit revised.
(1/1)
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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