Preliminary Data Sheet μ PA2811T1L R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 MOS FIELD EFFECT TRANSISTOR Description The μ PA2811T1L is P-channel MOS Field Effect Transistor designed for DC/DC converter and power management applications of portable equipment. Features • VDSS −30 V (TA = 25°C) • Low on-state resistance ⎯ RDS(on) = 15 mΩ MAX. (VGS = −10 V, ID = −19 A) • 4.5 V Gate-drive available • Built-in gate protection diode • Small & thin type surface mount package with heat spreader (8-pin HVSON) • Halogen free and RoHS compliant Ordering Information Part No. μ PA2811T1L-E1-AY ∗1 μ PA2811T1L-E2-AY ∗1 LEAD PLATING Pure Sn PACKING Tape 3000 p/reel Package 8-pin HVSON (3333) typ. 0.028 g Note: ∗1. Pb-free (This product does not contain Pb in external electrode.) Absolute Maximum Ratings (TA = 25°C) Item Drain to Source Voltage (VGS = 0 V) Gate to Source Voltage (VDS = 0 V) Drain Current (DC) (TC = 25°C) Drain Current (pulse) ∗1 Total Power Dissipation ∗2 Total Power Dissipation (PW = 10 sec) ∗2 Total Power Dissipation (TC = 25°C) Channel Temperature Storage Temperature Single Avalanche Current ∗3 Single Avalanche Energy ∗3 Symbol VDSS VGSS ID(DC) ID(pulse) PT1 PT2 PT3 Tch Tstg IAS EAS Ratings −30 m25 m19 m76 1.5 3.8 52 150 −55 to +150 −19 36 Unit V V A A W W W °C °C A mJ Thermal Resistance Channel to Ambient Thermal Resistance ∗2 Channel to Case (Drain) Thermal Resistance Rth(ch-A) Rth(ch-C) 83.3 2.4 °C/W °C/W Notes: ∗1. PW ≤ 10 μs, Duty Cycle ≤ 1% ∗ 2. Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt ∗ 3. Starting Tch = 25°C, VDD = −15 V, RG = 25 Ω, VGS = −20 → 0 V, L = 100 μH R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 Page 1 of 6 Chapter Title Electrical Characteristics (TA = 25°C) Item Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance ∗1 Drain to Source On-state Resistance ∗1 Symbol IDSS IGSS VGS(off) | yfs | RDS(on)1 Min Max −1 m10 −2.5 12 20 1360 310 240 10 14 100 70 30 5 10 0.9 31 27 15 28 −1.0 7.0 RDS(on)2 Ciss Coss Crss td(on) tr td(off) tf QG QGS QGD VF(S-D) trr Qrr Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge Body Diode Forward Voltage ∗1 Reverse Recovery Time Reverse Recovery Charge Typ Unit μA μA V S mΩ mΩ pF pF pF ns ns ns ns nC nC nC V ns nC Test Conditions VDS = −30 V, VGS = 0 V VGS = m20 V, VDS = 0 V VDS = −10 V, ID = −1 mA VDS = −10 V, ID = −9.5 A VGS = −10 V, ID = −19 A VGS = −4.5 V, ID = −9.5 A VDS = −10 V, VGS = 0 V, f = 1 MHz VDD = −15 V, ID = −9.5 A, VGS = −10 V, RG = 10 Ω VDD = −24 V, VGS = −10 V, ID = −19 A IF = 19 A, VGS = 0 V IF = 19 A, VGS = 0 V, di/dt = 100 A/μs Note: ∗1. Pulsed TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL 50 Ω PG. VGS = −20 → 0 V VDD RG PG. VGS(−) VGS Wave Form 0 VGS 10% 90% VDD VDS(−) − IAS BVDSS VDS ID VGS(−) 0 VDS Wave Form τ VDD Starting Tch τ = 1 μs Duty Cycle ≤ 1% VDS 90% 90% 10% 10% 0 td(on) tr td(off) ton tf toff TEST CIRCUIT 3 GATE CHARGE D.U.T. PG. IG = −2 mA RL 50 Ω VDD R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 Page 2 of 6 Chapter Title Typical Characteristics (TA = 25°C) FORWARD BIAS SAFE OPERATING AREA DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA -1000 100 ID - Drain Current - A dT - Percentage of Rated Power - % 120 80 60 40 ID(pulse) = −76 A -100 1 ms PW = 200 μs 100 μs ID(DC) = −19 A -10 o S( d it e ) Lim 0 V 1i =− S n) RD G (V 100 ms Power Dissipation Limited -1 20 TC = 25°C Single Pulse 0 0 25 50 75 100 125 150 -0.1 -0.1 175 TC - Case Temperature - °C -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W 1000 Rth(ch-A) = 83.3°C/W 100 10 Rth(ch-C) = 2.4°C/W 1 0.1 Single Pulse Rth(ch-A): Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt 0.01 100 μ 1m 10 m 100 m 1 PW - Pulse Width - s 10 DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE -100 V GS = −10 V -70 -60 ID - Drain Current - A ID - Drain Current - A -100 -10 -80 1000 FORWARD TRANSFER CHARACTERISTICS Pulsed -90 100 −4.5 V -50 -40 -30 -20 -10 0 Tch = −55°C −25°C 25°C 75°C 125°C 150°C -1 -0.1 -0.01 -0.001 V DS = -10 V Pulsed -0.0001 0 -0.5 -1 -1.5 -2 -2.5 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 VDS - Drain to Source Voltage - V VGS - Gate to Source Voltage - V R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 Page 3 of 6 Chapter Title GATE CUT-OFF VOLTAGE vs. CHANNEL FORWARD TRANSFER ADMITTANCE vs. DRAIN TEMPERATURE CURRENT | yfs | - Forward Transfer Admittance - S -2.0 -1.5 -1.0 -0.5 Pulsed VDS = -10 V, ID = -1 mA 0 RDS(on) - Drain to Source On-state Resistance - mΩ -75 -25 25 75 125 175 100 Tch = -55°C -25°C 25°C 75°C 125°C 150°C 10 1 0.1 0.01 -0.001 Pulsed V DS = -10 V -0.01 -0.1 -1 -10 -100 Tch - Channel Temperature - °C ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT GATE TO SOURCE VOLTAGE 50 Pulsed 40 30 20 V GS = -4.5 V -10 V 10 0 -0.1 -1 -10 -100 ID - Drain Current - A RDS(on) - Drain to Source On-state Resistance - mΩ VGS(off) - Gate Cut-off Voltage - V -2.5 40 Pulsed 30 20 ID = -19 A 10 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 VGS - Gate to Source Voltage - V CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE DRAIN TO SOURCE ON-STATE RESISTANCE vs. 10000 30 25 Ciss, Coss, Crss - Capacitance - pF RDS(on) - Drain to Source On-state Resistance - mΩ CHANNEL TEMPERATURE VGS = -4.5 V ID = -9.5 A 20 15 -10 V, -19 A 10 5 Pulsed 0 -75 -25 25 75 125 Tch - Channel Temperature - °C R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 175 Ciss 1000 Coss Crss 100 10 -0.1 VGS = 0 V f = 1 MHz -1 -10 -100 VDS - Drain to Source Voltage - V Page 4 of 6 Chapter Title DYNAMIC INPUT/OUTPUT CHARACTERISTICS -12 VGS VDD = -24 V -15 V -25 -10 -6 V -20 -8 -15 -6 -10 -4 -5 -2 ID = -19 A 0 0 0 5 10 15 20 QG - Gate Charge - nC R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 25 30 100 IF - Diode Forward Current - A VDS VGS - Gate to Source Voltage - V -30 VDS - Drain to Source Voltage - V SOURCE TO DRAIN DIODE FORWARD VOLTAGE -10 V 10 -4.5 V VGS = 0 V 1 0.1 Pulsed 0.01 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VF(S-D) - Source to Drain Voltage - V Page 5 of 6 Chapter Title Package Drawings (Unit: mm) 8 7 6 5 4 3.3±0.15 0.22±0.05 0.9±0.05 0.10 S 0 +0.05 –0 3.0±0.1 0.10 M 0.32±0.05 3 3.3±0.15 1 2 3.15±0.1 0.65 8-pin HVSON (3333) 0.35 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain 2.34±0.1 0.2 0.4±0.1 0.4±0.1 1.75±0.1 Equivalent Circuit Drain Body Diode Gate Gate Protection Diode Remark Source The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. R07DS0191EJ0100 Rev.1.00 Jan 11, 2011 Page 6 of 6 μ PA2811T1L Data Sheet Revision History Rev. Date Page 1.00 Jan 11, 2011 − Description Summary First Edition Issued All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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