RENESAS NP75P04YLG-E2-AY

Preliminary Data Sheet
NP75P04YLG
R07DS0183EJ0200
Rev.2.00
Mar 16, 2011
MOS FIELD EFFECT TRANSISTOR
Description
The NP75P04YLG is P-channel MOS Field Effect Transistor designed for high current switching applications.
Features
• Low on-state resistance
⎯ RDS(on) = 9.7 mΩ MAX. (VGS = −10 V, ID = −37.5 A)
⎯ RDS(on) = 14 mΩ MAX. (VGS = −5 V, ID = −37.5 A)
• Logic level drive type
• Gate to Source ESD protection diode built in
• Designed for automotive application and AEC-Q101 qualified
Ordering Information
Part No.
NP75P04YLG -E1-AY ∗1
LEAD PLATING
Pure Sn (Tin)
PACKING
Tape 2500 p/reel
NP75P04YLG -E2-AY ∗1
Package
8-pin HSON, Taping (E1 type)
8-pin HSON, Taping (E2 type)
∗
Note: 1. Pb-free (This product does not contain Pb in the external electrode.)
Absolute Maximum Ratings (TA = 25°C)
<R>
<R>
Item
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) ∗1
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C) ∗2
Channel Temperature
Storage Temperature
Single Avalanche Current ∗3
Single Avalanche Energy ∗3
Symbol
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
PT2
Tch
Tstg
IAS
EAS
Ratings
−40
m20
m75
m225
138
1.0
175
−55 to +175
35
123
Unit
V
V
A
A
W
W
°C
°C
A
mJ
Thermal Resistance
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance ∗2
Rth(ch-C)
Rth(ch-A)
1.09
150
°C/W
°C/W
Notes: ∗1. TC = 25°C, PW ≤ 10 μs, Duty Cycle ≤ 1%
∗
2. Mounted on glass epoxy substrate of 40 mm x 40 mm x 0.8 mmt
*3. Starting Tch = 25°C, VDD = −20 V, RG = 25 Ω, L = 100 μH, VGS = −20 → 0 V
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
Page 1 of 6
NP75P04YLG
Chapter Title
Electrical Characteristics (TA = 25°C)
Item
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ∗1
Symbol
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)1
Drain to Source On-state
Resistance ∗1
Min
Typ
−1.0
31
−1.7
63
7.7
9.3
3200
460
250
12
11
320
180
91
14
26
1.02
43
57
RDS(on)2
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ∗1
Reverse Recovery Time
Reverse Recovery Charge
Max
−1
m10
−2.5
9.7
14
4800
600
450
24
27
640
440
140
1.5
Unit
μA
μA
V
S
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
Test Conditions
VDS = −40 V, VGS = 0 V
VGS = m20 V, VDS = 0 V
VDS = VGS, ID = −250 μ A
VDS = −5 V, ID = −37.5 A
VGS = −10 V, ID = −37.5 A
VGS = −5 V, ID = −37.5 A
VDS = −25 V,
VGS = 0 V,
f = 1 MHz
VDD = −20 V, ID = −37.5 A,
VGS = −10 V,
RG = 0 Ω
VDD = −32 V,
VGS = −10 V,
ID = −75 A
IF = −75 A, VGS = 0 V
IF = −75 A, VGS = 0 V,
di/dt = −100 A/μ s
Note: ∗1. Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
PG.
VGS = −20 → 0 V
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
50 Ω
VDD
VGS(−)
RL
Wave Form
RG
PG.
VGS
0
VGS
10%
90%
VDD
VDS(−)
90%
BVDSS
IAS
90%
VDS
VGS(−)
0
VDS
10%
0
10%
Wave Form
VDS
ID
τ
VDD
Starting Tch
τ = 1 μs
Duty Cycle ≤ 1%
td(on)
tr
ton
td(off)
tf
toff
TEST CIRCUIT 3 GATE CHARGE
PG.
D.U.T.
IG = −2 mA
RL
50 Ω
VDD
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
Page 2 of 6
NP75P04YLG
Chapter Title
DERATING FACTOR OF FORWARD BIAS SAFE
TOTAL POWER DISSIPATION vs.
OPERATING AREA
CASE TEMPERATURE
160
100
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
Typical Characteristics (TA = 25°C)
80
60
40
20
140
120
100
80
60
40
20
0
0
0
25
50
75
100
125
150
175
0
25
TC - Case Temperature - °C
50
75
100
125
150
175
TC - Case Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
-100
ID(pulse)
d
ite
Lim V)
)
0
on
1
(
−
S
RD S =
(VG
PW
=1
00
μs
s
1m
-10
Power Dissipation Limited
ms
10
ID - Drain Current - A
-1000
-1
Tc=25℃
Single Pulse
-0.1
-0.1
-1
-10
-100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
rth(t) - Transient Thermal Resistance - °C/W
1000
Rth(ch-A): 150°C/W
100
10
Rth(ch-C): 1.09°C/W
1
0.1
Single pulse
Mounted on glass epoxy substrate of 40 mm x 40 mm x 0.8 mmt
0.01
100 μ
1m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
Page 3 of 6
NP75P04YLG
Chapter Title
DRAIN CURRENT vs.
FORWARD TRANSFER CHARACTERISTICS
DRAIN TO SOURCE VOLTAGE
-1000
-300
-100
V GS = −10 V
-200
ID - Drain Current - A
ID - Drain Current - A
-250
−5 V
-150
-100
-50
TA = −55°C
−25°C
25°C
75°C
-10
125°C
150°C
175°C
-1
-0.1
-0.01
V DS = −10 V
Pulsed
Pulsed
0
-0.001
0
-1
-2
-3
-4
-5
-6
-7
-8
0
-1
-4
-5
GATE TO SOURCE THRESHOLD VOLTAGE
FORWARD TRANSFER ADMITTANCE vs. DRAIN
vs. CHANNEL TEMPERATURE
CURRENT
-2.5
V DS = V GS
ID = −250 μA
-2
-1.5
-1
-0.5
0
-100
-50
0
50
100
150
200
100
TA = −55°C
−25°C
25°C
75°C
125°C
150°C
175°C
10
V DS = −5 V
Pulsed
1
-0.1
-1
Tch - Channel Temperature - °C
-10
-100
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
GATE TO SOURCE VOLTAGE
35
Pulsed
30
25
20
15
10
V GS = −5 V
−10 V
5
0
-0.1
-1
-10
-100
ID - Drain Current - A
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
-1000
RDS(on) - Drain to Source On-state Resistance - mΩ
RDS(on) - Drain to Source On-state Resistance - mΩ
-3
VGS - Gate to Source Voltage - V
| yfs | - Forward Transfer Admittance - S
VGS(th) - Gate to Source Threshold Voltage - V
VDS - Drain to Source Voltage - V
-2
25
Pulsed
20
ID = −75 A
−37.5 A
−15 A
15
10
5
0
0
-5
-10
-15
-20
VGS - Gate to Source Voltage - V
Page 4 of 6
NP75P04YLG
Chapter Title
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
10000
ID = −37.5 A
Pulsed
18
16
14
V GS = −5 V
12
10
−10 V
8
6
4
2
0
-100
-50
0
50
100
150
1000
Crss
100
V GS = 0 V
f = 1 MHz
Tch - Channel Temperature - °C
-1
-10
-100
VDS - Drain to Source Voltage - V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
-12
-40
1000
VDS - Drain to Source Voltage - V
td( of f )
tf
100
td(on)
10
V DD = −20 V
V GS = −10 V
RG = 0 Ω
tr
1
-0.1
-35
V DD = −32 V
−20 V
−8 V
-30
-25
-10
-6
-15
-4
-10
V DS
-5
-10
-100
0
20
40
-2
ID = −75 A
-0
-1
-8
V GS
-20
ID - Drain Current - A
60
80
-0
100
QG - Gate Charge - nC
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
1000
trr - Reverse Recovery Time - ns
-1000
IF - Diode Forward Current - A
Coss
10
-0.1
200
SWITCHING CHARACTERISTICS
td(on), tr, td(off), tf - Switching Time - ns
Ciss
-100
V GS = −10 V
-10
0V
-1
Pulsed
-0.1
100
10
di/dt = −100 A/μs
V GS = 0 V
1
0
0.5
1
VF(S-D) - Source to Drain Voltage - V
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
1.5
0.1
1
10
100
IF - Drain Current - A
Page 5 of 6
VGS - Gate to Source Voltage - V
20
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
CHANNEL TEMPERATURE
NP75P04YLG
Chapter Title
Package Drawings (Unit: mm)
1.27
8-pin HSON (Mass: 0.13 g TYP.)
1
5
+0.1
5.0 ±0.2
6
4
0.42 −0.05
7
3
6.0 ±0.2
5.15 ±0.2
8
2
0.10 S
3.8 ±0.2
1.45 MAX.
0.73
0.4
0.42 ±0.05
0
+0.05
−0
0.10 M
5.4 ±0.2
1, 2, 3 : Source
4
: Gate
5, 6, 7, 8: Drain
3.18 ±0.2
0.6 ±0.15
0.8 ±0.15
Equivalent Circuit
Drain
Body
Diode
Gate
Gate
Protection
Diode
Remark
Source
The diode connected between the gate and source of the transistor serves as a protector against
ESD. When this device actually used, an additional protection circuit is externally required if a
voltage exceeding the rated voltage may be applied to this device.
R07DS0183EJ0200 Rev.2.00
Mar 16, 2011
Page 6 of 6
Revision History
NP75P04YLG Data Sheet
Rev.
Date
Page
1.00
2.00
Oct 22, 2010
Mar 16, 2011
−
p.1
Description
Summary
First Edition Issued
Repetitive Avalanche Current -> Single Avalanche Current
Repetitive Avalanche Energy -> Single Avalanche Energy
Modification of Note *3
All trademarks and registered trademarks are the property of their respective owners.
C-1
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