RENESAS R5F2154CEKFP

Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
RENESAS MCU
1.
R01DS0043EJ0010
Rev.0.10
Mar 15, 2011
Overview
1.1
Features
The R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group single-chip microcontrollers (MCUs)
incorporate the R8C CPU core, which provides sophisticated instructions for a high level of efficiency. With 1
Mbyte of address space, the CPU core is capable of executing instructions at high speed. In addition, it features a
multiplier for high-speed arithmetic processing.
Power consumption is low, and additional power control is possible by selecting the operating mode. The R8C/54E
Group, R8C/54F Group, R8C/54G Group, R8C/54H Group are also designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface on the same chip,
reduces the number of system components.
The R8C/54E Group and R8C/54F Group incorporate one channel of CAN module, ideal for the LAN systems of
automotive and factory automation applications.
The R8C/54G Group and R8C/54H Group do not incorporate the CAN module.
The R8C/54E Group and R8C/54G Group also have on-chip data flash (1 KB × 4 blocks) with background
operation (BGO) function.
1.1.1
Applications
Automotive, etc.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 1 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the R8C/54E Group Specifications. Tables 1.3 and 1.4 outline the R8C/54F Group
Specifications. Tables 1.5 and 1.6 outline the R8C/54G Group Specifications. Tables 1.7 and 1.8 outline the
R8C/54H Group Specifications.
Table 1.1
Item
CPU
R8C/54E Group Specifications (1)
Function
Central
processing unit
Memory
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits  32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits  32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
See Table 1.9 R8C/54E Group Product List.
ROM, RAM,
data flash
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 2 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.2
1. Overview
R8C/54E Group Specifications (2)
Item
Timer
Function
Description
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
Timers RD_0
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (threephase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
2 channels
UART0_1
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
(SSU)
Clock
2 channels (also used for the I2C bus)
SSU_0 and
Synchronous
(2 channels can be used only for communication function priority pin assignment
serial interface SSU_1
(only 1 channel for others))
2
2 channels (also used for the SSU)
(I C bus)
I2C_0 and I2C_1 (2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
Hardware LIN
HW-LIN_1
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
CAN module
CAN_0
1 channel: 16 mailboxes (ISO11898-1 standard compliant)
A/D converter
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
Comparator B
2 circuits
CRC calculator
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
Flash memory
Debug functions
Operating frequency/
Power supply voltage
Current consumption
Operating ambient temperature
Package
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
T.B.D.
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Note:
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 3 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.3
Item
1. Overview
R8C/54F Group Specifications (1)
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits  32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits  32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM
See Table 1.10 R8C/54F Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
CPU
Function
Central
processing unit
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 4 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.4
1. Overview
R8C/54F Group Specifications (2)
Item
Timer
Function
Description
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
Timers RD_0
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (threephase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
2 channels
UART0_1
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
(SSU)
Clock
2 channels (also used for the I2C bus)
SSU_0 and
Synchronous
(2 channels can be used only for communication function priority pin assignment
serial interface SSU_1
(only 1 channel for others))
2
2 channels (also used for the SSU)
(I C bus)
I2C_0 and I2C_1 (2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
Hardware LIN
HW-LIN_1
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
CAN module
CAN_0
1 channel: 16 mailboxes (ISO11898-1 standard compliant)
A/D converter
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
Comparator B
2 circuits
CRC calculator
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
Flash memory
Debug functions
Operating frequency/
Power supply voltage
Current consumption
Operating ambient temperature
Package
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance: 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
T.B.D.
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Note:
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 5 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.5
Item
CPU
1. Overview
R8C/54G Group Specifications (1)
Function
Central
processing unit
Memory
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits  32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits  32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
See Table 1.11 R8C/54G Group Product List.
ROM, RAM,
data flash
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 6 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.6
1. Overview
R8C/54G Group Specifications (2)
Item
Timer
Function
Description
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
Timers RD_0
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (threephase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
2 channels
UART0_1
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
(SSU)
Clock
2 channels (also used for the I2C bus)
SSU_0 and
Synchronous
(2 channels can be used only for communication function priority pin assignment
serial interface SSU_1
(only 1 channel for others))
2
2 channels (also used for the SSU)
(I C bus)
I2C_0 and I2C_1 (2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
Hardware LIN
HW-LIN_1
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
A/D converter
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
Comparator B
2 circuits
CRC calculator
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
Flash memory
Debug functions
Operating frequency/
Power supply voltage
Current consumption
Operating ambient temperature
Package
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance:10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• BGO (background operation) function (data flash)
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
T.B.D.
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Note:
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 7 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.7
Item
1. Overview
R8C/54H Group Specifications (1)
Description
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V)
200 ns (CPU clock = 5 MHz, VCC = 1.8 V to 2.7 V)
• Multiplier: 16 bits × 16 bits  32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits  32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Memory
ROM, RAM
See Table 1.12 R8C/54H Group Product List.
Voltage
Voltage detection • Power-on reset
detection
circuit
• Voltage detection with three check points (the detection levels for voltage
detection 0 and voltage detection 1 can be selected.)
I/O ports
Programmable
• Input only: 1
I/O ports
• CMOS I/O: 43, selectable pull-up resistor
• Simplified peripheral mapping controller (PMC) allows communication function
priority pin assignment selection.
Clock
Clock generation • 4 circuits: XIN clock oscillation circuit,
circuits
high-speed on-chip oscillator (with frequency adjustment function),
low-speed on-chip oscillator,
PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected
• Low-power mode: Standard operating mode (high-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode
Interrupts
• Number of interrupt vectors: 69
• External interrupt inputs: 9 (INT × 5, key input × 4)
• Priority levels: 7
Event link controller (ELC)
• Events output from peripheral functions can be linked to events input to
different peripheral functions.
(22 sources × 7 types of event link operations)
• Events can be handled independently from interrupt requests.
Watchdog timer
• 14 bits × 1
• Selectable reset start function
• Selectable low-speed on-chip oscillator for the watchdog timer
DTC (data transfer controller)
• 1 channel
• Activation sources: 36
• Transfer modes: 2 (normal mode, repeat mode)
CPU
Function
Central
processing unit
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 8 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.8
1. Overview
R8C/54H Group Specifications (2)
Item
Timer
Function
Description
Timers RJ_0 and 16 bits × 1: 2 circuits integrated on-chip
RJ_1
Timer mode (periodic timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
Timers RB2_0
16 bits × 1: 1 circuits integrated on-chip
Timer mode (periodic timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timers RC_0
16 bits (with 4 capture/compare registers) × 1: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 3 pins), PWM2 mode (PWM output: 1 pin)
Timers RD_0
16 bits (with 4 capture/compare registers) × 2: 1 circuit integrated on-chip
Timer mode (input capture function, output compare function), PWM mode
(output: 6 pins), reset synchronous PWM mode (three-phase waveform output
(6 pins), sawtooth wave modulation), complementary PWM mode (threephase waveform output (6 pins), triangular wave modulation), PWM3 mode
(PWM output with fixed period: 2 pins)
Timer RE2
8 bits × 1
Compare match timer mode
Serial interface UART0_0 and
2 channels
UART0_1
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode
UART2
1 channel
Clock synchronous serial I/O mode, clock asynchronous serial I/O mode,
special mode 3 (IE mode), multiprocessor communication mode
(SSU)
Clock
2 channels (also used for the I2C bus)
SSU_0 and
Synchronous
(2 channels can be used only for communication function priority pin assignment
serial interface SSU_1
(only 1 channel for others))
2
2 channels (also used for the SSU)
(I C bus)
I2C_0 and I2C_1 (2 channels can be used only for communication function priority pin assignment
(only 1 channel for others))
LIN module
HW-LIN_0 and
Hardware LIN
HW-LIN_1
2 channels (Timers RJ_0 and RJ_1, UART0_0 and UART0_1 are used)
A/D converter
Resolution: 10 bits × 12 channels, sample and hold function, sweep mode
Comparator B
2 circuits
CRC calculator
CRC-CCITT (X16 + X12 + X5 + 1), CRC-16 (X16 + X15 + X2 + 1) compliant
Flash memory
Debug functions
Operating frequency/
Power supply voltage
Current consumption
Operating ambient temperature
Package
• Program/erase voltage: VCC = 2.7 V to 5.5 V
• Read voltage: VCC = 1.8 V to 5.5 V
• Program/erase endurance: 1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• 1-wire debug interface provided (dedicated hardware provided)
• Hot plug connection is supported, allowing the debugger interface to be
connected during user mode operation.
CPU clock = 32 MHz (VCC = 2.7 V to 5.5 V)
CPU clock = 5 MHz (VCC = 1.8 V to 2.7 V)
T.B.D.
-40 C to 85 C (J version)
-40 C to 125 C (K version) (1)
48-pin LQFP
Package code: PLQP0048KB-A (previous code: 48P6Q-A)
Note:
1. Specify the K version if it is to be used.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 9 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1.2
1. Overview
Product List
Table 1.9 shows the R8C/54E Group Product List. Figure 1.1 shows the R8C/54E Group Product Part Number
Structure. Table 1.10 shows the R8C/54F Group Product List. Figure 1.2 shows the R8C/54F Group Product Part
Number Structure. Table 1.11 shows the R8C/54G Group Product List. Figure 1.3 shows the R8C/54G Group
Product Part Number Structure. Table 1.12 shows the R8C/54H Group Product List. Figure 1.4 shows the R8C/54H
Group Product Part Number Structure.
Table 1.9
R8C/54E Group Product List
Part No.
R5F21546EJFP
R5F21547EJFP
R5F21548EJFP
R5F2154AEJFP
R5F2154CEJFP
R5F21546EKFP
R5F21547EKFP
R5F21548EKFP
R5F2154AEKFP
R5F2154CEKFP
Current of Mar 2011
Internal ROM Capacity
Program ROM
Data Flash
32 Kbytes
1 Kbyte × 4
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Package Type
Remarks
PLQP0048KB-A
J version
K version
Part No. R 5 F 21 54 C E J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7  7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54E Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
R8C/54E Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 10 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.10
R8C/54F Group Product List
Part No.
R5F21546FJFP
R5F21547FJFP
R5F21548FJFP
R5F2154AFJFP
R5F2154CFJFP
R5F21546FKFP
R5F21547FKFP
R5F21548FKFP
R5F2154AFKFP
R5F2154CFKFP
1. Overview
Current of Mar 2011
Internal ROM Capacity
Internal RAM Capacity Package Type
Program ROM
32 Kbytes
2.5 Kbytes
PLQP0048KB-A
48 Kbytes
4 Kbytes
64 Kbytes
6 Kbytes
96 Kbytes
8 Kbytes
128 Kbytes
10 Kbytes
32 Kbytes
2.5 Kbytes
48 Kbytes
4 Kbytes
64 Kbytes
6 Kbytes
96 Kbytes
8 Kbytes
128 Kbytes
10 Kbytes
Remarks
J version
K version
Part No. R 5 F 21 54 C F J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7  7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54F Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
R8C/54F Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 11 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.11
R8C/54G Group Product List
Part No.
R5F21546GJFP
R5F21547GJFP
R5F21548GJFP
R5F2154AGJFP
R5F2154CGJFP
R5F21546GKFP
R5F21547GKFP
R5F21548GKFP
R5F2154AGKFP
R5F2154CGKFP
1. Overview
Current of Mar 2011
Internal ROM Capacity
Program ROM
Data Flash
32 Kbytes
1 Kbyte × 4
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
32 Kbytes
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
Internal RAM
Capacity
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Package Type
Remarks
PLQP0048KB-A
J version
K version
Part No. R 5 F 21 54 C G J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7  7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54G Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
R8C/54G Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 12 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.12
R8C/54H Group Product List
Part No.
R5F21546HJFP
R5F21547HJFP
R5F21548HJFP
R5F2154AHJFP
R5F2154CHJFP
R5F21546HKFP
R5F21547HKFP
R5F21548HKFP
R5F2154AHKFP
R5F2154CHKFP
1. Overview
Current of Mar 2011
Internal ROM Capacity
Internal RAM Capacity Package Type
Program ROM
32 Kbytes
2.5 Kbytes
PLQP0048KB-A
48 Kbytes
4 Kbytes
64 Kbytes
6 Kbytes
96 Kbytes
8 Kbytes
128 Kbytes
10 Kbytes
32 Kbytes
2.5 Kbytes
48 Kbytes
4 Kbytes
64 Kbytes
6 Kbytes
96 Kbytes
8 Kbytes
128 Kbytes
10 Kbytes
Remarks
J version
K version
Part No. R 5 F 21 54 C H J FP
Package type:
FP: PLQP0048KB-A
(0.5 mm pin pitch, 7  7 mm square body)
Classification
J: Operating ambient temperature -40 °C to 85 °C
K: Operating ambient temperature -40 °C to 125 °C
Availability of CAN, Data flash
E: CAN module: Yes; Data flash: Yes
F: CAN module: Yes; Data flash: No
G: CAN module: No; Data flash: Yes
H: CAN module: No; Data flash: No
ROM capacity
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/54H Group
R8C/5x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
R8C/54H Group Product Part Number Structure
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 13 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1.3
1. Overview
Block Diagram
Figure 1.5 shows the Block Diagram.
I/O ports
8
8
8
6
Port P0
Port P1
Port P2
Port P3
5
1
8
Port P4
Port P6
PMC (Peripheral Mapping Controller)
System clock generation circuit
Peripheral functions
Timers
Timer RJ (16 bits  2)
Timer RB2 (16 bits  1)
Timer RC (16 bits  1)
Timer RD (16 bits  2)
Timer RE2 (8 bits  1)
A/D converter
(10 bits  12 channels)
UART0
(8 bits  2 channels)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
Low-speed on-chip oscillator
(for watchdog timer)
PLL frequency synthesizer
Voltage detection circuit
UART2
(8 bits  1 channel)
DTC
Comparator B
CAN module (1)
(1 channel)
Event link controller
Synchronous serial
communication unit (SSU/I2C)
(8 bits  2 channels)
Watchdog timer
(14 bits)
Memory
R8C CPU core
R0H
R1H
CRC calculator
LIN module
(2 channels)
R0L
R1L
R2
R3
A0
A1
FB
ROM (2)
SB
USP
ISP
INTB
PC
FLG
RAM (3)
Multiplier
PMC (Peripheral Mapping Controller)
Port P9
4
Notes:
1. Available only in the R8C/54E Group and the R8C/54F Group.
2. ROM size varies with the product.
3. RAM size varies with the product.
Figure 1.5
Block Diagram
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 14 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1.4
1. Overview
Pin Assignment
25
26
27
28
29
30
31
32
33
34
37
24
38
23
R8C/54E Group
R8C/54F Group
R8C/54G Group
R8C/54H Group
39
40
41
42
43
22
21
20
19
18
17
44
45
16
PLQP0048KB-A (48P6Q-A)
(Top view)
46
15
12
11
10
9
8
7
6
5
P1_3/KI3/AN11/TRBO_0/TRCIOC_0/TRDIOD1_0
P1_4/TXD_0/TRCCLK_0
P1_5/RXD_0/TRJIO_0/INT1
P1_6/CLK_0/SSI_0
P1_7/INT1/TRJIO_0
P2_0/TRDIOA0_0/TRDCLK_0/TXD2/INT1/RXD2/TRCIOB_0
P2_1/TRDIOB0_0/TRDIOC0_0/TRCIOC_0
P2_2/TRDIOC0_0/TRDIOB0_0/TRCIOD_0
P2_3/TRDIOD0_0
P2_4/TRDIOA1_0/IVCMP3
P2_5/TRDIOB1_0/IVREF3
P2_6/TRDIOC1_0
MODE
P4_3
P4_4
RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P2_7/TRDIOD1_0
P3_5/SCL_0/SSCK_0/TRCIOD_0/CLK2/TRDIOD1_0/TRDIOA0_0/TRDCLK_0
P3_3/SSI_0/INT3/TRCCLK_0/SCS_0/CTS2/RTS2/TRDIOD0_0
P3_4/SDA_0/SCS_0/TRCIOC_0/SSI_0/RXD2/TXD2/TRDIOC1_0/TRDIOB0_0
4
13
3
14
48
2
47
1
P0_6/AN1/TRCIOD_0
P0_5/AN2/CLK2/TRCIOB_0
P0_4/AN3/TMRE2O/TRCIOB_0
P4_2/VREF
P6_0/TMRE2O
P6_2/CRX_0 (1)/CLK_1
P6_1/CTX_0 (1)
P0_3/AN4/CLK_1/TRCIOB_0
P0_2/AN5/RXD_1/TRCIOA_0/TRCTRG_0/TRJIO_1/INT2
P0_1/AN6/TXD_1/TRCIOA_0/TRCTRG_0/TRJO_1
P0_0/AN7/TXD2/TRCIOA_0/TRCTRG_0
P3_7/SSO_0/TXD2/RXD2/TRJO_0/SDA_0/INT3/TRCCLK_0/TRDIOC0_0
35
36
P0_7/AN0/TRCIOC_0
P6_3/TXD_1/TRJO_1
P6_4/RXD_1/INT2/TRJIO_1
P6_5/INT4/CLK2/CLK_1/TRCIOB_0
P3_0/TRJO_0
P3_1/TRBO_0/CTS2/RTS2
P1_0/KI0/AN8/TRCIOD_0/TRDIOA1_0/IVREF1
P1_1/KI1/AN9/TRCIOA_0/TRCTRG_0/TRDIOB1_0/IVCMP1
P1_2/Kl2/AN10/TRCIOB_0/TRDIOC1_0
P6_7/INT3/RXD2/TRCIOD_0
P6_6/INT2/TXD2/TRCIOC_0
P4_5/INT0/RXD2
Figure 1.6 shows Pin Assignment (Top View). Tables 1.13 to 1.17 list the Pin Name Information by Pin Number.
Note:
1. Available only in the R8C/54E Group and the R8C/54F Group.
Figure 1.6
Pin Assignment (Top View)
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 15 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.13
Port
Pin No.
P0_0
47
P0_1
46
P0_2
45
P0_3
44
P0_4
39
P0_5
38
P0_6
37
P0_7
36
P1_0
30
P1_1
29
P1_2
28
P1_3
24
Pin Name Information by Pin Number (INT, URAT0, and UART2)
INT
INT0
INT1
21
P1_7
20
INT1
INT1
17 (1)
P2_3
16 (1)
P2_4
15
P2_5
14
P2_6
13
P2_7
12
P3_0
32
P3_1
31
P3_3
2
P3_4
3
P3_5
1
P3_7
48
P4_2
40
P4_3
5
P4_4
6
P4_5
25
P4_6
10
P4_7
8
P6_0
41
P6_1
43
P6_2
42
P6_3
35
P6_4
34
P6_5
33
P6_6
26
P6_7
27
P9_4
19 (1)
P9_5
18 (1)
P9_6
17 (1)
P9_7
16 (1)
TXD_1
RXD_0
RXD_1
UART2
CLK_0
CLK_1
TXD2
RXD2
CTS2
RTS2
CLK2
RXD_1
CLK2
P1_6
P2_2
TXD_0
CLK_1
23
19 (1)
INT4
TXD_1
22
18 (1)
UART0
INT3
INT2
P1_5
P2_0
INT2
TXD2
P1_4
P2_1
1. Overview
TXD_0
INT1
RXD_0
CLK_0
TXD2
RXD2
INT3
TXD2
RXD2
TXD2
RXD2
CTS2
RTS2
CTS2
RTS2
CLK2
INT3
INT0
RXD2
CLK_1
TXD_1
INT2
RXD_1
INT4
INT2
CLK_1
CLK2
TXD2
INT3
RXD2
Note:
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 16 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.14
Port
Pin No.
Pin Name Information by Pin Number (CAN and SSU)
CAN (1)
CTX_0
P0_0
1. Overview
CRX_0
SSU/I2C
SCL_0
SCL_1
SDA_0
SDA_1
SSI_0
SSI_1
SCS_0
SCS_1
SSCK_0
SSCK_1
SSO_0
SSO_1
47
P0_1
46
P0_2
45
P0_3
44
P0_4
39
P0_5
38
P0_6
37
P0_7
36
P1_0
30
P1_1
29
P1_2
28
P1_3
24
P1_4
23
P1_5
22
P1_6
21
P1_7
20
P2_0
19 (2)
P2_1
18 (2)
P2_2
17 (2)
P2_3
16 (2)
P2_4
15
P2_5
14
P2_6
13
P2_7
12
P3_0
32
P3_1
31
P3_3
2
P3_4
3
P3_5
1
P3_7
48
P4_2
40
P4_3
5
P4_4
6
P4_5
25
P4_6
10
P4_7
8
P6_0
41
P6_1
43
P6_2
42
P6_3
35
P6_4
34
P6_5
33
P6_6
26
P6_7
27
P9_4
19 (2)
P9_5
18 (2)
P9_6
17 (2)
P9_7
16 (2)
SSI_0
SDA_0
SSI_0
SCS_0
SSI_0
SCS_0
SCL_0
SSCK_0
SDA_0
SSO_0
CTX_0
CRX_0
SSI_1
SDA_1
SCL_1
SCS_1
SSCK_1
SSO_1
Notes:
1. Available only in the R8C/54E Group and the R8C/54F Group.
2. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 17 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.15
1. Overview
Pin Name Information by Pin Number (Timer RJ, Timer RB2, and Timer RC)
Timer RJ
Timer RB2
Timer RC
Port
Pin No.
P0_0
47
P0_1
46
P0_2
45
P0_3
44
TRCIOB_0
P0_4
39
TRCIOB_0
P0_5
38
TRCIOB_0
P0_6
37
P0_7
36
P1_0
30
P1_1
29
P1_2
28
P1_3
24
P1_4
23
P1_5
22
P1_6
21
P1_7
20
P2_0
19 (1)
P2_1
18 (1)
P2_2
17 (1)
P2_3
16 (1)
P2_4
15
P2_5
14
P2_6
13
P2_7
12
P3_0
32
P3_1
31
P3_3
2
P3_4
3
P3_5
1
P3_7
48
P4_2
40
P4_3
5
P4_4
6
P4_5
25
P4_6
10
P4_7
8
P6_0
41
P6_1
43
P6_2
42
P6_3
35
P6_4
34
P6_5
33
P6_6
26
P6_7
27
P9_4
19 (1)
P9_5
18 (1)
P9_6
17 (1)
P9_7
16 (1)
TRJO_0
TRJO_1
TRJIO_0
TRJIO_1
TRBO_0
TRCCLK_0
TRJO_1
TRJIO_1
TRCIOA_0
TRCIOB_0
TRCIOC_0
TRCIOD_0
TRCTRG_0
TRCIOA_0
TRCTRG_0
TRCIOA_0
TRCTRG_0
TRCIOA_0
TRCTRG_0
TRCIOD_0
TRCIOC_0
TRCIOD_0
TRCIOA_0
TRCTRG_0
TRCIOB_0
TRBO_0
TRCIOC_0
TRCCLK_0
TRJIO_0
TRJIO_0
TRCIOB_0
TRCIOC_0
TRCIOD_0
TRJO_0
TRBO_0
TRCCLK_0
TRCIOC_0
TRCIOD_0
TRJO_0
TRCCLK_0
TRJO_1
TRJIO_1
TRCIOB_0
TRCIOC_0
TRCIOD_0
Note:
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 18 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.16
Port
Pin No.
P0_0
47
P0_1
46
P0_2
45
P0_3
44
P0_4
39
P0_5
38
P0_6
37
P0_7
36
P1_0
30
P1_1
29
P1_2
28
P1_3
24
P1_4
23
P1_5
22
P1_6
21
Pin Name Information by Pin Number (Timer RD and Timer RE2)
Timer RD
TRDCLK_0
TRDIOA0_0
TRDIOB0_0
TRDIOC0_0
18 (1)
TRDIOB0_0
TRDIOC0_0
P2_2
17 (1)
TRDIOB0_0
TRDIOC0_0
P2_3
16 (1)
P2_4
15
P2_5
14
P2_6
13
P2_7
12
P3_0
32
P3_1
31
P3_3
2
P3_4
3
P3_5
1
P3_7
48
P4_2
40
P4_3
5
10
P4_7
8
P6_0
41
P6_1
43
P6_2
42
P6_3
35
P6_4
34
P6_5
33
P6_6
26
P6_7
27
P9_4
19 (1)
P9_5
18 (1)
P9_6
17 (1)
P9_7
16 (1)
TRDIOD1_0
TMRE2O
TRDIOD1_0
P2_1
P4_6
TRDIOC1_0
TRDIOC1_0
20
6
TRDIOB1_0
TRDIOB1_0
19 (1)
25
Timer RE2
TRDIOA1_0
TRDIOA1_0
P2_0
P4_5
TRDIOD0_0
TMRE2O
P1_7
P4_4
1. Overview
TRDCLK_0
TRDIOA0_0
TRDIOD0_0
TRDIOA1_0
TRDIOB1_0
TRDIOC1_0
TRDIOD1_0
TRDIOD0_0
TRDIOB0_0
TRDCLK_0
TRDIOC1_0
TRDIOA0_0
TRDIOD1_0
TRDIOC0_0
TMRE2O
Note:
1. Pin assignments change depending on the PMC function.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 19 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.17
Port
Pin No.
P0_0
47
Pin Name Information by Pin Number (Others)
Others
AN7
P0_1
46
AN6
P0_2
45
AN5
P0_3
44
AN4
P0_4
39
AN3
P0_5
38
AN2
P0_6
37
AN1
P0_7
36
AN0
P1_0
30
KI0
AN8
IVREF1
P1_1
29
KI1
AN9
IVCMP1
P1_2
28
KI2
AN10
P1_3
24
KI3
AN11
P1_4
23
P1_5
22
P1_6
21
P1_7
20
P2_0
19 (1)
P2_1
18 (1)
P2_2
17 (1)
P2_3
16 (1)
P2_4
15
IVCMP3
P2_5
14
IVREF3
P2_6
13
P2_7
12
P3_0
32
P3_1
31
P3_3
2
P3_4
3
P3_5
1
P3_7
48
P4_2
40
P4_3
5
VREF
P4_4
6
P4_5
25
P4_6
10
XIN
P4_7
8
XOUT
P6_0
41
P6_1
43
P6_2
42
P6_3
35
P6_4
34
P6_5
33
P6_6
26
P6_7
27
P9_4
19 (1)
P9_5
18 (1)
P9_6
17 (1)
P9_7
16 (1)
1. Overview
Note:
1. Pin assignments change depending on the PMC function.
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
1.5
1. Overview
Pin Functions
Tables 1.18 and 1.19 list Pin Functions.
Table 1.18
Pin Functions (1)
Item
Power supply input
Pin Name
VCC, VSS
I/O
—
Analog power supply
input
Reset input
AVCC, AVSS
—
MODE
XIN clock input
XIN clock output
INT interrupt input
Key input interrupt
RESET
MODE
XIN
XOUT
INT0 to INT4
I
I
I
I/O
I
I
Description
Apply 2. 7 V through 5.5 V to the VCC pin when the
CPU clock = 32 MHz and apply 1.8 V through 2.7 V to
this pin when the CPU clock = 5 MHz.
Apply 0 V to the VSS pin.
Power supply input for the A/D converter.
Connect a capacitor between pins AVCC and AVSS.
Applying a low level to this pin resets the MCU.
Connect this pin to the VCC pin via a resistor.
I/O for the XIN clock generation circuit.
Connect a ceramic resonator or a crystal oscillator
between pins XIN and XOUT. (1)
To use an external clock, input it to the XIN pin and
leave the XOUT pin open.
INT interrupt input.
Key input interrupt input.
KI0 to KI3
Timers RJ_0 and RJ_1 TRJIO_0, TRJIO_1
I/O
Input/output for timer RJ.
TRJO_0, TRJO_1
O
Output for timer RJ.
Timers RB2_0
TRBO_0
O
Output for timer RB2.
Timers RC_0
TRCCLK_0
I
External clock input.
TRCTRG_0
I
External trigger input.
TRCIOA_0, TRCIOB_0,
I/O
Input/output for timer RC.
TRCIOC_0, TRCIOD_0
Timers RD_0
TRDIOA0_0,
I/O
Input/output for timer RD.
TRDIOA1_0,
TRDIOB0_0,
TRDIOB1_0,
TRDIOC0_0,
TRDIOC1_0,
TRDIOD0_0,
TRDIOD1_0
TRDCLK_0
I
External clock input.
Timer RE2
TMRE2O
O
Divided clock output.
Serial interface
CLK_0, CLK_1
I/O
Transfer clock input/output.
(UART0)
RXD_0, RXD_1
I
Serial data input.
TXD_0, TXD_1
O
Serial data output.
I
Input for transmission control.
Serial interface
CTS2
(UART2)
O
Output for reception control.
RTS2
RXD2
I
Serial data input.
TXD2
O
Serial data output.
CLK2
I/O
Transfer clock input/output.
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 1.19
1. Overview
Pin Functions (2)
Item
Synchronous serial
communication unit
(SSU_0, SSU_1)
Pin Name
SSI_0, SSI_1
I/O
I/O
I/O
Description
Data input/output.
Chip-select input/output.
SCS_0, SCS_1
SSCK_0, SSCK_1
I/O
Clock input/output.
SSO_0, SSO_1
I/O
Data input/output.
SCL_0, SCL_1
I/O
Clock input/output.
I2C bus
SDA_0, SDA_1
I/O
Data input/output.
(I2C_0 and I2C_1)
I
Data input for CAN.
CAN module (CAN_0) (1) CRX_0
CTX_0
O
Data output for CAN.
Reference voltage input VREF
I
Reference voltage input for the A/D converter.
A/D converter
AN0 to AN11
I
Analog input for the A/D converter.
Comparator B
IVCMP1, IVCMP3
I
Analog voltage input for comparator B.
IVREF1, IVREF3
I
Reference voltage input for comparator B.
I/O ports
P0_0 to P0_7,
I/O
8-bit CMOS input/output ports.
P1_0 to P1_7,
Each port has an I/O select direction register, enabling
P2_0 to P2_7,
switching input and output for each pin.
P3_0 and P3_1,
For input ports, the presence or absence of a pull-up
P3_3 to P3_5, P3_7,
resistor can be selected by a program.
P4_3 to P4_7,
All ports can be used as LED drive (high drive) ports.
P6_0 to P6_7,
P9_4 to P9_7
Input port
P4_2
I
Input-only port.
Note:
1. Available only in the R8C/54E Group and the R8C/54F Group.
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the 13 CPU Registers. The registers R0, R1, R2, R3, A0, A1, and FB form a single register bank. The
CPU has two register banks.
b31
b15
b8
b7
b0
R2
R0H (R0 high-order byte) R0L (R0 low-order byte)
R3
R1H (R1 high-order byte) R1L (R1 low-order byte)
R2
Data registers (1)
R3
A0
Address registers (1)
A1
Frame base register (1)
FB
b19
b15
b0
INTBH
INTBL
Interrupt table register
The higher 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
U
Flag register
b0
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bits
Processor interrupt priority level
Reserved bit
Note:
1. These registers form a single register bank.
The CPU has two register banks.
Figure 2.1
CPU Registers
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Page 23 of 52
Under development
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3.
R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers.
The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). In the
same way as with R0 and R2, R3 and R1 can be used as a 32-bit data register (R3R1).
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined
with A0 and used as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5
Program Counter (PC)
PC is a 20-bit register that indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch
between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register used for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register that indicates the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. It must only be set to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0.
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Mar 15, 2011
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Under development
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is 0, and are enabled when the I
flag is 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1. The U flag is set to 0 when a hardware
interrupt request is acknowledged or the INT instruction for a software interrupt numbered from 0 to 31 is
executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns eight processor interrupt priority levels from 0 to 7. If a requested interrupt has
higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
The write value must be 0. The read value is undefined.
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Mar 15, 2011
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Under development
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3.
3. Address Space
Address Space
3.1
R8C/54E Group Memory Map
Figure 3.1 shows the R8C/54E Group Memory Map. The R8C/54E Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (2)
0FFDCh
06FFFh
07000h
Undefined instruction
Overflow
Internal ROM
(data flash) (1)
BRK instruction
Address match
07FFFh
Single-step
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
Internal ROM
(program ROM)
(Reserved)
Reset
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the CAN, DTC, and other SFR areas.
3. The blank areas are reserved. No access is allowed.
Part Number
Internal ROM
Capacity
Internal RAM
Address 0YYYYh Address ZZZZZh
Capacity
Address 0XXXXh
00DFFh
R5F21546EJFP, R5F21546EKFP
32 Kbytes
08000h
0FFFFh
2.5 Kbytes
R5F21547EJFP, R5F21547EKFP
48 Kbytes
08000h
13FFFh
4 Kbytes
013FFh
R5F21548EJFP, R5F21548EKFP
64 Kbytes
08000h
17FFFh
6 Kbytes
01BFFh
R5F2154AEJFP, R5F2154AEKFP
96 Kbytes
08000h
1FFFFh
8 Kbytes
023FFh
R5F2154CEJFP, R5F2154CEKFP
128 Kbytes
08000h
27FFFh
10 Kbytes
02BFFh
Figure 3.1
R8C/54E Group Memory Map
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Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3.2
3. Address Space
R8C/54F Group Memory Map
Figure 3.2 shows the R8C/54F Group Memory Map. The R8C/54F Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (1)
0FFDCh
06FFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
Address break
Internal ROM
(program ROM)
0FFFFh
(Reserved)
Reset
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Addresses 06800h to 06FFFh are used for the CAN, DTC, and other SFR areas.
2. The blank areas are reserved. No access is allowed.
Part Number
Internal RAM
Internal ROM
Capacity
Address 0YYYYh Address ZZZZZh
Capacity
Address 0XXXXh
R5F21546FJFP, R5F21546FKFP
32 Kbytes
08000h
0FFFFh
2.5 Kbytes
00DFFh
R5F21547FJFP, R5F21547FKFP
48 Kbytes
08000h
13FFFh
4 Kbytes
013FFh
R5F21548FJFP, R5F21548FKFP
64 Kbytes
08000h
17FFFh
6 Kbytes
01BFFh
R5F2154AFJFP, R5F2154AFKFP
96 Kbytes
08000h
1FFFFh
8 Kbytes
023FFh
R5F2154CFJFP, R5F2154CFKFP
128 Kbytes
08000h
27FFFh
10 Kbytes
02BFFh
Figure 3.2
R8C/54F Group Memory Map
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Under development
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3.3
3. Address Space
R8C/54G Group Memory Map
Figure 3.3 shows the R8C/54G Group Memory Map. The R8C/54G Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated at addresses 07000h to 07FFFh.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (2)
0FFDCh
06FFFh
07000h
Undefined instruction
Overflow
Internal ROM
(data flash) (1)
BRK instruction
Address match
07FFFh
Single-step
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
Internal ROM
(program ROM)
0FFFFh
(Reserved)
Reset
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. Addresses 06800h to 06FFFh are used for the DTC and other SFR areas.
3. The blank areas are reserved. No access is allowed.
Part Number
Internal RAM
Internal ROM
Capacity
Address 0YYYYh Address ZZZZZh
Capacity
Address 0XXXXh
R5F21546GJFP, R5F21546GKFP
32 Kbytes
08000h
0FFFFh
2.5 Kbytes
00DFFh
R5F21547GJFP, R5F21547GKFP
48 Kbytes
08000h
13FFFh
4 Kbytes
013FFh
R5F21548GJFP, R5F21548GKFP
64 Kbytes
08000h
17FFFh
6 Kbytes
01BFFh
R5F2154AGJFP, R5F2154AGKFP
96 Kbytes
08000h
1FFFFh
8 Kbytes
023FFh
R5F2154CGJFP, R5F2154CGKFP
128 Kbytes
08000h
27FFFh
10 Kbytes
02BFFh
Figure 3.3
R8C/54G Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 28 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3.4
3. Address Space
R8C/54H Group Memory Map
Figure 3.4 shows the R8C/54H Group Memory Map. The R8C/54H Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. Up to 32 Kbytes of the internal ROM (program ROM) is allocated at lower
addresses, beginning with address 0FFFFh. The area in excess of 32 Kbytes is allocated at higher addresses,
beginning with address 10000h.
For example, a 64-Kbyte internal ROM is allocated at addresses 08000h to 17FFFh.
The fixed interrupt vector table is allocated at addresses 0FFDCh to 0FFFFh. The start address of each interrupt
routine is stored here.
The internal RAM is allocated at higher addresses, beginning with address 00400h. For example, a 6-Kbyte
internal RAM is allocated at addresses 00400h to 01BFFh. The internal RAM is used not only for data storage but
also as a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated at addresses 00000h to 02FFFh and addresses 06800h to 06FFFh.
Peripheral function control registers are allocated here. All unallocated locations within the SFRs are reserved and
cannot be accessed by users.
00000h
SFR
002FFh
00400h
Internal RAM
0XXXXh
06800h
SFR (1)
0FFDCh
06FFFh
Undefined instruction
Overflow
BRK instruction
Address match
Single-step
Watchdog timer, oscillation stop detection, voltage monitor
0YYYYh
Address break
Internal ROM
(program ROM)
0FFFFh
(Reserved)
Reset
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Addresses 06800h to 06FFFh are used for the DTC and other SFR areas.
2. The blank areas are reserved. No access is allowed.
Part Number
Internal RAM
Internal ROM
Capacity
Address 0YYYYh Address ZZZZZh
Capacity
Address 0XXXXh
R5F21546HJFP, R5F21546HKFP
32 Kbytes
08000h
0FFFFh
2.5 Kbytes
00DFFh
R5F21547HJFP, R5F21547HKFP
48 Kbytes
08000h
13FFFh
4 Kbytes
013FFh
R5F21548HJFP, R5F21548HKFP
64 Kbytes
08000h
17FFFh
6 Kbytes
01BFFh
R5F2154AHJFP, R5F2154AHKFP
96 Kbytes
08000h
1FFFFh
8 Kbytes
023FFh
R5F2154CHJFP, R5F2154CHKFP
128 Kbytes
08000h
27FFFh
10 Kbytes
02BFFh
Figure 3.4
R8C/54H Group Memory Map
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 29 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
3.5
3. Address Space
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 3.1 to 3.23 list the SFR
Information. Table 3.23 lists the ID code Area, Option Function Select Area.
SFR Information (1) (1)
Table 3.1
Address
00000h
00001h
00002h
00003h
00004h
00005h
00006h
00007h
00008h
00009h
0000Ah
0000Bh
0000Ch
0000Dh
0000Eh
0000Fh
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
00019h
0001Ah
0001Bh
0001Ch
0001Dh
0001Eh
0001Fh
00020h
00021h
00022h
00023h
00024h
00025h
00026h
00027h
00028h
00029h
0002Ah
0002Bh
0002Ch
0002Dh
0002Eh
0002Fh
00030h
00031h
00032h
00033h
00034h
Symbol
Register Name
After Reset
PM0
PM1
Processor Mode Register 0
Processor Mode Register 1
00h
10000000b
PRCR
CM0
CM1
OCD
CM3
CM4
Protect Register
System Clock Control Register 0
System Clock Control Register 1
Oscillation Stop Detection Register
System Clock Control Register 3
System Clock Control Register 4
00h
00101000b
00100000b
00h
00h
00000001b
PCLKR1
Peripheral Clock Select Register 1
00h
FRA0
High-Speed On-Chip Oscillator Control Register 0
00h
FRA2
High-Speed On-Chip Oscillator Control Register 2
00h
PLC0
PLCF
PLL Control Register 0
PLL Function Clock Control Register 1
00010010b
00h
RISR
Reset Interrupt Select Register
WDTR
WDTS
WDTC
CSPR
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Count Source Protection Mode Register
10000000b or
00000000b
FFh
FFh
01111111b
10000000b or
00000000b
RSTFR
Reset Source Determination Register
00XXXXXXb
SVDC
STBY VDC Power Control Register
00h
CMPA
VCAC
OCVREFCR
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
On-Chip Reference Voltage Control Register
00h
00h
00h
VCA2
Voltage Detection Register 2
00000000b or
00100000b
00035h
00036h VD1LS
Voltage Detection 1 Level Select Register
00037h
00038h VW0C
Voltage Monitor 0 Circuit Control Register
00039h VW1C
Voltage Monitor 1 Circuit Control Register
X: Undefined
Notes:
1. The blank areas are reserved. No access is allowed.
2. Depends on the CSPROINI bit in the OFS register.
3. Depends on the LVDASI bit in the OFS register.
R01DS0043EJ0010 Rev.0.10
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Remarks
(Note 2)
(Note 2)
(Note 3)
00000111b
11001010b or 11001011b (Note 3)
10001010b
Page 30 of 52
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Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.2
3. Address Space
SFR Information (2) (1)
Address
Symbol
Register Name
0003Ah VW2C
Voltage Monitor 2 Circuit Control Register
0003Bh
0003Ch
0003Dh
0003Eh
0003Fh
00040h
00041h FMRDYIC
Interrupt Control Register
00042h TRJIC_1
Interrupt Control Register
00043h
00044h
00045h
00046h INT4IC
Interrupt Control Register
00047h TRCIC_0
Interrupt Control Register
00048h TRD0IC_0
Interrupt Control Register
00049h TRD1IC_0
Interrupt Control Register
0004Ah TRE2IC
Interrupt Control Register
0004Bh U2TIC
Interrupt Control Register
0004Ch U2RIC
Interrupt Control Register
0004Dh KUPIC
Interrupt Control Register
0004Eh ADIC
Interrupt Control Register
0004Fh SSUIC_0/IICIC_0 Interrupt Control Register
00050h
00051h U0TIC_0
Interrupt Control Register
00052h U0RIC_0
Interrupt Control Register
00053h U0TIC_1
Interrupt Control Register
00054h U0RIC_1
Interrupt Control Register
00055h INT2IC
Interrupt Control Register
00056h TRJIC_0
Interrupt Control Register
00057h
00058h TRB2IC_0
Interrupt Control Register
00059h INT1IC
Interrupt Control Register
0005Ah INT3IC
Interrupt Control Register
0005Bh
0005Ch
0005Dh INT0IC
Interrupt Control Register
0005Eh U2BCNIC
Interrupt Control Register
0005Fh
00060h
00061h
00062h
00063h
00064h
00065h
00066h
00067h
00068h
00069h
0006Ah
0006Bh
0006Ch CANRXIC_0
Interrupt Control Register
0006Dh CANTXIC_0
Interrupt Control Register
0006Eh CANERIC_0
Interrupt Control Register
0006Fh
00070h
00071h
00072h VCMP1IC
Interrupt Control Register
00073h VCMP2IC
Interrupt Control Register
00074h
00075h
00076h
00077h
00078h
00079h SSUIC_1/IICIC_1 Interrupt Control Register
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
10001010b
Remarks
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Page 31 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.3
3. Address Space
SFR Information (3) (1)
Address
Symbol
Register Name
0007Ah
0007Bh
0007Ch
0007Dh
0007Eh
0007Fh
00080h U0MR_0
UART0_0 Transmit/Receive Mode Register
00081h U0BRG_0
UART0_0 Bit Rate Register
00082h U0TB_0
UART0_0 Transmit Buffer Register
00083h
00084h U0C0_0
UART0_0 Transmit/Receive Control Register 0
00085h U0C1_0
UART0_0 Transmit/Receive Control Register 1
00086h U0RB_0
UART0_0 Receive Buffer Register
00087h
00088h U0IR_0
UART0_0 Interrupt Flag and Enable Register
00089h
0008Ah
0008Bh
0008Ch LINCR2_0
LIN_0 Special Function Register
0008Dh
0008Eh LINCT_0
LIN_0 Control Register
0008Fh LINST_0
LIN_0 Status Register
00090h U0MR_1
UART0_1 Transmit/Receive Mode Register
00091h U0BRG_1
UART0_1 Bit Rate Register
00092h U0TB_1
UART0_1 Transmit Buffer Register
00093h
00094h U0C0_1
UART0_1 Transmit/Receive Control Register 0
00095h U0C1_1
UART0_1 Transmit/Receive Control Register 1
00096h U0RB_1
UART0_1 Receive Buffer Register
00097h
00098h U0IR_1
UART0_1 Interrupt Flag and Enable Register
00099h
0009Ah
0009Bh
0009Ch LINCR2_1
LIN_1 Special Function Register
0009Dh
0009Eh LINCT_1
LIN_1 Control Register
0009Fh LINST_1
LIN_1 Status Register
000A0h
000A1h
000A2h
000A3h
000A4h
000A5h
000A6h
000A7h
000A8h
000A9h
000AAh
000ABh
000ACh
000ADh
000AEh
000AFh
000B0h
000B1h
000B2h
000B3h
000B4h
000B5h
000B6h
000B7h
000B8h
000B9h
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
XXh
XXh
XXh
00001000b
00000010b
XXXXh
00h
00h
00h
00h
00h
XXh
XXh
XXh
00001000b
00000010b
XXXXh
00h
00h
00h
00h
Page 32 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.4
3. Address Space
SFR Information (4) (1)
Address
Symbol
Register Name
000BAh
000BBh
000BCh
000BDh
000BEh
000BFh
000C0h U2MR
UART2 Transmit/Receive Mode Register
000C1h U2BRG
UART2 Bit Rate Register
000C2h U2TB
UART2 Transmit Buffer Register
000C3h
000C4h U2C0
UART2 Transmit/Receive Control Register 0
000C5h U2C1
UART2 Transmit/Receive Control Register 1
000C6h U2RB
UART2 Receive Buffer Register
000C7h
000C8h U2RXDF
UART2 Digital Filter Function Select Register
000C9h
000CAh
000CBh
000CCh
000CDh
000CEh
000CFh
000D0h U2SMR5
UART2 Special Mode Register 5
000D1h
000D2h
000D3h
000D4h
000D5h U2SMR3
UART2 Special Mode Register 3
000D6h
000D7h U2SMR
UART2 Special Mode Register
000D8h
000D9h
000DAh
000DBh
000DCh
000DDh
000DEh
000DFh
000E0h IICCR_0
I2C_0 Control Register
000E1h SSBR_0
SS_0 Bit Counter Register
000E2h SITDR_0
SI_0 Transmit Data Register
000E3h
000E4h SIRDR_0
SI_0 Receive Data Register
000E5h
000E6h SICR1_0
SI_0 Control Register 1
000E7h SICR2_0
SI_0 Control Register 2
000E8h SIMR1_0
SI_0 Mode Register 1
000E9h SIER_0
SI_0 Interrrupt Enable Register
000EAh SISR_0
SI_0 Status Register
000EBh SIMR2_0
SI_0 Mode Register 2
000ECh
000EDh
000EEh
000EFh
000F0h IICCR_1
I2C_1 Control Register
000F1h SSBR_1
SS_1 Bit Counter Register
000F2h SITDR_1
SI_1 Transmit Data Register
000F3h
000F4h SIRDR_1
SI_1 Receive Data Register
000F5h
000F6h SICR1_1
SI_1 Control Register 1
000F7h SICR2_1
SI_1 Control Register 2
000F8h SIMR1_1
SI_1 Mode Register 1
000F9h SIER_1
SI_1 Interrrupt Enable Register
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00001000b
00000010b
0000h
00h
00h
00h
00h
00001110b
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b
00h
00h
00h
00001110b
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b
00h
Page 33 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.5
Address
000FAh
000FBh
000FCh
000FDh
000FEh
000FFh
00100h
00101h
00102h
00103h
00104h
00105h
00106h
00107h
00108h
00109h
0010Ah
0010Bh
0010Ch
0010Dh
0010Eh
0010Fh
00110h
00111h
00112h
00113h
00114h
00115h
00116h
00117h
00118h
00119h
0011Ah
0011Bh
0011Ch
0011Dh
0011Eh
0011Fh
00120h
00121h
00122h
00123h
00124h
00125h
00126h
00127h
00128h
00129h
0012Ah
0012Bh
0012Ch
0012Dh
0012Eh
0012Fh
00130h
00131h
00132h
00133h
00134h
3. Address Space
SFR Information (5) (1)
Symbol
SISR_1
SIMR2_1
SI_1 Status Register
SI_1 Mode Register 2
00h
00h
TRJ_0
Timer RJ_0 Counter Register
FFFFh
TRJCR_0
TRJIOC_0
TRJMR_0
TRJISR_0
Timer RJ_0 Control Register
Timer RJ_0 I/O Control Register
Timer RJ_0 Mode Register
Timer RJ_0 Event Pin Select Register
00h
00h
00h
00h
TRJ_1
Timer RJ_1 Counter Register
FFFFh
TRJCR_1
TRJIOC_1
TRJMR_1
TRJISR_1
Timer RJ_1 Control Register
Timer RJ_1 I/O Control Register
Timer RJ_1 Mode Register
Timer RJ_1 Event Pin Select Register
00h
00h
00h
00h
TRBCR_0
TRBOCR_0
TRBIOC_0
TRBMR_0
TRBPRE_0
Timer RB2_0 Control Register
Timer RB2_0 One-Shot Control Register
Timer RB2_0 I/O Control Register
Timer RB2_0 Mode Register
Timer RB2_0 Prescaler Register
Timer RB2_0 Primary/Secondary Register (Lower 8 Bits)
Timer RB2_0 Primary Register
Timer RB2_0 Primary Register (Higher 8 Bits)
Timer RB2_0 Secondary Register
Timer RB2_0 Secondary Register (Higher 8 Bits)
Timer RB2_0 Interrupt Request and Status Register
Timer RC_0 Counter
00h
00h
00h
00h
FFh
00135h
TRBPR_0
00136h
TRBSC_0
Register Name
00137h TRBIR_0
00138h TRCCNT_0
00139h
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
FFh
FFh
00h
0000h
Page 34 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.6
3. Address Space
SFR Information (6) (1)
Address
Symbol
Register Name
0013Ah TRCGRA_0
Timer RC_0 General Register A
0013Bh
0013Ch TRCGRB_0
Timer RC_0 General Register B
0013Dh
0013Eh TRCGRC_0
Timer RC_0 General Register C
0013Fh
00140h TRCGRD_0
Timer RC_0 General Register D
00141h
00142h TRCMR_0
Timer RC_0 Mode Register
00143h TRCCR1_0
Timer RC_0 Control Register 1
00144h TRCIER_0
Timer RC_0 Interrupt Enable Register
00145h TRCSR_0
Timer RC_0 Status Register
00146h TRCIOR0_0
Timer RC_0 I/O Control Register 0
00147h TRCIOR1_0
Timer RC_0 I/O Control Register 1
00148h TRCCR2_0
Timer RC_0 Control Register 2
00149h TRCDF_0
Timer RC_0 Digital Filter Function Select Register
0014Ah TRCOER_0
Timer RC_0 Output Enable Register
0014Bh TRCADCR_0
Timer RC_0 A/D Conversion Trigger Control Register
0014Ch TRCOPR_0
Timer RC_0 Output Waveform Manipulation Register
0014Dh TRCELCCR_0
Timer RC_0 ELC Cooperation Control Register
0014Eh
0014Fh
00150h
00151h
00152h
00153h
00154h
00155h
00156h
00157h
00158h
00159h
0015Ah
0015Bh
0015Ch
0015Dh
0015Eh
0015Fh
00160h
00161h
00162h
00163h
00164h
00165h
00166h
00167h
00168h
00169h
0016Ah
0016Bh
0016Ch
0016Dh
0016Eh
0016Fh
00170h TRESEC
Timer RE2 Counter Data Register
00171h TREMIN
Timer RE2 Compare Data Register
00172h
00173h
00174h
00175h
00176h
00177h TRECR
Timer RE2 Control Register
00178h TRECSR
Timer RE2 Count Source Select Register
00179h
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
FFFFh
FFFFh
FFFFh
FFFFh
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00011000b
00h
01111111b
11110000b
00h
00h
00h
00h
00000100b
00001000b
Page 35 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.7
3. Address Space
SFR Information (7) (1)
Address
Symbol
Register Name
0017Ah TREIFR
Timer RE2 Interrupt Flag Register
0017Bh TREIER
Timer RE2 Interrupt Enable Register
0017Ch
0017Dh
0017Eh
0017Fh TREPRC
Timer RE2 Protect Register
00180h TRDELC_0
Timer RD_0 ELC Register
00181h
00182h TRDADCR_0
Timer RD_0 Trigger Control Register
00183h TRDSTR_0
Timer RD_0 Start Register
00184h TRDMR_0
Timer RD_0 Mode Register
00185h TRDPMR_0
Timer RD_0 PWM Mode Register
00186h TRDFCR_0
Timer RD_0 Function Control Register
00187h TRDOER1_0
Timer RD_0 Output Master Enable Register 1
00188h TRDOER2_0
Timer RD_0 Output Master Enable Register 2
00189h TRDOCR_0
Timer RD_0 Output Control Register
0018Ah TRDDF0_0
Timer RD_0 Digital Filter Function Select Register 0
0018Bh TRDDF1_0
Timer RD_0 Digital Filter Function Select Register 1
0018Ch
0018Dh
0018Eh
0018Fh
00190h TRDCR0_0
Timer RD_0 Control Register 0
00191h TRDIORA0_0
Timer RD_0 I/O Control Register A0
00192h TRDIORC0_0
Timer RD_0 I/O Control Register C0
00193h TRDSR0_0
Timer RD_0 Status Register 0
00194h TRDIER0_0
Timer RD_0 Interrupt Enable Register 0
00195h TRDPOCR0_0
Timer RD_0 PWM Mode Output Level Control Register 0
00196h TRD0_0
Timer RD_0 Counter 0
00197h
00198h TRDGRA0_0
Timer RD_0 General Register A0
00199h
0019Ah TRDGRB0_0
Timer RD_0 General Register B0
0019Bh
0019Ch TRDGRC0_0
Timer RD_0 General Register C0
0019Dh
0019Eh TRDGRD0_0
Timer RD_0 General Register D0
0019Fh
001A0h TRDCR1_0
Timer RD_0 Control Register 1
001A1h TRDIORA1_0
Timer RD_0 I/O Control Register A1
001A2h TRDIORC1_0
Timer RD_0 I/O Control Register C1
001A3h TRDSR1_0
Timer RD_0 Status Register 1
001A4h TRDIER1_0
Timer RD_0 Interrupt Enable Register 1
001A5h TRDPOCR1_0
Timer RD_0 PWM Mode Output Level Control Register 1
001A6h TRD1_0
Timer RD_0 Counter 1
001A7h
001A8h TRDGRA1_0
Timer RD_0 General Register A1
001A9h
001AAh TRDGRB1_0
Timer RD_0 General Register B1
001ABh
001ACh TRDGRC1_0
Timer RD_0 General Register C1
001ADh
001AEh TRDGRD1_0
Timer RD_0 General Register D1
001AFh
001B0h
to
001FFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
00h
10001000b
10001000b
11100000b
11100000b
11111000b
0000h
FFFFh
FFFFh
FFFFh
FFFFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
0000h
FFFFh
FFFFh
FFFFh
FFFFh
Page 36 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.8
3. Address Space
SFR Information (8) (1)
Address
Symbol
Register Name
00200h AD0
A/D Register 0
00201h
00202h AD1
A/D Register 1
00203h
00204h AD2
A/D Register 2
00205h
00206h AD3
A/D Register 3
00207h
00208h AD4
A/D Register 4
00209h
0020Ah AD5
A/D Register 5
0020Bh
0020Ch AD6
A/D Register 6
0020Dh
0020Eh AD7
A/D Register 7
0020Fh
00210h
00211h
00212h
00213h
00214h ADMOD
A/D Mode Register
00215h ADINSEL
A/D Input Select Register
00216h ADCON0
A/D Control Register 0
00217h ADCON1
A/D Control Register 1
00218h
00219h
0021Ah
0021Bh
0021Ch
0021Dh
0021Eh
0021Fh
00220h
00221h
00222h
00223h
00224h
00225h
00226h
00227h
00228h INTCMP
Comparator B Control Register 0
00229h
0022Ah
0022Bh
0022Ch
0022Dh
0022Eh
0022Fh
00230h INTEN
External Input Enable Register 0
00231h INTEN1
External Input Enable Register 1
00232h INTF
INT Input Filter Select Register 0
00233h INTF1
INT Input Filter Select Register 1
00234h INTPOL
INT Input Polarity Switch Register
00235h
00236h KIEN
Key Input Interrupt Enable Register
00237h
00238h MSTCR0
Module Standby Control Register 0
00239h MSTCR1
Module Standby Control Register 1
0023Ah MSTCR2
Module Standby Control Register 2
0023Bh MSTCR3
Module Standby Control Register 3
0023Ch
0023Dh
0023Eh
0023Fh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
11000000b
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Page 37 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.9
3. Address Space
SFR Information (9) (1)
Address
Symbol
Register Name
00240h
00241h
00242h
00243h
00244h
00245h
00246h
00247h
00248h
00249h
0024Ah
0024Bh
0024Ch
0024Dh
0024Eh
0024Fh
00250h
00251h
00252h FST
Flash Memory Status Register
00253h
00254h FMR0
Flash Memory Control Register 0
00255h FMR1
Flash Memory Control Register 1
00256h FMR2
Flash Memory Control Register 2
00257h
00258h
00259h
0025Ah
0025Bh
0025Ch
0025Dh
0025Eh
0025Fh
00260h AIADR0L
Address Match Interrupt Address 0L Register
00261h
00262h AIADR0H
Address Match Interrupt Address 0H Register
00263h AIEN0
Address Match Interrupt Enable 0 Register
00264h AIADR1L
Address Match Interrupt Address 1L Register
00265h
00266h AIADR1H
Address Match Interrupt Address 1H Register
00267h AIEN1
Address Match Interrupt Enable 1 Register
00268h
00269h
0026Ah
0026Bh
0026Ch
0026Dh
0026Eh
0026Fh
00270h
00271h
00272h
00273h
00274h
00275h
00276h
00277h
00278h
00279h
0027Ah
0027Bh
0027Ch
0027Dh
0027Eh
0027Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
10000X00b
00h
00h
00h
XXXXh
0000XXXXb
00h
XXXXh
0000XXXXb
00h
Page 38 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.10
3. Address Space
SFR Information (10) (1)
Address
Symbol
Register Name
00280h DTCTL
DTC Activation Control Register
00281h
00282h
00283h
00284h
00285h
00286h
00287h
00288h DTCEN0
DTC Activation Enable Register 0
00289h DTCEN1
DTC Activation Enable Register 1
0028Ah DTCEN2
DTC Activation Enable Register 2
0028Bh DTCEN3
DTC Activation Enable Register 3
0028Ch DTCEN4
DTC Activation Enable Register 4
0028Dh DTCEN5
DTC Activation Enable Register 5
0028Eh DTCEN6
DTC Activation Enable Register 6
0028Fh
00290h CRCSAR
SFR Snoop Address Register
00291h
00292h CRCMR
CRC Control Register
00293h
00294h CRCD
CRC Data Register
00295h
00296h CRCIN
CRC Input Register
00297h
00298h
00299h
0029Ah
0029Bh
0029Ch
0029Dh
0029Eh
0029Fh
002A0h TRJ_0SR
Timer RJ_0 Pin Select Register
002A1h TRJ_1SR
Timer RJ_1 Pin Select Register
002A2h
002A3h
002A4h TRBSR
Timer RB2 Pin Select Register
002A5h TRCCLKSR
Timer RCCLK Pin Select Register
002A6h TRC_0SR0
Timer RC_0 Pin Select Register 0
002A7h TRC_0SR1
Timer RC_0 Pin Select Register 1
002A8h
002A9h TRD_0SR0
Timer RD_0 Pin Select Register 0
002AAh TRD_0SR1
Timer RD_0 Pin Select Register 1
002ABh
002ACh
002ADh TIMSR
Timer Pin Select Register
002AEh U_0SR
UART0_0 Pin Select Register
002AFh U_1SR
UART0_1 Pin Select Register
002B0h
002B1h
002B2h U2SR0
UART2 Pin Select Register 0
002B3h U2SR1
UART2 Pin Select Register 1
002B4h SSUIIC_0SR
SSU/IIC_0 Pin Select Register
002B5h
002B6h INTSR0
INT Interrupt Input Pin Select Register 0
002B7h
002B8h
002B9h PINSR
I/O Function Pin Select Register
002BAh
002BBh
002BCh
002BDh
002BEh PMCSEL
Pin Assignment Select Register
002BFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00h
00h
00h
00h
0000h
00h
0000h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Page 39 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.11
3. Address Space
SFR Information (11) (1)
Address
Symbol
Register Name
002C0h PUR0
Pull-Up Control Register 0
002C1h PUR1
Pull-Up Control Register 1
002C2h PUR2
Pull-Up Control Register 2
002C3h
002C4h
002C5h
002C6h
002C7h
002C8h P1DRR
Port P1 Drive Capacity Control Register
002C9h P2DRR
Port P2 Drive Capacity Control Register
002CAh
002CBh
002CCh DRR0
Drive Capacity Control Register 0
002CDh DRR1
Drive Capacity Control Register 1
002CEh DRR2
Drive Capacity Control Register 2
002CFh
002D0h VLT0
Input Threshold Control Register 0
002D1h VLT1
Input Threshold Control Register 1
002D2h VLT2
Input Threshold Control Register 2
002D3h
002D4h
002D5h
002D6h
002D7h
002D8h
002D9h
002DAh
002DBh
002DCh
002DDh
002DEh
002DFh
002E0h PORT0
Port P0 Register
002E1h PORT1
Port P1 Register
002E2h PD0
Port P0 Direction Register
002E3h PD1
Port P1 Direction Register
002E4h PORT2
Port P2 Register
002E5h PORT3
Port P3 Register
002E6h PD2
Port P2 Direction Register
002E7h PD3
Port P3 Direction Register
002E8h PORT4
Port P4 Register
002E9h
002EAh PD4
Port P4 Direction Register
002EBh
002ECh PORT6
Port P6 Register
002EDh
002EEh PD6
Port P6 Direction Register
002EFh
002F0h
002F1h PORT9
Port P9 Register
002F2h
002F3h PD9
Port P9 Direction Register
002F4h
002F5h
002F6h
002F7h
002F8h
002F9h
002FAh
002FBh
002FCh
002FDh
002FEh
002FFh
00300h On-chip RAM for On-chip RAM for firmware
to
firmware
003FFh
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
00h
XXh
00h
XXh
00h
Page 40 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.12
3. Address Space
SFR Information (12) (1)
Address
Symbol
Register Name
00400h On-chip RAM
On-chip RAM
to
02BFFh
02C00h
to
069FFh
06A00h ELSELR0
Event Output Destination Select Register 0
06A01h ELSELR1
Event Output Destination Select Register 1
06A02h ELSELR2
Event Output Destination Select Register 2
06A03h ELSELR3
Event Output Destination Select Register 3
06A04h ELSELR4
Event Output Destination Select Register 4
06A05h
06A06h
06A07h
06A08h ELSELR8
Event Output Destination Select Register 8
06A09h ELSELR9
Event Output Destination Select Register 9
06A0Ah ELSELR10
Event Output Destination Select Register 10
06A0Bh ELSELR11
Event Output Destination Select Register 11
06A0Ch ELSELR12
Event Output Destination Select Register 12
06A0Dh ELSELR13
Event Output Destination Select Register 13
06A0Eh ELSELR14
Event Output Destination Select Register 14
06A0Fh ELSELR15
Event Output Destination Select Register 15
06A10h ELSELR16
Event Output Destination Select Register 16
06A11h ELSELR17
Event Output Destination Select Register 17
06A12h ELSELR18
Event Output Destination Select Register 18
06A13h ELSELR19
Event Output Destination Select Register 19
06A14h ELSELR20
Event Output Destination Select Register 20
06A15h ELSELR21
Event Output Destination Select Register 21
06A16h ELSELR22
Event Output Destination Select Register 22
06A17h ELSELR23
Event Output Destination Select Register 23
06A18h ELSELR24
Event Output Destination Select Register 24
06A19h
06A1Ah
06A1Bh
06A1Ch
06A1Dh
06A1Eh
06A1Fh
06A20h
06A21h
06A22h
06A23h
06A24h
06A25h
06A26h
06A27h
06A28h
06A29h
06A2Ah
06A2Bh
06A2Ch
06A2Dh
06A2Eh
06A2Fh
06A30h
06A31h
to
06BFFh
06C00h
Area for storing DTC transfer vector 0
06C01h
Area for storing DTC transfer vector 1
06C02h
Area for storing DTC transfer vector 2
06C03h
Area for storing DTC transfer vector 3
06C04h
Area for storing DTC transfer vector 4
06C05h
06C06h
06C07h
06C08h
Area for storing DTC transfer vector 8
06C09h
Area for storing DTC transfer vector 9
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 41 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.13
3. Address Space
SFR Information (13) (1)
Address
Symbol
Register Name
06C0Ah
Area for storing DTC transfer vector 10
06C0Bh
Area for storing DTC transfer vector 11
06C0Ch
Area for storing DTC transfer vector 12
06C0Dh
Area for storing DTC transfer vector 13
06C0Eh
Area for storing DTC transfer vector 14
06C0Fh
Area for storing DTC transfer vector 15
06C10h
Area for storing DTC transfer vector 16
06C11h
Area for storing DTC transfer vector 17
06C12h
Area for storing DTC transfer vector 18
06C13h
Area for storing DTC transfer vector 19
06C14h
Area for storing DTC transfer vector 20
06C15h
Area for storing DTC transfer vector 21
06C16h
Area for storing DTC transfer vector 22
06C17h
Area for storing DTC transfer vector 23
06C18h
Area for storing DTC transfer vector 24
06C19h
Area for storing DTC transfer vector 25
06C1Ah
Area for storing DTC transfer vector 26
06C1Bh
Area for storing DTC transfer vector 27
06C1Ch
Area for storing DTC transfer vector 28
06C1Dh
Area for storing DTC transfer vector 29
06C1Eh
Area for storing DTC transfer vector 30
06C1Fh
Area for storing DTC transfer vector 31
06C20h
Area for storing DTC transfer vector 32
06C21h
Area for storing DTC transfer vector 33
06C22h
06C23h
06C24h
06C25h
06C26h
Area for storing DTC transfer vector 38
06C27h
Area for storing DTC transfer vector 39
06C28h
06C29h
06C2Ah
Area for storing DTC transfer vector 42
06C2Bh
06C2Ch
06C2Dh
06C2Eh
06C2Fh
06C30h
06C31h
Area for storing DTC transfer vector 49
06C32h
Area for storing DTC transfer vector 50
06C33h
Area for storing DTC transfer vector 51
06C34h
Area for storing DTC transfer vector 52
06C35h
06C36h
06C37h
06C38h
06C39h
06C3Ah
06C3Bh
06C3Ch
06C3Dh
06C3Eh
06C3Fh
06C40h DTCCR0
DTC Control Register 0
06C41h DTBLS0
DTC Block Size Register 0
06C42h DTCCT0
DTC Transfer Count Register 0
06C43h DTRLD0
DTC Transfer Count Reload Register 0
06C44h DTSAR0
DTC Source Address Register 0
06C45h
06C46h DTDAR0
DTC Destination Address Register 0
06C47h
06C48h DTCCR1
DTC Control Register 1
06C49h DTBLS1
DTC Block Size Register 1
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
Page 42 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.14
3. Address Space
SFR Information (14) (1)
Address
Symbol
Register Name
06C4Ah DTCCT1
DTC Transfer Count Register 1
06C4Bh DTRLD1
DTC Transfer Count Reload Register 1
06C4Ch DTSAR1
DTC Source Address Register 1
06C4Dh
06C4Eh DTDAR1
DTC Destination Address Register 1
06C4Fh
06C50h DTCCR2
DTC Control Register 2
06C51h DTBLS2
DTC Block Size Register 2
06C52h DTCCT2
DTC Transfer Count Register 2
06C53h DTRLD2
DTC Transfer Count Reload Register 2
06C54h DTSAR2
DTC Source Address Register 2
06C55h
06C56h DTDAR2
DTC Destination Address Register 2
06C57h
06C58h DTCCR3
DTC Control Register 3
06C59h DTBLS3
DTC Block Size Register 3
06C5Ah DTCCT3
DTC Transfer Count Register 3
06C5Bh DTRLD3
DTC Transfer Count Reload Register 3
06C5Ch DTSAR3
DTC Source Address Register 3
06C5Dh
06C5Eh DTDAR3
DTC Destination Address Register 3
06C5Fh
06C60h DTCCR4
DTC Control Register 4
06C61h DTBLS4
DTC Block Size Register 4
06C62h DTCCT4
DTC Transfer Count Register 4
06C63h DTRLD4
DTC Transfer Count Reload Register 4
06C64h DTSAR4
DTC Source Address Register 4
06C65h
06C66h DTDAR4
DTC Destination Address Register 4
06C67h
06C68h DTCCR5
DTC Control Register 5
06C69h DTBLS5
DTC Block Size Register 5
06C6Ah DTCCT5
DTC Transfer Count Register 5
06C6Bh DTRLD5
DTC Transfer Count Reload Register 5
06C6Ch DTSAR5
DTC Source Address Register 5
06C6Dh
06C6Eh DTDAR5
DTC Destination Address Register 5
06C6Fh
06C70h DTCCR6
DTC Control Register 6
06C71h DTBLS6
DTC Block Size Register 6
06C72h DTCCT6
DTC Transfer Count Register 6
06C73h DTRLD6
DTC Transfer Count Reload Register 6
06C74h DTSAR6
DTC Source Address Register 6
06C75h
06C76h DTDAR6
DTC Destination Address Register 6
06C77h
06C78h DTCCR7
DTC Control Register 7
06C79h DTBLS7
DTC Block Size Register 7
06C7Ah DTCCT7
DTC Transfer Count Register 7
06C7Bh DTRLD7
DTC Transfer Count Reload Register 7
06C7Ch DTSAR7
DTC Source Address Register 7
06C7Dh
06C7Eh DTDAR7
DTC Destination Address Register 7
06C7Fh
06C80h DTCCR8
DTC Control Register 8
06C81h DTBLS8
DTC Block Size Register 8
06C82h DTCCT8
DTC Transfer Count Register 8
06C83h DTRLD8
DTC Transfer Count Reload Register 8
06C84h DTSAR8
DTC Source Address Register 8
06C85h
06C86h DTDAR8
DTC Destination Address Register 8
06C87h
06C88h DTCCR9
DTC Control Register 9
06C89h DTBLS9
DTC Block Size Register 9
06C8Ah DTCCT9
DTC Transfer Count Register 9
06C8Bh DTRLD9
DTC Transfer Count Reload Register 9
06C8Ch DTSAR9
DTC Source Address Register 9
06C8Dh
06C8Eh DTDAR9
DTC Destination Address Register 9
06C8Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
XXh
XXh
XXXXh
Remarks
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
Page 43 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.15
3. Address Space
SFR Information (15) (1)
Address
Symbol
Register Name
06C90h DTCCR10
DTC Control Register 10
06C91h DTBLS10
DTC Block Size Register 10
06C92h DTCCT10
DTC Transfer Count Register 10
06C93h DTRLD10
DTC Transfer Count Reload Register 10
06C94h DTSAR10
DTC Source Address Register 10
06C95h
06C96h DTDAR10
DTC Destination Address Register 10
06C97h
06C98h DTCCR11
DTC Control Register 11
06C99h DTBLS11
DTC Block Size Register 11
06C9Ah DTCCT11
DTC Transfer Count Register 11
06C9Bh DTRLD11
DTC Transfer Count Reload Register 11
06C9Ch DTSAR11
DTC Source Address Register 11
06C9Dh
06C9Eh DTDAR11
DTC Destination Address Register 11
06C9Fh
06CA0h DTCCR12
DTC Control Register 12
06CA1h DTBLS12
DTC Block Size Register 12
06CA2h DTCCT12
DTC Transfer Count Register 12
06CA3h DTRLD12
DTC Transfer Count Reload Register 12
06CA4h DTSAR12
DTC Source Address Register 12
06CA5h
06CA6h DTDAR12
DTC Destination Address Register 12
06CA7h
06CA8h DTCCR13
DTC Control Register 13
06CA9h DTBLS13
DTC Block Size Register 13
06CAAh DTCCT13
DTC Transfer Count Register 13
06CABh DTRLD13
DTC Transfer Count Reload Register 13
06CACh DTSAR13
DTC Source Address Register 13
06CADh
06CAEh DTDAR13
DTC Destination Address Register 13
06CAFh
06CB0h DTCCR14
DTC Control Register 14
06CB1h DTBLS14
DTC Block Size Register 14
06CB2h DTCCT14
DTC Transfer Count Register 14
06CB3h DTRLD14
DTC Transfer Count Reload Register 14
06CB4h DTSAR14
DTC Source Address Register 14
06CB5h
06CB6h DTDAR14
DTC Destination Address Register 14
06CB7h
06CB8h DTCCR15
DTC Control Register 15
06CB9h DTBLS15
DTC Block Size Register 15
06CBAh DTCCT15
DTC Transfer Count Register 15
06CBBh DTRLD15
DTC Transfer Count Reload Register 15
06CBCh DTSAR15
DTC Source Address Register 15
06CBDh
06CBEh DTDAR15
DTC Destination Address Register 15
06CBFh
06CC0h DTCCR16
DTC Control Register 16
06CC1h DTBLS16
DTC Block Size Register 16
06CC2h DTCCT16
DTC Transfer Count Register 16
06CC3h DTRLD16
DTC Transfer Count Reload Register 16
06CC4h DTSAR16
DTC Source Address Register 16
06CC5h
06CC6h DTDAR16
DTC Destination Address Register 16
06CC7h
06CC8h DTCCR17
DTC Control Register 17
06CC9h DTBLS17
DTC Block Size Register 17
06CCAh DTCCT17
DTC Transfer Count Register 17
06CCBh DTRLD17
DTC Transfer Count Reload Register 17
06CCCh DTSAR17
DTC Source Address Register 17
06CCDh
06CCEh DTDAR17
DTC Destination Address Register 17
06CCFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
XXh
XXh
XXh
XXh
XXXXh
Remarks
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
Page 44 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.16
3. Address Space
SFR Information (16) (1)
Address
Symbol
Register Name
06CD0h DTCCR18
DTC Control Register 18
06CD1h DTBLS18
DTC Block Size Register 18
06CD2h DTCCT18
DTC Transfer Count Register 18
06CD3h DTRLD18
DTC Transfer Count Reload Register 18
06CD4h DTSAR18
DTC Source Address Register 18
06CD5h
06CD6h DTDAR18
DTC Destination Address Register 18
06CD7h
06CD8h DTCCR19
DTC Control Register 19
06CD9h DTBLS19
DTC Block Size Register 19
06CDAh DTCCT19
DTC Transfer Count Register 19
06CDBh DTRLD19
DTC Transfer Count Reload Register 19
06CDCh DTSAR19
DTC Source Address Register 19
06CDDh
06CDEh DTDAR19
DTC Destination Address Register 19
06CDFh
06CE0h DTCCR20
DTC Control Register 20
06CE1h DTBLS20
DTC Block Size Register 20
06CE2h DTCCT20
DTC Transfer Count Register 20
06CE3h DTRLD20
DTC Transfer Count Reload Register 20
06CE4h DTSAR20
DTC Source Address Register 20
06CE5h
06CE6h DTDAR20
DTC Destination Address Register 20
06CE7h
06CE8h DTCCR21
DTC Control Register 21
06CE9h DTBLS21
DTC Block Size Register 21
06CEAh DTCCT21
DTC Transfer Count Register 21
06CEBh DTRLD21
DTC Transfer Count Reload Register 21
06CECh DTSAR21
DTC Source Address Register 21
06CEDh
06CEEh DTDAR21
DTC Destination Address Register 21
06CEFh
06CF0h DTCCR22
DTC Control Register 22
06CF1h DTBLS22
DTC Block Size Register 22
06CF2h DTCCT22
DTC Transfer Count Register 22
06CF3h DTRLD22
DTC Transfer Count Reload Register 22
06CF4h DTSAR22
DTC Source Address Register 22
06CF5h
06CF6h DTDAR22
DTC Destination Address Register 22
06CF7h
06CF8h DTCCR23
DTC Control Register 23
06CF9h DTBLS23
DTC Block Size Register 23
06CFAh DTCCT23
DTC Transfer Count Register 23
06CFBh DTRLD23
DTC Transfer Count Reload Register 23
06CFCh DTSAR23
DTC Source Address Register 23
06CFDh
06CFEh DTDAR23
DTC Destination Address Register 23
06CFFh
06D00h
to
06DFFh
06E00h CMB0_0
CAN_0 Mailbox 0
06E01h
06E02h
06E03h
06E04h
06E05h
06E06h
06E07h
06E08h
06E09h
06E0Ah
06E0Bh
06E0Ch
06E0Dh
06E0Eh
06E0Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
XXh
XXh
XXh
XXh
XXXXh
Remarks
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXXXh
XXXXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 45 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.17
3. Address Space
SFR Information (17) (1)
Address
Symbol
Register Name
06E10h CMB1_0
CAN_0 Mailbox 1
06E11h
06E12h
06E13h
06E14h
06E15h
06E16h
06E17h
06E18h
06E19h
06E1Ah
06E1Bh
06E1Ch
06E1Dh
06E1Eh
06E1Fh
06E20h CMB2_0
CAN_0 Mailbox 2
06E21h
06E22h
06E23h
06E24h
06E25h
06E26h
06E27h
06E28h
06E29h
06E2Ah
06E2Bh
06E2Ch
06E2Dh
06E2Eh
06E2Fh
06E30h CMB3_0
CAN_0 Mailbox 3
06E31h
06E32h
06E33h
06E34h
06E35h
06E36h
06E37h
06E38h
06E39h
06E3Ah
06E3Bh
06E3Ch
06E3Dh
06E3Eh
06E3Fh
06E40h CMB4_0
CAN_0 Mailbox 4
06E41h
06E42h
06E43h
06E44h
06E45h
06E46h
06E47h
06E48h
06E49h
06E4Ah
06E4Bh
06E4Ch
06E4Dh
06E4Eh
06E4Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 46 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.18
3. Address Space
SFR Information (18) (1)
Address
Symbol
Register Name
06E50h CMB5_0
CAN_0 Mailbox 5
06E51h
06E52h
06E53h
06E54h
06E55h
06E56h
06E57h
06E58h
06E59h
06E5Ah
06E5Bh
06E5Ch
06E5Dh
06E5Eh
06E5Fh
06E60h CMB6_0
CAN_0 Mailbox 6
06E61h
06E62h
06E63h
06E64h
06E65h
06E66h
06E67h
06E68h
06E69h
06E6Ah
06E6Bh
06E6Ch
06E6Dh
06E6Eh
06E6Fh
06E70h CMB7_0
CAN_0 Mailbox 7
06E71h
06E72h
06E73h
06E74h
06E75h
06E76h
06E77h
06E78h
06E79h
06E7Ah
06E7Bh
06E7Ch
06E7Dh
06E7Eh
06E7Fh
06E80h CMB8_0
CAN_0 Mailbox 8
06E81h
06E82h
06E83h
06E84h
06E85h
06E86h
06E87h
06E88h
06E89h
06E8Ah
06E8Bh
06E8Ch
06E8Dh
06E8Eh
06E8Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 47 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.19
3. Address Space
SFR Information (19) (1)
Address
Symbol
Register Name
06E90h CMB9_0
CAN_0 Mailbox 9
06E91h
06E92h
06E93h
06E94h
06E95h
06E96h
06E97h
06E98h
06E99h
06E9Ah
06E9Bh
06E9Ch
06E9Dh
06E9Eh
06E9Fh
06EA0h CMB10_0
CAN_0 Mailbox 10
06EA1h
06EA2h
06EA3h
06EA4h
06EA5h
06EA6h
06EA7h
06EA8h
06EA9h
06EAAh
06EABh
06EACh
06EADh
06EAEh
06EAFh
06EB0h CMB11_0
CAN_0 Mailbox 11
06EB1h
06EB2h
06EB3h
06EB4h
06EB5h
06EB6h
06EB7h
06EB8h
06EB9h
06EBAh
06EBBh
06EBCh
06EBDh
06EBEh
06EBFh
06EC0h CMB12_0
CAN_0 Mailbox 12
06EC1h
06EC2h
06EC3h
06EC4h
06EC5h
06EC6h
06EC7h
06EC8h
06EC9h
06ECAh
06ECBh
06ECCh
06ECDh
06ECEh
06ECFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 48 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.20
3. Address Space
SFR Information (20) (1)
Address
Symbol
Register Name
06ED0h CMB13_0
CAN_0 Mailbox 13
06ED1h
06ED2h
06ED3h
06ED4h
06ED5h
06ED6h
06ED7h
06ED8h
06ED9h
06EDAh
06EDBh
06EDCh
06EDDh
06EDEh
06EDFh
06EE0h CMB14_0
CAN_0 Mailbox 14
06EE1h
06EE2h
06EE3h
06EE4h
06EE5h
06EE6h
06EE7h
06EE8h
06EE9h
06EEAh
06EEBh
06EECh
06EEDh
06EEEh
06EEFh
06EF0h CMB15_0
CAN_0 Mailbox 15
06EF1h
06EF2h
06EF3h
06EF4h
06EF5h
06EF6h
06EF7h
06EF8h
06EF9h
06EFAh
06EFBh
06EFCh
06EFDh
06EFEh
06EFFh
06F00h
06F01h
06F02h
06F03h
06F04h
06F05h
06F06h
06F07h
06F08h
06F09h
06F0Ah
06F0Bh
06F0Ch
06F0Dh
06F0Eh
06F0Fh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 49 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.21
3. Address Space
SFR Information (21) (1)
Address
Symbol
Register Name
06F10h CMKR0_0
CAN_0 Mask Register 0
06F11h
06F12h
06F13h
06F14h CMKR1_0
CAN_0 Mask Register 1
06F15h
06F16h
06F17h
06F18h CMKR2_0
CAN_0 Mask Register 2
06F19h
06F1Ah
06F1Bh
06F1Ch CMKR3_0
CAN_0 Mask Register 3
06F1Dh
06F1Eh
06F1Fh
06F20h CFIDCR0_0
CAN_0 FIFO Received ID Compare Register 0
06F21h
06F22h
06F23h
06F24h CFIDCR1_0
CAN_0 FIFO Received ID Compare Register 1
06F25h
06F26h
06F27h
06F28h
06F29h
06F2Ah CMKIVLR_0
CAN_0 Mask Invalid Register
06F2Bh
06F2Ch
06F2Dh
06F2Eh CMIER_0
CAN_0 Mailbox Interrupt Enable Register
06F2Fh
06F30h CMCTL0_0
CAN_0 Message Control Register 0
06F31h CMCTL1_0
CAN_0 Message Control Register 1
06F32h CMCTL2_0
CAN_0 Message Control Register 2
06F33h CMCTL3_0
CAN_0 Message Control Register 3
06F34h CMCTL4_0
CAN_0 Message Control Register 4
06F35h CMCTL5_0
CAN_0 Message Control Register 5
06F36h CMCTL6_0
CAN_0 Message Control Register 6
06F37h CMCTL7_0
CAN_0 Message Control Register 7
06F38h CMCTL8_0
CAN_0 Message Control Register 8
06F39h CMCTL9_0
CAN_0 Message Control Register 9
06F3Ah CMCTL10_0
CAN_0 Message Control Register 10
06F3Bh CMCTL11_0
CAN_0 Message Control Register 11
06F3Ch CMCTL12_0
CAN_0 Message Control Register 12
06F3Dh CMCTL13_0
CAN_0 Message Control Register 13
06F3Eh CMCTL14_0
CAN_0 Message Control Register 14
06F3Fh CMCTL15_0
CAN_0 Message Control Register 15
06F40h CCTLR_0
CAN_0 Control Register
06F41h
06F42h CSTR_0
CAN_0 Status Register
06F43h
06F44h CBCR_0
CAN_0 Bit Configuration Register
06F45h
06F46h
06F47h CCLKR_0
CAN_0 Clock Select Register
06F48h CRFCR_0
CAN_0 Receive FIFO Control Register
06F49h CRFPCR_0
CAN_0 Receive FIFO Pointer Control Register
06F4Ah CTFCR_0
CAN_0 Transmit FIFO Control Register
06F4Bh CTFPCR_0
CAN_0 Transmit FIFO Pointer Control Register
06F4Ch CEIER_0
CAN_0 Error Interrupt Enable Register
06F4Dh CEIFR_0
CAN_0 Error Interrupt Factor Judge Register
06F4Eh CRECR_0
CAN_0 Receive Error Count Register
06F4Fh CTECR_0
CAN_0 Transmit Error Count Register
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
After Reset
Remarks
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00000101b
00h
00000101b
00h
00h
00h
00h
00h
10000000b
XXh
10000000b
XXh
00h
00h
00h
00h
Page 50 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Table 3.22
SFR Information (22) (1)
Address
Symbol
Register Name
06F50h CECSR_0
CAN_0 Error Code Store Register
06F51h CCSSR_0
CAN_0 Channel Search Support Register
06F52h CMSSR_0
CAN_0 Mailbox Search Status Register
06F53h CMSMR_0
CAN_0 Mailbox Search Mode Register
06F54h CTSR_0
CAN_0 Time Stamp Register
06F55h
06F56h CAFSR_0
CAN_0 Acceptance Filter Support Register
06F57h
06F58h CTCR_0
CAN_0 Test Control Register
06F59h
06F5Ah
06F5Bh
06F5Ch
06F5Dh
06F5Eh
06F5Fh
06F60h
06F61h
06F62h
06F63h
06F64h
06F65h
06F66h
06F67h
06F68h
06F69h
06F6Ah
06F6Bh
06F6Ch
06F6Dh
06F6Eh
06F6Fh
06F70h
06F71h
06F72h
06F73h
06F74h
06F75h
06F76h
06F77h
06F78h
06F79h
06F7Ah
06F7Bh
06F7Ch
06F7Dh
06F7Eh CANISR_0
CAN_0 Interrupt Status Register
06F7Fh CANIE_0
CAN_0 Interrupt Control Register
06F80h
to
06FFFh
X: Undefined
Note:
1. The blank areas are reserved. No access is allowed.
Table 3.23
3. Address Space
After Reset
00h
XXh
10000000b
00h
0000h
Remarks
XXh
XXh
00h
00h
00h
ID code Area, Option Function Select Area
Address
Symbol
Area Name
After Reset
Address size
:
0FFDBh OFS2
Option Function Select Register 2
:
0FFFFh OFS
Option Function Select Register
Note:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not perform any additional writes to the option function select area. Erasure of the block including the option function select area will cause
the option function select area to be set to FFh.
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
Page 51 of 52
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
37
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
24
bp
c
c1
*2
E
HE
b1
Reference Dimension in Millimeters
Symbol
48
13
1
ZE
Terminal cross section
12
c
A
F
A2
Index mark
ZD
S
A1
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
R01DS0043EJ0010 Rev.0.10
Mar 15, 2011
*3
bp
Detail F
x
8.8
8.8
0
0.17
0.09
0°
L1
y S
Min
6.9
6.9
e
x
y
ZD
ZE
L
L1
0.35
Nom Max
7.0 7.1
7.0 7.1
1.4
9.0 9.2
9.0 9.2
1.7
0.1 0.2
0.22 0.27
0.20
0.145 0.20
0.125
8°
0.5
0.08
0.10
0.75
0.75
0.5 0.65
1.0
Page 52 of 52
REVISION HISTORY
R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group Datasheet
Description
Rev.
Date
0.01
Dec 17, 2010
—
0.10
Mar 15, 2011
1 to 22
1. Overview R8C/54F Group, R8C/54G Group, and R8C/54H Group added
27 to 29
3.2, 3.3, and 3.4 added
Page
40
Summary
First Edition issued
Table 3.11 Port register symbol revised
All trademarks and registered trademarks are the property of their respective owners.
C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
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6.
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Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
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The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Colophon 1.1