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DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA2718GR SWITCHING P-CHANNEL POWER MOS FET PACKAGE DRAWING (Unit: mm) DESCRIPTION The µ PA2718GR is P-Channel MOS Field Effect Transistor designed for power management applications of notebook computers and Li-ion battery protection circuit. 8 5 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8 : Drain FEATURES • Low on-state resistance RDS(on)1 = 9.0 mΩ MAX. (VGS = −10 V, ID = −6.5 A) RDS(on)2 = 14.5 mΩ MAX. (VGS = −4.5 V, ID = −6.5 A) • Low Ciss: Ciss = 2810 pF TYP. • Built-in gate protection diode • Small and surface mount package (Power SOP8) ORDERING INFORMATION PART NUMBER PACKAGE µ PA2718GR Power SOP8 6.0 ±0.3 4 4.4 5.37 MAX. 0.8 0.15 +0.10 –0.05 1.44 0.05 MIN. 1.8 MAX. 1 0.5 ±0.2 0.10 1.27 0.78 MAX. 0.40 +0.10 –0.05 0.12 M ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS –30 V Gate to Source Voltage (VDS = 0 V) VGSS m20 V Drain Current (DC) ID(DC) m13 A Drain Current (pulse) Note1 ID(pulse) m130 A Total Power Dissipation Note2 PT1 2 W Total Power Dissipation Note3 PT2 2 W Channel Temperature Tch 150 °C Storage Temperature Tstg –55 to +150 °C Single Avalanche Current Note4 IAS −13 A Single Avalanche Energy Note4 EAS 16.9 mJ Notes 1. 2. 3. 4. EQUIVALENT CIRCUIT Drain Body Diode Gate Gate Protection Diode Source PW ≤ 10 µs, Duty Cycle ≤ 1% Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm, PW = 10 sec Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. G16952EJ1V0DS00 (1st edition) Date Published July 2004 NS CP(K) Printed in Japan 2004 µ PA2718GR ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = −30 V, VGS = 0 V –1 µA Gate Leakage Current IGSS VGS = m20 V, VDS = 0 V m10 µA –2.5 V Gate Cut-off Voltage Forward Transfer Admittance Note Drain to Source On-state Resistance Note VGS(off) VDS = −10 V, ID = −1 mA –1.0 | yfs | VDS = −10 V, ID = −6.5 A 9 RDS(on)1 VGS = −10 V, ID = −6.5 A 7.2 9.0 mΩ RDS(on)2 VGS = −4.5 V, ID = −6.5 A 9.9 14.5 mΩ RDS(on)3 VGS = −4.0 V, ID = −6.5 A 11.8 18.2 mΩ S Input Capacitance Ciss VDS = −10 V 2810 pF Output Capacitance Coss VGS = 0 V 710 pF Reverse Transfer Capacitance Crss f = 1 MHz 460 pF Turn-on Delay Time td(on) VDD = −15 V, ID = −6.5 A 13 ns VGS = −10 V 18 ns RG = 10 Ω 510 ns 310 ns Rise Time tr Turn-off Delay Time td(off) Fall Time tf Total Gate Charge QG VDD = −24 V 67 nC Gate to Source Charge QGS VGS = −10 V 6.5 nC QGD ID = −13 A 19 nC Gate to Drain Charge Body Diode Forward Voltage Note VF(S-D) IF = 13 A, VGS = 0 V 0.84 V Reverse Recovery Time trr IF = 13 A, VGS = 0 V 180 ns Reverse Recovery Charge Qrr di/dt = 50 A/µs 14 nC Note Pulsed TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME D.U.T. RG = 25 Ω D.U.T. L RL 50 Ω PG. VGS = −20 → 0 V VDD RG PG. VGS(−) VGS Wave Form 0 VGS 10% 90% VDD VDS(−) − IAS BVDSS VDS ID VGS(−) 0 VDS Wave Form τ VDD Starting Tch τ = 1 µs Duty Cycle ≤ 1% TEST CIRCUIT 3 GATE CHARGE D.U.T. PG. 2 IG = −2 mA RL 50 Ω VDD Data Sheet G16952EJ1V0DS VDS 90% 90% 10% 10% 0 td(on) tr td(off) ton tf toff µ PA2718GR ELECTRICAL CHARACTERISTICS (TA = 25°C) TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 120 2.8 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 Mounted on ceramic substrate of 1200 mm2 x 2.2 mm 2.4 2 1.6 1.2 0.8 0.4 0 0 0 25 50 75 100 125 150 0 175 25 50 75 100 125 150 175 TA - Ambient Temperature - °C TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA -1000 PW = 100 µs RDS(on)Limited (at VGS = −10 V) ID(DC) -10 1 ms DC 10 ms -1 Power Dissipation Limited -0.1 TA = 25°C Single pulse Mounted on ceramic substrate of 100ms 2 1200 mm x 2.2 mm -0.01 -0.01 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(ch-A) - Transient Thermal Resistance - °C/W ID - Drain Current - A ID(pulse) -100 1000 Rth(ch-A)2 100 Rth(ch-A)1 10 1 Single pulse, TA = 25°C Rth(ch-A)1 : Mounted on ceramic substrate of 1200 mm2 x 2.2 mm Rth(ch-A)2 : Mounted on glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm 0.1 100 µ 1m 10 m 100 m 1 PW - Pulse Width - s Data Sheet G16952EJ1V0DS 10 100 1000 3 µ PA2718GR DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE -150 VDS = −10 V Pulsed −4.5 V VGS = −10 V ID - Drain Current - A ID - Drain Current - A -100 Pulsed -125 FORWARD TRANSFER CHARACTERISTICS -100 −4 V -75 -50 -10 TA = 150°C 75°C 25°C −40°C -1 -0.1 -25 -0.01 0 0 -0.5 -1 -1.5 0 -2 -1 GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE | yfs | - Forward Transfer Admittance - S VGS(off) - Gate Cut-off Voltage - V VDS = −10 V ID = −1 mA -1.5 -1.0 -0.5 0 0 50 100 150 V DS = −10 V Pulsed -10 TA = 150°C 75°C 25°C −40°C -1 -0.1 -0.1 Pulsed 30 V GS = −10 V −4.5 V −4 V 10 0 -100 -1000 RDS(on) - Drain to Source On-state Resistance - mΩ RDS(on) - Drain to Source On-state Resistance - mΩ 40 -10 -10 -100 DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 40 Pulsed ID = −6.5 A 30 20 10 ID - Drain Current - A 4 -1 ID - Drain Current - A DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT -1 -5 -100 Tch - Channel Temperature - °C 20 -4 FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT -2.5 -50 -3 VGS - Gate to Source Voltage - V VDS - Drain to Source Voltage - V -2.0 -2 0 0 -5 -10 -15 VGS - Gate to Source Voltage - V Data Sheet G16952EJ1V0DS -20 DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE 20 10000 Ciss, Coss, Crss - Capacitance - pF VGS = −10 V −4.5 V −4 V 15 10 5 ID = −6.5 A Pulsed Ciss 1000 Coss Crss 100 VGS = 0 V f = 1 MHz 0 -50 0 50 100 10 -0.1 150 Tch - Channel Temperature - °C -100 DYNAMIC INPUT/OUTPUT CHARACTERISTICS 10000 -15 -30 VDD = −15 V VGS = −10 V RG = 10 Ω 1000 VDS - Drain to Source Voltage - V td(on), tr, td(off), tf - Switching Time - ns -10 VDS - Drain to Source Voltage - V SWITCHING CHARACTERISTICS td(off) tf 100 tr td(on) 10 1 -0.1 ID = −13 A VDD = −24 V −15 V −6 V -20 -10 -5 -10 VGS VDS 0 0 -1 -10 -100 0 ID - Drain Current - A 20 40 60 80 QG - Gate Charge - nC SOURCE TO DRAIN DIODE FORWARD VOLTAGE REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 1000 1000 Pulsed trr - Reverse Recovery Time - ns IF - Diode Forward Current - A -1 100 V GS = −10 V 10 0V 1 0.1 0.01 VGS = 0 V di/dt = 50 A/µs 100 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 VF(S-D) - Source to Drain Voltage - V 0.1 1 10 100 IF - Diode Forward Current - A Data Sheet G16952EJ1V0DS 5 VGS - Gate to Source Voltage - V RDS(on) - Drain to Source On-state Resistance - mΩ µ PA2718GR µ PA2718GR SINGLE AVALANCHE CURRENT vs. INDUCTIVE LOAD SINGLE AVALANCHE ENERGY DERATING FACTOR 120 Energy Derating Factor - % IAS - Single Avalanche Current - A -100 IAS = −13 A -10 -1 EAS = 16.9 mJ VDD = −15 V VGS = −20 → 0 V RG = 25 Ω Starting Tch = 25°C 80 60 40 20 -0.1 10 m 0 100 m 1 10 25 50 75 100 125 150 Starting Tch - Starting Channel Temperature - °C L - Inductive Load - H 6 VDD = −15 V RG = 25 Ω VGS = −20 → 0 V IAS ≤ −13 A 100 Data Sheet G16952EJ1V0DS µ PA2718GR • The information in this document is current as of July, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. • NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. 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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1