Standard ICs Segment-type LCD driver BU9729K The BU9729K is a driver for segmented liquid crystal displays, which enables connection with a microcomputer through a serial interface. 4-bit common output and an internal power supply circuit for LCD drive make it possible to configure a low-cost display system. Applications •Movie projectors, car audio equipment, telephones •1)Features Serial interface (8-bit length). 2) Display RAM: 72bits, internal (up to 72 segments can be displayed). 3) Internal power supply circuit for liquid crystal drive. 4) Display duty: 1 / 4. 5) Low-voltage and low-current operation supported. •Block diagram VLCD LCD Driver Bias Circuit VC VDD VSS SEG1 SD SCK C/D SEG2 Serial Interface Address Counter Display Data RAM (DD RAM) CS LCD Segment Driver 18bits SEG18 Command / Data Register Timing Generator Common Counter LCD Common Driver 4bits COM2 COM3 OSC2 COM4 OSC1 Command Decoder COM1 1 Standard ICs BU9729K SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 •Pin assignments 24 23 22 21 20 19 18 17 SEG13 27 14 COM4 SEG14 28 13 COM3 SEG15 29 12 COM2 SEG16 30 11 COM1 SEG17 31 10 C/D SEG18 32 9 CS 1 2 3 4 5 6 7 8 SD SEG1 SCK 15 VDD 26 VLCD SEG12 VC SEG2 VSS 16 OSC2 25 OSC1 SEG11 Fig.1 2 Standard ICs BU9729K •Pin descriptions Pin name Pin No. I/O OSC1 1 I OSC2 2 O VSS 3 — VC 4 VLCD 5 VDD 6 — SCK 7 I 8 I — Function These are the I / O pins for the internal oscillator. Resistance should be connected between the pins when the internal clock is operating. When an external clock is operating, input should be done from OSC1, and OSC2 should be left open. This is the VSS pin. This is the power supply pin for LCD drive. The condition VLCD ⭌ VC ⭌ VSS must be satisfied. This is the VDD pin. This is the shift lock input pin for serial data. The contents of the SD pin are read one bit at a time at the rising edge of this pin. This is the serial data input pin. SD Display data and commands are input here. When this is “0”, display data is not displayed, and when “1”, the data is displayed. This is the chip select signal input pin. 9 CS I When this is LOW, SD input can be received. The SCK counter is incremented at the timing at which CS goes from HIGH to LOW. This is the signal input which recognizes whether the SD input consists of commands or display data. 10 C/D I When the SCK of the eighth clock rises, this pin judges the input to be display data if the level is LOW, and a command if the level is HIGH. COM1 These are the common output pins for LCD drive. 11 ~ 14 ~ O They are connected to the commons of the LCD panel. COM4 SEG1 These are the segment output pins for LCD drive. 15 ~ 32 ~ O They are connected to the segments of the LCD panel. SEG18 •Absolute maximum ratings (Ta = 25°C, V SS = 0V) Parameter Symbol Limits Unit Power supply voltage 1 VDD – 0.3 ~ + 7.0 V VLCD – 0.3 ~ + 7.0∗1 V Pd 400∗2 mW Power supply voltage 2 Power dissipation Operating temperature Topr – 20 ~ + 75 °C Storage temperature Tstg – 55 ~ + 125 °C VIN – 0.3 ~ VDD + 0.3 V VOUT – 0.3 ~ VDD + 0.3 V Input voltage Output voltage ∗1 The condition VLCD ⭌ VC ⭌ VSS must be satisfied. ∗2 Reduced by – 4.0mW for each increase in Ta of 1°C over 25°C. 3 Standard ICs BU9729K •Recommended operating conditions (Ta = 25°C, V SS Parameter = 0V) Symbol Min. Typ. Max. Unit Power supply voltage 1 VDD 2.5 — 5.5 V — Power supply voltage 2 VLCD 2.5 — 5.5 V The condition VLCD ⭌ VC ⭌ VSS must be satisfied. Oscillation frequency fOSC — 36 — kHz characteristics •DCElectrical characteristics (unless otherwise noted, V DD Parameter Input high level voltage Input low level voltage Min. Typ. Max. VIH1 0.8 × — VDD — 0.2 × VDD 0 Rf = 470kΩ = 2.5V to 5.5V, VSS = 0V, Ta = 25°C) Symbol VIL1 Conditions VDD Unit Applicable pin Conditions V — V — OSC1, SD, SCK, C / D, CS — LCD driver on-resistance∗1 RON — — 30 kΩ ∆VON = 0.1V SEG1 ~ 32, COM1 ~ 4 Input high level current 2 IIL2 — — 2 µA VIN = 0 OSC1, SD, SCK, C / D, CS Input low level current IIH –2 — — µA VIN = VDD Input capacitance Current consumption CI IDD OSC1, SD, SCK, C / D ,CS — — 5 — pF — 0.05 1 µA While quiescent∗2 — 8 25 µA When “ALL OFF” is displayed — 40 80 µA For display operations∗3 — 100 250 µA For access operations∗4 SD,SCK, C / D, CS VDD ∗1 The internal power supply impedance is not included in the LCD driver on-resistance. ∗2 All input is fixed at either VDD or VSS. ∗3 Except for Rf = 470kΩ and OSC1, all input is fixed at VDD or VSS. ∗4 Rf = 470kΩ, fSCK = 200kHz. AC characteristics (unless otherwise noted, VDD = 2.5V to 5.5V, VSS = 0V, Ta = 25°C) Parameter SCK rise time Symbol Min. Typ. Max. Unit Conditions tTLH — — 100 ns — SCK fall time tTHL — — 100 ns — SCK cycle time tCYC 800 — — ns — Command wait time tWAIT 800 — — ns — SCK pulse width HIGH tWH1 300 — — ns — SCK pulse width LOW tWL1 300 — — ns — Data setup time tSU1 100 — — ns — Data hold time tH1 100 — — ns — CS pulse width HIGH tWH2 300 — — ns — CS pulse width LOW tWL2 6400 — — ns — CS setup time tSU2 100 — — ns — CS hold time tH2 100 — — ns — C / D setup time tSU3 100 — — ns — C / D hold time tH3 100 — — ns 8th rise of SCK used as reference C / D-CS time∗5 tCCH 100 — — ns CS rise used as reference C / D-SCK time∗5 tSCH 100 — — ns 8th fall of SCK used as reference ∗5 4 Should satisfy either one of these conditions. Standard ICs BU9729K •Input / output circuits Pin name SD SCK C/D CS I/O Equivalent circuit I Pin name I/O SEG1 ~ SEG18 O Equivalent circuit VLCD VDD COM1 ~ COM4 IN OUT VLCD GND GND OSC1 OSC2 I O VDD OSC1 OSC2 GND 5 Standard ICs BU9729K •Timing charts tWH2 tWL2 CS tSU2 tH2 tCYC tWH1 SCK tWL1 tSU1 tTLH1 tTHL tH1 SD tCCH tSCH tSU3 tH3 C/D Fig. 2 Interface timing tCYC tWA / T SCK SD D7 D6 D0 D7 Fig. 3 Command cycle Data format •Serial data is transmitted using four-line clock synchronous transmission. Serial data with a length of eight bits is input synchronized to SCK. If C / D is HIGH at the rise of the 8 × nth clock of SCK, the serial data is recognized as a command, and if C / D is LOW, the serial data is recognized as display data. Serial data is input sequentially, starting from the MSB. 6 Standard ICs BU9729K explanation of commands •TheDetailed following commands (C / D is HIGH at the 8 × nth clock of SCK) are available for the BU9729K. (1) Address Set MSB 0 LSB 0 0 A A A A A Address data displayed in binary format as AAAAA is set for the address counter. The address is incremented by two each time input of the display data (8 bits of data) is completed. (2) Display On MSB 0 LSB 0 1 ∗ ∗ ∗ ∗ ∗ ∗: Don't Care All displays light, regardless of the contents of the display data RAM (DDRAM). At this point, the contents of the DDRAM do not change. (3) Display Off MSB 0 LSB 1 0 ∗ ∗ ∗ ∗ ∗ ∗: Don't Care All displays go out, regardless of the contents of the DDRAM. At this point, the contents of the DDRAM do not change. (4) Display Start MSB 0 LSB 1 1 ∗ ∗ ∗ ∗ ∗ ∗: Don't Care The display begins, in accordance with the contents of the DDRAM. (5) Display Data RAM (DDRAM) Write MSB 1 LSB 0 0 ∗ D D D D ∗: Don't Care The binary 4-bit data DDDD is written to the DDRAM. The address is that specified by the Address Set command. After this command is executed, the address is automatically incremented by + 1. 7 Standard ICs BU9729K (6) Reset LSB MSB 1 1 ∗ 0 ∗ ∗ ∗ ∗ ∗: Don't Care This command should be executed after the power supply has been turned on and before any other command is executed. This command causes the BU9729K to initialize the following: Display Off Address Counter Reset of functions •(1)Description Register The BU9729K has an 8-bit command / data register. Serial data is read in 8-clock units of SCK. If the data read into the register is displayed data (C / D is LOW at the eighth clock of SCK), it is written to the DDRAM. If it is command data (C / D is HIGH at the eighth clock of SCK), it is output to the command decoder to control the BU9729K. (2) Address counter The address counter indicates DDRAM addresses. When the Address Set command is written to a command or data register, the address data is sent automatically to the address counter. After data has been written to the DDRAM, the address counter increments automatically by either + 1 or + 2. The amount by which the counter increments is determined automatically, based on the following status. DDRAM 8-bit writing (C / D is LOW at the eighth clock of SCK) → + 2 DDRAM 4-bit writing (C / D is HIGH at the eighth clock of SCK) → + 1 When the address counter has counted to the address 11H, it becomes 00H the next time it is incremented. (3) Display data RAM (DDRAM) The display data RAM (DDRAM) is used to store display data. It has a capacity of 18 addresses × 4 bits. The relationship between the DDRAM and the display position is shown below. DD RAM address 00 8 01 02 03 04 05 06 07 ········· 0F 10 11 0 COM1 1 COM2 2 COM3 3 COM4 Standard ICs BU9729K DDRAM addresses set for the address counter are in hexadecimal format, and are displayed as shown below. MSB AC4 LSB AC3 AC2 AC1 AC0 (Example) When the DDRAM address is "11" (display position: SEG18) MSB LSB 1 0 0 0 1 1 1 Display data input to the command / data register (C / D = LOW) is divided into the first four bits and the last four bits, with the specified DDRAM address being written to the first four, and the specified address + 1 being written to the last four. The four bits of display data are written sequentially to the bits of the DDRAM, starting from the MSB on both sides. MSB LSB D7 D6 D5 D4 D3 bit0) (bit3 Specified address (bit3 D2 D1 D0 Specified address + 1 bit0) When a DDRAM Write command is input (C / D = HIGH), the four bits of display data in the DDRAM Write command are written to the specified DDRAM address. The four bits are written sequentially, starting from the MSB, to the bits of the DDRAM, starting with the MSB of the DDRAM. MSB LSB 1 0 0 ∗ D3 DDRAM Write command D2 D1 D0 Display data (bit3 bit0) (4) Timing generator Connecting Rf between OSC1 and OSC2 causes oscillation of the internal oscillator circuit and generates a display timing signal. Operation can also be initiated by inputting an external clock. OSC1 OSC1 EXIT CLOCK INPUT OSC2 OPEN Rf OSC2 (Rf can be used to change the oscillation frequency.) Fig. 4 Rf oscillator circuit Fig. 5 External clock input 9 Standard ICs BU9729K (5) LCD driver power supply The LCD driver power supply is generated by the BU9729K. V1 = 2 · VC / 3, V2 = VC / 3 is generated internally. VDD VLCD VC VSS Fig. 6 Example of power supply connection (6) LCD drive circuit The LCD drive circuit is configured of 4 common drivers and 18 segment drivers. When oscillation begins, any effective common output automatically outputs a selective waveform, while the others output non-selective waveforms. Segment output automatically outputs drive waveforms, based on the display data and common counter. The common and segment output waveforms are shown in the following examples. 10 Standard ICs BU9729K •LCD drive waveforms Frame interval VC V1 COM1 V2 VSS VC V1 COM2 V2 VSS VC V1 COM3 V2 VSS VC V1 COM4 V2 VSS VC COM1 COM2 COM3 COM4 0 0 0 0 (No SEGn corresponding from COM1 to COM4 are displayed.) V1 V2 VSS VC 1 0 0 0 (Only SEGn corresponding to COM1 are displayed.) V1 V2 VSS VC SEG1 0 1 0 0 (Only SEGn corresponding to COM2 are displayed.) V1 ~ SEG18 V2 VSS VC 0 1 0 1 (Only SEGn corresponding to COM2 and COM4 are displayed.) V1 V2 VSS VC 1 1 1 1 (All SEGn corresponding from COM1 to COM4 are displayed.) V1 V2 VSS Fig. 7 11 Standard ICs BU9729K VDD has to satisfy the following conditions. Instruction receipt possible VDD ⭌ 2.5V tWAIT < 1ms VDD < 0.3V 0 < tON < 10ms •External dimensions (Units: mm) 9.0 ± 0.3 7.0 ± 0.2 17 16 32 9 1.45 ± 0.1 0.05 1 0.8 8 0.4 ± 0.1 QFP32 12 0.4 9.0 ± 0.3 7.0 ± 0.2 24 25 0.15 ± 0.1 0.15