Standard ICs LCD driver for segment-type LCDs BU9728AKV The BU9728AKV is a segment-type LCD system driver which can accommodate microcomputer control and a serial interface. An internal 4-bit common output and LCD drive power supply circuit enable configuration of a display system at low cost. Applications •Movie projectors, car audio systems, telephones •1)Features Serial interface. (8-bit length) 4) Display duty: 1 / 4 5) Can be driven with low voltage and low current dissipation. 2) Display RAM: Internal, 128 bits. (up to 128 segments can be displayed) 3) Internal power supply circuit for LCD drive. •Absolute maximum ratings (Ta = 25°C, V SS Parameter = 0V) Symbol Limits Unit Power supply voltage 1 VDD – 0.3 ~ + 7.0 V Power supply voltage 2 VLCD – 0.3 ~ + VDD V Pd 400∗ mW Operating temperature Topr – 20 ~ + 75 °C Storage temperature Tstg – 55 ~ + 125 °C Power dissipation ∗ Reduced by 4.0mW for each increase in Ta of 1°C over 25°C . •Recommended operating conditions (Ta = 25°C, V SS Parameter Power supply voltage 1 = 0V) Symbol Min. Typ. Max. Unit VDD 2.5 — 5.5 V — The following relationship should be maintained: VDD ⭌ V1 ⭌ V2 ⭌ V3 ⭌ VSS. Power supply voltage 2 (VDD - V3) VLCD 0 — VDD V Oscillation frequency fOSC — 36 — kHz Conditions Rf = 470kΩ 1 Standard ICs BU9728AKV •Block diagram VDD LCD Driver Bias Circuit RESET V1 V2 V3 VSS SD SCK C/D CS SEG0 Serial Interface LCD Segment Driver 32bits Address Counter Display Data RAM (DD RAM) SEG31 Command / Data Register COM0 Timing Generator 2 LCD Common Driver 4bits Common Counter SEG8 SEG9 SEG10 SEG11 SEG20 36 35 34 33 32 31 30 29 28 27 26 25 37 24 SEG7 SEG21 38 23 SEG6 SEG22 39 22 SEG5 SEG23 40 21 SEG4 SEG24 41 20 SEG3 SEG25 42 19 SEG2 SEG26 43 18 SEG1 SEG27 44 17 SEG0 SEG28 45 16 RESET SEG29 46 15 COM3 SEG30 47 14 COM2 SEG31 48 13 COM1 4 5 6 7 8 9 10 11 12 OSC2 V1 V2 V3 VSS VDD SCK SD COM0 3 C/D 2 CS 1 OSC1 BU9728AKV COM1 COM2 COM3 OSC2 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG19 SEG18 OSC1 Command Decoder •Pin assignments SEG1 Standard ICs BU9728AKV •Pin descriptions Pin name Pin NO. I/O OSC1 OSC2 1 2 I O Input / output pins for the internal oscillator. Resistance is connected between these pins when the internal clock is running. When an external clock is running, the clock is input from OSC1 and OSC2 is left open. V1 ~ V3 3~5 — These are power supply pins for LCD drive. The following relationship must be satisfied: VDD ⭌ V1 ⭌ V2 ⭌ V3 ⭌ VSS (Low) . VSS 6 — This is the VSS power supply pin. VDD 7 — Function This is the VDD power supply pin. SCK 8 I This is the shift clock input pin for serial data. The contents of the SD pin are read one bit at a time at the rising edge of SCK. SD 9 I This is the serial data input pin, used to input display data and commands. Display data is displayed when this is "1" and not displayed when it is "0". CS 10 I This is the chip select signal input pin. When this pin is LOW, SD input can be received. The SCK counter is reset when the CS pin goes from HIGH to LOW. C/D 11 I This signal detects whether the SD input is command or display data. If the pin is LOW at the rising edge of the 8th SCK pulse, the input is recognized as display data, and if HIGH, the input is recognized as command data. 12 ~ 15 O These are the common output pins for LCD drive. They are connected to the LCD panel commons. 16 I This is the reset input pin. When this pin is LOW, the BU9728AKV is initialized. It resets the address counter and turns the display off. 17 ~ 48 O These are the segment output pins for LCD drive. They are connected to the LCD panel segments. COM0 COM3 RESET SEG0 SEG31 •Input / output equivalent circuits Pin name I / O Equivalent Circuit Pin name I / O I SEG0 O VLCD ~ SD SCK C/D CS Equivalent Circuit SEG31 VDD IN OUT VLCD COM0 ~ GND COM3 OSC1 OSC2 GND VDD — OSC1 OSC2 GND RESET I VDD IN GND 3 Standard ICs BU9728AKV characteristics •DCElectrical characteristics (unless otherwise noted, V DD Parameter Symbol Input high level voltage VIH1 Min. = 2.5 ~ 5.5V, VSS = 0V, Ta = 25°C) Typ. Max. Unit Conditions — VDD V — 0.2 × VDD 0.8 × VDD Pin OSC1, SD, SCK, C / D, CS RESET Input low level voltage VIL1 0 — LCD driver ON resistance∗1 RON — — 30 kΩ Input low level current 1 IIL1 — — 100 µA VIN = 0V RESET Input low level current 2 IIL2 — — 2 µA VIN = 0V OSC1, SD, SCK, C / D, CS Input high level current IIH –2 — — µA VIN = VDD OSC1, SD, SCK, C / D, CS, RESET Input capacitance CIN — 5 — pF — — 0.05 1 µA In wait state∗2 — 40 80 µA When display is operating∗3 — 100 250 µA During access operation∗4 IDD Current dissipation — V ∆VON = 0.1V SEG0 ~ 31, COM0 ~ 3 SD, SCK, C / D, CS VDD ∗1 Internal power supply impedance is not included in the LCD driver ON resistance. ∗2 All inputs, including V3 = 0V and OSC1, are fixed at either VDD or VSS. ∗3 Except for V3 = 0V, Rf = 470kΩ , and OSC1, all inputs are fixed at either VDD or VSS. ∗4 V3 = 0V, Rf = 470kΩ , f = 200kHz SCK AC characteristics (unless otherwise noted, VDD = 2.5 ~ 5.5V, VSS = 0V, Ta = 25°C) Parameter SCK rise time Symbol Min. Typ. Max. Unit Conditions tTLH — — 100 ns — SCK fall time tTHL — — 100 ns — SCK cycle time tCYC 800 — — ns — Command wait time tWAIT 800 — — ns — SCK pulse width "H" tWH1 300 — — ns — SCK pulse width "L" tWL1 300 — — ns — Data setup time tSU1 100 — — ns — Data hold time tH1 100 — — ns — CS pulse width "H" tWH2 300 — — ns — CS pulse width "L" tWL2 6400 — — ns — CS set-up time tSU2 100 — — ns — CS hold time tH2 100 — — ns — C / D set-up time tSU3 100 — — ns — C / D hold time tH3 100 — — ns Use rise for 8th CK of SCK as standard C / D - CS time∗5 tCCH 100 — — ns Use CS riss as standard C / D - SCK time∗5 tSCH 100 — — ns Use rise for 8th CK of SCK as standard ∗5 4 Only one (either one) of the conditions needs to be satisfied. Standard ICs BU9728AKV •Timing charts tWL2 tWH2 CS tSU2 tH2 tCYC tWH1 SCK tWL1 tTLH tSU1 tTHL tH1 SD tCCH tSCH tSU3 tH3 C/D Fig.1 Interface timing tCYC tWAIT SCK SD D7 D6 D0 D7 Fig.2 Command cycle Data format •Serial data is 4-line data transmitted in synchronization with the clock. Serial data with a bit length of 8 bits is input in synchronization with SCK. If C / D is HIGH at the rising edge of the 8 × nth SCK clock pulse, the serial data is recognized as command data, and if C / D is LOW, the serial data is recognized as display data. Serial data is input in sequential order, starting from the MSB. 5 Standard ICs BU9728AKV look at commands •TheA detailed BU9728AKV has the following commands (C / D is HIGH at 8 × nth clock pulse of SCK). (1) Address Set MSB 0 LSB 0 0 A A A A A AAAAA and the address data displayed in binary format are set in the address counter. Each time input of the display data (8 bits) has been completed, the address is incremented by + 2. (2) Display On MSB 0 LSB 0 1 ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant All display segments light, regardless of the contents of the Display Data RAM (DDRAM). The contents of the DDRAM do not change. (3) Display Off MSB 0 LSB 1 0 ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant All display segments go out, regardless of the contents of the DDRAM. The contents of the DDRAM do not change. (4) Display Start MSB 0 LSB 1 1 ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant Display begins, in accordance with the contents of the DDRAM. (5) Rewrite Display Data RAM (DDRAM) MSB 1 LSB 0 0 ∗ D D D D ∗ Irrelevant The binary bit data DDDD is written to the DDRAM. The data is written to the address specified by the Address Set command, and after this command is executed, the address is automatically incremented by + 1. (6) Reset MSB 1 LSB 1 0 ∗ ∗ ∗ ∗ ∗ ∗ Irrelevant This command should be executed before any other command, immediately after the power supply is turned on. This command resets the BU9728AKV to the following status: • Display is off • Address counter is reset 6 Standard ICs BU9728AKV •Description of functions (1) Register The BU9728AKV has a command / data register configured of eight bits. Serial data is read in 8-pulse units of the SCK clock. If the data read to the register is display data (C / D is LOW at the 8th clock pulse of SCK), it is written to the DDRAM, and if the data is command data (C / D is HIGH at the 8th clock pulse of SCK), it is output to a command decoder and used to control the BU9728AKV. (2) Address counter The address counter indicates the DDRAM address. When the set address is written to the command / data register, the address data is automatically sent to the address counter. After the data is written to the DDRAM, the address counter is automatically incremented by either + 1 or + 2. The amount by which the counter is incremented is determined automatically, based on the following statuses: 8 bits written to DDRAM (C / D LOW at 8th clock pulse of SCK) → + 2 4 bits written to DDRAM (C / D HIGH at 8th clock pulse of SCK) → + 1 When the address counter reaches 1FH, it will be reset back to 00H the next time it is incremented. (3) Display Data RAM (DDRAM) The Display Data RAM (DDRAM) is where displays are stored. The capacity of the DDRAM is 32 addresses × 4 bits. The illustration below shows the relationship between the DDRAM and the display positions. DDRAM address 00 01 02 03 04 05 06 07 1D 1E 1F 0 COM0 1 COM1 2 COM2 3 COM3 SEG31 SEG30 SEG29 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 bit DDRAM addresses set in the address counter are in hexadecimal format and are indicated as follows. MSB AC4 LSB AC3 AC2 AC1 AC0 (Example) For a DDRAM address of “14” (display position: SEG20) MSB 1 1 LSB 0 1 0 0 4 7 Standard ICs BU9728AKV The display data input to the command / data register (when C / D is LOW) is written to the DDRAM address and the address consisting of the specified address + 1, which are indicated by the upper four and lower four bits of the data, respectively. The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the DDRAM bits. MSB LSB D6 D7 D5 D4 D3 Specified address (bit3 D2 D1 D0 Specified address + 1 bit0) (bit3 bit0) If the Rewrite DDRAM command is input (C / D is HIGH), the four bits of the display data in the Rewrite DDRAM command are written to the specified DDRAM address. The four bits of the display data are written sequentially, starting from the MSB, to the MSB of the DDRAM bits. MSB LSB 0 1 0 ∗ D3 Rewrite DDRAM command D2 D1 D0 Display data (bit3 bit0) (4) Timing generator Connecting Rf between OSC1 and OSC2 causes the internal oscillator circuit to start oscillating, and generates a display timing signal. The oscillator can also be started by inputting an external clock. OSC1 OSC1 EXIT CLOCK INPUT OSC2 OPEN Rf OSC2 Fig. 3 Rf oscillator circuit Fig. 4 External clock input (5) LCD drive power supply The LCD drive power supply is generated by the BU9728AKV. The LCD drive voltage (VLCD) is supplied by VDD - V3, and the power supply is generated by V1 = 2 • VLCD / 3, V2 = VLCD / 3. If an external bleeder resistance is used to supply the LCD drive voltage externally, the following relationship must be observed: VDD = V1 ⭌ V2 ⭌ V3 ⭌ VSS VDD VDD V1 V1 V2 V2 V3 V3 VSS VSS Fig. 5 Example of connection when using internal power supply Fig. 6 Example of connection when using external power supply (6) LCD drive circuit The LCD drive circuit is configured of four common drivers and 32 segment drivers. When oscillation begins, selected waveforms are output automatically for valid common outputs by the common counter, and de-selected waveforms are output for other outputs. For segment outputs, drive waveforms are output automatically by the display data and common counter. The following page shows examples of common / segment output waveforms. 8 Standard ICs •LCD drive waveforms BU9728AKV Frame cycle VDD V1 COM0 V2 V3 VDD V1 COM1 V2 V3 VDD V1 COM2 V2 V3 VDD V1 COM3 V2 V3 VDD V1 COM0 COM1 COM2 COM3 0 0 0 0 Display none of the segments COM0 to 3. V2 V3 VDD V1 1 0 0 Display segment which applies to COM0. 0 0 1 0 Display segment which applies to COM1. 0 V2 V3 VDD SEG0 V1 ~ SEG31 V2 V3 VDD V1 0 1 0 1 Display segments which apply to COM1 and COM3. V2 V3 VDD V1 1 1 1 1 Display segments which apply to COM0 to COM3. V2 V3 9 Standard ICs BU9728AKV •External dimensions (Units: mm) 9.0 ± 0.3 7.0 ± 0.2 24 48 13 1 1.425 ± 0.1 0.10 25 0.5 12 0.125 ± 0.1 0.2 ± 0.1 0.10 VQFP48 10 0.5 7.0 ± 0.2 9.0 ± 0.3 36 37