ETC SED1520

SED1520/21
DOT MATRIX LCD DRIVER
S-MOS Systems, Inc.
October, 1996
Version 1.0 (Preliminary)
371-1.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
1
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THIS PAGE INTENTIONALLY BLANK
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S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
371-1.0
Table of Contents
1.0
2.0
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3
1.4
SED1520 Family Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Model Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
3.0
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description of Circuit Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 Busy Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Display Start Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.4 Column Address Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.5 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.6 Display Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.7 Common Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.8 Display Data Latch Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.9 LCD Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.10 Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.11 Oscillation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.12 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
4.0
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.1 Power Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.2 System Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.3 LCD Drive Circuit Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1
4.2
4.3
4.4
4.5
4.6
Display ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Display Start Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Set Page Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Column Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Write Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7
4.8
4.9
4.10
Read Display Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Select ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Static Drive ON/OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Select Duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Table of Contents
4.11 Read Modify Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11.1 Cursor Blinking Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12.1 End Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Save Power (Combined Command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14.1 External Resistor Division Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
5.2
5.3
6.0
SED1520FOA - SED1520FOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SED1520FAA - SED1520FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SED1520FOA - SED1521FOA *1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SED1520FAA - SED1521FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD44103CH - SED1521FAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty 1/16, 10 characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty 1/16, 23 characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty 1/32, 33 characters x 4 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty 1/32, 20 kanji characters x 2 lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duty 1/32, 2–screen display, 20 kanji characters x 4 lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
44
44
45
Plastic QFP 5-100 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PAD LAYOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.1 Pad Layout (SED1520D/SED1521D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.1 Al Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.1.2 Au Bump Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.2 Pad Coordinates (SED1520DAB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
41
41
41
42
42
PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1
10.0
80 Family MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
68 Family MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TYPICAL CONNECTIONS WITH LCD PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1
8.2
8.3
8.4
8.5
9.0
31
32
35
35
36
37
LCD DRIVER INTERCONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1
7.2
7.3
7.4
7.5
8.0
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1 System Bus Read/Write I (80 Family MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 System Bus Read/Write II (68 Family MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Display Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPU INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.1
6.2
7.0
27
28
28
28
29
29
29
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50
50
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371-1.0
1.0 General Description
1.0
1.1
1.0 – 1.2
GENERAL DESCRIPTION
DESCRIPTION
The SED1520 is a dot matrix LCD driver LSI intended for display of characters and graphics. The
bit-addressable display data, which is sent from a microcomputer, is stored in a built-in display data
RAM and generates the LCD drive signal.
The SED1520 incorporates innovative circuit design strategies to assure very low current dissipation and a wide range of operating voltages. With these features, the SED1520 permits the user to
implement high-performance handy systems operating from a miniature battery.
In order for the user to adaptively configure his system, the SED1520 family offers two application
forms. One form allows an LCD display of 12 characters × 2 lines with an indicator with a single
chip. The other is dedicated to driving a total of 80 segments, enabling a medium-size display to
be achieved by using a minimum number of drivers.
1.2
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-power CMOS technology
Fast CPU 8-bit data interface (80xx, 68xx)
Segment output . . . . . . . . . . 61 outputs
Common output . . . . . . . . . . 16 outputs
Duty cycle . . SED1520 . . . 1/16 to 1/32
SED1521 . . . 1/8 to 1/32
Built-in display data RAM. . . 2560 bits
Rich display command setting
On-chip CR oscillation circuit
Recommended expansion segment driver: 80 bit
Master/slave operation is supported
Low power consumption . . . 30µW
LCD voltage . . . . . . . . . . . . . 3.5 to 13V
Single power supply. . . . . . . 2.4 to 7.0V
Package . . . . . . . . . . . . . . . . QFP5-100 pin (FOA, FAA)
QFP15-100 pin (FOC, FAC)
Al pad (DOA, DAA)
Au bump (DOB, DAB)
TAB (TOA)
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1.3 – 1.4
1.3
1.0 General Description
SED1520 FAMILY SPECIFICATIONS
Product Name
Clock Frequency
On Chip
External
SED1520FOA
18kHz
18kHz
SED1521FOA
—
18kHz
SED1520FAA
—
2kHz
SED1521FAA
—
2kHz
1.4
Applicable Driver
SED1520FOA,
SED1521FOA
SED1520FAA,
SED1521FAA,
HD44103CH
No. of SEG
Drivers
No. of COM
Drivers
61
16
80
0
61
16
80
0
MODEL CLASSIFICATION
Operating Clock
Model Name
Internal
oscillator
SED1520FO*
18KHz
SED1520FA*
—
6
Connectable Drivers
SEG
Driver
COM
Driver
18KHz
SED1520FO*, SED1521FO*
61 ports
16 ports
2KHz
SED1520FA*, SED1521FA*
61 ports
16 ports
External
clock
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2.0 Block Diagrams
2.0
2.1
2.0 – 2.1
BLOCK DIAGRAMS
SYSTEM BLOCK DIAGRAM
COM0~COM15
28 CHAR × 2 LINES
SEG0~SEG60
SED1520
SEG0~SEG79
FR
Ck
SED1521
VDD
M/S
M/S
GND
DATA
CONTROL
CPU (68xx, 80xx)
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2.2 – 2.2
2.2
2.0 Block Diagrams
BLOCK DIAGRAM
D0 ∼ D7
A 0 , CS
(OSC1)
E , R/W
(RD)(WR)
RES
MPU INTERFACE
BUS
HOLDER
COMMAND
DECODER
STATUS
LOW ADDRESS
REGISTER
COLUMN ADDRESS REGISTER
FR
DISPLAY
TIMING
GENERATOR
COLUMN ADDRESS COUNTER
CL
(OSC2)
INTERNAL BUS
COLUMN ADDRESS DECODER
DISPLAY START LINE REGISTER
LINE COUNTER
LINE ADDRESS DECODER
I/O BUFFER
DISPLAY DATA RAM
2560 BITS
COMMON
COUNTER
DISPLAY DATA LATCH CIRCUIT
LCD DRIVER CIRCUIT
V2 , V 3 , V 5
CM0 ∼ CM 15
(SG61 ∼SG76)
60
V1 , V 4 , M/S
(SG77 ∼SG79)
SG0 ∼ SG
VDD
VSS
8
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2.0 Block Diagrams
2.3
2.3 – 2.3.1.3
DESCRIPTION OF CIRCUIT BLOCKS
2.3.1 MPU Interface
2.3.1.1
Selection of Interface Type
The SED1520 Series uses 8 bits of bi-directional data bus (D0–D7) to transfer data. The reset pin
is capable of selecting MPU interface; setting the polarity of RES to either “H” or “L” can provide
direct interface of the SED1520 with a 68 or 80 family MPU (see Table 1 below).
With CS at high level, the SED1520 is independent from the MPU bus and stays in standby mode.
In this mode, however, the reset signal is input independently of the internal status.
Table 1
Type
A0
E
R/W
CS
D0–D7
“L” active
68 MPU
↑
↑
↑
↑
↑
“H” active
80 MPU
↑
RD
WR
↑
↑
Polarity of RES
2.3.1.2
Identification of Data Bus Signals
The SED1520 uses a combination of A0, E, R/W, (RD, WR) to identify a data bus signal.
Table 2
Common
68 MPU
A0
R/W
RD
WR
1
1
0
1
Read display data
1
0
1
0
Write display data
0
1
0
1
Read status
0
0
1
0
Write to internal register (command)
2.3.1.3
80 MPU
Function
Access to Display Data RAM and Internal Register
In order to make matching of operating frequencies between the MPU and the display data RAM
or internal register, the SED1520 performs a sort of LSI–LSI pipelining via the bus holder attached
to the internal data bus.
Consider the case where the MPU reads the content of the display data RAM. In the first data read
cycle (dummy), the data is stored on the bus holder. In the next data read cycle, the data is read
from the bus holder to the system bus.
Also, consider the case where the MPU writes data to the display data RAM. In the first data write
cycle, the data is held on the bus holder. The data is written to the display data RAM before the
next data write cycle begins.
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2.3.1.4 – 2.3.1.5
2.0 Block Diagrams
Therefore, MPU’s access to the SED1520 is affected not by display data RAM access time (tACC,
tDS) but by cycle time (tCYC). This leads to faster transfer of data to and from the MPU. If the cycle
time requirement is not met, the MPU has only to execute the NOP instruction and this is apparently equivalent to execution of a waiting operation. However, there is a restriction on the read
sequence of the display data RAM; when an address is set, its data is output not to the first read
instruction (immediately following the address setting operation) but to the second read instruction.
Thus, one dummy read cycle is necessary after an address set or write cycle. This relation is
shown in Figures 2.3.1.4 and 2.3.1.5.
2.3.1.4
Write Timing Diagram
WR
MPU
DATA
Internal
Timing
N
Bus
Holder
N+1
N
N+2
N+1
N+3
N+2
N+3
WR
2.3.1.5
Read Timing Diagram
WR
RD
MPU
DATA
N
Address Set
at N
N
n
Dummy Read
Data Read
at N
n+1
Data Read
at N+1
WR
Internal
Timing
RD
Column
Address
Bus
Holder
N
N
N+1
n
N+2
n+1
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n+2
371-1.0
2.0 Block Diagrams
2.3.2 – 2.3.6
2.3.2 Busy Flag
Busy flag being “1” means that the SED1520 is performing its internal operation and any instruction
other than Read Status is disabled. The busy flag is output to pin D7 by a Read Status instruction.
As long as the cycle time (tCYC) requirement is met, the flag need not be checked before each command and this dramatically improves the MPU performance.
2.3.3 Display Start Line Register
This register is a pointer which determines the start line corresponding to COM0 (normally, the uppermost line of display) for display of data in the display data RAM. It is used for scrolling the display or changing the page from one to another. Executing the Set Display Start Line command
sets 5 bits of display start address in this register. Its content is preset in the line counter at each
timing the FR signal changes. The line counter is incremented synchronously to a CL input, thus
generating a line address for sequential reading of 80 bits of data from the display data RAM to the
LCD driver circuit.
2.3.4 Column Address Counter
The column address counter is a 7–bit presettable counter which gives column addresses of the
display data RAM as shown in Fig. 2.3.8.1. When a Read/Write Display Data command comes in,
the counter is incremented by 1. For any nonexisting address over 50H, the counter is locked and
not incremented.
The column address counter is independent from the page register.
2.3.5 Page Register
This register gives a page address of the display data RAM as shown in Fig. 2.3.8.1. The Set Page
Address command permits the MPU to access a new page of the display data RAM.
2.3.6 Display Data RAM
Dot data for display is stored in this RAM. Since the MPU and LCD driver circuit operate independently of each other, data can be changed asynchronously without adverse effect on the display.
One bit of the display data RAM is assigned to one bit of LCD:
LCD on = “1”
LCD off = “0”
The ADC command inverts the assignment relationship between a display data RAM column address and a segment output (see Fig. 2.3.8.1).
371-1.0
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2.3.7 – 2.3.8
2.0 Block Diagrams
2.3.7 Common Timing Generator
This circuit generates common timing and frame (FR) signals from the basic clock (CL). The Select Duty command selects a duty of 1/16 or 1/32. The 1/32 duty is achieved by a two-chip (master
and slave) configuration (common multi-chip system).
2.3.7.1
Common Timing Diagram
FR
(Master
Output)
Master
Common
0
1
2
14 15
Slave
Common
0
16 17
30 31
1
15
16 17
31
2.3.8 Display Data Latch Circuit
The display data latch circuit temporarily stores the data which will be output from the display
data RAM to the LCD driver circuit at one-common intervals. The display ON/OFF and Static
Driver ON/OFF commands control the latched data so that the data in the display data RAM
remains unchanged.
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371-1.0
ADC
SEG Pin D0=“I” D0=“O”
SEG 0 4FH 00H
01
1 4E
02
2 4D
03
3 4C
04
4 4B
05
5 4A
06
6 49
07
7 48
Column Address
DATA
D0
D1
D2
D1,D2=0,0 D3
D4
D5
D6
D7
D0
D1
D2
0,1
D3
D4
D5
D6
D7
D0
D1
D2
1,0
D3
D4
D5
D6
D7
D0
D1
D2
1,1
D3
D4
D5
D6
D7
Page Address
Page 3
Page 2
Page 1
Page 0
4D
4E
4F
02
01
00
371-1.0
1/16
Start
Assignment
(In this example,
the display start
line is set at
address 08.)
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Line
Associated
address Line (ex.)
Display Area
Common
Output
COM 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2.3.8.1
77
78
79
2.0 Block Diagrams
2.3.8.1 – 2.3.8.1
Relationship between Display Data RAM Locations and Addresses (Display Start
Line: 08)
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2.3.9 – 2.3.11
2.0 Block Diagrams
2.3.9 LCD Driver Circuit
This circuit generates 80 sets of multiplexer that generate quartet levels for LCD driving. Display
data in the display data latch, common timing generator output and FR signal are combined to output an LCD driving waveform.
2.3.10 Display Timing Generator
This circuit generates an internal display timing signal from the basic clock (CL) and frame signal (FR).
The frame signal FR makes the LCD driver circuit generate a dual frame AC driving waveform
(type B) to drive LCD, while making both the line counter and common timing generator synchronized to the FR signal output LSI (dedicated common driver or the SED1520 master LSI). To
achieve these functions, the FR signal must be a clock with a duty of 50% which is synchronized
to the frame period.
The clock CL is a clock used to operate the line counter. For a system in which both the SED1520
and SED1521F coexist, they should be of LSI types having the same clock frequency to be applied
to pin CL.
2.3.11 Oscillation Circuit
This circuit is a low-power CR oscillator which uses an oscillation resistor Rf alone to adjust the
oscillation frequency. It generates display timing signals. The SED1520 is available in two LSI
types if classified by oscillation: one LSI type contains an oscillation circuit and the other uses an
externally provided clock.
The oscillation resistor Rf is connected as shown below. Where an LSI containing an oscillation
circuit is operated with an external clock, it is necessary to input the clock with the same phase as
OSC2 of the master LSI to OSC2 of the slave LSI.
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371-1.0
2.0 Block Diagrams
2.3.11.1 – 2.3.11.2
2.3.11.1 LSI Containing Oscillator
VDD
Master LSI
M/S
Slave LSI
M/S
(CL)
OSC2
(CS)
OSC1
VSS
*1
*2
(CL)
OSC2
Open
(
)
Rf
(CS)
OSC1
* As the parasitic capacitance in this portion increases, the oscillation frequency will shift to a lower level. The Rf must
have a smaller value than the specification.
* For a system having two or more slave LSIs, a CMOS buffer is necessary.
2.3.11.2 LSI Operating with External Clock
371-1.0
Y-Driver
SED1521FAA
CL2
CL
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2.3.12 – 2.3.12
2.0 Block Diagrams
2.3.12 Reset Circuit
This circuit senses the leading edge or trailing edge of RES and initializes the system when its
power is switched on.
Initialization:
(a) Display off
(b) Display start line register: First line
(c) Static drive off
(d) Column address counter: Address 0
(e) Page address register: Page 0
(f) Select duty: 1/32
(g) Select ADC: Forward (ADC command D0 = “0”, ADC status flag = “1”)
(h) Read modify write off
The input at pin RES is level-sensed to select an MPU interface mode as shown in Table 1. For
interfacing with an 80 family MPU, an “H” active reset signal is input to pin RES. For interfacing
with a 68 family MPU, an “L” active reset signal is input to the pin. (See Fig. 7.)?????
As exemplified in section 6 “MPU Interface”, pin RES is connected to the MPU reset pin. Thus the
SED1520 and the MPU are initialized at the same time. If system is initialized by pin RES at poweron, it may no longer be reset.
The Reset command causes initialization (b), (d) and (e).
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371-1.0
2.0 Block Diagrams
2.3.12.1 – 2.3.12.1
2.3.12.1 Example of LCD Driving Waveform
1/5 bias, 1/16 duty
1/6 bias, 1/32 duty
0 1 2 3
0 1 2 3
COM 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
15
31
FR
VDD
VSS
COM0
VDD
V1
V2
V3
V4
V5
COM1
VDD
V1
V2
V3
V4
V5
COM2
SEG 0
1
2
3
4
SEG0
SEG1
COM0~SEG0
COM0~SEG1
371-1.0
15 0 1 2 3
31 0 1 2 3
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
–V 1
–V 2
–V 3
–V 4
–V 5
V5
V4
V3
V2
V1
VDD
–V 1
–V 2
–V 3
–V 4
–V 5
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2.3.12.1 – 2.3.12.1
2.0 Block Diagrams
THIS PAGE INTENTIONALLY BLANK
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371-1.0
3.0 Pin Configuration
3.0
PIN CONFIGURATION
PIN CONFIGURATION
DB1
DB0
VSS
R/W(WR)
E(RD)
CL(OSC2)
CS(OSC1)
AO
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
3.1
3.0 – 3.1
80
75
70
65
60
55
50
85
45
90
SED1520/SED1521
40
Index
95
35
100
1
5
10
15
20
25
30
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V5
V3
V2
M/5
V4
V1
COM0
COM1
COM2
COM3
COM4
371-1.0
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3.2 – 3.2.2
3.2
3.0 Pin Configuration
PIN DESCRIPTION
Product name
Pin No.
74
75
96~100, 1~11
93
94
95
SED1520FOA
OSC1
OSC2
COM0~COM15*
M/S
V4
V1
SED1521FOA
CS
CL
SEG76~SEG61
SEG79
SEG78
SEG77
SED1520FAA
CS
CL
COM0~COM15*
M/S
V4
V1
SED1521FAA
CS
CL
SEG76~SEG61
SEG79
SEG78
SEG77
* Master LSI common outputs COM0–COM15 correspond to slave LSI outputs COM31–COM16.
3.2.1 Power Signals
VDD
Connected to +5V power. Common to MPU power pin VCC.
VSS
0V, connected to system GND.
V1–V5
Multi-level power used to drive LCDs. Voltage specified to each LCD cell is divided by
resistors or impedance-converted by an operational amplifier before being applied. Each
voltage to be applied must be based on VDD, while fulfilling the following conditions:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3.2.2 System Bus Interface Signals
D7–D0
8–bit, tri-state, bi-directional I/O bus. Normally, connected to the data bus of an 8–/16–
bit standard microcomputer.
A0
Input pin. Normally, the LSB of the MPU address bus is connected to this input pin to
provide data/command selection.
0: Display control data on D7–D0
1: Display data on D7–D0
RES
Input pin. The SED1520 can be reset or initialized by setting RES to low level (if it is
interfaced with a 68 family MPU) or high level (if with an 80 family MPU). This reset operation occurs when an edge of the RES signal is sensed. The level input selects the
type of interface with the 68 or 80 family MPU:
High level: Interface with 68 family MPU
Low level: Interface with 80 family MPU
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371-1.0
3.0 Pin Configuration
3.2.3 – 3.2.3
CS
Chip Select input signal which is normally obtained by decoding an address bus signal. Effective with “L” active and a chip operating with external clocks. For a chip containing an oscillator, CS works as an oscillation amplifier input pin to which an
oscillation resistor (Rf) is connected. In this case, RD, WR and E must be a signal
ANDed with CS.
E(RD)
Chip interfaced with 68 family MPU:
Enable Clock signal input for the 68 family MPU.
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family MPU RD signal is connected.
With this signal held at “L”, the SED1520 data bus works as output.
R/W (WR)
Chip interface with 68 family MPU:
Read/Write control signal input pin.
R/W = “H” : Read
R/W = “L” : Write
Chip interfaced with 80 family MPU:
“L” Active input pin to which the 80 family WR is connected. The signal
on the data bus is fetched by the leading edge of WR.
3.2.3 LCD Drive Circuit Signals
CL
Input signal effective with a chip using external clocks. This display data latch signal
increments the line counter (at the trailing edge) or the common counter (at the leading edge). CL is connected to CL2 of the common driver. For a chip containing an
oscillator, this pin works as the oscillation amplifier output pin to which an oscillation
resistor (Rf) is connected.
FR
LCD AC signal I/O pin. Connected to pin M of the common driver.
I/O selection:
Chip containing commons
M/S = 1 : Output
M/S = 0 : Input
Chip containing segments alone
: Input
371-1.0
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21
3.2.3.1 – 3.2.3.2
SEG0–
SEG79
3.2.3.1
3.0 Pin Configuration
LCD column (segment) driving output. One of the VDD, V2, V3 and V5 levels is
selected by a combination of the content of display RAM and the FR signal.
LCD Column (Segment) Driving Output Timing
FR
DATA
Output Level
COM0–
COM15
(COM31–
COM16)
3.2.3.2
0
1
0
V2
1
VDD
1
V5
0
V3
LCD common (row) driving output. One of the VDD, V1, V4 and V5 levels is
selected by a combination of the output of the common counter and the FR
signal. The common (row) scanning order for the slave LSI is reverse to that for
the master LSI.
LCD common (row) driving output
FR
Counter Output
Output Level
M/S
(SEG79)
1
1
VS
0
0
V1
1
VDD
0
V4
Input signal which selects the master or slave LSI. Connected to VDD or VSS.
M/S = VDD: Master
M/S = VSS : Slave
M/S selection changes the function of pins FR, COM0–COM15, OSC1 (CS) and
OSC2 (CL):
M/S
FR
COM output
OSC1
OSC2
VDD
Output
COM0–COM15
Input
Output
VSS
Input
COM31–COM16
NC
Input
The common scanning order for the slave driver is reverse to that for master.
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371-1.0
4.0 Commands
4.0
4.0 – 4.2
COMMANDS
Table 3 lists the commands used with the SED1520. This LSI uses a combination of A0, R/W (RD,
WR) to identify a data bus signal. Interpretation and execution of a command depends not on external clock but on internal timing alone. Therefore, a command can be executed so fast that no
busy check is needed.
A detailed description of commands follows.
4.1
DISPLAY ON/OFF
This command forces all display to turn on or off.
R/W
A0 RD WR D7
0
1
0
1
D0
0
1
0
1
1
1
D
D 0 = Display OFF
1 = Display ON
4.2
DISPLAY START LINE
This command specifies a line address (shown in Fig. 2.3.8.1) thus marking the display line that
corresponds to COM0. Display begins with the specified line address and covers as many lines as match
the display duty in address ascending order. Dynamic line address change with the Display Start Line
command enables column-wise scrolling or page change.
R/W
A0 RD WR D7
0
1
0
1
D0
1
0
A4
A3
A2
A1
A0
– High-order bits
A4
A3
A2
A1
A0
Line address
0
0
0
0
0
0
0
0
0
0
1
1
1
371-1.0
1
—
—
—
—
1
1
1
31
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4.3 – 4.4
4.3
4.0 Commands
SET PAGE ADDRESS
This command is used to specify a page address equivalent to a row address for MPU access to
the display data RAM. A required bit of the display data RAM can be accessed by specifying its
page address and column address. Changing the page address causes no change in display.
R/W
A0 RD WR D7
0
4.4
1
0
1
D0
0
1
1
1
0
A1
A1
A0
Page
0
0
0
0
1
1
1
0
2
1
1
3
A0
COLUMN ADDRESS
This command specifies a display data RAM column address. The column address is incremented
by 1 each time the MPU accesses from the set address to the display data RAM. Thus, it is possible for the MPU to gain continuous access to only the data. This incrementing stops with address
80; the page address is not continuously changed.
R/W
A0 RD WR D7
D0
0
1
0
0
A6
A5
A4
A3
A6
A5
A4
A3
A2
A1
A0
Column address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
A2
A1
—
—
—
—
1
1
1
1
A0
79
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371-1.0
4.0 Commands
4.5
4.5 – 4.6
READ STATUS
R/W
A0
0
RD WR D7
0
1
D0
Busy ADC
ON/
OFF
Reset
0
0
0
0
BUSY:
BUSY being “1” means that system is performing an internal operation or is reset. No
command is accepted before BUSY = “0”. As long as the cycle time requirement is met,
no BUSY check is needed.
ADC:
Indicates assignment of column addresses to segment drivers.
0: Inverted (column address 79-n ↔ segment driver n)
1: Forward (column address n ↔ segment driver n)
ON/OFF: Indicates display on or off.
0: Display on
1: Display off
This bit has polarity reverse to the Display ON/OFF command.
RESET:
Indicates that system is being initialized by the RES signal or the Reset command.
0: Display mode
1: Being reset
4.6
WRITE DISPLAY DATA
This command allows the MPU to write 8 bits of data into the display data RAM. Once the data is
written, the column address is automatically incremented by 1; this enables the MPU to write multiword data continuously.
R/W
A0 RD WR D7
1
1
371-1.0
0
D0
Write data
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4.7 – 4.9
4.7
4.0 Commands
READ DISPLAY DATA
This command allows the MPU to read 8 bits of data from the display data RAM location specified
by a column address and a page address. Once the data is read, the column address is automatically incremented by 1; this enables the MPU to read multi-word data continuously.
A dummy read is needed immediately after the column address is set. For details, see 3. (1)–(c).??
R/W
A0 RD WR D7
1
4.8
0
D0
1
Read data
SELECT ADC
This command inverts the relation of assignment between display data RAM column addresses
and segment driver outputs. In other words, the Select ADC command can software-invert the order of segment driver output pins, reducing the restrictions on the configuration of ICs at LCD module assembly. For details, see Fig. 2.3.8.1.
Incrementing the column address by 1, which takes place after the MPU writing or reading display
data, follows the sequence of column addresses specified in Fig. 2.3.8.1.
A0 RD WR D7
0
1
0
1
D = 0:
D = 1:
4.9
D0
0
1
0
0
0
0
D
Clockwise output (forward)
Counterclockwise output (reverse)
STATIC DRIVE ON/OFF
This command forces all display to be on and, at the same time, all common output to be selected.
R/W
A0 RD WR D7
0
1
0
1
D = 0:
D = 1:
D0
0
1
0
0
1
0
D
Static drive off
Static drive on
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4.0 Commands
4.10
4.10 – 4.11
SELECT DUTY
This command is used to select the duty (degree of multiplexity) of LCD driving. It is valid for the
SED1520F (actively operating LSI) only, not valid for the SED1521F (passively operating LSI).
The SED1521F operates with any duty determined by the FR signal.
R/W
A0 RD WR D7
0
1
0
1
D = 0:
D = 1:
D0
0
1
0
1
0
0
D
Duty 1/16
Duty 1/32
If the system contains both SED1520FOA (internal oscillation) and the SED1521FOA LSIs, they
must have the same duty.
4.11
READ MODIFY WRITE
This command is used with the End command in a pair. Once it has been entered, the column
address will be incremented not by the Read Display Data command but by the Write Display Data
command only. This mode will stay until the End command is entered.
Entry of the End command causes the column address to return to the address which was valid
when the Read Modify Write command was entered. This function lessens the load of the MPU
when the data in a specific display area are repeatedly updated (as blinking cursor).
R/W
A0 RD WR D7
0
1
0
1
D0
1
1
0
0
0
0
0
Even in the Read Modify Write mode, any command other than Read/Write Data and Set Column
Address may be used.
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4.11.1 – 4.12.1
4.0 Commands
4.11.1 Cursor Blinking Sequence
Page Address Set
Column Address Set
Read Modify Write
Dummy Read
Data Read
Data Write
No
Modify
Ended?
End
4.12
END
This command cancels the Read Modify Write command, returning the column address to the initial mode address.
R/W
A0 RD WR D7
0
1
0
1
D0
1
1
0
1
1
1
0
4.12.1 End Timing
Column
Address
Return
N
N+1
N+2
Read Modify Write Mode Set
N+m
N
End
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371-1.0
4.0 Commands
4.13
4.13 – 4.14.1
RESET
This command initializes the display start line register, column address counter, and page address
counter without any effect on the display data RAM. For details, see section 2.3.12.
The reset operation follows entry of the Reset command.
R/W
A0 RD WR D7
0
1
0
1
D0
1
1
0
0
0
1
0
Initialization at power-on is performed not by the Reset command but by a reset signal applied to
the RES pin.
4.14
SAVE POWER (COMBINED COMMAND)
Static drive going on with display off invokes power-saving mode, reducing current consumption
to nearly static current level. During this mode, the SED1520 holds the following conditions:
(a) It stops driving the LCD; the segment and common driver outputs are at VDD level.
(b) Oscillation and external clock input are disabled; OSC2 is in floating condition.
(c) The display data and operational mode are held.
The power-saving mode is cancelled by display on or static drive off.
If an external resistor division circuit is used to give LCD driving voltage level, the current flowing
into the resistors must be cut off by the power-save signal.
4.14.1 External Resistor Division Circuit
VDD
VDD
V1
V2
SED1520
V3
V4
–•
V5
Power
Save
Signal
VSSH
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29
4.14.1 – 4.14.1
4.0 Commands
Table 3 Commands
Command
Code
Function
A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0
(1)
Display ON/OFF
0
1
0
1
0
1
(2)
Display start line
0
1
0
1
1
0
(3)
Set page address
0
1
0
1
0
1
(4)
Set column
(segment) address
0
1
0
0
0
1
1
1
0/1
Turns all display on or off, independently of display RAM data or internal status.
1: ON
0: OFF (Power-saving mode with static drive on)*
Display Start Address Specifies RAM line corresponding to uppermost
(0–31)
line (COM0) of display.
1
1
0
Page
(0–3)
Sets display RAM page in page address register.
Sets display RAM column address in column
address register.
Column Address (0–79)
0
1
RESET
0
ON/OFF
Read status
ADC
(5)
Busy
Reads the following status:
0
0
0
0
BUSY
1: Internal operation, 0: Ready
ADC
1: CW output (forward),
0: CCW output (reverse)
ON/OFF
1: Display off, 0: Display on
RESET
1: Being reset, 0: Normal
(6)
Write display data
1
1
0
Write Data
Writes data from
data bus into
display RAM.
(7)
Read display data
1
0
1
Read Data
Reads data from
display RAM onto
data bus.
Display RAM location
whose address has been
preset is accessed. After
access, the column
address is incremented
by 1.
(8)
Select ADC
0
1
0
1
0
1
0
0
0
0
Used to invert relationship of assignment
between display RAM column addresses and
0/1 segment driver outputs.
0: CW output (forward)
1: CCW output (reverse)
(9)
Static drive ON/
OFF
0
1
0
1
0
1
0
0
1
0
Selects normal display or static driving operation.
0/1 1: Static drive (power-saving mode)
0: Normal driving
(10)
Select duty
0
1
0
1
0
1
0
1
0
0
Selects LCD cell driving duty.
0/1 1: 1/32
0: 1/16
(11) Read modify write
0
1
0
1
1
1
0
0
0
0
0
Increments column address counter by 1 when
display data is written. (This is not done when
data is read.)
(12)
End
0
1
0
1
1
1
0
1
1
1
0
Clears read modify write mode.
(13)
Reset
0
1
0
1
1
1
0
0
0
1
0
Sets display start line register on the first line.
Also sets column address counter and page
address counter to 0.
* With display off (command (1)), static drive going on (9) invokes power-saving mode.
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371-1.0
5.0 Electrical Characteristics
5.0
5.1
5.0 – 5.1
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Standard
Unit
Supply voltage (1)
VSS
–8.0 ~ +0.3
V
Supply voltage (2)
V5
–16.5 ~ +0.3
V
Supply voltage (3)
V1, V4
V2, V3
V5 ~ +0.3
V
Input voltage
VIN
VSS – 0.3 ~ +0.3
V
Output voltage
VO
VSS – 0.3 ~ +0.3
V
Allowable loss
PD
250
mW
Operating temperature
TOPR
–30 ~ +85
°C
Storage temperature
TSTG
–65 ~ +150
°C
TSOLDER
260/10 (at leads)
°C/Sec
Soldering temperature/time
Notes:
1. All voltages are based on VDD = 0V.
2. The following condition must always hold true with voltages V1, V2, V3, V4 and V5:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3. The LSI may be permanently damaged if used with any value in excess of the absolute maximum ratings. During normal
operation, the LSI should preferably be used within the specified electrical characteristics. Failure to meet them can
cause the LSI to malfunction or lose its reliability.
4. Generally, flat package LSIs may have moisture resistance lowered when solder dipped. In mounting LSIs on a board,
it is recommended to use a method which is least unlikely to give thermal stress on the package resin.
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31
5.2 – 5.2
5.2
5.0 Electrical Characteristics
DC CHARACTERISTICS
VDD = 0V, Ta = –20 ~ 75°C
Parameter
Symbol
Operating Recommended
voltage
Allowable
(1)*1
VSS
Recommended
Operating Allowable
voltage
Allowable
(2)
Allowable
High level input voltage
Low level input voltage
V5
Low level output voltage
Min.
Typ.
Max.
–5.5
–5.0
–4.5
–7.0
–2.4
–13.0
–3.5
–13.0
Unit
Applicable
pin
V
VSS
V
V5 *10
V1, V2
0.6 × V5
VDD
V
V1, V2
V3, V4
V5
0.4 × V5
V
V3, V4
VIHT
VSS +
2.0
VDD
VIHC
0.2 × VSS
VDD
VILT
VSS
VSS + 0.8
VILC
VSS
0.8 × VSS
VOHT
High level output voltage
Condition
IOH = –3.0mA
*2
V
*3
V
*2
*3
V
*4
*5
OSC2
V
*4
*5
OSC2
VSS +
2.4
VOHC1 IOH = –2.0mA
VSS + 2.4
VOHC2 IOH = –120µA
0.2 × VSS
VOLT
IOL = 3.0mA
VSS + 0.4
VOLC1
IOL = 2.0mA
VSS + 0.4
VOLC2
IOL = 120µA
0.8 × VSS
Input leakage current
ILI
–1.0
1.0
µA
*6
Output leakage current
ILO
–3.0
3.0
µA
*7
LCD driver ON resistor
RON
Ta = 25°C
KΩ
SEG 0 ~ 79
*11
COM 0 ~ 15
Static current dissipation
IDDQ
µA
VDD
IDD (1)
µA
VDD *12
*13
*14
V5 = –5.0V
Dynamic current dissipation
IDD (2)
Input pin capacitance
CIN
V5 = –3.5V
5.0
7.5
10.0
50.0
CS = CL = VDD
0.05
1.0
fCL = 2KHz
During
display
Rf = 1MΩ
V5 = –5.0V
fCL = 18KHz
2.0
5.0
9.5
15.0
5.0
10.0
During access
tCYC = 200KHz
300
500
µA
*8
Ta = 25°C
f = 1MHz
5.0
8.0
pF
All input
pins
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371-1.0
5.0 Electrical Characteristics
5.2 – 5.2
(Continued)
VDD = 0V, Ta = –20 ~ 75°C
Parameter
Condition
Min.
Typ.
Max.
Rf = 1.0MΩ ± 2%
VSS = –5.0V
15
18
21
Rf = 1.0MΩ ± 2%
VSS = –3.0V
11
16
21
Symbol
Oscillation frequency
Reset time
fOSC
tR
1.0
1000
Unit
Applicable
pin
KHz
*9
µs
RES
Notes:
*1.
Operation over a wide range of voltages is guaranteed except where a sudden voltage
change occurs during access.
Pins A0, D0–D7, E(RD), R/W (WR) and CS
Pins CL, FR, M/S and RES
Pins D0–D7
Pin FR
Pins A0, E (RD), R/W (WR), CS, CL and RES
Applicable when pins D0–D7 and FR are at high impedance.
This value is current consumption when a vertical stripe pattern is written at tCYC. Current
consumption during access is nearly proportionate to access frequency (tCYC). Only TDD (1)
is consumed while no access is made.
Relationship between oscillation frequency, frame and Rf (SED1520FOA)
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
Ta = 25°C
VSS = –5V
Ta = 25°C
VSS = –5V
30
Frame (Hz)
fOSC (kHz)
Duty 1/16, 1/32
200
40
20
100
10
0
371-1.0
0.5
1.0
1.5
Rf (MΩ)
2.0
2.5
0
0.5
1.0 1.5
Rf (MΩ)
2.0
2.5
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5.2 – 5.2
5.0 Electrical Characteristics
Notes (continued):
Relationship between external clock (fCL) and frame (SED1520FAA)
Frame (Hz)
200
1/32
1/16
100
0
1
2
3
fCL (kHz)
*10. Operating voltage ranges of VSS and V5
V5 (V)
–15
–10
Operating
Voltage
Range
–5
0
–2
–4
VSS (V)
–6
–8
*11. Resistance with a voltage of 0.1V applied between the output pin (SEG, COM) and each power pin (V1, V2, V3, V4). It is specified within the operating voltage range.
*12, 13, 14. Current consumed by each discrete IC, not including LCD panel and wiring capacitances.
*12. Applicable to SED1520FAA and SED1521FAA
*13. Applicable to SED1520FOA
*14. Applicable to SED1521FOA
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371-1.0
5.0 Electrical Characteristics
5.3
5.3 – 5.3.1
TIMING CHARACTERISTICS
5.3.1 System Bus Read/Write I (80 Family MPU)
tAH8
A0, CS
tAW8
tCYC8
tCC
WR, RD
tDS8
D0 ~ D7
(WRITE)
tACC8
tDH8
tOH8
D0 ~ D7
(READ)
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: ns
Signal
Symbol
A0, CS
t AH8
t AW8
Address hold time
Address setup time
10
20
WR, RD
t CYC8
t CC
System cycle time
Control pulse width
1000
200
t DS8
Data setup time
80
t DH8
Data hold time
10
t ACC8
RD access time
t OH8
Output disable time
D0–D7
Parameter
Min.
10
Max.
Condition
90
CL = 100pF
60
*1. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
*2. The rise or fall time of input signals should be less than 15 ns.
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5.3.2 – 5.3.2
5.0 Electrical Characteristics
5.3.2 System Bus Read/Write II (68 Family MPU)
tCYC6
E
tAW6
tEW
R/W
tAH6
A0, CS
tDS6
tDH6
D0 ~ D7
(WRITE)
tACC6
tOH6
D0 ~ D7
(READ)
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: ns
Signal
Symbol
A0, CS
R/W
t CYC6*1
t AW6
t AH6
D0–D7
t DS6
Data setup time
80
t DH6
Data hold time
10
tOH6
Output disable time
10
t ACC6
E
t EW
Parameter
Min.
System cycle time
Address setup time
Address hold time
Condition
60
CL = 100pF
1000
20
10
Access time
Enable pulse width
Max.
90
Read
100
Write
80
*1. t CYC6 indicates the cycle time during which CS•E = “H”. It does not mean the cycle time of signal E.
*2. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
*3. The rise or fall time of input signals should be less than 15 ns.
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5.0 Electrical Characteristics
5.3.3 – 5.3.3.2
5.3.3 Display Control Timing
CL
tWLCL
tWHCL
tDFR
tf
tr
FR
5.3.3.1
Input Timing
Ta = –20 to 75°C, VSS = –5.0V ± 10%
Unit: µs (tWLCL, tWHCL, tDFR), ns (tr, tf)
Signal
Symbol
CL
tWLCL
Low level pulse width
35
tWHCL
High level pulse width
35
FR
5.3.3.2
Parameter
Min.
Typ.
Max.
tr
Rise time
30
150
tf
Fall time
30
150
0.2
2.0
tDFR
FR delay time
–2.0
Condition
Output Timing
Ta = –20 to 75°C, VSS = –5.0V ± 10%, Unit: µs
Signal
Symbol
FR
tDFR
Parameter
Min.
FR delay time
Typ.
Max.
Condition
0.2
0.4
CL = 100pF
*1. The listed FR input delay time applies to the SED1521 and SED1520 (slave).
The listed FR output delay time applies to the SED1520 (master).
*2. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value).
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5.3.3.2 – 5.3.3.2
5.0 Electrical Characteristics
THIS PAGE INTENTIONALLY BLANK
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371-1.0
6.0 MPU Interface
6.0
6.1
6.0 – 6.1
MPU INTERFACE
80 FAMILY MPU
VDD
VCC
A0
VCC
A0
A 2 ∼A 7
CS
Decoder
IORQ
MPU
SED1520
D0 ∼ D 7
GND
D0 ∼ D 7
RD
RD
WR
WR
RES
RES
VSS
VS
RESET
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6.2 – 6.2
6.2
6.0 MPU Interface
68 FAMILY MPU
VDD
VCC
A0
VCC
A0
A 0 ∼ A 13
CS
Decoder
VMA
MPU
SED1520
D0 ∼ D 7
D0 ∼ D 7
E
E
GND
R/W
R/W
RES
RES
VSS
VS
RESET
* These examples also apply to the SED1521FOA/SED1521FAA.
* The SED1520 (containing an oscillator) does not have pin CS. The output ORed with CS must be applied to pins A0,
RD (E) and WR (R/W).
A0
Decoder
CS
SED1520FOA
D0~D7
RD(E)
WR(R/W)
RES
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7.0 LCD Driver Interconnections
7.0
LCD DRIVER INTERCONNECTIONS
SED1520FOA - SED1520FOA
FR
OSC2
M/S
OSC1
VDD
FR
COM
To
SEG
LCD
SED1520FOA
Slave
OSC2
To LCD
To
SEG
LCD
SED1520FOA
Master
OSC1
7.1
7.0 – 7.3
To LCD COM
M/S
VSS
Rf
7.2
SED1520FAA - SED1520FAA
To LCD
To
SEG
LCD
SED1520FAA
Master
COM
To
SEG
LCD
SED1520FAA
Slave
To LCD COM
FR
CL
CL
M/S
FR
VDD
M/S
VSS
External Clock
SED1520FOA - SED1521FOA *1
(
Rf
371-1.0
FR
OSC2
OSC1
M/S
FR
VDD
To
SEG
LCD
SED1521FOA
)
COM
OSC2
To LCD
To
SEG
LCD
SED1520FOA
OSC1
7.3
*2
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7.4 – 7.5
7.4
7.0 LCD Driver Interconnections
SED1520FAA - SED1521FAA
To LCD
To
SEG
LCD
SED1520FAA
COM
To
SEG
LCD
SED1521FAA
FR
CL
CL
M/S
FR
VDD
External Clock
HD44103CH - SED1521FAA
To
SEG
LCD
SED1521FAA
Segment Driver
FR
M
CL
To
COM
LCD
HD44103CH
Common Driver
CL
7.5
*1. In this connection, the duty of the SED1521FOA must be the same as that of the SED1520FOA.
*2. A CMOS buffer is needed for a system having two or more slave LSIs.
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8.0 Typical Connections with LCD Panel
8.0
8.1
8.0 – 8.2
TYPICAL CONNECTIONS WITH LCD PANEL
DUTY 1/16, 10 CHARACTERS X 2 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
LCD 16 × 61
16
1
61
SEG
SED1520
COM
8.2
DUTY 1/16, 23 CHARACTERS X 2 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
16
COM
371-1.0
LCD 16 × 141
1
61
62
141
SEG
SEG
SED1520
SED1521
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8.3 – 8.4
8.3
8.0 Typical Connections with LCD Panel
DUTY 1/32, 33 CHARACTERS X 4 LINES
(Full dot LCD panel: 1 character = 6 × 8 dots)
1
LCD 32 × 202
16
17
1
COM
61
62
142
141
202
SEG
SEG
SEG
SED1520
Master
SED1521
SED1520
Slave
32
COM
* SED1521F may be omitted. If it is not used, the panel consists of 32 × 122 dots.
Note: Type AA (using external clock) and type 0A (containing an oscillator) cannot coexist for the same panel.
8.4
DUTY 1/32, 20 KANJI CHARACTERS X 2 LINES
1
LCD 32 × 320
COM
HD44103CH
(Kanji – Character 16 x 16 dots)
32
1
80
81
160
161
240
241
320
SEG
SEG
SEG
SEG
SED1521FAA
(1)
SED1521FAA
(2)
SED1521FAA
(3)
SED1521FAA
(4)
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371-1.0
8.0 Typical Connections with LCD Panel
8.5
8.5 – 8.5
DUTY 1/32, 2–SCREEN DISPLAY, 20 KANJI CHARACTERS X 4 LINES
SED1521FAA
(5)
SED1521FAA
(6)
SED1521FAA
(7)
SED1521FAA
(8)
SEG
SEG
SEG
SEG
COM
64
371-1.0
LCD 64 × 320
32
33
COM
HD44103CH
1
1
80
81
160
161
240
241
320
SEG
SEG
SEG
SEG
SED1521FAA
(1)
SED1521FAA
(2)
SED1521FAA
(3)
SED1521FAA
(4)
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8.5 – 8.5
8.0 Typical Connections with LCD Panel
THIS PAGE INTENTIONALLY BLANK
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371-1.0
9.0 Package Dimensions
9.0
9.1
9.0 – 9.1
PACKAGE DIMENSIONS
PLASTIC QFP 5-100 PIN
25.6 ± 0.4
20 ± 0.1
80
51
Index
100
31
2.7 ± 0.1
1
0.15± 0.05
19.6 ± 0.4
50
14 ± 0.1
81
30
0.65 ±
0.1
0.30 ±
0.1
0 ~12°
1.5 ±0.3
2.8
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9.1 – 9.1
9.0 Package Dimensions
THIS PAGE INTENTIONALLY BLANK
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371-1.0
10.0 Pad Layout
10.0
10.1
10.0 – 10.1
PAD LAYOUT
PAD LAYOUT (SED1520D/SED1521D)
100
1
95
90
85
80
5
75
Y
10
70
15
X
65
7.04 mm
20
60
25
55
SED1520DAA
30
35
40
45
50
4.80 mm
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10.1.1 – 10.1.2
10.0 Pad Layout
10.1.1 Al Pad
Chip Specification
Chip size
Chip thickness
Pad size
Dimensions (mm)
7.04 × 4.80
0.400 ± 0.025
0.10 × 0.10
10.1.2 Au Bump Pad
Chip Specification
Dimensions (mm)
Chip size
7.04 × 4.80
Chip thickness
0.525 ± 0.025
Pad size
0.132 × 0.111
Pad pitch
0.199 min
Bump height
0.020 + 0.01 to –0.005
50 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
371-1.0
10.0 Pad Layout
10.2
10.2 – 10.2
PAD COORDINATES (SED1520DAB)
Pad
X
Y
Pad
Y
SEG3
4641
4148
70
SEG2
4641
4347
159
71
SEG1
4641
4547
1901
159
72
SEG0
4641
4789
SEG33
2100
159
73
A0
4641
5048
40
SEG32
2300
159
74
CS
4641
5247
5310
41
SEG31
2499
159
75
CL
4641
5447
159
5111
42
SEG30
2699
159
76
E(RD)
4641
5646
COM13
159
4911
43
SEG29
2898
159
77
R/W (WR)
4641
5846
10
COM14
159
4712
44
SEG28
3098
159
78
VSS
4641
6107
11
COM15
159
4512
45
SEG27
3297
159
79
DB0
4641
6307
12
SEG60
159
4169
46
SEG26
3497
159
80
DB1
4641
6506
13
SEG59
159
3969
47
SEG25
2696
159
81
DB2
4295
6884
14
SEG58
159
3770
48
SEG24
3896
159
82
DB3
4095
6884
15
SEG57
159
3570
49
SEG23
4095
159
83
DB4
3896
6884
16
SEG56
159
3371
50
SEG22
4295
159
84
DB5
3696
6884
17
SEG55
159
3075
51
SEG21
4641
482
85
DB6
3497
6884
18
SEG54
159
2876
52
SEG20
4641
681
86
DB7
3297
6884
19
SEG53
159
2676
53
SEG19
4641
881
87
VDD
3098
6884
20
SEG52
159
2477
54
SEG18
4641
1080
88
RES
2898
6884
21
SEG51
159
2277
55
SEG17
4641
1280
89
FR
2699
6884
22
SEG50
159
2078
56
SEG16
4641
1479
90
V5
2699
6884
23
SEG49
159
1878
57
SEG15
4641
1679
91
V3
2300
6884
24
SEG48
159
1679
58
SEG14
4641
1878
92
V2
2100
6884
25
SEG47
159
1479
59
SEG13
4641
2078
93
M/S
1901
6884
26
SEG46
159
1280
60
SEG12
4641
2277
94
V4
1701
6884
27
SEG45
159
1080
61
SEG11
4641
2477
95
V1
1502
6884
28
SEG44
159
881
62
SEG10
4641
2676
96
COM0
1302
6884
29
SEG43
159
681
63
SEG9
4641
2876
97
COM1
1103
6884
30
SEG42
159
482
64
SEG8
4641
3075
98
COM2
903
6884
31
SEG41
504
159
65
SEG7
4641
3275
99
COM3
704
6884
32
SEG40
704
159
66
SEG6
4641
3474
100
COM4
504
6884
33
SEG39
903
159
67
SEG5
4641
3674
34
SEG38
1103
159
68
SEG4
4641
3948
Name
1
COM5
159
2
COM6
3
Y
Pad
X
No.
X
No.
Name
No.
Name
6507
35
SEG37
1302
159
69
159
6308
36
SEG36
1502
159
COM7
159
6108
37
SEG35
1701
4
COM8
159
5909
38
SEG34
5
COM9
159
5709
39
6
COM10
159
5510
7
COM11
159
8
COM12
9
371-1.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
51
10.2 – 10.2
10.0 Pad Layout
S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
October 1996
© Copyright 1996 S-MOS Systems, Inc.
Printed in U.S.A.
52 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
371-1.0
371-1.0