Standard ICs Picture cell driver for STN (LCD driver) BU9716BK / BU9716BKV The BU9716BK and BU9716BKV are man-machine interface ICs designed for applications such as multi-media portable terminals. Specifically, these products are used as driver ICs for operating mode display LCD panels in portable terminals, household appliances, and other similar products. The number of display cells includes 32 segments and 3 commons, enabling drive of up to 96 cells. Applications •Multi-media portable terminals, POS terminals, ECR terminals, short wave radios, telephones, cameras, VCRs, movie projectors, car audio systems, and others •1)Features Up to 32 segment outputs and 3 common outputs 3) Either 1 / 2 or 1 / 3 can be selected for power supply for LCD display. can be displayed, for a total of 96 segments. 2) 1 / 3 duty display. •Absolute maximum ratings (Ta = 25°C, V SS Parameter Power supply voltage Power dissipation BU9716BK BU9716BKV Input voltage = 0V) Symbol Limits Unit VDD – 0.3 ~ + 7.0 V 500∗1 Pd mW 400∗2 VIN – 0.3 ~ VDD + 0.3 Operating temperature Topr Storage temperature Tstg V °C – 40 ~ + 85 °C – 55 ~ + 125 ∗1 Reduced by 5mW for each increase in Ta of 1°C over 25°C . ∗2 Reduced by 4mW for each increase in Ta of 1°C over 25°C . •Recommended operating conditions (Ta = 25°C, V SS Parameter Power supply voltage Input voltage Symbol Min. = 0V) Typ. Max. Unit VDD 4.5 — 5.5 V VDD1 0 2 / 3VDD VDD V VDD2 0 1 / 3VDD VDD V 1 Standard ICs BU9716BK / BU9716BKV •Block diagram VDD1 LCD Power VDD2 RES CS CTRL Logic DATA Latch DI CK OSC OSC S32 36 34 22 25 37 24 N.C. S22 COM3 S22 COM3 S21 RES S21 RES S20 VDD S20 VDD S19 VDD1 S19 VDD1 S18 VDD2 S17 VSS VSS S16 OSC S16 OSC S15 CS S15 CS S14 CK S14 CK S13 DI S12 N.C. S11 S10 S9 S8 S7 N.C. 12 1 S5 S9 S10 S8 S7 S6 S5 S4 S3 S2 S1 S13 13 S6 11 1 S17 48 S4 12 S3 44 S2 DI S18 BU9716BKV S1 BU9716BK VDD2 S11 COM2 2 COM2 23 33 N.C. S31 S23 S30 S25 S26 S27 S28 S29 S24 S4 S30 S31 S32 COM1 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 COM1 •Pin assignments S3 S2 S1 Segment Driver COM3 COM2 COM1 Common Driver S12 Standard ICs BU9716BK / BU9716BKV •Pin descriptions (BU9716BK) Pin No. Pin name I / O Processing when not used Function 1 - 32 S1 - S32 O Output pin for segment data. Outputs consistent LCD drive voltage to the data corresponding to COM1 to COM3. OPEN 33 34 35 COM1 COM2 COM3 O Common driver output. The frame frequency is fC = (fOSC / 384) Hz OPEN 36 RES I Reset input. At RES = L, internal data (including control data) is reset. VDD 41 OSC — Oscillator pin (for common and segment alternating waveforms) VSS 42 CS I Chip select input. At CS = H, data can be transferred. VSS 43 CK I Synchronous clock input for serial data transfer VSS 44 DI I Serial data input VSS 38 VDD1 — Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to VDD2. OPEN 39 VDD2 — Internal reference voltage for LCD drive. In 1 / 2 bias mode, this is connected to VDD1. OPEN •Electrical characteristics (unless otherwise noted, Ta = 25°C, V DD Parameter Symbol Min. Input high level voltage VIH 0.8VDD Input low level voltage VIL 0 Input high level current IIH 0 Input low level current IIL 0 Output high level voltage Output low level voltage Intermediate output voltage Power supply current Typ. = 4.5V to 5.5V, VSS = 0V) Max. Unit Conditions — VDD V CS, CK, DI, RES — 0.2VDD V CS, CK, DI, RES — 6.0 µA CS, CK, DI, RES, VI = VDD — 6.0 µA CS, CK, DI, RES, VI = VSS VSOH — VDD – 1.0 — V S1 ~ S32, IO = – 20µA VCOH — VDD – 1.0 — V COM1 ~ COM3, IO = – 100µA VSOL — 1.0 — V S1 ~ S32, IO = – 20µA VCOL — 1.0 — V COM1 ~ COM3, IO = – 100µA VCM1 — 1 / 2VDD ± 1.0 — V COM1 ~ COM3, 1 / 2Bias VSM1 — 2 / 3VDD ± 1.0 — V S1 ~ S32, 1 / 3Bias VCM2 — 2 / 3VDD ± 1.0 — V COM1 ~ COM3, 1 / 3Bias VSM2 — 1 / 3VDD ± 1.0 — V S1 ~ S32, 1 / 3Bias VCM3 — 1 / 3VDD ± 1.0 — V COM1 ~ COM3, 1 / 3Bias IQ — 30 70 µA Low-power mode IDD — 100 300 µA fOSC = 38kHz 3 Standard ICs BU9716BK / BU9716BKV characteristics •ACElectrical characteristics (unless otherwise noted, Ta = 25°C, V = 4.5V to 5.5V, VSS = 0V) DD Parameter Symbol Pin Min. Typ. Max. Unit R OSC — 47 — kΩ Recommended external resistance Recommended external capacitance C OSC — 1000 — pF fOSC OSC 19 38 76 kHz Data setup time tDS CK, DI 100 — — ns Data hold time tDH CK, DI 100 — — ns Guaranteed oscillation range CS setup time tCS CS, CK 100 — — ns CS hold time tCH CS, CK 100 — — ns CK "H" pulse width tCKH CK 100 — — ns CK "L" pulse width tCKL CK 100 — — ns Rise time tr CS, CK, DI — — 300 ns Fall time tf CS, CK, DI — — 300 ns AC timing waveform (1) When CK is stopped at “L” 0.8VDD tCS CS tCKH 0.8VDD tDS tCH 0.2VDD 0.8VDD 0.5VDD CK tCKL 0.5VDD tDH 0.2VDD tr tf DI (2) When CK is stopped at “H” 0.8VDD CS CK tCS tCKH 0.2VDD 0.5VDD tDS DI 4 tDH tCKL 0.8VDD 0.2VDD 0.5VDD tr tf tCH 0.2VDD Standard ICs BU9716BK / BU9716BKV •Measurement circuit IDD, IQ VDD 1 P. G. SW4 A A CS, CK DI, RES 2 S1 ~ S32 IIH, LH 1 SW2 SW1 1 V1 2 V2 1 SW3 COM1 ~ COM3 VDD1 2 0.047µF 3 2 VDD2 OSC VCM1, VCM2, VCM3 VSM1, VSM2 V IO 0.047µF V VSOH, VSOL VCOH, VCOL VSS 1000pF, 47kΩ GND GND ∗ P. G.: Control signal generator for programmable signal generator, etc. Fig.1 Measurement conditions Parameter Symbol Input high level voltage VIH Input low level voltage VIL Input high level current IIH Input low level current Output high level voltage Output low level voltage IIL VSOH VCOH VSOL VCOL SW1 SW2 SW3 SW4 2 — — 1 2 — — 2 1 3 2 1 3 2 VCM1 2 VSM1 Intermediate output voltage Current dissipation VCM2 2 1 VCM3 2 IDD AC characteristics 2 1 1 2 Set as P.G. input voltage; mode switching test V2 = VDD V2 = VSS Pattern 1, IO = – 20µA Pattern 1, IO = – 100µA Pattern 2, IO = 20µA Pattern 2, IO = 100µA Pattern 3 1 1 VSM2 IQ 1 Conditions Pattern 4 1 1 Pattern 4 Pattern 5 Pattern 5 2 — — 1 2 — — 1 Pattern 6 Test after power on Used as P.G. input condition Measurement pattern CS DI CS DI CK CS DI CK CS DI CK Fig.5 Fig.4 CS DI CK Pattern 4 Pattern 3 Fig.3 Fig.2 CS DI CK Pattern 2 Pattern 1 CK Pattern 5 Fig.6 Pattern 6 Fig.7 5 Standard ICs BU9716BK / BU9716BKV Circuit operation •Timing charts (1) When CK is stopped at “L” CS CK DI D1 D2 D3 D96 0 0 0 Display data 0 0 BM LC OE Control code Fig.8 When CS is HIGH, data can be transferred. Data is sent to the shift register at the rising edge of CK. After all of the DI data has been transferred, CS should be set to LOW. The voltage corresponding to the display data transferred at the falling edge of CS is output. (2) When CK is stopped at “H” CS CK DI D1 D2 D3 D96 0 0 Display data 0 0 Control code Fig.9 Control code table OE 0 1 Output enable control Normal operation All display data is 0; no display (internal oscillation circuit is operating) BM 0 1 1 / 3 bias 1 / 2 bias LC 0 1 6 0 Bias mode control Low power mode control Normal operation Low power mode = The internal oscillation circuit stops oscillating, and segment and common output = 0 BM LC OE Standard ICs BU9716BK / BU9716BKV Correspondence between display data input and segments Segment S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 COM3 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 COM1 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 Segment S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 COM3 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 COM2 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 COM1 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 7 Standard ICs •Timing chart BU9716BK / BU9716BKV fO = fOSC / 384 fO = fOSC / 384 VDD COM 1 VDD VDD1 VDD2 VSS VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD COM 2 VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD COM 3 VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when all LCD segments for COM1, 2, and 3 are out VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when only the LCD segment for COM1 is lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when only the LCD segment for COM2 is lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when the LCD segments for COM1 and 2 are lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when only the LCD segment for COM3 is lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when the LCD segments for COM1 and 3 are lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when the LCD segments for COM2 and 3 are lit up VDD1, VDD2 VSS VDD VDD1 VDD2 VSS VDD LCD driver output when all the LCD segments for COM1, 2 and 3 are lit up VDD1, VDD2 VSS 1 / 2 bias 1 / 3 duty waveform Fig.10 8 1 / 3 bias 1 / 3 duty waveform Standard ICs BU9716BK / BU9716BKV •Application example 1 47kΩ 1000pF GND OSC VDD VDD COM1 COM2 RES COM3 VSS S1 VDD1 VDD2 S2 BU9716BK / BKV Controller 96 S3 Segment S4 LCD S5 C ⭌ 0.047µF S6 CS CK S32 DI 1 / 2 bias mode Fig.11 47kΩ 1000pF GND OSC VDD VDD COM1 COM2 RES COM3 VSS S1 VDD1 C ⭌ 0.047 µF VDD2 S2 BU9716BK / BKV Controller S3 96 Segment S4 LCD S5 C ⭌ 0.047µF S6 CS CK S32 DI 1 / 3 bias mode Fig.12 9 Standard ICs BU9716BK / BU9716BKV •Application example 2 47kΩ 1000pF GND OSC VDD VDD COM1 COM2 RES ∗1 COM3 VSS S1 R Controller VDD1 S2 VDD2 S3 R BU9716BK / BKV 96 Segment S4 LCD S5 C ⭌ 0.047µF S6 CS CK S32 DI 1 / 2 bias mode Fig.13 47kΩ 1000pF GND OSC VDD VDD COM1 COM2 RES ∗2 R COM3 VSS S1 VDD1 S2 R VDD2 Controller S3 BU9716BK / BKV R 96 Segment S4 LCD S5 C ⭌ 0.047µF S6 CS CK S32 DI 1 / 3 bias mode Fig. 14 The resistance values and capacitance for∗1 and ∗2 should be set to match the LCD panel, and should be checked using test operation. 10 Standard ICs BU9716BK / BU9716BKV Make sure of the following when resetting when the power is on. • When using the external reset terminal, make RST = “L” at 1 ms or more with VDD at 1.8V or more. • When not using the external reset terminal, VDD has to satisfy the following conditions. Instruction receipt possible VDD ⭌ 1.8V tWAIT ⭌ 1ms VDD < 0.3V 0 < tON < 10ms •External dimensions (Units: mm) BU9716BK BU9716BKV 0.8 11 0.35 ± 0.1 QFP44 0.15 ± 0.1 0.15 37 25 24 48 13 1 0.5 12 0.5 7.0 ± 0.2 9.0 ± 0.3 12 1.425 ± 0.1 0.10 44 1 2.15 ± 0.1 36 22 34 0.05 9.0 ± 0.3 7.0 ± 0.2 1.2 10.0 ± 0.2 14.0 ± 0.3 14.0 ± 0.3 10.0 ± 0.2 33 23 0.125 ± 0.1 0.2 ± 0.1 0.10 VQFP48 11