A 50MHz-16GHz Low Distortion SOI
Voltage Controlled Attenuator IC with IIP3 >
+38dBm and Control Range of > 25dB
Ed Franzwa, Alan Ellis, Brad Nelson, Marcus Granger-Jones and Greg Valenti
Outline
• Motivation
• Technical Approach
• Circuit Design
• Analysis of Distortion
• Mechanical and Thermal Design
• Measured Results
• Conclusions
Motivation & Requirement
Broadband Voltage Controlled Attenuator
• General Purpose and wideband up to 16GHz apps
• Test equipment, military equipment, wideband apps
• Very high linearity IIP3 > +38dBm
• Attenuation range > 25dB
• Temperature compensated
• Linear in dB control
Low cost and easy to use
• MMIC silicon implementation
• Eliminate pin diodes
• No discrete external support circuitry
Technical Approach
SOI CMOS Attenuator MMIC
• Low cost process
• Based on „Pi‟ & „T‟ attenuators
• Integrated bias control
• No external components or module
• Low parasitic capacitance on SOI
Stacked FET techniques
• Distributed RF signal
• IIP3 proportional to 20log{Nstack}
Flip chip
• Low parasitic inductance
• High volume low cost plastic package
Functional Block Diagram
Attenuator Structure
T Attenuator Structure
Control B
Control C
. . x N Series . .
Devices
. . x N Series . .
Devices
. . x N Series . .
Devices
RFOUT
RFIN
2 x N Shunt
Devices
x N Shunt
Devices
Control A
x N Shunt
Devices
Control D
RFIN
Attenuation
Stage 1
Attenuation
Stage 2
Vcontrol
Vbg / R
generator
Preconditioning
Stage
Control A
Control B
Control C
Control D
RFOUT
Controlling Distortion in RF Section Design
Attenuator Type
• Selection of attenuator topology and position for multi-stage
design
Relative sequencing of threshold (VGS) crossing
• Threshold sequencing for series and shunt RF FETs
Physical resistors in RF sections
• Careful placement of physical resistors moves the threshold
(VGS) crossing of RF FETs versus absolute attenuation
Distortion Analysis
Reference “Intermodulation Distortion in
CMOS Attenuators & Switches” H. Dogan &
R. Meyer JSSC 03/07
Reference [1] “A Broadband High Dynamic
Range Voltage Controlled Attenuator MMIC
with IIP3 > 47dBm over entire analog control
range”
M. Granger-Jones, IMS 2011, TU2G-1
Assumptions
- Gate current insignificant – very large gate resistors
- Substrate current insignificant – insulating oxide layer
- Vds across each device is equal
Why We Get Such High Bandwidth
Plastic Mold Compound
Handle wafer
High Resistivity Handle Wafer
1kohm-cm
Csb
BOX
Buried Oxide
Device
Layer
Cgd
Cgs
Low parasitic C
due to thick
Buried Oxide layer
Cgs, Cgd, Csb & Cdb
in series with
high value resistor
Rb
gnd
Rg
Flip Chip - No wire bonds
Vgdc
Flip Chip Die and Package
Open Top Package (no over mold)
Bumped Die Photo
RF In
RF Out
Package:
• 16 Pin 3x3 mm QFN
footprint
• 4 layer laminate
• Filled Cu vias
• SMD‟s optional
Thermal Design
• Flip chip SOI devices inherently
have a long cooling path to the
outside world.
• Heat dissipating features are
fabricated on thin, low conductivity
structures.
THERMAL
CONDUCTIVITY THICKNESS
MATERIAL
(W/mK)
(um)
Si handle wafer
140
150.0
Si active layer
0.145
140
SiO2 BOX layer
1.5
1.000
SiO2 bump layer
1.5
6.920
Heat path is across die and
passivation, through solder bumps, and
into the package substrate (not shown).
• Heat dissipating structure
Temperature Prediction and Measurement
RF Input Power 24dBm, 85°C PCB Temperature
• Finite element simulation including die, • Measured IR scan results
bump, and substrate.
• View is from die backside and through
• Simulation peak temperature is 127°C die.
• Peak temperature of 124°C
Test PCB
PCB characteristics
• CPW transmission lines using low
loss dielectric material
• CPW to module transition
optimized with EM analysis
• Each PCB includes test coupon for
loss de-embedding
•
1.3dB loss at 16GHz
•
17dB return loss connector launches
at 16GHz
Insertion Loss vs. Control Voltage
Vdd= 3.3V
Attenuation vs Control Voltage over Temperature (7GHz)
0
Attenuation (dB)
-5
Linear in dB
Control Voltage
Characteristic
-10
-15
-20
25C
-25
-40C
-30
85C
-35
-40
0
1
2
3
Control Voltage (V)
4
5
Insertion Loss vs. Frequency
Insertion Loss, Temp 25C, 0.2V Steps
0
3dB BW
~ 16GHz
-5
S21 (dB)
-10
-15
-20
-25
-30
Atten Range
~ 25dB
-35
-40
0
2000
4000
6000
8000
10000 12000 14000 16000 18000 20000
Frequency (MHz)
Note: PCB Loss De-embedded (1.3dB at 16GHz)
Input IP3 vs. Control Voltage
IIP3 vs Control Voltage vs Temp
75
0
70
5
65
10
60
15
55
20
50
25
Attenuation (dB)
IIP3 (dBm)
7GHz and 7.001GHz
Pin=+17dBm/tone
45
Upper_25C
40
Upper_-40C
35
Upper_85C
30
0
0.5
1
Attenuator stage handoff
1.5
2
2.5
3
Control Voltage (V)
3.5
4
4.5
5
First stage Shunt FET control at VTH
Input Return Loss vs. Freq. and Attenuation
Input Return Loss, Temp 25C
Worst Case
-7.1dB
0
-5
S11 (dB)
-10
-15
-20
-25
-30
-35
-40
0
2000
4000
6000
8000
10000 12000 14000 16000 18000 20000
Frequency (MHz)
Output Return Loss vs. Freq. and Attenuation
Output Return Loss, Temp 25C
Worst Case
-8.2dB
0
-5
-10
S22 (dB)
-15
-20
-25
-30
-35
-40
0
2000
4000
6000
8000
10000 12000 14000 16000 18000 20000
Frequency (MHz)
Performance Comparison
Units
This Work
Prototype
Reference
Sun
Poitrenaud
HMC712LP3C
TGL4203-SM
[2]
[5]
[3]
[4]
Freq Range
(GHz)
0.05-16
2-18
5-30
5-26.5GHz
DC-30
IIP3 vs atten WC
(dBm)
38
NA
27
31
19
Atten Range
(dB)
25
13
25
28
17
Insertion Loss WC
(dB)
5.0
2.7
5.5
5.0
2
Current
(mA)
1.2
near zero
near zero
near zero
near zero
IP1dB
(dBm)
>25
26
25
NA
10
Temp stability WC
(dBp-p)
1.7
NA
NA
2
0.9
GaAs MESFET
LF QFN 3x3
0.25um PHEMT
LF QFN 3x3
Technology
Package
Difficulty
# Control lines
(mm)
CMOS SOI
GaAs MESFET GaAs MESFET
Lam QFN 3x3
Bare Die
LF QFN 3x3
Simple
Moderate
Moderate
Moderate
Difficult
1
1
2
2
2
Input IP3 vs. Frequency
Worst Case Input IP3 at 25C
45
Input IP3 (dBm)
40
35
30
25
20
15
0
2
4
6
8
10
12
14
16
Frequency(GHz)
Worst case IIP3 across entire attenuation
range at each frequency
Tested at 10dBm input power per tone
18
38.5dBm
min thru
16GHz
Summary
• Quantum leap forward in performance & cost
• Very linear, IIP3 > +38dBm
• Low current of 1.2mA
• Small size, 3x3 laminate module
• Low cost SOI CMOS process
• Temperature Compensated
• One broadband MMIC addresses multiple applications
• 50MHz to 16GHz
• Architecture able to trade IP3 for BW
• Ready for higher levels of CMOS integration
• Plug & Play!
• No external components
• Inherently good performance over PVT