Rev. 1.41, Dec. 2014 K4A4G045WD K4A4G085WD 4Gb D-die DDR4 SDRAM 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) 1.2V datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. (C) 2014 Samsung Electronics Co., Ltd.GG All rights reserved. -1- Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Revision History Revision No. History Draft Date Remark Editor 1.0 - First SPEC release Feb. 2014 - S.H.Kim 1.1 - Add x8 Product Feb. 2014 - S.H.Kim 1.2 - Add IDD & IPP value of x8GProduct. May. 2014 - S.H.Kim - Change IPP Value of x4 Product. 1.21 - Corrected typo. Jun. 2014 - S.H.Kim 1.3 - Change [Table 3] Input/Output function description on page 8~9 Sep. 2014 - J.Y.Lee Sep. 2014 - J.Y.Lee Dec. 2014 - J.Y.Lee - Change [Table 8] Allowed time before ringback(tDVAC) for CK_t - CK_c on page 13 - Add Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ) on page 18 - Change Alert_n output Drive Characteristic on page 26 - Change Speed Bin on page 31~34 - Change IDD, IPP and IDDQ Measurement Conditions on page 35 - Change [Table 34] Timings used for IDD, IPP and IDDQ MeasurementLoop Patterns on page 37 - Change [Table 41] IDD4W, IDD4WA, IDD4WB and IDD4W_par Measure ment-Loop Pattern on page 46 - Change [Table 42] IDD4WC Measurement-Loop Pattern on page 47 - Change [Table 48] Silicon pad I/O Capacitance on page 52 - Change [Table 52] Timing Parameters by Speed Grade - Change The DQ input receiver compliance mask for voltage and timing on page 62 - Change [Figure 26] DQS to DQ and DQ to DQ Timings at DRAM Balls on page 62 - Delete [Figure 25] DQS to DQS Timings at DRAM latch - Delete [Figure 26] DQ TdlPW and SRIN_divw defintion - Add [Figure 27] Slew Rate Conditions For Rising Transition on page 63 - Add [Figure 28] Slew Rate Conditions For Falling Transition on page 63 - Change [Table 52] DRAM DQs In Receive Mode on page 64 - Change [Table 53] Function Matrix on page 65 1.4 - Add DRAM Data Timing (tDVWd , tDVWp ) on page 56 - Change FBGA Package Dimension on page 7 1.41 - Corrected typo. -2- K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM Table Of Contents 4Gb D-die DDR4 SDRAM 1. Ordering Information .....................................................................................................................................................4 2. Key Features.................................................................................................................................................................4 3. Package pinout/Mechanical Dimension & Addressing..................................................................................................5 3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 5 3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6 3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 7 4. Input/Output Functional Description..............................................................................................................................8 5. DDR4 SDRAM Addressing ...........................................................................................................................................10 6. Absolute Maximum Ratings ..........................................................................................................................................11 7. AC & DC Operating Conditions.....................................................................................................................................11 8. AC & DC Input Measurement Levels ...........................................................................................................................12 8.1 AC & DC Logic Input Levels for Single-ended Signals ............................................................................................ 12 8.2 VREF Tolerances .................................................................................................................................................... 12 8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 13 8.3.1. Differential Signals Definition ........................................................................................................................... 13 8.3.2. Differential Swing Requirement for Clock (CK_t - CK_c) ................................................................................. 13 8.3.3. Single-ended Requirements for Differential Signals ........................................................................................ 14 8.3.4. Address, Command and Control Overshoot and Undershoot Specifications................................................... 15 8.3.5. Clock Overshoot and Undershoot Specifications ............................................................................................. 15 8.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications ................................................................. 16 8.4 Slew Rate Definitions .............................................................................................................................................. 17 8.4.1. Slew Rate Definitions for Differential Input Signals (CK) ................................................................................. 17 8.4.2. Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ).................................................................. 18 8.5 Differential Input Cross Point Voltage...................................................................................................................... 19 8.6 CMOS Rail to Rail Input Levels ............................................................................................................................... 20 8.6.1. CMOS Rail to Rail Input Levels for RESET_n ................................................................................................. 20 8.7 AC and DC Logic Input Levels for DQS Signals...................................................................................................... 21 8.7.1. Differential Signal Definition ............................................................................................................................. 21 8.7.2. Differential Swing Requirements for DQS (DQS_t - DQS_c) ........................................................................... 21 8.7.3. Peak Voltage Calculation Method .................................................................................................................... 21 8.7.4. Differential Input Cross Point Voltage .............................................................................................................. 22 8.7.5. Differential Input Slew Rate Definition.............................................................................................................. 23 9. AC and DC Output Measurement Levels......................................................................................................................24 9.1 Output Driver DC Electrical Characteristics............................................................................................................. 24 9.1.1. Alert_n Output Drive Characteristic.................................................................................................................. 26 9.1.2. Output Driver Characteristic of Connectivity Test ( CT ) Mode ........................................................................ 26 9.2 Single-ended AC & DC Output Levels..................................................................................................................... 27 9.3 Differential AC & DC Output Levels......................................................................................................................... 27 9.4 Single-ended Output Slew Rate .............................................................................................................................. 28 9.5 Differential Output Slew Rate .................................................................................................................................. 29 9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode .......................................................................... 30 9.7 Test Load for Connectivity Test Mode Timing ......................................................................................................... 30 10. Speed Bin ...................................................................................................................................................................31 10.1 Speed Bin Table Note ........................................................................................................................................... 34 11. IDD and IDDQ Specification Parameters and Test Conditions ...................................................................................35 11.1 IDD, IPP and IDDQ Measurement Conditions....................................................................................................... 35 11.2 4Gb DDR4 SDRAM D-die IDD Specification Table ............................................................................................... 50 12. Input/Output Capacitance ...........................................................................................................................................52 13. Electrical Characteristics & AC Timing .......................................................................................................................54 13.1 Reference Load for AC Timing and Output Slew Rate .......................................................................................... 54 13.2 tREFI ..................................................................................................................................................................... 54 13.3 Timing Parameters by Speed Grade ..................................................................................................................... 55 13.4 The DQ Input Receiver Compliance Mask for Voltage and Timing ....................................................................... 61 13.5 DDR4 Function Matrix ........................................................................................................................................... 65 -3- Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 1. Ordering Information [ Table 1 ] Samsung 4Gb DDR4 D-die ordering information table Organization DDR4-2133 (15-15-15) DDR4-2400 (17-17-17)2 Package 1Gx4 K4A4G045WD-BCPB K4A4G045WD-BCRC 78 FBGA 512Mx8 K4A4G085WD-BCPB K4A4G085WD-BCRC 78 FBGA NOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. Backward compatible to DDR4-2133(15-15-15) 2. Key Features [ Table 2 ] 4Gb DDR4 D-die Speed bins Speed DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 11-11-11 13-13-13 15-15-15 17-17-17 Unit tCK(min) 1.25 1.071 0.938 0.833 ns CAS Latency 11 13 15 17 nCK tRCD(min) 13.75 13.92 14.06 14.16 ns tRP(min) 13.75 13.92 14.06 14.16 ns tRAS(min) 35 34 33 32 ns tRC(min) 48.75 47.92 47.06 46.16 ns • JEDEC standard 1.2V (1.14V~1.26V) • VDDQ = 1.2V (1.14V~1.26V) • 800 MHz fCK for 1600Mb/sec/pin,933 MHz fCK for 1866Mb/sec/pin, 1067MHz fCK for 2133Mb/sec/pin, 1200MHz fCK for2400Mb/sec/pin • 16 Banks (4 Bank Groups) • Programmable CAS Latency(posted CAS): 10,11,12,13,14,15,16,17,18 • Programmable Additive Latency: 0, CL-2 or CL-1 clock • Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866) ,11,14 (DDR4-2133) and 12,16 (DDR4-2400) • 8-bit pre-fetch • Burst Length: 8, 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS] • Bi-directional Differential Data-Strobe • Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%) The 4Gb DDR4 SDRAM D-die is organized as a 64Mbit x 4 I/Os x 16banks or 32Mbit x8 I/Os x 16banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 2400Mb/sec/pin (DDR42400) for general applications. The chip is designed to comply with the following key DDR4 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR4 device operates with a single 1.2V (1.14V~1.26V) power supply and 1.2V (1.14V~1.26V) . The 4Gb DDR4 D-die device is available in 78ball FBGAs(x4/x8). • On Die Termination using ODT pin • Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95 C • Asynchronous Reset • • • • • • • • • • • Package : 78 balls FBGA - x4/x8 All of Lead-Free products are compliant for RoHS All of products are Halogen-free CRC(Cyclic Redundancy Check) for Read/Write data security Command address parity check DBI(Data Bus Inversion) Gear down mode POD (Pseudo Open Drain) interface for data input/output Internal VREF for data inputs External VPP for DRAM Activating Power PPR is supported NOTE : 1. This data sheet is an abstract of full DDR4 specification and does not cover the common features which are described in “DDR4 SDRAM Device Operation & Timing Diagram”. 2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. -4- Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 3. Package pinout/Mechanical Dimension & Addressing 3.1 x4 Package Pinout (Top view) : 78ball FBGA Package 1 2 3 A VDD VSSQ B VPP C 7 8 9 NC NC VSSQ VSS A VDDQ DQS_c DQ1 VDDQ ZQ B VDDQ DQ0 DQS_t VDD VSS VDDQ C D VSSQ NC DQ2 DQ3 NC VSSQ D E VSS VDDQ NC NC VDDQ VSS E F VDD NC ODT CK_t CK_c VDD F G VSS NC CKE CS_n NC NC G H VDD WE_n A14 ACT_n RAS_n VSS H VREFCA BG0 A10 AP CAS_n A15 A12 BC_n BG1 VDD J K VSS BA0 A4 A3 BA1 VSS K L RESET_n A6 A0 A1 A5 ALERT_n L M VDD A8 A2 A9 A7 VPP M N VSS A11 PAR NC A13 VDD N J 4 5 6 1 Ball Locations (x4) A B C Populated ball Ball not populated D E F G H Top view (See the balls through the package) J K L M N -5- 2 3 4 5 6 7 8 9 Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 3.2 x8 Package Pinout (Top view) : 78ball FBGA Package 1 2 3 7 8 9 VDD VSSQ TDQS_c DM_n, DBI_n, TDQS_t VSSQ VSS A B VPP VDDQ C VDDQ DQ0 DQS_c DQ1 VDDQ ZQ B DQS_t VDD VSS VDDQ D VSSQ C DQ4 DQ2 DQ3 DQ5 VSSQ E D VSS VDDQ DQ6 DQ7 VDDQ VSS E F VDD NC ODT CK_t CK_c VDD F G VSS NC CKE CS_n NC NC G H VDD WE_n A14 ACT_n CAS_n RAS_n VSS H J VREFCA BG0 A10 AP A12 BC_n BG1 VDD J K VSS BA0 A4 A3 BA1 VSS K L RESET_n A6 A0 A1 A5 ALERT_n L M VDD A8 A2 A9 A7 VPP M N VSS A11 PAR NC A13 VDD N A 4 5 6 1 Ball Locations (x8) A B C Populated ball Ball not populated D E F G H Top view (See the balls through the package) J K L M N -6- 2 3 4 5 6 7 8 9 Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 3.3 FBGA Package Dimension (x4/x8) 0.80 x 8 6.40 0.80 (Datum A) 1.60 Units : Millimeters A #A1 INDEX MARK 3.20 B 0.80 0.80 (Datum B) 4.80 A B C D E F G H J K L M N 0.80 x12 = 9.60 9 8 7 6 5 4 3 2 1 11.00 0.10 7.50 0.10 78 - 0.48 Solder ball (Post Reflow 0.50 0.05) 0.2 M A B 0.10MAX BOTTOM VIEW 7.50 0.10 11.00 0.10 #A1 0.37 0.05 1.10 0.10 TOP VIEW -7- Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 4. Input/Output Functional Description [ Table 3 ] Input/Output function description Symbol Type CK_t, CK_c Input CKE, (CKE1) Input CS_n, (CS1_n) Input C0,C1,C2 Input ODT, (ODT1) Input ACT_n Input RAS_n/A16. CAS_n/ A15. WE_n/A14 Input DM_n/DBI_n/TDQS_t, (DMU_n/DBIU_n), (DML_n/DBIL_n) Input/Output BG0 - BG1 Input BA0 - BA1 Input A0 - A17 Input A10 / AP Input A12 / BC_n Input RESET_n Input DQ Input / Output DQS_t, DQS_c, DQSU_t, DQSU_c, DQSL_t, DQSL_c Input / Output Function Clock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c. Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, they must be maintained during all operations (including Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK_t,CK_cSGODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self-Refresh. Chip Select: All commands are masked when CS_n is registered HIGH. CS_n provides for external Rank selection on systems with multiple Ranks. CS_n is considered part of the command code. Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked component. Chip ID is considered part of the command code On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the DDR4 SDRAM. When enabled, ODT is only applied to each DQ, DQS_t, DQS_c and DM_n/DBI_n/ TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 conurations. For x16 conuration ODT is applied to each DQ, DQSU_t, DQSU_c, DQSL_t, DQSL_c, DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM. Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14 Command Inputs: RAS_n/A16, CAS_n/A15 and WE_n/A14 (along with CS_n) define the command being entered. Those pins have multi function. ForG example, for activation with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command defined in command truth table Input Data Mask and Data Bus Inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on both edges of DQS. DM is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only supported in X8 Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command is being applied. BG0 also determines which mode register is to be accessed during a MRS cycle. X4/8 have BG0 and BG1 but X16 has only BG0 Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines which mode register is to be accessed during a MRS cycle. Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/ Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/ BC_n, RAS_n/A16, CAS_n/A15 and WE_n/A14 have additional functions, see other rows.The address inputs also provide the op-code during Mode Register Set commands.A17 is only defined for the x4 conuration. Auto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by bank addresses. Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-thefly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details. Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD, Data Input/ Output: Bi-directional data bus. If CRC is enabled via Mode register then CRC code is added at the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor specific datasheets to determine which DQ is used. Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended. -8- Symbol Rev. 1.41 datasheet K4A4G045WD K4A4G085WD Type TDQS_t, TDQS_c Output PAR Input ALERT_n Input/Output TEN Input DDR4 SDRAM Function Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/ TDQS_c that is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/ TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1. Command and Address Parity Input : DDR4 Supports Even Parity check in DRAM with MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/ A14,BG0-BG1,BA0-BA1,A17-A0, and C0-C2 (3DS devices). Input parity should maintain at the rising edge of the clock and at the same time with command & address with CS_n LOW Alert : It has multi functions such as CRC error flag , Command and Address Parity error flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as input. Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin must be bounded to VDD on board. Connectivity Test Mode Enable : Required on X16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. No Connect: No internal electrical connection is present. NC VDDQ Supply DQ Power Supply: 1.2 V +/- 0.06 V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.2 V +/- 0.06 V VSS Supply Ground VPP Supply DRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max) VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration NOTE Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supply termination. -9- Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 5. DDR4 SDRAM Addressing 2 Gb Addressing Table Configuration Bank Address 512 Mb x4 256 Mb x8 128 Mb x16 # of Bank Groups 4 4 2 BG Address BG0~BG1 BG0~BG1 BG0 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A14 A0~A13 A0~A13 Column Address A0~A9 A0~A9 A0~A9 Page size 512B 1KB 2KB 4 Gb Addressing Table Configuration Bank Address 1 Gb x4 512 Mb x8 256 Mb x16 # of Bank Groups 4 4 2 BG Address BG0~BG1 BG0~BG1 BG0 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A15 A0~A14 A0~A14 Column Address A0~A9 A0~A9 A0~A9 Page size 512B 1KB 2KB 8 Gb Addressing Table Configuration Bank Address 2 Gb x4 1 Gb x8 512 Mb x16 # of Bank Groups 4 4 2 BG Address BG0~BG1 BG0~BG1 BG0 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A16 A0~A15 A0~A15 Column Address A0~A9 A0~A9 A0~A9 Page size 512B 1KB 2KB 4 Gb x4 2 Gb x8 1 Gb x16 16 Gb Addressing Table Configuration Bank Address # of Bank Groups 4 4 2 BG Address BG0~BG1 BG0~BG1 BG0 Bank Address in a BG BA0~BA1 BA0~BA1 BA0~BA1 Row Address A0~A17 A0~A16 A0~A16 Column Address A0~A9 A0~A9 A0~A9 Page size 512B 1KB 2KB NOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits - 10 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 6. Absolute Maximum Ratings [ Table 4 ] Absolute Maximum DC Ratings Symbol VDD VDDQ VPP VIN, VOUT TSTG Parameter Rating Units NOTE Voltage on VDD pin relative to Vss -0.3 ~ 1.5 V 1,3 Voltage on VDDQ pin relative to Vss -0.3 ~ 1.5 V 1,3 Voltage on VPP pin relative to Vss -0.3 ~ 3.0 V 4 Voltage on any pin except VREFCA relative to Vss -0.3 ~ 1.5 V 1,3,5 Storage Temperature -55 to +100 °C 1,2 NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300 mV of each other at all times;and VREFCA must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500 mV; VREFCA may be equal to or less than 300 mV 4. VPP must be equal or greater than VDD/VDDQ at all times. 5. Overshoot area above 1.5 V is specified in section 8.3.4, 8.3.5 and section 8.3.6. 7. AC & DC Operating Conditions [ Table 5 ] Recommended DC Operating Conditions Symbol Parameter VDD Rating Unit NOTE 1.26 V 1,2,3 1.2 1.26 V 1,2,3 2.5 2.75 V 3 Min. Typ. Max. Supply Voltage 1.14 1.2 VDDQ Supply Voltage for Output 1.14 VPP Peak-to-Peak Voltage 2.375 NOTE : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. DC bandwidth is limited to 20MHz. - 11 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8. AC & DC Input Measurement Levels 8.1 AC & DC Logic Input Levels for Single-ended Signals [ Table 6 ] Single-ended AC & DC input levels for Command and Address Symbol Parameter VIH.CA(DC75) DDR4-1600/1866/2133/2400 Unit NOTE Min. Max. DC input logic high VREFCA+ 0.075 VDD V VIL.CA(DC75) DC input logic low VSS VREFCA-0.075 V VIH.CA(AC100) AC input logic high VREF + 0.1 Note 2 V 1 VIL.CA(AC100) AC input logic low Note 2 VREF - 0.1 V 1 VREFCA(DC) Reference Voltage for ADD, CMD inputs 0.49*VDD 0.51*VDD V 2,3 NOTE : 1. See “Overshoot and Undershoot Specifications” . 2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV) 3. For reference : approx. VDD/2 ± 12mV 8.2 VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 6 on page 12. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. voltage VDD VSS time Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in 1 . This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings. - 12 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.3 AC & DC Logic Input Levels for Differential Signals 8.3.1 Differential Signals Definition tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK) VIH.DIFF.AC.MIN VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC NOTE : 1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope. 2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope. 8.3.2 Differential Swing Requirement for Clock (CK_t - CK_c) [ Table 7 ] Differential AC & DC Input Levels Symbol Parameter VIHdiff DDR4 -1600/1866/2133 DDR4 -2400 unit NOTE NOTE 3 V 1 NOTE 3 TBD V 1 NOTE 3 2 x (VIH(AC) - VREF) NOTE 3 V 2 2 x (VIL(AC) - VREF) NOTE 3 2 x (VIL(AC) - VREF) V 2 min max min max differential input high +0.150 NOTE 3 TBD VILdiff differential input low NOTE 3 -0.150 VIHdiff(AC) differential input high ac 2 x (VIH(AC) - VREF) VILdiff(AC) differential input low ac NOTE 3 NOTE: 1. Used to define a differential signal slew-rate. 2. for CK_t - CK_c use VIHCA/VILCA(AC) of ADD/CMD and VREFCA; 3. These values are not defined; however, the differential signals CK_t - CK_c, need to be within the respective limits (VIHCA(DC) max, VILCA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. [ Table 8 ] Allowed Time Before Ringback (tDVAC) for CK_t - CK_c tDVAC [ps] @ |VIH/Ldiff(AC)| = 200mV Slew Rate [V/ns] min max > 4.0 120 - 4.0 115 - 3.0 110 - 2.0 105 - 1.8 100 - 1.6 95 - 1.4 90 - 1.2 85 - 1.0 80 - < 1.0 80 - - 13 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals. CK_t and CK _c have to approximately reach VSEHmin / VSELmax [approximately equal to the ac-levels { VIH.CA(AC) / VIL.CA(AC)} for ADD/CMD signals] in every half-cycle. Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g. if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK _c . VDD or VDDQ VSEH min VSEH VDD/2 or VDDQ/2 CK VSEL max VSEL VSS or VSSQ time Figure 3. Single-ended requirement for differential signals Note that while ADD/CMD signal requirements are with respect to VREFCA, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. [ Table 9 ] Single-ended Levels for CK_t, CK_c Symbol VSEH VSEL Parameter Single-ended high-level for CK_t , CK_c Single-ended low-level for CK_t , CK_c DDR4-1600/1866/2133 Min Max DDR4-2400 Min Max Unit NOTE (VDD/2)+0.100 NOTE3 TBD NOTE3 V 1, 2 NOTE3 (VDD/2)-0.100 NOTE3 TBD V 1, 2 NOTE : 1. For CK_t - CK_c use VIH.CA/VIL.CA(AC) of ADD/CMD; 2. VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; 3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (VIH.CA(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. - 14 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.3.4 Address, Command and Control Overshoot and Undershoot Specifications [ Table 10 ] AC Overshoot/Undershoot Specification for Address, Command and Control Pins Specification Parameter Unit DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Maximum peak amplitude above VDD Absolute Max allowed for overshoot area 0.06 0.06 0.06 0.06 V Delta value between VDD Absolute Max and VDD Max allowed for overshoot area 0.24 0.24 0.24 0.24 V Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 V-ns Maximum overshoot area per 1tCK Above Absolute Max 0.0083 0.0071 0.0062 0.0055 V-ns Maximum overshoot area per 1tCK Between Absolute Max and VDD Max 0.2550 0.2185 0.1914 0.1699 V-ns Maximum undershoot area per 1tCK Below VSS 0.2644 0.2265 0.1984 0.1762 V-ns (A0-A13,BG0-BG1,BA0-BA1,ACT_n,RAS_n,CAS_n/A15,WE_n/A14,CS_n,CKE,ODT,C2-C0) Overshoot Area above VDD Absolute Max VDD Absolute Max Volts (V) Overshoot Area Between VDD Absolute Max and VDD Max VDD 1 tCK VSS Undershoot Area below VSS Figure 4. Address, Command and Control Overshoot and Undershoot Definition 8.3.5 Clock Overshoot and Undershoot Specifications [ Table 11 ] AC Overshoot/Undershoot Specification for Clock Specification Parameter Unit DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Maximum peak amplitude above VDD Absolute Max allowed for overshoot area 0.06 0.06 0.06 0.06 V Delta value between VDD Absolute Max and VDD Max allowed for overshoot area 0.24 0.24 0.24 0.24 V Maximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 V Maximum overshoot area per 1UI Above Absolute Max 0.0038 0.0032 0.0028 0.0025 V-ns Maximum overshoot area per 1UI Between Absolute Max and VDD Max 0.1125 0.0964 0.0844 0.0750 V-ns Maximum undershoot area per 1UI Below VSS 0.1144 0.0980 0.0858 0.0762 V-ns (CK_t, CK_c) Overshoot Area above VDD Absolute Max VDD Absolute Max Volts (V) VDD Overshoot Area Between VDD Absolute Max and VDD Max 1UI VSS Undershoot Area below VSS Figure 5. Clock Overshoot and Undershoot Definition - 15 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.3.6 Data, Strobe and Mask Overshoot and Undershoot Specifications [ Table 12 ] AC Overshoot/Undershoot Specification for Data, Strobe and Mask Specification Parameter Maximum peak amplitude above Max absolute level of Vin, Vout DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 0.16 0.16 0.16 0.16 Unit V Overshoot area Between Max Absolute level of Vin, Vout and VDDQ Max 0.24 0.24 0.24 0.24 V Undershoot area Between Min absolute level of Vin, Vout and VSSQ 0.30 0.30 0.30 0.30 V Maximum peak amplitude below Min absolute level of Vin, Vout 0.10 0.10 0.10 0.10 V Maximum overshoot area per 1UI Above Max absolute level of Vin, Vout 0.0150 0.0129 0.0113 0.0100 V-ns Maximum overshoot area per 1UI Between Max absolute level of Vin,Vout and VDDQ Max 0.1050 0.0900 0.0788 0.0700 V-ns Maximum undershoot area per 1UI Between Min absolute level of Vin,Vout and VSSQ 0.1050 0.0900 0.0788 0.0700 V-ns Maximum undershoot area per 1UI Below Min absolute level of Vin,Vout 0.0150 0.0129 0.0113 0.0100 V-ns (DQ, DQS_t, DQS_c, DM_n, DBI_n, TDQS_t, TDQS_c) Overshoot area above Max absolute level of Vin,Vout Max absolute level of Vin, Vout Volts (V) VDDQ Overshoot Area Between Max absolute level of Vin,Vout and VDDQ Max 1UI VSSQ Undershoot area between Min absolute level of Vin,Vout and VSSQ Min absolute level of Vin, Vout Undershoot area below Min absolute level of Vin,Vout Figure 6. Data, Strobe and Mask Overshoot and Undershoot Definition - 16 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.4 Slew Rate Definitions 8.4.1 Slew Rate Definitions for Differential Input Signals (CK) Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 13 and Figure 7. [ Table 13 ] Differential Input Slew Rate Definition Measured Description From Differential input slew rate for rising edge(CK_t - CK_c) V Differential input slew rate for falling edge(CK_t - CK_c) V IHdiffmin ILdiffmax Defined by To V IHdiffmin VIHdiffmin - VILdiffmax DeltaTRdiff V VIHdiffmin - VILdiffmax DeltaTFdiff ILdiffmax NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds. Differential Input Voltage(i,e, CK_t - CK_c) Delta TRdiff V IHdiffmin 0 V Delta TFdiff Figure 7. Differential Input Slew Rate definition for CK, CK - 17 - ILdiffmax K4A4G045WD K4A4G085WD Rev. 1.41 datasheet DDR4 SDRAM 8.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD ) Delta TRsingle V IHCA(AC) Min V IHCA(DC) Min VREFCA(DC) V ILCA(DC) Max V ILCA(AC) Max Delta TFsingle NOTE : 1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single 2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF single 3. Single-ended signal rising edge from VILCA(DC)Max to VIHCA(DC)Min must be monotonic slope. 4. Single-ended signal falling edge from VIHCA(DC)Min to VILCA(DC)Max must be monotonic slope. Figure 8. Single-ended Input Slew Rate definition for CMD and ADD - 18 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.5 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. VDD CK_t Vix VDD/2 Vix CK_c VSEL VSEH VSS Figure 9. Vix Definition (CK) [ Table 14 ] Cross Point Voltage for Differential Input Signals (CK) Symbol DDR4-1600/1866/2133 Parameter min max - Area of VSEH, VSEL VSEL =< VDD/2 145mV VDD/2 - 145mV =< VSEL =< VDD/2 100mV VlX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c -120mV -(VDD/2 - VSEL) + 25mV Symbol Parameter VDD/2 + 100mV =< VSEH =< VDD/2 + 145mV VDD/2 + 145mV =< VSEH (VSEH - VDD/2) 25mV 120mV DDR4-2400 min max - Area of VSEH, VSEL TBD TBD TBD TBD VlX(CK) Differential Input Cross Point Voltage relative to VDD/2 for CK_t, CK_c TBD TBD TBD TBD - 19 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.6 CMOS Rail to Rail Input Levels 8.6.1 CMOS Rail to Rail Input Levels for RESET_n [ Table 15 ] CMOS Rail to Rail Input Levels for RESET_n Parameter Symbol Min Max Unit NOTE AC Input High Voltage VIH(AC)_RESET 0.8*VDD VDD V 6 DC Input High Voltage VIH(DC)_RESET 0.7*VDD VDD V 2 DC Input Low Voltage VIL(DC)_RESET VSS 0.3*VDD V 1 AC Input Low Voltage VIL(AC)_RESET VSS 0.2*VDD V 7 Rising time TR_RESET - 1.0 us 4 RESET pulse width tPW_RESET 1.0 - us 3,5 NOTE : 1.After RESET_n is registered LOW, RESET_n level shall be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, SDRAM may not be reset. 2. Once RESET_n is registered HIGH, RESET_n level must be maintained above VIH(DC)_RESET, otherwise, SDRAM operation will not be guaranteed until it is reset asserting RESET_n signal LOW. 3. RESET is destructive to data contents. 4. No slope reversal(ringback) requirement during its level transition from Low to High. 5. This definition is applied only “Reset Procedure at Power Stable”. 6. Overshoot might occur. It should be limited by the Absolute Maximum DC Ratings. 7. Undershoot might occur. It should be limited by Absolute Maximum DC Ratings tPW_RESET 0.8*VDD 0.7*VDD 0.3*VDD 0.2*VDD TR_RESET Figure 10. RESET_n Input Slew Rate Definition - 20 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 8.7 AC and DC Logic Input Levels for DQS Signals 8.7.1 Differential Signal Definition Figure 11. Definition of differential DQS Signal AC-swing Level 8.7.2 Differential Swing Requirements for DQS (DQS_t - DQS_c) [ Table 16 ] Differential AC and DC Input Levels for DQS Symbol Parameter VIHDiffPeak VILDiffPeak VIH.DIFF.Peak Voltage VIL.DIFF.Peak Voltage DDR4-1600/1866/2133 Min 186 Note2 Max Note2 -186 DDR4-2400 Min TBD TBD Max TBD TBD Unit Note mV mV 1 1 NOTE : 1.Used to define a differential signal slew-rate. 2.These values are not defined; however, the differential signals DQS_t - DQS_c, need to be within the respective limits Overshoot, Undershoot Specification for single-ended signals. 8.7.3 Peak Voltage Calculation Method The peak voltage of Differential DQS signals are calculated in a following equation. VIH.DIFF.Peak Voltage = Max(f(t)) VIL.DIFF.Peak Voltage = Min(f(t)) f(t) = VDQS_t - VDQS_c - 21 - datasheet K4A4G045WD K4A4G085WD Rev. 1.41 DDR4 SDRAM Figure 12. Definition of differential DQS Peak Voltage 8.7.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet the requirements in Table 17. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the mid level that is VrefDQ.Vix Definition (DQS) Figure 13. Vix Definition (DQS) - 22 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 17 ] Cross Point Voltage for Differential Input Signals (DQS) Symbol Parameter Vix_DQS_ratio DQS Differential input crosspoint voltage ratio DDR4-1600/1866/2133 DDR4-2400 Min Max Min Max - 25 - 25 Unit Note % 1, 2, 3 NOTE : 1. The base level of Vix_DQS_FR/RF is VrefDQ that is DDR4 SDRAM internal setting value by Vref Training. 2. Vix_DQS_FR is defined by this equation : Vix_DQS_FR = |Min(f(t)) x Vix_DQS_Ratio| 3. Vix_DQS_RF is defined by this equation : Vix_DQS_RF = Max(f(t)) x Vix_DQS_Ratio 8.7.5 Differential Input Slew Rate Definition Input slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in are Figure 11 and Figure 12. NOTE : 1. Differential signal rising edge from VILDiff_DQS to VIHDiff_DQS must be monotonic slope. 2. Differential signal falling edge from VIHDiff_DQS to VILDiff_DQS must be monotonic slope. Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c [ Table 18 ] Differential Input Slew Rate Definition for DQS_t, DQS_c Description Defined by From To Differential input slew rate for rising edge(DQS_t - DQS_c) VILDiff_DQS VIHDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiff Differential input slew rate for falling edge(DQS_t - DQS_c) VIHDiff_DQS VILDiff_DQS |VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiff [ Table 19 ] Differential Input Level for DQS_t, DQS_c Symbol Parameter VIHDiff_DQS VILDiff_DQS Differntial Input High Differntial Input Low DDR4-1600/1866/2133 Min 136 - Max -136 DDR4-2400 Min TBD TBD Max TBD TBD Unit NOTE mV mV [ Table 20 ] Differential Input Slew Rate for DQS_t, DQS_c Symbol Parameter SRIdiff Differential Intput Slew Rate DDR4-1600/1866/2133 DDR4-2400 Min Max Min Max TBD 18 TBD TBD - 23 - Unit V/ns NOTE Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 9. AC and DC Output Measurement Levels 9.1 Output Driver DC Electrical Characteristics The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows: The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu = VDDQ -Vout I out under the condition that RONPd is off RONPd = Vout I out under the condition that RONPu is off Chip In Drive Mode Output Drive To other circuity like RCV, ... VDDQ IPu RONPu DQ RONPd Iout IPd Vout VSSQ Figure 15. Output driver - 24 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 21 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range; after proper ZQ calibration RONNOM Resistor Vout Min Nom Max Unit NOTE VOLdc= 0.5*VDDQ 0.8 1 1.1 RZQ/7 1,2 RON34Pd VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/7 1,2 VOHdc= 1.1* VDDQ 0.9 1 1.25 RZQ/7 1,2 1,2 34 RON34Pu RON48Pd 48 RON48Pu VOLdc= 0.5* VDDQ 0.9 1 1.25 RZQ/7 VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/7 1,2 VOHdc= 1.1* VDDQ 0.8 1 1.1 RZQ/7 1,2 VOLdc= 0.5*VDDQ 0.8 1 1.1 RZQ/5 1,2 VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/5 1,2 VOHdc= 1.1* VDDQ 0.9 1 1.25 RZQ/5 1,2 VOLdc= 0.5* VDDQ 0.9 1 1.25 RZQ/5 1,2 VOMdc= 0.8* VDDQ 0.9 1 1.1 RZQ/5 1,2 VOHdc= 1.1* VDDQ 0.8 1 1.1 RZQ/5 1,2 Mismatch between pull-up and pull-down, MMPuPd VOMdc= 0.8* VDDQ -10 - 10 % 1,2,3,4 Mismatch DQ-DQ within byte variation pull-up, MMPudd VOMdc= 0.8* VDDQ - - 10 % 1,2,4 Mismatch DQ-DQ within byte variation pull-dn, MMPddd VOMdc= 0.8* VDDQ - - 10 % 1,2,4 NOTE : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity(TBD). 2. Pull-up and pull-dn output driver impedances are recommended to be calibrated at 0.8 * VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.5 * VDDQ and 1.1 * VDDQ. 3. Measurement definition for mismatch between pull-up and pull-down, MMPuPd : Measure RONPu and RONPD both at 0.8*VDD separately; Ronnom is the nominal Ron value MMPuPd = RONPu -RONPd RONNOM *100 4. RON variance range ratio to RON Nominal value in a given component, including DQS_t and DQS_c. MMPudd = MMPddd = RONPuMax -RONPuMin RONNOM RONPdMax -RONPdMin RONNOM 5. This parameter of x16 device is specified for Upper byte and Lower byte. - 25 - *100 *100 Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 9.1.1 Alert_n Output Drive Characteristic A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows: RONPd = Vout l Iout l under the condition that RONPu is off Alert Driver DRAM Alert RONPd Iout IPd Vout VSSQ Resistor RONPd Vout Min Max Unit NOTE VOLdc= 0.1* VDDQ 0.3 1.2 34Ω 1 VOMdc = 0.8* VDDQ 0.4 1.2 34Ω 1 VOHdc = 1.1* VDDQ 0.4 1.4 34Ω 1 NOTE : 1. VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD. 9.1.2 Output Driver Characteristic of Connectivity Test ( CT ) Mode Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test ( CT ) Mode. The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows: RONPu_CT = RONPd_CT = VDDQ-VOUT l Iout l VOUT l Iout l Chip In Driver Mode Output Driver VDDQ IPu_CT To other circuity like RCV,... RON Pu_CT DQ Iout RON Pd_CT Vout IPd_CT VSSQ Figure 16. Output Driver - 26 - RONNOM_CT Rev. 1.41 datasheet K4A4G045WD K4A4G085WD Resistor RONPd_CT 34 RONPu_CT DDR4 SDRAM Vout Max Units NOTE VOBdc = 0.2 x VDDQ 1.9 34 1 VOLdc = 0.5 x VDDQ 2.0 34 1 VOMdc = 0.8 x VDDQ 2.2 34 1 VOHdc = 1.1 x VDDQ 2.5 34 1 VOBdc = 0.2 x VDDQ 2.5 34 1 VOLdc = 0.5 x VDDQ 2.2 34 1 VOMdc = 0.8 x VDDQ 2.0 34 1 VOHdc = 1.1 x VDDQ 1.9 34 1 NOTE : 1. Connectivity test mode uses un-calibrated drivers, showing the full range over PVT. No mismatch between pull up and pull down is defined. 9.2 Single-ended AC & DC Output Levels [ Table 22 ] Single-ended AC & DC Output Levels Symbol Parameter DDR4-1600/1866/2133/2400 Units VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V NOTE VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V VOH(AC) AC output high measurement level (for output SR) (0.7 + 0.15) x VDDQ V 1 VOL(AC) AC output low measurement level (for output SR) (0.7 - 0.15) x VDDQ V 1 NOTE : 1. The swing of ± 0.15 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ. 9.3 Differential AC & DC Output Levels [ Table 23 ] Differential AC & DC Output Levels Symbol Parameter DDR4-1600/1866/2133/2400 Units NOTE VOHdiff(AC) AC differential output high measurement level (for output SR) +0.3 x VDDQ V 1 VOLdiff(AC) AC differential output low measurement level (for output SR) -0.3 x VDDQ V 1 NOTE : 1. The swing of ± 0.3 × VDDQ is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7Ω and an effective test load of 50Ω to VTT = VDDQ at each of the differential outputs. - 27 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 9.4 Single-ended Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 24 and Figure 17. [ Table 24 ] Single-ended Output Slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / Delta TRse Single ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / Delta TFse NOTE : 1. Output slew rate is verified by design and characterization, and may not be subject to production test. VOH(AC) VTT VOL(AC) delta TFse delta TRse Figure 17. Single-ended Output Slew Rate Definition [ Table 25 ] Single-ended Output Slew Rate Parameter Single ended output slew rate Symbol SRQse DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Min Max Min Max Min Max Min Max 4 9 4 9 4 9 4 9 Units V/ns Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals For Ron = RZQ/7 setting NOTE : 1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane. -Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). -Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 9 V/ns applies - 28 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 9.5 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 26 and Figure 18. [ Table 26 ] Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VOLdiff(AC) VOHdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] / Delta TRdiff Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC)-VOLdiff(AC)] /Delta TFdiff NOTE : 1. Output slew rate is verified by design and characterization, and may not be subject to production test. VOHdiff(AC) VTT VOLdiff(AC) delta TFdiff delta TRdiff Figure 18. Differential Output Slew Rate Definition [ Table 27 ] Differential Output Slew Rate Parameter Differential output slew rate Symbol DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Min Max Min Max Min Max Min Max 8 18 8 18 8 18 8 18 SRQdiff Description: SR: Slew Rate Q: Query Output (like in DQ, which stands for Data-in, Query-Output) diff: Differential Signals For Ron = RZQ/7 setting - 29 - Units V/ns Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 9.6 Single-ended AC & DC Output Levels of Connectivity Test Mode Following output parameters will be applied for DDR4 SDRAM Output Signal during Connectivity Test Mode. [ Table 28 ] Single-ended AC & DC Output Levels of Connectivity Test Mode Symbol Parameter DDR4-1600/1866/2133 /2400 Unit Notes VOH(DC) DC output high measurement level (for IV curve linearity) 1.1 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.8 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.5 x VDDQ V VOB(DC) DC output below measurement level (for IV curve linearity) 0.2 x VDDQ V VOH(AC) AC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V 1 VOL(AC) AC output below measurement level (for output SR) VTT - (0.1 x VDDQ) V 1 Unit Notes NOTE 1. The effective test load is 50Ω terminated by VTT = 0.5 * VDDQ. VOH(AC) 0.5 * VDDQ VTT VOL(AC) TR_output_CT TR_output_CT Figure 19. Output Slew Rate Definition of Connectivity Test Mode [ Table 29 ] Single-ended Output Slew Rate of Connectivity Test Mode Parameter DDR4-1600/1866/2133/2400 Symbol Min Max Output signal Falling time TF_output_CT - 10 ns/V Output signal Rising time TR_output_CT - 10 ns/V 9.7 Test Load for Connectivity Test Mode Timing The reference load for ODT timings is defined in Figure 18. VDDQ CT_INPUTS DQ, DM DQSL , DQSL DQSU , DQSU DQS , DQS DUT Rterm = 50 ohm VSSQ Timing Reference Points Figure 20. Connectivity Test Mode Timing Reference Load - 30 - 0.5*VDDQ Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 10. Speed Bin [ Table 30 ] DDR4-1600 Speed Bins and Operations Speed Bin DDR4-1600 CL-nRCD-nRP 11-11-11 Unit NOTE Parameter Symbol min max Internal read command to first data tAA 13.75 18.00 ns 10 Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 10 ACT to internal read or write delay time tRCD 13.75 - ns 10 PRE command period tRP 13.75 - ns 10 ACT to PRE command period tRAS 35 9 x tREFI ns 10 tRC 48.75 - ns 10 ns 1,2,3,4,9 ns 1,2,3,4,9 ns 1,2,3,4 ns 1,2,3,4 ns 1,2,3 ACT to ACT or REF command period Normal CWL = 9 CWL = 9,11 Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) Reserved CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) 1.25 CL = 12 CL = 14 tCK(AVG) 1.25 1.5 1.6 Reserved <1.5 <1.5 Supported CL Settings 10,11,12 nCK Supported CL Settings with read DBI 12,13,14 nCK Supported CWL Settings 9,11 nCK [ Table 31 ] DDR4-1866 Speed Bins and Operations Speed Bin DDR4-1866 CL-nRCD-nRP Parameter 13-13-13 Symbol min Unit NOTE max Internal read command to first data tAA 13.92 18.00 ns 10 Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns 10 ACT to internal read or write delay time tRCD 13.92 - ns 10 PRE command period tRP 13.92 - ns 10 ACT to PRE command period tRAS 34 9 x tREFI ns 10 ACT to ACT or REF command period tRC 47.92 - ns 10 ns 1,2,3,4,9 CWL = 9 CWL = 9,11 CWL = 10,12 Normal Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) CL = 10 CL = 12 tCK(AVG) Reserved 1.5 1.6 Reserved ns 1,2,3,4,9 ns 4 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,6 CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,6 CL = 12 CL = 14 tCK(AVG) ns 1,2,3,4 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4 CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3 Reserved Supported CL Settings 10,11,12,13,14 nCK Supported CL Settings with read DBI 12,13,14,15,16 nCK Supported CWL Settings 9,10,11,12 nCK - 31 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 32 ] DDR4-2133 Speed Bins and Operations Speed Bin DDR4-2133 CL-nRCD-nRP 15-15-15 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period tRC Normal CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 Unit NOTE 18.00 ns 10 tAA(max) + 3nCK ns 10 - ns 10 - ns 10 9 x tREFI ns 10 - ns 10 min max 14.06 (13.75)5 tAA(min) + 3nCK 14.06 (13.75)5 14.06 (13.75)5 33 47.06 (46.75)5 Read DBI CL = 9 CL = 11 tCK(AVG) ns 1,2,3,4,9 CL = 10 CL = 12 tCK(AVG) 1.5 Reserved 1.6 ns 1,2,3,4,9 CL = 11 CL = 13 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,7 CL = 12 CL = 14 tCK(AVG) 1.25 <1.5 ns 1,2,3,7 CL = 13 CL = 15 tCK(AVG) 1.071 <1.25 ns 1,2,3,4,7 CL = 14 CL = 16 tCK(AVG) 1.071 <1.25 ns 1,2,3,7 CL = 14 CL = 17 tCK(AVG) ns 1,2,3,4 CL = 15 CL = 18 tCK(AVG) 0.938 <1.071 ns 1,2,3,4 CL = 16 CL = 19 tCK(AVG) 0.938 ns 1,2,3 Reserved <1.071 Supported CL Settings 10,11.12,13,14,15,16 nCK Supported CL Settings with read DBI 12,13,14,15,16,18,19 nCK Supported CWL Settings 9,10,11,12,14 nCK - 32 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 33 ] DDR4-2400 Speed Bins and Operations Speed Bin DDR4-2400 CL-nRCD-nRP 17-17-17 Parameter Symbol Internal read command to first data tAA Internal read command to first data with read DBI enabled tAA_DBI ACT to internal read or write delay time tRCD PRE command period tRP ACT to PRE command period tRAS ACT to ACT or REF command period tRC Normal CWL = 9 CWL = 9,11 CWL = 10,12 CWL = 11,14 CWL = 12,16 Unit NOTE 18.00 ns 10 tAA(max) + 3nCK ns 10 - ns 10 - ns 10 9 x tREFI ns 10 - ns 10 ns 1,2,3,4,9 ns 1,2,3,4,9 min max 14.16 (13.75)5 tAA(min) + 3nCK 14.16 (13.75)5 14.16 (13.75)5 32 46.16 (45.75)5 Read DBI CL = 9 CL = 11 tCK(AVG) CL = 10 CL = 12 tCK(AVG) Reserved 1.5 1.6 CL = 10 CL = 12 tCK(AVG) CL = 11 CL = 13 tCK(AVG) 1.25 Reserved CL = 12 CL = 14 tCK(AVG) 1.25 CL = 12 CL = 14 tCK(AVG) CL = 13 CL = 15 tCK(AVG) 1.071 CL = 14 CL = 16 tCK(AVG) 1.071 CL = 14 CL = 17 tCK(AVG) CL = 15 CL = 18 tCK(AVG) 0.938 CL = 16 CL = 19 tCK(AVG) 0.938 CL = 15 CL = 18 tCK(AVG) CL = 16 CL = 19 tCK(AVG) CL = 17 CL = 20 tCK(AVG) 0.833 <0.938 CL = 18 CL = 21 tCK(AVG) 0.833 <0.938 <1.5 <1.5 ns 4 ns 1,2,3,4,8 ns 1,2,3,8 ns 4 <1.25 ns 1,2,3,4,8 <1.25 ns 1,2,3,8 ns 4 <1.071 ns 1,2,3,4,8 <1.071 ns 1,2,3,8 ns 1,2,3,4 ns 1,2,3,4 ns 1,2,3 Reserved Reserved Reserved Reserved Supported CL Settings 10,11,12,13,14,15,16,17,18 nCK Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21 nCK Supported CWL Settings 9,10,11,12,14,16 nCK - 33 - K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM 10.1 Speed Bin Table Note Absolute Specification - VDDQ = VDD = 1.20V +/- 0.06 V - VPP = 2.5V +0.25/-0.125 V - The values defined with above-mentioned table are DLL ON case. - DDR4-1600, 1866, 2133 and 2400 Speed Bin Tables are valid only when Geardown Mode is disabled. 1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next ‘Supported CL’, where tAA = 12.5ns and tCK(avg) = 1.3 ns should only be used for CL = 10 calculation. 3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED. 4. ‘Reserved’ settings are not allowed. User must program a different value. 5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported. 6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/ Characterization. 9. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. 10. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables. - 34 - K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM 11. IDD and IDDQ Specification Parameters and Test Conditions 11.1 IDD, IPP and IDDQ Measurement Conditions In this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure 21 shows the setup and test load for IDD, IPP and IDDQ measurements. l l l IDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4RA, IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with all VDD balls of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents. IPP currents have the same definition as IDD except that the current on the VPP supply is measured. IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 22. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD, IPP and IDDQ measurements, the following definitions apply: l “0” and “LOW” is defined as VIN <= VILAC(max). l “1” and “HIGH” is defined as VIN >= VIHAC(min). l “MID-LEVEL” is defined as inputs are VREF = VDD / 2. l Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 34. l l l l l l Basic IDD, IPP and IDDQ Measurement Conditions are described in Table 35. Detailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 36 through Table 44. IDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; Qoff = 0B (Output Buffer enabled) in MR1; TDQS_t disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR5; Gear down mode disabled in MR3 Read/Write DBI disabled in MR5; DM disabled in MR5 Attention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. Define D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed. Define D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} apply invert of BG/BA changes when directed above. - 35 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD IDD VDD RESET CK_t/CK_c CKE CS C ACT,RAS,CAS,WE A,BG,BA ODT ZQ IPP DDR4 SDRAM IDDQ VPP VDDQ DDR4 SDRAM DQS_t/DQS_c DQ DM VSS VSSQ NOTE: 1. DIMM level Output test load condition may be different from above Figure 21. Measurement Setup and Test Load for IDD, IPP and IDDQ Measurements Application specific IDDQ TestLad memory channel environment Channel IO Powe Simulatin IDDQ Simuaion IDDQ Measurement X X Correlation Channel IO Power Number Figure 22. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement. - 36 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 34 ] Timings Used for IDD, IPP and IDDQ Measurement-Loop Patterns DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 11-11-11 13-13-13 15-15-15 17-17-17 tCK 1.25 1.071 0.938 0.833 ns CL 11 13 15 17 nCK CWL 11 12 14 16 nCK nRCD 11 13 15 17 nCK nRC 39 45 51 56 nCK nRAS 28 32 36 39 nCK nRP 11 13 15 17 nCK x4 16 16 16 16 nCK x8 20 22 23 26 nCK x16 28 28 32 36 nCK x4 4 4 4 4 nCK Symbol nFAW nRRDS nRRDL Unit x8 4 4 4 4 nCK x16 5 5 6 7 nCK x4 5 5 6 6 nCK x8 5 5 6 6 nCK 6 6 7 8 nCK tCCD_S x16 4 4 4 4 nCK tCCD_L 5 5 6 6 nCK tWTR_S 2 3 3 3 nCK tWTR_L 6 7 8 9 nCK nRFC 2Gb 128 150 171 193 nCK nRFC 4Gb 208 243 278 313 nCK nRFC 8Gb 280 327 374 421 nCK TBD nCK - 37 - K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM [ Table 35 ] Basic IDD, IPP and IDDQ Measurement Conditions Symbol Description Operating One Bank Active-Precharge Current (AL=0) IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: High between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 36 on page 41; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 36 on page 41); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 36 on page 41 IDD0A IPP0 Operating One Bank Active-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD0 Operating One Bank Active-Precharge IPP Current Same condition with IDD0 Operating One Bank Active-Read-Precharge Current (AL=0) IDD1 CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: High between ACT, RD and PRE; Command, Address, Bank Group Address, Bank Address Inputs, Data IO: partially toggling according to Table 37 on page 42; DM_n: stable at 1; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 37 on page 42); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 37 on page 42 IDD1A IPP1 Operating One Bank Active-Read-Precharge Current (AL=CL-1) AL = CL-1, Other conditions: see IDD1 Operating One Bank Active-Read-Precharge IPP Current Same condition with IDD1 Precharge Standby Current (AL=0) IDD2N CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 38 on page 43; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 38 on page 43 IDD2NA IPP2N Precharge Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD2N Precharge Standby IPP Current Same condition with IDD2N Precharge Standby ODT Current IDD2NT CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 39 on page 44; Data IO: VSSQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: toggling according to Table 39 on page 44; Pattern Details: see Table 39 on page 44 IDDQ2NT Precharge Standby ODT IDDQ Current (Optional) Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current IDD2NL IDD2NG IDD2ND IDD2N_par IDD2P Precharge Standby Current with CAL enabled Same definition like for IDD2N, CAL enabled3 Precharge Standby Current with Gear Down mode enabled Same definition like for IDD2N, Gear Down mode enabled3,5 Precharge Standby Current with DLL disabled Same definition like for IDD2N, DLL disabled3 Precharge Standby Current with CA parity enabled Same definition like for IDD2N, CA parity enabled3 Precharge Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IPP2P Precharge Power-Down IPP Current Same condition with IDD2P IDD2Q Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IDD3N Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 38 on page 43; Data IO: VDDQ; DM_n: stable at 1;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 38 on page 43 - 38 - K4A4G045WD K4A4G085WD datasheet Symbol IDD3NA Rev. 1.41 DDR4 SDRAM Description Active Standby Current (AL=CL-1) AL = CL-1, Other conditions: see IDD3N IPP3N Active Standby IPP Current Same condition with IDD3N IDD3P Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: stable at 1; Command, Address, Bank Group Address, Bank Address Inputs: stable at 0; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0 IPP3P Active Power-Down IPP Current Same condition with IDD3P IDD4R Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 82; AL: 0; CS_n: High between RD; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 40 on page 45; Data IO: seamless read data burst with different data between one burst and the next one according to Table 40 on page 45; DM_n: stable at 1; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 40 on page 45); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 40 on page 45 IDD4RA Operating Burst Read Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4R IDD4RB Operating Burst Read Current with Read DBI Read DBI enabled3, Other conditions: see IDD4R IPP4R Operating Burst Read IPP Current Same condition with IDD4R IDDQ4R (Optional) Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current IDDQ4RB (Optional) Operating Burst Read IDDQ Current with Read DBI Same definition like for IDD4RB, however measuring IDDQ current instead of IDD current IDD4W Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n: High between WR; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 41 on page 46; Data IO: seamless write data burst with different data between one burst and the next one according to Table 41 on page 46; DM_n: stable at 1; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 41 on page 46); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at HIGH; Pattern Details: see Table 41 on page 46 IDD4WA Operating Burst Write Current (AL=CL-1) AL = CL-1, Other conditions: see IDD4W IDD4WB Operating Burst Write Current with Write DBI Write DBI enabled3, Other conditions: see IDD4W IDD4WC Operating Burst Write Current with Write CRC Write CRC enabled3, Other conditions: see IDD4W IDD4W_par Operating Burst Write Current with CA Parity CA Parity enabled3, Other conditions: see IDD4W IPP4W Operating Burst Write IPP Current Same condition with IDD4W IDD5B Burst Refresh Current (1X REF) CKE: High; External clock: On; tCK, CL, nRFC: see Table 34 on page 37; BL: 81; AL: 0; CS_n: High between REF; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 43 on page 48; Data IO: VDDQ; DM_n: stable at 1; Bank Activity: REF command every nRFC (see Table 43 on page 48); Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 43 on page 48 IPP5B Burst Refresh Write IPP Current (1X REF) Same condition with IDD5B IDD5F2 Burst Refresh Current (2X REF) tRFC=tRFC_x2, Other conditions: see IDD5B IPP5F2 Burst Refresh Write IPP Current (2X REF) Same condition with IDD5F2 IDD5F4 Burst Refresh Current (4X REF) tRFC=tRFC_x4, Other conditions: see IDD5B IPP5F4 Burst Refresh Write IPP Current (4X REF) Same condition with IDD5F4 - 39 - K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM Symbol Description IDD6N Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; Low Power Array Self Refresh (LP ASR) : Normal4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n: stable at 1; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL IPP6N Self Refresh IPP Current: Normal Temperature Range Same condition with IDD6N IDD6E Self-Refresh Current: Extended Temperature Range) TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Extended4; CKE: Low; External clock: Off; CK_t and CK_c: LOW; CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MIDLEVEL IPP6E Self Refresh IPP Current: Extended Temperature Range Same condition with IDD6E IDD6R Self-Refresh Current: Reduced Temperature Range TCASE: 0 - 45 °C; Low Power Array Self Refresh (LP ASR) : Reduced4; CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MIDLEVEL IPP6R Self Refresh IPP Current: Reduced Temperature Range Same condition with IDD6R IDD6A Auto Self-Refresh Current TCASE: 0 - 95°C; Low Power Array Self Refresh (LP ASR) : Auto4;CKE: Low; External clock: Off; CK_t and CK_c#: LOW; CL: see Table 34 on page 37; BL: 81; AL: 0; CS_n#, Command, Address, Bank Group Address, Bank Address, Data IO: High; DM_n:stable at 1; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: MID-LEVEL IPP6A Auto Self-Refresh IPP Current Same condition with IDD6A IDD7 Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 34 on page 37; BL: 81; AL: CL-1; CS_n: High between ACT and RDA; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 44 on page 49; Data IO: read data bursts with different data between one burst and the next one according to Table 44 on page 49; DM_n: stable at 1; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 44 on page 49; Output Buffer and RTT: Enabled in Mode Registers2; ODT Signal: stable at 0; Pattern Details: see Table 44 on page 49 IPP7 Operating Bank Interleave Read IPP Current Same condition with IDD7 IDD8 Maximum Power Down Current TBD IPP8 Maximum Power Down IPP Current Same condition with IDD8 NOTE : 1. Burst Length: BL8 fixed by MRS: set MR0 [A1:0=00]. 2. Output Buffer Enable - set MR1 [A12 = 0] : Qoff = Output buffer enabled - set MR1 [A2:1 = 00] : Output Driver Impedance Control = RZQ/7 RTT_Nom enable - set MR1 [A10:8 = 011] : RTT_NOM = RZQ/6 RTT_WR enable - set MR2 [A10:9 = 01] : RTT_WR = RZQ/2 RTT_PARK disable - set MR5 [A8:6 = 000] 3. CAL enabled : set MR4 [A8:6 = 001] : 1600MT/s 010] : 1866MT/s, 2133MT/s 011] : 2400MT/s Gear Down mode enabled :set MR3 [A3 = 1] : 1/4 Rate DLL disabled : set MR1 [A0 = 0] CA parity enabled :set MR5 [A2:0 = 001] : 1600MT/s,1866MT/s, 2133MT/s 010] : 2400MT/s Read DBI enabled : set MR5 [A12 = 1] Write DBI enabled : set :MR5 [A11 = 1] 4. Low Power Array Self Refresh (LP ASR) : set MR2 [A7:6 = 00] : Normal 01] : Reduced Temperature range 10] : Extended Temperature range 11] : Auto Self Refresh 5. IDD2NG should be measured after sync pulse(NOP) input. - 40 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 0 0 0 - 0 0 0 0 - 3,4 D_#, D_# 1 1 1 1 1 0 0 32 3 0 0 0 7 F 0 - ... repeat pattern 1...4 until nRAS - 1, truncate if necessary 0 0 0 0 0 0 0 0 - PRE 0 1 0 1 0 0 0 1*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead 2 2*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead 3 3*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 4*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 5*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 6*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 7 7*nRC repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead 8 8*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 9 9*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead 10 10*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 11 11*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead 2= 2, BA[1:0] = 3 instead 13 14 15 13*nRC 14*nRC 15*nRC Data4 repeat pattern 1...4 until nRC - 1, truncate if necessary 1 12 A[2:0] 0 0 A[6:3] 0 0 A[9:7] 0 0 A[10]/AP 0 0 A[13,11] 0 0 A12/BC_n 0 0 BA[1:0] 0 0 BG[1:0]2 0 0 C[2:0]3 0 0 ODT 0 0 ... Static High WE_n/ A14 0 1 nRAS toggling CAS_n/ A15 0 D, D RAS_n ACT ACT_n 0 1,2 CS_n Command 0 Cycle Number Sub-Loop CKE CK_t /CK_c [ Table 36 ] IDD0, IDD0A and IPP0 Measurement-Loop Pattern1 repeat Sub-Loop 0, use BG[1:0] 2 repeat Sub-Loop 0, use BG[1:0] = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. DQ signals are VDDQ. - 41 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM CS_n ACT_n RAS_n CAS_n/A15 WE_n/A14 ODT C[2:0]3 BG[1:0]2 BA[1:0] A12/BC_n A[13,11] A[10]/AP A[9:7] A[6:3] A[2:0] 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 b 3 0 0 0 7 F 0 - 0 Cycle Number Command Data4 Sub-Loop CKE CK_t, CK_c [ Table 37 ] IDD1, IDD1A and IPP1 Measurement-Loop Pattern1 3, 4 D#, D# ... repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary nRCD -AL RD 1 0 1 1 1 1 1 0 1 1 0 0 0 3 0 ... repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF 0 0 0 0 0 0 0 - ... repeat pattern 1...4 until nRC - 1, truncate if necessary 1*nRC + 0 ACT 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 - 1*nRC + 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1*nRC + 3, 4 D#, D# 1 1 1 1 1 0 0 3b 3 0 0 0 7 F 0 - ... repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if necessary 1 Static High toggling 1*nRC + nRCD - AL RD 0 1 1 0 1 0 0 1 ... repeat pattern 1...4 until nRAS - 1, truncate if necessary 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00 0 0 0 0 0 0 0 - 1*nRC + nRAS PRE ... repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary 2 2*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead 3 3*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 4*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 5*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 6*nRC repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 8 7*nRC repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead 9 9*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 0 instead 10 10*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead 11 11*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 2 instead 12 12*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead 13 13*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 1 instead 14 14*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead 15 15*nRC repeat Sub-Loop 1, use BG[1:0]2 = 2, BA[1:0] = 3 instead 16 16*nRC repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ. - 42 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Static High toggling A[6:3] A[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 7 F 0 0 3 0 0 0 7 F 0 0 2 D#, D# 1 1 1 1 1 0 0 32 3 D#, D# 1 1 1 1 1 0 0 2 1 4-7 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 20-23 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 7 28-31 repeat Sub-Loop 0, use BG[1:0]2 = 1, BA[1:0] = 0 instead 8 32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 9 36-39 repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 1 instead 10 40-43 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 11 44-47 repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 3 instead 12 48-51 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead 13 52-55 repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 2 instead 14 56-59 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead 15 60-63 repeat Sub-Loop 0, use BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. DQ signals are VDDQ. - 43 - 3 A[13,11] 0 0 BA[1:0] 0 0 BG[1:0]2 0 0 C[2:0]3 0 0 ODT A[9:7] A12/BC_n WE_n/A14 CAS_n/A15 1 1 RAS_n D, D D, D ACT_n 0 1 CS_n Data4 Cycle Number A[10]/AP 0 Command Sub-Loop CKE CK_t, CK_c [ Table 38 ] IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P Measurement-Loop Pattern1 Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Static High A[2:0] 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 3 2 3 0 0 0 7 F 0 - 3 2 3 0 0 0 7 F 0 - D#, D# D#, D# 1 1 1 1 1 1 1 1 1 1 ODT D, D D, D 2 0 0 0 A[9:7] A[10]/AP A[13,11] A12/BC_n BA[1:0] BG[1:0]2 C[2:0]3 WE_n/A14 CAS_n/A15 RAS_n ACT_n 0 1 CS_n Data4 3 toggling Command A[6:3] 0 Cycle Number Sub-Loop CKE CK_t, CK_c [ Table 39 ] IDD2NT and IDDQ2NT Measurement-Loop Pattern1 2 1 4-7 repeat Sub-Loop 0, but ODT = 1 and BG[1:0] = 1, BA[1:0] = 1 instead 2 8-11 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 2 instead 3 12-15 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 3 instead 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 1 instead 5 20-23 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 2 instead 6 24-27 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 0, BA[1:0] = 3 instead 7 28-31 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 1, BA[1:0] = 0 instead 8 32-35 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 0 instead 9 36-39 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 1 instead 10 40-43 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 2 instead 11 44-47 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 3 instead 12 48-51 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 1 instead 13 52-55 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 2 instead 14 56-59 repeat Sub-Loop 0, but ODT = 0 and BG[1:0]2 = 2, BA[1:0] = 3 instead 15 60-63 repeat Sub-Loop 0, but ODT = 1 and BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. DQ signals are VDDQ. - 44 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM CS_n ACT_n RAS_n CAS_n/A15 WE_n/A14 ODT C[2:0]3 BG[1:0]2 BA[1:0] A12/BC_n A[13,11] A[10]/AP A[9:7] A[6:3] A[2:0] 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 3 0 0 0 7 F 0 - Cycle Number Command Data4 Sub-Loop CKE CK_t, CK_c [ Table 40 ] IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop Pattern1 0 2,3 D#, D# 1 1 1 1 1 0 0 32 4 RD 0 1 1 0 1 0 0 1 1 0 0 0 7 F 0 D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00 5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 2 3 0 0 0 7 F 0 - 1 Static High toggling 6,7 D#, D# 1 1 1 1 1 0 3 2 2 8-11 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 3 12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 20-23 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 7 28-31 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead 8 32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 9 36-39 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead 10 40-43 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 11 44-47 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead 12 48-51 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead 13 52-55 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead 14 56-59 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead 15 60-63 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are used according to RD Commands, otherwise VDDQ. 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. Burst Sequence driven on each DQ signal by Read Command. - 45 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM CS_n ACT_n RAS_n CAS_n/A15 WE_n/A14 ODT C[2:0]3 BG[1:0]2 BA[1:0] A12/BC_n A[13,11] A[10]/AP A[9:7] A[6:3] A[2:0] 0 WR 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF 1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 - 3 0 0 0 7 F 0 - Cycle Number Command Data4 Sub-Loop CKE CK_t, CK_c [ Table 41 ] IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop Pattern1 0 2,3 D#, D# 1 1 1 1 1 1 0 32 4 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00 5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 - 0 2 3 0 0 0 7 F 0 - 1 Static High toggling 6,7 D#, D# 1 1 1 1 1 1 3 2 2 8-11 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 3 12-15 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 20-23 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 24-27 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 7 28-31 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead 8 32-35 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 9 36-39 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead 10 40-43 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 11 44-47 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead 12 48-51 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead 13 52-55 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead 14 56-59 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead 15 60-63 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are used according to WR Commands, otherwise VDDQ. 2. BG1 is don’t care for x16 device 3. C[2:0] are used only for 3DS device 4. Burst Sequence driven on each DQ signal by Write Command. - 46 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM Static High 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1,2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 - 0 2 3 0 0 0 7 F 0 - D#, D# 1 1 1 1 1 1 3 A[6:3] 0 ODT WR 3,4 A[9:7] A[10]/AP A[13,11] A12/BC_n BA[1:0] BG[1:0]2 C[2:0]3 WE_n/A14 CAS_n/A15 RAS_n ACT_n 0 D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF D8=CRC CS_n Data4 5 WR 0 1 1 0 1 1 0 1 1 0 0 0 7 F 0 D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00 D8=CRC 6,7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 - 0 32 3 0 0 0 7 F 0 - 8,9 toggling Command A[2:0] 0 Cycle Number Sub-Loop CKE CK_t, CK_c [ Table 42 ] IDD4WC Measurement-Loop Pattern1 D#, D# 1 1 1 1 1 1 2 2 10-14 repeat Sub-Loop 0, use BG[1:0] = 0, BA[1:0] = 2 instead 3 15-19 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 20-24 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 5 25-29 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead 6 30-34 repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 7 35-39 repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead 8 40-44 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 9 45-49 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead 10 50-54 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 11 55-59 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead 12 60-64 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead 13 65-69 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead 14 70-74 repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead 15 75-79 repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device. 3. C[2:0] are used only for 3DS device. 4. Burst Sequence driven on each DQ signal by Write Command. - 47 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 0 Static High toggling A[2:0] A[6:3] A[9:7] A[10]/AP A[13,11] A12/BC_n BA[1:0] BG[1:0]2 C[2:0]3 ODT WE_n/A14 CAS_n/A15 RAS_n ACT_n CS_n REF 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 2 3 0 0 0 7 F 0 - 2 3 0 0 0 7 F 0 - 4 2 Data4 0 3 1 Command Cycle Number Sub-Loop CKE CK_t, CK_c [ Table 43 ] IDD5B Measurement-Loop Pattern1 D#, D# D#, D# 1 1 1 1 1 1 1 1 1 1 0 0 0 3 3 2 4-7 repeat pattern 1...4, use BG[1:0] = 1, BA[1:0] = 1 instead 8-11 repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 2 instead 12-15 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead 16-19 repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead 20-23 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead 24-27 repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead 28-31 repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead 32-35 repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 instead 36-39 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead 40-43 repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead 44-47 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead 48-51 repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead 52-55 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead 56-59 repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 3 instead 60-63 repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead 64 ... nRFC - 1 repeat Sub-Loop 1, Truncate, if necessary NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device. 3. C[2:0] are used only for 3DS device. 4. DQ signals are VDDQ. - 48 - For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM RAS_n CAS_n/A15 WE_n/A14 ODT C[2:0]3 BG[1:0]2 BA[1:0] A12/BC_n A[13,11] A[10]/AP A[9:7] A[6:3] A[2:0] ACT ACT_n 0 CS_n Command Cycle Number Sub-Loop CKE CK_t, CK_c [ Table 44 ] IDD7 Measurement-Loop Pattern1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RDA 0 1 1 0 1 0 2 D 1 0 0 0 0 0 3 D# 1 1 1 1 1 0 - 0 0 D0=00, D1=FF D2=FF, D3=00 D4=FF, D5=00 D6=00, D7=FF 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 - 0 32 3 0 0 0 7 F 0 - 0 0 0 0 - 0 D0=FF, D1=00 D2=00, D3=FF D4=00, D5=FF D6=FF, D7=00 0 Static High toggling 1 ... repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary nRRD ACT 0 0 0 1 0 1 0 0 0 1 0 0 0 1 1 1 1 0 0 0 nRRD + 1 RDA ... repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD > 4. Truncate if necessary 2 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 2 instead 3 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 3 instead 4 4*nRRD repeat pattern 2 ... 3 until nFAW - 1, if nFAW > 4*nRRD. Truncate if necessary 5 nFAW repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 1 instead 6 nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 2 instead 7 nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 0, BA[1:0] = 3 instead 8 nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 1, BA[1:0] = 0 instead 9 nFAW + 4*nRRD repeat Sub-Loop 4 0 1 10 2*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 0 instead 11 2*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 1 instead 12 2*nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 2 instead 13 2*nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 3 instead 14 2*nFAW + 4*nRRD repeat Sub-Loop 4 15 3*nFAW repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 1 instead 16 3*nFAW + nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 2 instead 17 3*nFAW + 2*nRRD repeat Sub-Loop 0, use BG[1:0]2 = 2, BA[1:0] = 3 instead 18 3*nFAW + 3*nRRD repeat Sub-Loop 1, use BG[1:0]2 = 3, BA[1:0] = 0 instead 19 3*nFAW + 4*nRRD repeat Sub-Loop 4 20 4*nFAW repeat pattern 2 ... 3 until nRC - 1, if nRC > 4*nFAW. Truncate if necessary NOTE : 1. DQS_t, DQS_c are VDDQ. 2. BG1 is don’t care for x16 device. 3. C[2:0] are used only for 3DS device. 4. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are VDDQ. - 49 - Data4 0 0 For x4 and x8 only Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 11.2 4Gb DDR4 SDRAM D-die IDD Specification Table IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. [ Table 45 ] IDD and IDDQ Specification 1Gx4 (K4A4G045WD) 512Mx8 (K4A4G085WD) DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V IDD Max. IDD Max. IDD Max. IDD Max. IDD0 33 34 33 34 mA IDD0A 36 38 36 38 mA IDD1 41 42 43 45 mA Symbol Unit IDD1A 44 46 46 49 mA IDD2N 16 18 16 18 mA IDD2NA 23 25 23 25 mA IDD2NT 18 20 18 20 mA IDD2NL 14 15 14 15 mA IDD2NG 19 20 19 20 mA IDD2ND 14 15 14 15 mA IDD2N_par 19 20 19 20 mA IDD2P 11 11 11 11 mA IDD2Q 15 17 15 17 mA IDD3N 30 32 30 32 mA IDD3NA 35 37 35 37 mA IDD3P 15 16 15 16 mA IDD4R 83 90 95 104 mA IDD4RA 85 94 98 108 mA IDD4RB 84 92 97 106 mA IDD4W 72 76 77 81 mA IDD4WA 76 80 81 86 mA IDD4WB 72 76 77 82 mA IDD4WC 65 68 70 74 mA IDD4W_par 81 87 81 87 mA IDD5B 153 154 153 155 mA IDD5F2 128 128 128 128 mA IDD5F4 97 97 97 97 mA IDD6N 12 12 12 12 mA IDD6E 16 16 16 16 mA IDD7 138 140 147 149 mA IDD8 7 7 7 7 mA NOTE IDD and IPP values are for full operating range of voltage and temperature unless otherwise noted. IDD and IPP values are for full operating range voltage and temperature unless otherwise noted. - 50 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 46 ] IPP Specification 512Mx8 (K4A4G085WD) 1Gx4 (K4A4G045WD) DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V 1.2V 1.2V 1.2V IPP Max. IPP Max. IPP Max. IPP Max. IPP0 4 4 4 4 mA IPP1 4 4 4 4 mA IPP2N 3 3 3 3 mA IPP2P 3 3 3 3 mA IPP3N 3 3 3 3 mA IPP3P 3 3 3 3 mA Symbol Unit IPP4R 3 3 3 3 mA IPP4W 3 3 3 3 mA IPP5B 18 18 18 18 mA IPP5F2 15 15 15 15 mA IPP5F4 11 11 11 11 mA IPP6N 4 4 4 4 mA IPP6E 4 4 4 4 mA IPP7 7.5 7.5 7.5 7.5 mA IPP8 2 2 2 2 mA NOTE [ Table 47 ] IDD6 Specification Symbol Temperature Range Value Value 1Gx4 (K4A4G045WD) 512Mx8 (K4A4G085WD) DDR4-2133 DDR4-2400 DDR4-2133 DDR4-2400 15-15-15 17-17-17 15-15-15 17-17-17 1.2V Unit NOTE 1.2V IDD6N 0 - 85 oC 12 12 12 12 mA 3,4 IDD6E 0 - 95 oC 16 16 16 16 mA 4,5 NOTE : 1. Some IDD currents are higher for x16 organization due to larger page-size architecture. 2. Max. values for IDD currents considering worst case conditions of process, temperature and voltage. 3. Applicable for MR2 settings A6=0 and A7=0. 4. Include a max value for IDD6. 5. Applicable for MR2 settings A6=0 and A7=1. IDD6E is only specified for devices which support the Extended Temperature Range feature. - 51 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 12. Input/Output Capacitance [ Table 48 ] Silicon Pad I/O Capacitance Symbol Parameter CIO DDR4-1600/1866/2133 DDR4-2400 Unit NOTE 1.15 pF 1,2,3 -0.1 0.1 pF 1,2,3,11 0.05 - 0.05 pF 1,2,3,5 0.8 0.2 0.7 pF 1,3 min max min max Input/output capacitance 0.55 1.4 0.55 CDIO Input/output capacitance delta -0.1 0.1 CDDQS Input/output capacitance delta DQS_t and DQS_c - CCK Input capacitance, CK_t and CK_c 0.2 CDCK Input capacitance delta CK_t and CK_c - 0.05 - 0.05 pF 1,3,4 CI Input capacitance(CTRL, ADD, CMD pins only) 0.2 0.8 0.2 0.7 pF 1,3,6 CDI_ CTRL Input capacitance delta(All CTRL pins only) -0.1 0.1 -0.1 0.1 pF 1,3,7,8 CDI_ ADD_CMD Input capacitance delta(All ADD/CMD pins only) -0.1 0.1 -0.1 0.1 pF 1,2,9,10 CALERT Input/output capacitance of ALERT 0.5 1.5 0.5 1.5 pF 1,3 CZQ Input/output capacitance of ZQ 0.5 2.3 0.5 2.3 pF 1,3,12 CTEN Input capacitance of TEN 0.2 2.3 0.2 2.3 pF 1,3,13 NOTE: 1. This parameter is not subject to production test. It is verified by design and characterization. The silicon only capacitance is validated by de-embedding the package L & C parasitic. The capacitance is measured with VDD, VDDQ, VSS, VSSQ applied with all other signal pins floating. Measurement procedure tbd. 2. DQ, DM_n, DQS_T, DQS_C, TDQS_T, TDQS_C. Although the DM, TDQS_T and TDQS_C pins have different functions, the loading matches DQ and DQS 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value CK_T-CK_C 5. Absolute value of CIO(DQS_T)-CIO(DQS_C) 6. CI applies to ODT, CS_n, CKE, A0-A15, BA0-BA1, BG0-BG1, RAS_n, CAS_n/A15, WE_n/A14, ACT_n and PAR. 7. CDI CTRL applies to ODT, CS_n and CKE 8. CDI_CTRL = CI(CTRL)-0.5*(CI(CLK_T)+CI(CLK_C)) 9. CDI_ADD_ CMD applies to, A0-A15, BA0-BA1, BG0-BG1,RAS_n, CAS_n/A15, WE_n/A14, ACT_n and PAR. 10. CDI_ADD_CMD = CI(ADD_CMD)-0.5*(CI(CLK_T)+CI(CLK_C)) 11. CDIO = CIO(DQ,DM)-0.5*(CIO(DQS_T)+CIO(DQS_C)) 12. Maximum external load capacitance on ZQ pin: tbd pF. 13.TEN pin may be DRAM internally pulled low through a weak pull-down resistor to VSS. In this case CTEN might not be valid and system shall verify TEN signal with Vendor specific information. - 52 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 49 ] DRAM Package Electrical Specifications (x4/x8) Symbol Parameter ZIO DDR4-1600/1866 DDR4-2133/2400 Unit NOTE 85 1,2,4,5,10,11 14 42 ps 1,3,4,5,11 3.3 - 3.3 nH 11,12 0.78 - 0.78 pF 11,13 min max min max Input/output Zpkg 45 85 45 TdIO Input/output Pkg Delay 14 42 Lio Input/Output Lpkg - Cio Input/Output Cpkg - ZIO DQS DQS_t, DQS_c Zpkg 45 85 45 85 1,2,5,10,11 TdIO DQS DQS_t, DQS_c Pkg Delay 14 42 14 42 ps 1,3,5,10,11 Lio DQS DQS Lpkg - 3.3 - 3.3 nH 11,12 Cio DQS DQS Cpkg - 0.78 - 0.78 pF 11,13 DZDIO DQS Delta Zpkg DQS_t, DQS_c - 10 - 10 1,2,5,7,10 DTdDIO DQS Delta Delay DQS_t, DQS_c - 5 - 5 ps 1,3,5,7,10 ZI CTRL Input- CTRL pins Zpkg 50 90 50 90 1,2,5,9,10,11 TdI_ CTRL Input- CTRL pins Pkg Delay 14 42 14 42 ps 1,3,5,9,10,11 Li CTRL Input CTRL Lpkg - 3.4 - 3.4 nH 11,12 Ci CTRL Input CTRL Cpkg - 0.7 - 0.7 pF 11,13 ZIADD CMD Input- CMD ADD pins Zpkg 50 90 50 90 1,2,5,8,10,11 TdIADD_ CMD Input- CMD ADD pins Pkg Delay 14 45 14 45 ps 1,3,5,8,10,11 Li ADD CMD Input CMD ADD Lpkg - 3.6 - 3.6 nH 11,12 Ci ADD CMD Input CMD ADD Cpkg - 0.74 - 0.74 pF 11,13 ZCK CLK_t & CLK_c Zpkg 50 90 50 90 1,2,5,10,11 TdCK CLK_t & CLK_c Pkg Delay 14 42 14 42 ps 1,3,5,10,11 Li CLK Input CLK Lpkg - 3.4 - 3.4 nH 11,12 Ci CLK Input CLK Cpkg - 0.7 - 0.7 pF 11,13 DZDCK Delta Zpkg CLK_t & CLK_c - 10 - 10 1,2,5,6,10 DTdCK Delta Delay CLK_t & CLK_c - 5 - 5 ps 1,3,5,6,10 ZOZQ ZQ Zpkg 40 100 40 100 1,2,5,10,11 TdO ZQ ZQ Delay 20 90 20 90 ps 1,3,5,10,11 ZO ALERT ALERT Zpkg 40 100 40 100 1,2,5,10,11 TdO ALERT ALERT Delay 20 55 20 55 ps 1,3,5,10,11 NOTE : 1. This parameter is not subject to production test. It is verified by design and characterization. The package parasitic( L & C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS and VSSQ shorted and all other signal pins shorted at the die side(not pin). Measurement procedure tbd 2. Package only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg(total per pin) = GGGGLpkg/Cpkg 3. Package only delay(Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg(total per pin) = GGLpkgCpkg 4. Z & Td IO applies to DQ, DM, TDQS_T and TDQS_C 5. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 6. Absolute value of ZCK_t-ZCK_c for impedance(Z) or absolute value of TdCK_t-TdCK_c for delay(Td). 7. Absolute value of ZIO(DQS_t)-ZIO(DQS_c) for impedance(Z) or absolute value of TdIO(DQS_t)-TdIO(DQS_c) for delay(Td) 8. ZI & Td ADD CMD applies to A0-A13,A17, ACT_n, BA0-BA1, BG0-BG1, RAS_n/16, CAS_n/A15, WE_n/A14 and PAR. 9. ZI & Td CTRL applies to ODT, CS_n and CKE 10. This table applies to monolithic X4 and X8 devices. 11. Package implementations shall meet spec if the Zpkg and Pkg Delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown. 12. It is assumed that Lpkg can be approximated as Lpkg = Zo*Td. 13. It is assumed that Cpkg can be approximated as Cpkg = Td/Zo. - 53 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 13. Electrical Characteristics & AC Timing 13.1 Reference Load for AC Timing and Output Slew Rate Figure 23 represents the effective reference load of 50 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. VDDQ 50 Ohm DUT CK_t, CK_c DQ DQS_t DQS_c Timing Reference Point VTT = VDDQ Timing Reference Point Figure 23. Reference Load for AC Timing and Output Slew Rate 13.2 tREFI Average periodic Refresh interval (tREFI) of DDR4 SDRAM is defined as shown in the table. [ Table 50 ] tREFI by Device Density Parameter Average periodic refresh interval tREFI Symbol 2Gb 4Gb 8Gb Units 0C TCASE85C 7.8 7.8 7.8 s 85C TCASE95C 3.9 3.9 3.9 s - 54 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 13.3 Timing Parameters by Speed Grade [ Table 51 ] Timing Parameters by Speed Bin for DDR4-1600 to DDR4-2400 Speed Parameter DDR4-1600 DDR4-1866 DDR4-2133 DDR4-2400 Symbol MIN MAX MIN MAX MIN MAX MIN MAX tCK (DLL_OFF) 8 20 8 20 8 20 8 20 Units NOTE ns 35,36 Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period tCK(avg) 1.25 <1.5 1.071 <1.25 0.938 <1.071 0.833 <0.938 ns Average high pulse width tCH(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) Average low pulse width tCL(avg) 0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK(avg) Absolute Clock Period tCK(abs) tCK(avg)min + tJIT(per)min _to t tCK(avg)m ax + tJIT(per)m ax_tot tCK(avg)min + tJIT(per)min _to t tCK(avg)m ax + tJIT(per)m ax_tot tCK(avg)min + tJIT(per)min _to t tCK(avg)m ax + tJIT(per)m ax_tot tCK(avg)min + tJIT(per)min _to t tCK(avg)m ax + tJIT(per)m ax_tot tCK(avg) Absolute clock HIGH pulse width tCH(abs) 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) Absolute clock LOW pulse width tCL(abs) 0.45 - 0.45 - 0.45 - 0.45 - tCK(avg) 24 JIT(per)_tot -63 63 -54 54 -47 47 -42 42 ps 23 26 Clock Period Jitter- total Clock Period Jitter- deterministic JIT(per)_dj -31 31 -27 27 -23 23 -21 21 ps Clock Period Jitter during DLL locking period tJIT(per, lck) -50 50 -43 43 -38 38 -33 33 ps Cycle to Cycle Period Jitter 23 tJIT(cc)_total 125 107 94 83 ps 25 Cycle to Cycle Period Jitter deterministic tJIT(cc)_dj 63 54 47 42 ps 26 Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 100 86 75 67 ps Duty Cycle Jitter tJIT(duty) TBD TBD TBD TBD TBD TBD TBD TBD ps Cumulative error across 2 cycles tERR(2per) -92 92 -79 79 -69 69 -61 61 ps Cumulative error across 3 cycles tERR(3per) -109 109 -94 94 -82 82 -73 73 ps Cumulative error across 4 cycles tERR(4per) -121 121 -104 104 -91 91 -81 81 ps Cumulative error across 5 cycles tERR(5per) -131 131 -112 112 -98 98 -87 87 ps Cumulative error across 6 cycles tERR(6per) -139 139 -119 119 -104 104 -92 92 ps Cumulative error across 7 cycles tERR(7per) -145 145 -124 124 -109 109 -97 97 ps Cumulative error across 8 cycles tERR(8per) -151 151 -129 129 -113 113 -101 101 ps Cumulative error across 9 cycles tERR(9per) -156 156 -134 134 -117 117 -104 104 ps Cumulative error across 10 cycles tERR(10per) -160 160 -137 137 -120 120 -107 107 ps Cumulative error across 11 cycles tERR(11per) -164 164 -141 141 -123 123 -110 110 ps Cumulative error across 12 cycles tERR(12per) -168 168 -144 144 -126 126 -112 112 ps Cumulative error across 13 cycles tERR(13per) -172 172 -147 147 -129 129 -114 114 ps Cumulative error across 14 cycles tERR(14per) -175 175 -150 150 -131 131 -116 116 ps Cumulative error across 15 cycles tERR(15per) -178 178 -152 152 -133 133 -118 118 ps Cumulative error across 16 cycles tERR(16per) -180 189 -155 155 -135 135 -120 120 ps Cumulative error across 17 cycles tERR(17per) -183 183 -157 157 -137 137 -122 122 ps Cumulative error across 18 cycles tERR(18per) -185 185 -159 159 -139 139 -124 124 ps t ERR(nper)min t = ((1 + 0.68ln(n)) * tJIT(per)_total min) ERR(nper)max = ((1 + 0.68ln(n)) * tJIT(per)_total max) Cumulative error across n = 13, 14 . . . 49, 50 cycles tERR(nper) Command and Address setup time to CK_t, CK_c referenced to Vih(ac) / Vil(ac) levels tIS(base) 115 - 100 - 80 - 62 - ps Command and Address setup time to CK_t, CK_c referenced to Vref levels tIS(Vref) 215 - 200 - 180 - 162 - ps Command and Address hold time to CK_t, CK_c referenced to Vih(dc) / Vil(dc) levels tIH(base) 140 - 125 - 105 - 87 - ps Command and Address hold time to CK_t, CK_c referenced to Vref levels tIH(Vref) 215 - 200 - 180 - 162 - ps Control and Address Input pulse width for each input tIPW 600 - 525 - 460 - 410 - ps CAS_n to CAS_n command delay for same bank group tCCD_L max(5 nCK, 6.250 ns) - max(5 nCK, 5.355 ns) - max(5 nCK, 5.625 ns) - max(5 nCK, 5 ns) - nCK 34 CAS_n to CAS_n command delay for different bank group tCCD_S 4 - 4 - 4 - 4 - nCK 34 ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size tRRD_S(2K) Max(4nCK,6 ns) - Max(4nCK,5 .3ns) - Max(4nCK,5 .3ns) - Max(4nCK,5 .3ns) - nCK 34 ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size tRRD_S(\1K) Max(4nCK,5 ns) Max(4nCK,4 .2ns) Max(4nCK,3 .7ns) Max(4nCK,3 .3ns) - nCK 34 tRRD_S(1/2K) Max(4nCK,5 ns) Max(4nCK,4 .2ns) Max(4nCK,3 .7ns) Max(4nCK,3 .3ns) - nCK 34 ps Command and Address Timing ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size - 55 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD Speed DDR4-1600 DDR4 SDRAM DDR4-1866 DDR4-2133 DDR4-2400 Units NOTE - nCK 34 Max(4nCK,4 .9ns) - nCK 34 Max(4nCK,5 .3ns) Max(4nCK,4 .9ns) - nCK 34 Max(28nCK, 30ns) Max(28nCK, 30ns) Max(28nCK, 30ns) - ns 34 Max(20nCK, 25ns) Max(20nCK, 23ns) Max(20nCK, 21ns) Max(20nCK, 21ns) - ns 34 tFAW_1/2K Max(16nCK, 20ns) Max(16nCK, 17ns) Max(16nCK, 15ns) Max(16nCK, 13ns) - ns 34 Delay from start of internal write transaction to internal read command for different bank group tWTR_S max(2nCK,2. 5ns) - max(2nCK,2 .5ns) - max(2nCK,2 .5ns) - max (2nCK, 2.5ns) - 1,2,e,3 4 Delay from start of internal write transaction to internal read command for same bank group tWTR_L max(4nCK,7. 5ns) - max(4nCK,7 .5ns) - max(4nCK,7 .5ns) - max (4nCK,7.5ns ) - 1,34 Internal READ Command to PRECHARGE Command delay tRTP max(4nCK,7. 5ns) - max(4nCK,7 .5ns) - max(4nCK,7 .5ns) - max (4nCK,7.5ns ) - 34 WRITE recovery time tWR 15 - 15 - 15 - 15 - ns 1 Write recovery time when CRC and DM are enabled tWR_CRC _DM tWR+max (4nCK,3.75n s) - tWR+max (5nCK,3.75n s) - tWR+max (5nCK,3.75n s) - tWR+max (5nCK,3.75n s) - ns 1, 28 delay from start of internal write transaction to internal read command for different bank group with both CRC and DM enabled tWTR_S_C RC_DM tWTR_S+ma x (4nCK,3.75n s) - tWTR_S+ma x (5nCK,3.75n s) - tWTR_S+ma x (5nCK,3.75n s) - tWTR_S+ma x (5nCK,3.75n s) - ns 2, 29, 34 delay from start of internal write transaction to internal read command for same bank group with both CRC and DM enabled tWTR_L_C RC_DM tWTR_L+ma x (4nCK,3.75n s) - tWTR_L+ma x (5nCK,3.75n s) - tWTR_L+ma x (5nCK,3.75n s) - tWTR_L+ma x (5nCK,3.75n s) - ns 3,30, 34 DLL locking time tDLLK 597 - 597 - 768 - 768 - nCK Mode Register Set command cycle time tMRD 8 - 8 - 8 - 8 - nCK tMOD max(24nCK, 15ns) - max(24nCK, 15ns) - max(24nCK, 15ns) - max(24nCK, 15ns) - Parameter Symbol MIN ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size tRRD_L(2K) Max(4nCK,7. 5ns) Max(4nCK,6 .4ns) ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size tRRD_L(1K) Max(4nCK,6 ns) ACTIVATE to ACTIVATE Command delay to same bank group for 1/2KB page size tRRD_L(1/2K) Four activate window for 2KB page size Four activate window for 1KB page size Four activate window for 1/2KB page size Mode Register Set command update delay Multi-Purpose Register Recovery Time MAX MIN MAX MIN MAX MIN MAX Max(4nCK,6 .4ns) Max(4nCK,6 .4ns) Max(4nCK,5 .3ns) Max(4nCK,5 .3ns) Max(4nCK,6 ns) Max(4nCK,5 .3ns) tFAW_2K Max(28nCK, 35ns) tFAW_1K tMPRR 1 - 1 - 1 - 1 - nCK Multi Purpose Register Write Recovery Time tWR_MPR tMOD (min) + AL + PL - tMOD (min) + AL + PL - tMOD (min) + AL + PL - tMOD (min) + AL + PL - - Auto precharge write recovery + precharge time tDAL(min) DQ0 or DQL0 driven to 0 set-up time to first DQS rising edge tPDA_S 0.5 - 0.5 - 0.5 - 0.5 - UI 45,47 DQ0 or DQL0 driven to 0 hold time from last DQS fall-ing edge tPDA_H 0.5 - 0.5 - 0.5 - 0.5 - UI 46,47 tCAL 3 - 4 - 4 - 5 - nCK tDQSQ - 0.16 - 0.16 - 0.16 - 0.16 tCK(avg) /2 13,18 tQH 0.76 - 0.76 - 0.76 - 0.76 - tCK(avg) /2 13,17,1 8 Data Valid Window per device: tQH - tDQSQ for a device tDVWd 0.63 - 0.63 - 0.64 - 0.64 - UI 16,17,1 8 Data Valid Window per device, per pin: tQH tDQSQ each device’s output tDVWp 0.66 - 0.66 - 0.69 - 0.72 - UI 16,17,1 8 0.9 NOTE44 0.9 NOTE44 0.9 NOTE44 0.9 NOTE 44 tCK 40 NA NA NA NA NA NA 1.8 NOTE 44 tCK 41 Programmed WR + roundup ( tRP / tCK(avg)) 33 nCK CS_n to Command Address Latency CS_n to Command Address Latency DRAM Data Timing DQS_t,DQS_c to DQ skew, per group, per access DQ output hold time from DQS_t,DQS_c Data Strobe Timing DQS_t, DQS_c differential READ Preamble tRPRE DQS_t, DQS_c differential READ Postamble tRPST 0.33 TBD 0.33 TBD 0.33 TBD 0.33 TBD tCK DQS_t,DQS_c differential output high time tQSH 0.4 - 0.4 - 0.4 - 0.4 - tCK 21 DQS_t,DQS_c differential output low time tQSL 0.4 - 0.4 - 0.4 - 0.4 - tCK 20 0.9 - 0.9 - 0.9 - 0.9 - tCK 42 1.8 - tCK 43 DQS_t, DQS_c differential WRITE Preamble tWPRE NA NA NA DQS_t, DQS_c differential WRITE Postamble tWPST 0.33 TBD 0.33 TBD 0.33 TBD 0.33 TBD tCK DQS_t and DQS_c low-impedance time (Referenced from RL-1) tLZ(DQS) -450 225 -390 195 -360 180 -300 150 ps - 56 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD Speed Parameter DDR4-1600 DDR4 SDRAM DDR4-1866 DDR4-2133 DDR4-2400 Units NOTE Symbol MIN MAX MIN MAX MIN MAX MIN MAX DQS_t and DQS_c high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 225 - 195 - 180 - 150 ps DQS_t, DQS_c differential input low pulse width tDQSL 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK DQS_t, DQS_c differential input high pulse width tDQSH 0.46 0.54 0.46 0.54 0.46 0.54 0.46 0.54 tCK DQS_t, DQS_c rising edge to CK_t, CK_c rising edge (1 clock preamble) tDQSS -0.27 0.27 -0.27 0.27 -0.27 0.27 -0.27 0.27 tCK DQS_t, DQS_c falling edge setup time to CK_t, CK_c rising edge tDSS 0.18 - 0.18 - 0.18 - 0.18 - tCK DQS_t, DQS_c falling edge hold time from CK_t, CK_c rising edge tDSH 0.18 - 0.18 - 0.18 - 0.18 - tCK DQS_t, DQS_c rising edge output timing locatino from rising CK_t, CK_c with DLL On mode tDQSCK (DLL On) -225 225 -195 195 -180 180 -175 175 ps 37,38,3 9 DQS_t, DQS_c rising edge output variance window per DRAM tDQSCKI (DLL On) 290 ps 37,38,3 9 370 330 310 MPSM Timing Command path disable delay upon MPSM entry tMPED tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - Valid clock requirement after MPSM entry tCKMPE tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - tMOD(min) + tCPDED(min) - Valid clock requirement before MPSM exit tCKMPX tCKSRX(min ) - tCKSRX(min ) - tCKSRX(min ) - tCKSRX(min ) - Exit MPSM to commands not requiring a locked DLL tXMP tXS(min) - tXS(min) - tXS(min) - tXS(min) - tXMPDLL tXMP(min) + tXSDLL(min) - tXMP(min) + tXSDLL(min) - tXMP(min) + tXSDLL(min) - tXMP(min) + tXSDLL(min) - tMPX_S tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - tIS(min) + tIHL(min) - Power-up and RESET calibration time tZQinit 1024 - 1024 - 1024 - 1024 - nCK Normal operation Full calibration time tZQoper 512 - 512 - 512 - 512 - nCK tZQCS 128 - 128 - 128 - 128 - nCK tXPR max (5nCK,tRFC( min)+ 10ns) - max (5nCK,tRFC( min)+ 10ns) - max (5nCK,tRFC( min)+ 10ns) - max (5nCK,tRFC( min)+10ns) - Exit Self Refresh to commands not requiring a locked DLL tXS tRFC(min)+1 0ns - tRFC(min)+1 0ns - tRFC(min)+1 0ns - tRFC(min)+1 0ns - SRX to commands not requiring a locked DLL in Self Refresh ABORT tXS_ABORT(min ) tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - Exit Self Refresh to ZQCL,ZQCS and MRS (CL,CWL,WR,RTP and Gear Down) tXS_FAST (min) tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - tRFC4(min)+ 10ns - Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE(min)+1 nCK - tCKE(min)+1 nCK - tCKE(min)+1 nCK - tCKE(min)+1 nCK - Minimum CKE low width for Self refresh entry to exit timing with CA Parity enabled tCKESR_ PAR tCKE(min)+ 1nCK+PL - tCKE(min)+ 1nCK+PL - tCKE(min)+ 1nCK+PL - tCKE(min)+ 1nCK+PL - tCKSRE max(5nCK,1 0ns) - max(5nCK,1 0ns) - max(5nCK,1 0ns) - max (5nCK,10ns) - Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down when CA Parity is enabled tCKSRE_PAR max (5nCK,10ns) +PL - max (5nCK,10ns) +PL - max (5nCK,10ns) +PL - max (5nCK,10ns) +PL - Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX max(5nCK,1 0ns) - max(5nCK,1 0ns) - max(5nCK,1 0ns) - max (5nCK,10ns) - tXP max (4nCK,6ns) - max (4nCK,6ns) - max (4nCK,6ns) - max (4nCK,6ns) - tCKE max (3nCK, 5ns) - max (3nCK, 5ns) - max (3nCK, 5ns) - max (3nCK, 5ns) - tCPDED 4 - 4 - 4 - 4 - Exit MPSM to commands requiring a locked DLL CS setup time to CKE Calibration Timing Normal operation Short calibration time Reset/Self Refresh Timing Exit Reset from CKE HIGH to a valid command Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) Power Down Timing Exit Power Down with DLL on to any valid command;Exit Precharge Power Down with DLL frozen to commands not requiring a locked DLL CKE minimum pulse width Command pass disable delay - 57 - 31,32 nCK Rev. 1.41 datasheet K4A4G045WD K4A4G085WD Speed Parameter DDR4-1600 DDR4 SDRAM DDR4-1866 DDR4-2133 DDR4-2400 Units NOTE Symbol MIN MAX MIN MAX MIN MAX MIN MAX tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tACTPDEN 1 - 1 - 2 - 2 - nCK 7 Timing of PRE or PREA command to Power Down entry tPRPDEN 1 - 1 - 2 - 2 - nCK 7 Timing of RD/RDA command to Power Down entry tRDPDEN RL+4+1 - RL+4+1 - RL+4+1 - RL+4+1 - nCK Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) tWRPDEN WL+4+(tWR/ tCK(avg)) - WL+4+(tWR/ tCK(avg)) - WL+4+(tWR/ tCK(avg)) - WL+4+(tWR/ tCK(avg)) - nCK 4 tWRAPDEN WL+4+WR+ 1 - WL+4+WR+ 1 - WL+4+WR+ 1 - WL+4+WR+ 1 - nCK 5 Timing of WR command to Power Down entry (BC4MRS) tWRPBC4DEN WL+2+(tWR/ tCK(avg)) - WL+2+(tWR/ tCK(avg)) - WL+2+(tWR/ tCK(avg)) - WL+2+(tWR/ tCK(avg)) - nCK 4 Timing of WRA command to Power Down entry (BC4MRS) tWRAPBC4DEN WL+2+WR+ 1 - WL+2+WR+ 1 - WL+2+WR+ 1 - WL+2+WR+ 1 - nCK 5 Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 2 - 2 - nCK 7 Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) - - Mode Register Set command cycle time in PDA mode tMRD_PDA max(16nCK, 10ns) Mode Register Set command update delay in PDA mode tMOD_PDA Power Down Entry to Exit Timing Timing of ACT command to Power Down entry Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF) 6 PDA Timing max(16nCK, 10ns) tMOD max(16nCK, 10ns) tMOD max(16nCK, 10ns) tMOD - tMOD - ODT Timing Asynchronous RTT turn-on delay (PowerDown with DLL frozen) tAONAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns Asynchronous RTT turn-off delay (PowerDown with DLL frozen) tAOFAS 1.0 9.0 1.0 9.0 1.0 9.0 1.0 9.0 ns tADC 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tCK(avg) tWLMRD 40 - 40 - 40 - 40 - nCK 12 tWLDQSEN 25 - 25 - 25 - 25 - nCK 12 Write leveling setup time from rising CK_t, CK_c crossing to rising DQS_t/DQS_n crossing tWLS 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg) Write leveling hold time from rising DQS_t/ DQS_n crossing to rising CK_t, CK_ crossing tWLH 0.13 - 0.13 - 0.13 - 0.13 - tCK(avg) Write leveling output delay tWLO 0 9.5 0 9.5 0 9.5 0 9.5 ns Write leveling output error tWLOE RTT dynamic change skew Write Leveling Timing First DQS_t/DQS_n rising edge after write leveling mode is programmed DQS_t/DQS_n delay after write leveling mode is programmed ns CA Parity Timing Commands not guaranteed to be executed during this time tPAR_UNKNOWN - PL - PL - PL - PL - Delay from errant command to ALERT_n assertion tPAR_ALERT_ ON - PL+6ns - PL+6ns - PL+6ns - PL+6ns - Pulse width of ALERT_n signal when asserted tPAR_ALERT_ PW 48 96 56 112 64 128 72 144 nCK Time from when Alert is asserted till controller must start providing DES commands in Persistent CA parity mode tPAR_ALERT _RSP - 43 - 50 - 57 - 64 nCK Parity Latency PL 4 4 4 5 nCK CRC Error Reporting CRC error to ALERT_n latency tCRC_ALERT 3 13 3 13 3 13 3 13 ns CRC ALERT_n pulse width CRC_ALERT_ PW 6 10 6 10 6 10 6 10 nCK 2Gb 160 - 160 - 160 - 160 - ns 34 4Gb 260 - 260 - 260 - 260 - ns 34 8Gb 350 - 350 - 350 - 350 - ns 34 16Gb TBD - TBD - TBD - TBD - ns 34 2Gb 110 - 110 - 110 - 110 - ns 34 4Gb 160 - 160 - 160 - 160 - ns 34 8Gb 260 - 260 - 260 - 260 - ns 34 16Gb TBD - TBD - TBD - TBD - ns 34 tREFI tRFC1 (min) tRFC2 (min) - 58 - Speed Parameter tRFC4 (min) Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4-1600 Symbol MIN DDR4-1866 MAX MIN DDR4 SDRAM DDR4-2133 MAX MIN DDR4-2400 MAX MIN MAX Units NOTE 2Gb 90 - 90 - 90 - 90 - ns 34 4Gb 110 - 110 - 110 - 110 - ns 34 8Gb 160 - 160 - 160 - 160 - ns 34 16Gb TBD - TBD - TBD - TBD - ns 34 - 59 - K4A4G045WD K4A4G085WD datasheet Rev. 1.41 DDR4 SDRAM NOTE : 1. Start of internal write transaction is defined as follows : For BL8 (Fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL. 2. A separate timing parameter will cover the delay from write to read when CRC and DM are simultaneously enabled 3. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 4. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer. 5. WR in clock cycles as programmed in MR0. 6. tREFI depends on TOPER. 7. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 8. For these parameters, the DDR4 SDRAM device supports tnPARAM[nCK]=RU{tPARAM[ns]/tCK(avg)[ns]}, which is in clock cycles assuming all input clock jitter specifications are satisfied 9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR. 10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S. 11. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L. 12. The max values are system dependent. 13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are tbd. 14. The deterministic component of the total timing. Measurement method tbd. 15. DQ to DQ static offset relative to strobe per group. Measurement method tbd. 16. This parameter will be characterized and guaranteed by design. 17 When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of the input clock. (output deratings are relative to the SDRAM input clock). Example tbd. 18. DRAM DBI mode is off. 19. DRAM DBI mode is enabled. Applicable to x8 and x16 DRAM only. 20. tQSL describes the instantaneous differential output low pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge 21. tQSH describes the instantaneous differential output high pulse width on DQS_t - DQS_c, as measured from on falling edge to the next consecutive rising edge 22. There is no maximum cycle time limit besides the need to satisfy the refresh interval tREFI 23. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge 24. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge 25. Total jitter includes the sum of deterministic and random jitter terms for a specified BER. BER target and measurement method are tbd. 26. The deterministic jitter component out of the total jitter. This parameter is characterized and gauranteed by design. 27. This parameter has to be even number of clocks 28. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR. 29. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S. 30. When CRC and DM are both enabled tWTR_L_CRC_DM is used in place of tWTR_L. 31. After CKE is registered LOW, CKE signal level shall be maintained below VILDC for tCKE specification ( Low pulse width ). 32. After CKE is registered HIGH, CKE signal level shall be maintained above VIHDC for tCKE specification ( HIGH pulse width ). 33. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 34. Parameters apply from tCK(avg)min to tCK(avg)max at all standard JEDEC clock period values as stated in the Speed Bin Tables. 35. This parameter must keep consistency with Speed-Bin Tables shown in Device Operation. 36. DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. UI=tCK(avg).min/2 37. applied when DRAM is in DLL ON mode. 38. Assume no jitter on input clock signals to the DRAM 39. Value is only valid for RZQ/7 40. 1tCK toggle mode with setting MR4:A11 to 0 41. 2tCK toggle mode with setting MR4:A11 to 1, which is valid for DDR4-2400 speed grade. 42. 1tCK mode with setting MR4:A12 to 0 43. 2tCK mode with setting MR4:A12 to 1, which is valid for DDR4-2400 speed grade. 44. The maximum read preamble is bounded by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See Device Operation. to Data Strobe Relationship”. Boundary of DQS Low-Z occur one cycle earlier in 2tCK toggle mode which is illustrated in See Device Operation Preamble. 45.DQ falling signal middle-point of transferring from High to Low to first rising edge of DQS diff-signal cross-point 46. last falling edge of DQS diff-signal cross-point to DQ rising signal middle-point of transferring from Low to High 47. VrefDQ value must be set to either its midpoint or Vcent_DQ(midpoint) in order to capture DQ0 or DQL0 low level for entering PDA mode. - 60 - Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM 13.4 The DQ Input Receiver Compliance Mask for Voltage and Timing The DQ input receiver compliance mask for voltage and timing is shown in the figure below. The receiver mask (Rx Mask) defines area the input signal must not encroach in order for the DRAM input receiver to be expected to be able to successfully capture a valid input signal with BER of 1e-16; any input signal encroaching within the Rx Mask is subject to being invalid data. The Rx Mask is the receiver property for each DQ input pin and it is not the valid data-eye. Figure 24. DQ Receiver(Rx) compliance mask DQx DQz DQy (Smallest Vref_DQ Level) Vcent_DQx (Largest Vref_DQ Level) Vcent_DQz Vcent_DQy Vcent_DQ(midpoint) Vref variation (Component) Figure 25. Vcent_DQ Variation to Vcent_DQ(midpoint) The Vref_DQ voltage is an internal reference voltage level that shall be set to the properly trained setting, which is generally Vcent_DQ(midpoint), in order to have valid Rx Mask values. Vcent_DQ is defined as the midpoint between the largest Vref_DQ voltage level and the smallest Vref_DQ voltage level across all DQ pins for a given DDR4 DRAM component. Each DQ pin Vref level is defined by the center, i.e. widest opening, of the cumulative data input eye as depicted in Figure 24.This clarifies that any DDR4 DRAM component level variation must be accounted for within the DDR4 DRAM Rx mask.The component level Vref will be set by the system to account for Ron and ODT settings. - 61 - Rev. 1.41 datasheet DQS, DQs Data-in at DRAM Ball Rx Mask DDR4 SDRAM DQS, DQs Data-in at DRAM Ball Rx Mask - Alternative View DQS_t DQS_t DQS_c DQS_c DRAMa Rx Mask DQx-z 0.5xTdiVW 0.5xTdiVW VdiVW 0.5xTdiVW 0.5xTdiVW DRAMa TdiVW tDQS2DQ + 0.5 x TdiVW DRAMb Rx Mask VdiVW Rx Mask TdiVW DQy tDQ2DQ DQz VdiVW DRAMb tDQ2DQ Rx Mask Rx Mask DRAMb TdiVW DQz tDQ2DQ VdiVW DQy VdiVW tDQS2DQ DRAMb Rx Mask DQx-z TdiVW VdiVW K4A4G045WD K4A4G085WD tDQS2DQ + 0.5 x TdiVW tDQ2DQ VdiVW DQy Rx Mask TdiVW DQz tDQ2DQ DRAMc Rx Mask DRAMc VdiVW DQz Rx Mask DRAMc DQy Rx Mask TdiVW VdiVW DRAMc VdiVW tDQS2DQ tDQ2DQ NOTE : DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask. NOTE : DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with early skews (negative tDQS2DQ). NOTE : Figures show skew allowed between DRAM to DRAM and DQ to DQ for a DRAM. Signals assume data centered aligned at DRAM Latch. TdiPW is not shown; composite data-eyes shown would violate TdiPW. VCENT DQ(midpoint) is not shown but is assummed to be midpoint of VdiVW.. Figure 26. DQS to DQ and DQ to DQ Timings at DRAM Balls All of the timing terms in Figure 26 are measured at the VdIVW_voltage levels centered around Vcent_DQ(midpoint) and are referenced to the DQS_t/ DQS_c center aligned to the DQ per pin. - 62 - datasheet K4A4G045WD K4A4G085WD Rev. 1.41 DDR4 SDRAM The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in Figure 5A below: A low to high transition tr1 is measured from 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint) while tr2 is measured from the last transition through 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min) above Vcent_DQ(midpoint). Rising edge slew rate equations: srr1 = VdIVW(max) / tr1 srr2 = (VIHL_AC(min) – VdIVW(max)) / (2*tr2) Rx Mask 0.5*VdiVW(max) Vcent_DQ(midpoint) 0.5*VdiVW(max) VdiVW(max) 0.5*VHL_AC(min) 0.5*VHL_AC(min) VHL_AC(min) tr2 tr1 Figure 27. Slew Rate Conditions For Rising Transition The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in Figure 5B below: A high to low transition tf1 is measured from 0.5*VdiVW(max) above Vcent_DQ(midpoint) to the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint) while tf2 is measured from the last transition through 0.5*VdiVW(max) below Vcent_DQ(midpoint) to the first transition through the 0.5*VIHL_AC(min) below Vcent_DQ(pin mid). tr1 Rx Mask 0.5*VdiVW(max) Vcent_DQ(midpoint) 0.5*VdiVW(max) tr2 Figure 28. Slew Rate Conditions For Falling Transition - 63 - VdiVW(max) 0.5*VHL_AC(min) 0.5*VHL_AC(min) VHL_AC(min) Falling edge slew rate equations: srf1 = VdIVW(max) / tf1 srf2 = (VIHL_AC(min) – VdIVW(max)) / (2*tf2) Rev. 1.41 datasheet K4A4G045WD K4A4G085WD DDR4 SDRAM [ Table 52 ] DRAM DQs In Receive Mode; * UI=tck(avg)min/2 Symbol Parameter 1600/1866/2133 min 2400 max 136 Unit NOTE min max - 130 mV 1,2,10 - 0.2 UI* 1,2,10 160 - mV 3,4,10 UI* 5,10 VdIVW Rx Mask voltage - pk-pk - TdIVW Rx timing window - VIHL_AC DQ AC input swing pk-pk 186 TdIPW DQ input pulse width 0.58 tDQS2DQ Rx Mask DQS to DQ offset -0.17 0.17 -0.17 0.17 UI* 6, 10 tDQ2DQ Rx Mask DQ to DQ offset - tbd - tbd UI* 7 1.0 9 1.0 9 V/ns 8,10 - - 1.25 9 V/ns 8,10 Input Slew Rate over VdIVW if tCK >= 0.935ns srr1, srf1 Input Slew Rate over VdIVW if 0.935ns > tCK >= 0.625ns 0.2 - 0.58 srr2 Rising Input Slew Rate over 1/2 VIHL_AC 0.2*srr1 9 0.2*srr1 9 V/ns 9,10 srf2 Falling Input Slew Rate over 1/2 VIHL_AC 0.2*srf1 9 0.2*srf1 9 V/ns 9,10 NOTE : 1. Data Rx mask voltage and timing total input valid window where VdIVW is centered around Vcent_DQ( midpoint) after VrefDQ training is completed. The data Rx mask is applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER = e-16 when the RxMask is not violated. The BER will be characterized and extrapolated if necessary using a dual dirac method from a higher BER(tbd). 2. Defined over the DQ internal Vref range 1. 3. See Overshoot and Undershoot Specification. 4. DQ input pulse signal swing into the receiver must meet or exceed VIHL AC(min). . VIHL_AC(min) is to be achieved on an UI basis when a rising and falling edge occur in the same UI, i.e. a valid TdiPW. 5. DQ minimum input pulse width defined at the Vcent_DQ( midpoint). 6. DQS to DQ offset is skew between DQS and DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls over process, voltage, and temperature. 7. DQ to DQ offset is skew between DQs within a nibble (x4) or word (x8, x16) at the DDR4 SDRAM balls for a given component over process, voltage, and temperature. 8. Input slew rate over VdIVW Mask centered at Vcent_DQ( midpoint). Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7 V/ns of each other. 9. Input slew rate between VdIVW Mask edge and VIHL_AC(min) points. 10. All Rx Mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW(min), VdiVW(max), and minimum slew rate limits, then either TdiVW(min) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated. - 64 - K4A4G045WD K4A4G085WD Rev. 1.41 datasheet DDR4 SDRAM 13.5 DDR4 Function Matrix DDR4 SDRAM has several features supported by ORG and also by Speed. The following Table is the summary of the features. [ Table 53 ] Function Matrix (By ORG. V:Supported, Blank:Not supported) Functions x4 x8 x16 Write Leveling V V V Temperature controlled Refresh V V V Low Power Auto Self Refresh V V V Fine Granularity Refresh V V V Multi Purpose Register V V V Data Mask V V Data Bus Inversion V V V TDQS ZQ calibration V V V DQ Vref Training V V V Per DRAM Addressability V V V Mode Register Readout V V V CAL V V V WRITE CRC V V V CA Parity V V V Control Gear Down Mode V V V Programmable Preamble V V V Maximum Power Down Mode V V V Boundary Scan Mode Additive Latency V V 3DS V V - 65 - NOTE K4A4G045WD K4A4G085WD Rev. 1.41 datasheet DDR4 SDRAM [ Table 54 ] Function Matrix (By Speed. V:Supported, Blank:Not supported) DLL Off mode Functions Write Leveling DLL On mode equal or slower than 250Mbps 1600/1866/2133 Mbps 2400Mbps V V V Temperature controlled Refresh V V V Low Power Auto Self Refresh V V V Fine Granularity Refresh V V V Multi Purpose Register V V V Data Mask V V V Data Bus Inversion V V V V V TDQS ZQ calibration V V V DQ Vref Training V V V V V Per DRAM Addressability V V CAL V V WRITE CRC V V CA Parity V V Mode Register Readout V Control Gear Down Mode V Programmable Preamble ( = 2tCK) Maximum Power Down Mode V V Boundary Scan Mode V V V 3DS V V V - 66 - NOTE