M08035/M08045 SD, HD, 3G Multi-rate Reclocker The M08035/M08045 are serial digital video reclockers with integrated trace equalization and automatic rate detect (ARD) circuitry. The M08035 operates at data rates of 270 Mbps and 1485 Mbps, while the M08045 operates at data rates of 270 Mbps, 1485 Mbps, and 2970 Mbps. The M08035/M08045 have an input jitter tolerance (IJT) of greater than 0.6 unit intervals (UI) and can provide retimed serial outputs with very low output jitter. The reclocker requires a single, external, 27 MHz crystal, which is used as the reference clock. It includes per lane input equalization for up to 40" of FR4 trace and two connectors in addition to output de-emphasis. These devices feature integrated supply regulators, allowing them to be powered from 1.2 V, 1.8 V, 2.5 V, or 3.3 V supply voltages. When operating at 1.2 V, they consume only 230 mW at 3G and HD. Furthermore, the power rails for the core, input, and output circuitry are electrically independent and as such may be connected to different voltage rails on the board. This feature enables the M08035/M08045 to be DC coupled to any upstream or downstream device regardless of its input/output voltage level. These devices may be configured by setting the internal registers though standard two-wire and four-wire interfaces. Limited configuration is also possible through hardware pin settings. The M08035/M08045 are offered in green and RoHS compliant, 6 mm x 6 mm, 40-pin QFN packages. Applications Features • Surveillance/CCTV Cameras • Greater than 0.6 UI Input Jitter Tolerance • Industrial and Professional Cameras • Integrated 50 Ω input termination • Digital Video Recorders (DVR) • Input equalization and output de-emphasis for 40" of FR4 trace • Video Mixers and Switchers • 230 mW power consumption (1.2 V operation) • Digital Image Transmitter Devices • Integrated regulators for multi-voltage operation (1.2 V - 3.3 V) • Distribution Amplifiers • Electrically independent input, output, and core supply rails • Repeaters • Output enable/disable and configurable auto or manual bypass mode • Automatic and manual modes for rate indication and selection • Loss of Lock (LOL), Loss of Signal (LOS) and data rate Indication • Two-wire and four-wire serial interface programmability • Industrial operating temperature range (-40 °C to +85 °C) • Optional recovered serial clock output M08035/M08045 Block Diagram SDI0P SDI0N IE SDI1P SDI1N IE SDI2P SDI2N IE SDI3P SDI3N IE M08035, M08045 Data Sheet V1 080x5-DSH-001 4:1 Mux 50Ω Buffer W/ DE SDOAP SDOAN 50Ω Buffer W/ DE SDOB/SCLKOP SDOB/SCLKON Reclocker MACOM™ October 2014 Ordering Information Part Number Package Operating Temperature M08035G-11* 6x6 mm, 40-pin QFN package -40 °C to 85 °C M08045G-11* 6x6 mm, 40-pin QFN package -40 °C to 85 °C Revision History Revision Level Date V2 Release October 2014 A (V1) Release May 2011 Description Updated MODE_SEL, SDOB/SCLK_EN, xREG_EN description in Table 3-1. Initial release. M08035/M08045 Marking Diagram M08035 G-11 XXXX .X YYWW CC M08035, M08045 Data Sheet V1 080x5-DSH-001 M08045 G-11 XXXX .X YYWW CC MACOM™ Part Number Lot Number Date and Country Code 2 1.0 Electrical Characteristics Unless noted otherwise, specifications apply for typical recommended operating conditions shown in Table 1-2, with DVDDO = 1.2 V, AVDDCORE = 1.2 V, DVDDCORE = 1.2 V, AVDDI = 1.2 V, PCML inputs/outputs at 800 mVPPD (RLOAD = 50 Ω), and PRBS 210 – 1 test pattern at 2.97 Gbps. Table 1-1. Absolute Maximum Ratings Symbol Parameter Note Minimum Maximum Unit AVDDI Analog supply for input circuitry 1, 3 -0.5 3.6 V AVDDO Analog supply for output circuitry 1, 3 -0.5 3.6 V DVDDIO Digital supply for input/output circuitry 1, 3 -0.5 3.6 V DVDDCORE Digital core positive supply 1, 3 -0.5 1.5 V AVDDCORE Analog core positive supply 1, 3 -0.5 1.5 V TSTORE Storage Temperature 1, 3 -65 150 °C VMAX, IO Maximum/minimum input/output voltage on any input/output pin 1, 3 -0.5 AVDDI+0.5 V VESD, HBM Human Body Model (HBM) 1, 2, 3 -2 2 kV VESD, CDM Charge Device Model (CDM) 1, 2, 3 -500 500 V 1, 3 -150 150 mA LU Latch Up @ 85 °C NOTES: 1. Exposure of the device beyond the minimum/maximum limits may cause permanent damage. Limits listed in the above table are stress limits only, and do not imply functional operation within these limits. 2. HBM and CDM per JEDEC Class 2 (JESD22-A114-B). 3. Limits listed in the above table are stress limits only and do not imply functional operation within these limits. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 3 Electrical Characteristics Table 1-2. Recommended Operating Conditions Symbol Parameter Minimum Typical Maximum Unit DVDDIO Digital I/O positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 V AVDDI Analog input positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 V AVDDO Analog output positive supply 1.14 1.2, 1.8, 2.5, or 3.3 3.47 V AVDDCORE Analog core positive supply 1.14 1.2 1.26 V DVDDCORE Digital core positive supply 1.14 1.2 1.26 V Case Temperature -40 25 +85 °C TCASE Table 1-3. Symbol PTOTAL Power Consumption Specifications Parameter Total power consumption Conditions Note Typical Maximum Unit 1, 3 230 290 mW 1, 4 250 350 AVDDI = AVDDO=DVDDIO=DVDDCORE = 1, 3 240 300 AVDDCORE= 1.2 V 1, 4 260 360 DVDDCORE = AVDDCORE= 1.2 V 1, 3 260 370 AVDDI = DVDDIO = 1.2 V 1, 4 270 450 2, 3 720 1070 AVDDI = AVDDO=DVDDIO=DVDDCORE = AVDDCORE= 1.2 V SDO Swing Level 1 PTOTAL Total power consumption mW SDO Swing Level 2 PTOTAL Total power consumption mW AVDDO = 1.8 V SDO Swing Level 3 DVDDCORE = AVDDCORE= 1.2 V AVDDI = DVDDIO = 3.3 V AVDDO = 3.3 V SDO Swing Level 3 θJA Junction to ambient thermal resistance 5 35 — °C/W θJC Junction to case thermal resistance 5 3 — °C/W NOTE: 1. Internal regulators disabled. 2. Internal regulators enabled. 3. SDOB/SCLK disabled. 4. SDOB/SCLK enabled. 5. Airflow = 0 m/s. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 4 Electrical Characteristics Table 1-4. High Speed Input Electrical Specifications Symbol Parameter DR Input data rate (M08035) DR VIN Input data rate (M08045) Differential input voltage Conditions Minimum Typical Maximum Unit SD Operation — 270 — Mbps HD Operation — 1485, 1483.5 — Mbps Reclocker bypassed 18 — 3400 Mbps SD Operation — 270 — Mbps HD Operation — 1485, 1483.5 — Mbps 3G Operation — 2970, 2967 — Mbps Reclocker bypassed 18 — 3400 Mbps 300 800 1600 mVPPD AVDDI-0.6 — AVDDI+0.1 V 40 50 60 Ω 0, 2, 4, 6 — dB At the chip input (point blank) Note 1, 3 Input equalization disabled LOS enabled (default setting) VICM Input common mode voltage At the chip input (point blank) Input equalization disabled LOS enabled RIN Input Termination to AVDDI IE Input Equalization 2 — IIN Maximum high-speed input current 4 -100 100 mA NOTE: 1. For example, 1200 mVPPD = 600 mVPP for each single-ended terminal. 2. These values correspond to: off, small, medium, and large respectively. The small setting is not available in hardware mode. 3. When using long traces and input equalization enabled, MACOM recommends a minimum input swing of 400 mVPPD. With video stress patterns, DC coupling produces the best results. 4. Exposure of the device beyond the minimum/maximum limits may cause permanent damage. Limits listed in the above table are stress limits only, and do not imply functional operation within these limits. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 5 Electrical Characteristics Table 1-5. Symbol DR DR FCLOCK FCLOCK VOUT High Speed Output Electrical Specifications Parameter Conditions Minimum Typical Maximum Unit Output data rate (M08035) SD Operation — 270 — Mbps HD Operation — 1485, 1483.5 — Reclocker bypassed 18 — 3400 Output data rate (M08045) SD Operation — 270 — HD Operation — 1485, 1483.5 — 3G Operation — 2970, 2967 — Reclocker bypassed 18 — 3400 — 270 — — 1485, 1483.5 — — 270 — HD Operation — 1485, 1483.5 — 3G Operation — 2970, 2967 — Serial clock output frequency (M08035) SD Operation Serial clock output frequency (M08045) SD Operation Differential Output Swing (peak to peak, differential) 1, 7 HD Operation 1, 7 MHz MHz 2 470 600 720 Swing Level 2 2 600 800 970 Swing Level 3 2,3 960 1200 1500 DC coupled 2, 6 — AVDDO-VOUT/4 — — 85 130 ps Output common mode voltage tR/tF SDO output Rise/Fall Time From 20%-80% of the swing for all levels DCDDATA Mbps Swing Level 1 VOCM tR/tF Δ Note mVPPD Rise/Fall Time Mismatch From 20%-80% of the swing for all levels 6 — — 30 ps Output duty cycle distortion For all data rates 4 — — 15 ps 40 50 60 Ω — 0, 2, 4, 6 — dB ROUT Output Termination to AVDDO DE Output De-Emphasis 5 NOTE: 1. Serial clock output enabled. 2. Differential swing is maximum output level (De-emphasis is disabled or max level when de-emphasis is enabled), max level includes overshoot. 3. 1200 mVPPD requires AVDDO to be 1.8 V or higher. 4. Measured in reclocked mode. 5. These values correspond to: off, small, medium, and large respectively. The small setting is not available in hardware mode. 6. Guaranteed by design. 7. See Section 4.7 for information on clock data alignment. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 6 Electrical Characteristics Table 1-6. Digital Input/Output Electrical Characteristics Symbol Parameter Note Minimum Maximum Unit VOH Output Logic High 1 0.80 x DVDDIO — V VOL Output Logic Low 2 — 0.2 x DVDDIO V VIH Input Logic High — 0.85 x DVDDIO DVDDIO + 0.5 V VIF Input Logic Floating — 0.25 x DVDDIO 0.75 x DVDDIO V VIL Input Logic Low — 0 0.15 x DVDDIO V NOTE: 1. IOH = -3 mA 2. IOL = 3 mA Table 1-7. Symbol tLOCK FLBW, PEAK Reclocker Specifications (M08035) Parameter Lock time (asynchronous) Conditions Automatic rate detection enabled Loop bandwidth peaking Note Minimum Typical Maximum Unit 1 — — 6 ms 1 — 0.1 — dB MHz Loop bandwidth (nominal setting) HD operation (1.485 Gbps) 1 — 0.85 — SD operation (270 Mbps) 1 — 0.17 — JTOL Input jitter tolerance HD, and SD operation 2 > 0.6 — — UI p-p JGEN Total Output jitter HD operation (1.485 Gbps) 2, 3 — 0.04 0.06 UI p-p SD operation (270 Mbps) 2, 3 — 0.02 0.05 FLBW NOTE: 1. 0.2 UI input jitter applied at SDI input. 2. Measured with PRBS210-1. 3. Input jitter = 20 ps p-p. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 7 Electrical Characteristics Table 1-8. Symbol tLOCK FLBW, PEAK FLBW Reclocker Specifications (M08045) Parameter Lock time (asynchronous) Conditions Note Minimum Typical Maximum Unit 1 — — 6 ms 1 — 0.1 — dB 3G operation (2.97 Gbps) 1 — 1.7 — MHz HD operation (1.485 Gbps) 1 — 0.85 — SD operation (270 Mbps) 1 — 0.17 — Automatic rate detection enabled Loop bandwidth peaking Loop bandwidth (nominal setting) JTOL Input jitter tolerance 3G, HD, and SD operation 2 > 0.6 — — UI p-p JGEN Total Output jitter 3G operation (2.97 Gbps) 2, 3 — 0.07 0.11 UI p-p HD operation (1.485 Gbps) 2, 3 — 0.04 0.06 SD operation (270 Mbps) 2, 3 — 0.02 0.05 NOTE: 1. 0.2 UI input jitter applied at SDI input. 2. Measured with PRBS210-1. 3. Input jitter = 20 ps p-p. Table 1-9. Symbol FREF FREF, ppm CLOAD XTALP/N and Reference Clock Electrical Specifications Parameter Note Minimum Typical Maximum Unit XTAL/Ref clock frequency 3 — 27 — MHz XTAL/Ref clock frequency accuracy — -100 0 100 ppm XTAL load capacitance 1 — 20 — pF 2, 4 — — 1 ps 2 40 — 60 % CLOCKJITT Jitter (RMS) CLOCKDCT Reference clock duty cycle tolerance RIN Input impedance 2, 5 200 750 1500 Ω VIN Input amplitude 2 0.8 — 1.2 V tR/tF Rise/Fall time 2, 6 — 2 6 ns NOTE: 1. This capacitance is supplied internally (no external cap is required). 2. When using an external reference clock source, this should be AC coupled through a 0.1 µF capacitor. 3. When using an external clock a small increase in jitter may be seen. For best performance a crystal is recommended. 4. Jitter bandwidth is from 12 kHz to 20 MHz. 5. Measured with TDR module. 6. 10% to 90% rise and fall times. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 8 2.0 Typical Performance Characteristics Figure 2-1. M08035 Eye Diagram at Reclocker Input PRBS15 @ 1.485 Gbps Figure 2-2. M08035 Eye Diagram at Reclocker Output PRBS15 @ 1.485 Gbps Figure 2-3. M08045 Eye Diagram at Reclocker Input PRBS15 @ 3 Gbps Figure 2-4. M08045 Eye Diagram at Reclocker Output PRBS15 @ 3 Gbps M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 9 3.0 Pinout Diagram, Pin Description, and Package Drawing DVDDCORE DVDDIO SD/xHD SDOAP SDOAN AVDDO SDOB/SCLKP SDOB/SCLKN xALARM DVDDCORE 39 38 37 36 35 34 33 32 31 M08035/M08045 Pinout Diagram 40 Figure 3-1. MF0 1 30 XTALN/REFCLK MF1 2 29 XTALP MF2 3 28 MF5 MF3 4 27 SDOB/CLK_EN AVDDCORE 5 26 AVDDCORE SDI0P 6 25 SDI3N SDI0N 7 24 SDI3P AVDDI 8 23 AVDDI MODE_SEL 9 22 MF4 10 21 AVDDI 11 12 13 14 15 16 17 18 19 20 AVDDI SDI1P SDI1N AVDDCORE xREG_EN AVDDCORE AVDDI SDI2P SDI2N AVDDCO RE N/C M08035/M08045 6mmX6mm QFN Center Ground Pad M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 10 Pinout Diagram, Pin Description, and Package Drawing Table 3-1. M08035/M08045 Pin Description (1 of 2) Pin Name Pin Number(s) Type Description AVDDCORE 5, 14, 16, 20, 26 Power Analog positive supply AVDDI 8, 11, 17, 21, 23 Power Analog positive supply AVDDO 35 Power Analog positive supply DVDDCORE 31, 40 Power Digital Core Positive Supply DVDDIO 39 Power Digital Core Positive Supply AVSS Center Ground Pad Power Ground SDI0P, SDI0N 6, 7 PCML Input Data Input Lane0; true/complement SDI1P, SDI1N 12, 13 PCML Input Data Input Lane1; true/complement SDI2P, SDI2N 18, 19 PCML Input Data Input Lane2; true/complement SDI3P, SDI3N 24, 25 PCML Input Data Input Lane3; true/complement SDOAP, SDOAN 37, 36 PCML Output Data Output Lane A; true/complement SDOBP/SCLKP, SDOBN/SCLKN 34, 33 PCML Output Data Output Lane B; true/complement XTALP 29 Reference Clock 27 MHz reference XTAL connection XTALN/REFCLK 30 Reference Clock 27 MHz reference XTAL connection or 27 MHz reference clock input MODE_SEL 9 CMOS Input Sets the device control/configuration mode: L = Device is in register access mode with two-wire serial control (SIC2) F = Device is in hardware control mode (Hardware Mode) H = Device is in register access mode with four-wire serial control (SIC4) SDOB/SCLK_EN 27 CMOS Input SDOB/SCLK output enable: L = SDOB/SCLK output disabled F = Serial data output enabled H = Serial clock output enabled xREG_EN 15 CMOS Input Regulator enable control, as in Figure 3-6, but pull up resistor is to AVDDI. L = Integrated regulators enabled F = Integrated regulators disabled SD/xHD 38 CMOS Output CMOS SD/xHD rate indicator: L = HD/3G Data rate H = SD Rate xALARM 32 Output (Open Drain) Alarm indicator for all channels (Logical OR of all individual channel alarms). Termination - Open L = Alarm asserted H = Normal operation Serial Control Mode (two-wire/four-wire): xALARM in interrupt mode Hardware Mode: Not supported M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 11 Pinout Diagram, Pin Description, and Package Drawing Table 3-1. M08035/M08045 Pin Description (2 of 2) Pin Name Pin Number(s) Type Description MF0 1 CMOS Input Four-wire serial control Mode: Serial clock input (SCLK) Two-wire serial control Mode: Clock input from master host (SCL) Hardware Mode: Unused MF1 2 CMOS Input Four-wire serial control Mode: Serial data output (SO) Two-wire serial control Mode: Serial data I/O (SDA) Hardware Mode: Unused MF2 3 CMOS Input Four-wire serial control Mode: Serial data in (SI) Two-wire serial control Mode: Address bit 0 (ADD0) Hardware Mode: Input trace equalization control for all SDI inputs (IE_CTRL) H = Large Input EQ F = Medium Input EQ L = Input EQ disabled MF3 4 CMOS Input Four-wire serial control Mode: Active low chip select (xCS) Two-wire serial control Mode: Address bit 1 (ADD1) Hardware Mode: Output de-emphasis (DE) control for SDO outputs (DE_CTRL) H = Large Output DE F = Medium Output DE L = DE disabled MF4 22 CMOS Input Four-wire serial control Mode: Not used. Tie to DVDDIO or leave floating Two-wire serial control Mode: Address bit 2 (ADD2) Hardware Mode: Reclocker bypass control (RC_BYPASS) L/F = Normal operation, Reclocker not bypassed H = Reclocker bypassed MF5 28 CMOS Input Four-wire serial control Mode: Not used. Tie to AVSS or leave floating Two-wire serial control Mode: Address bit 3 (ADD3) Hardware Mode: SDO disable control for all outputs (SDO_DIS) H = SDO disabled output logic high L/F = SDO enabled NC M08035, M08045 Data Sheet V1 080x5-DSH-001 10 Reserved Do not connect MACOM™ 12 Pinout Diagram, Pin Description, and Package Drawing Figure 3-2. I-Analog AVDDI 50Ω SDIP AVSS Input Buffer with Trace Equalizer AVDDI 50Ω SDIN AVSS Figure 3-3. O-Analog AVDDO AVDD O 50Ω 50Ω SDON SDOP AVSS AVSS AVSS M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 13 Pinout Diagram, Pin Description, and Package Drawing Figure 3-4. Ref Clock AVDDI AVDD CORE AVDD I 500 kΩ XTALN/REFCLK 20pF 20pF REFCLK Figure 3-5. I-Digital With No Pull-up DVDD IO 2.0kΩ INPUT AVSS M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 14 Pinout Diagram, Pin Description, and Package Drawing Figure 3-6. I-Digital With Pull-up DVDD IO 100 KΩ 2.0KΩ INPUT AVSS Figure 3-7. I-Digital With Pull-down DVDD IO 2.0kΩ INPUT 100kΩ AVSS M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 15 Pinout Diagram, Pin Description, and Package Drawing Figure 3-8. 3-State/I-Digital DVDD IO DVDD IO VREF_HIGH DVDD IO 100 kΩ 2.0kΩ AVSS INPUT DVDD IO 100kΩ AVSS VREF_LOW AVSS Figure 3-9. AVSS O-Digital DVDDIO OUTPUT AVSS M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 16 Pinout Diagram, Pin Description, and Package Drawing Figure 3-10. O-Open Drain DVDD IO OUTPUT AVSS The M08035/M08045 are assembled in 40-pin, 6 mm x 6 mm Quad Flat No-Lead (QFN) packages. The exposed die paddle serves as the IC ground (AVSS), and the primary means of thermal dissipation. This die paddle should be soldered to the PCB. A cross-section of the QFN package is shown below. Figure 3-11. QFN Package Cross Section M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 17 Pinout Diagram, Pin Description, and Package Drawing Figure 3-12. Package Outline Drawing (Amkor) 2X C 0.10 0.10 A C 0.05 A1 D/2 A2 D1 0.10 N 1 2 E1/2 3 C C B E/2 E1 0.10 A3 2X D1/2 0.60 DIA. C A D A E B 2X 0 B 0.10 C SEATING PLANE C A SIDE VIEW TOP VIEW 2X 0.10 0.05 b M M C A B C D2 D2/2 4X P PIN#1 ID R0.20 N 4X P 1 2 0.45 (DATUM A OR B) 3 NX R (L) E2 (Ne-1) X e REF. e/2 e TERMINAL TIP E2/2 FOR EVEN TERMINAL/SIDE (MIN. 0.35) L e (MIN. 0.35) (Nd-1) X e REF. BOTTOM VIEW S Y M B O L <STANDARD> SYMBOLS EXPOSED PAD VARIATIONS MIN 4.20 D2 NOM 4.30 M08035, M08045 Data Sheet V1 080x5-DSH-001 MAX 4.40 MIN 4.20 E2 NOM 4.30 NOTE MAX 4.40 e N Nd Ne L b D2 E2 MACOM™ PITCH VARIATION D N S Y M B O L COMMON DIMENSIONS MIN. NOM. MAX. A A1 A2 A3 0.80 0.00 0.60 0.90 0.05 0.70 0.85 0.01 0.65 0.20 REF. N O T E O MIN. 0.30 0.18 NOM. 0.50 BSC 40 10 10 0.40 0.23 SEE EXPOSED PAD VARIATION SEE EXPOSED PAD VARIATION MAX. 0.50 0.30 T E D D1 E E1 0 P Q R 0 0.24 0.30 0.13 6.00 BSC 5.75 BSC 6.00 BSC 5.75 BSC 0.42 0.40 0.17 12˚ 0.60 0.65 0.23 18 Pinout Diagram, Pin Description, and Package Drawing Figure 3-13. Package Outline Drawing (ASE) M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 19 4.0 Functional Description 4.1 Functional Block Diagram Figure 4-1 illustrates the M08035/M08045 block diagram. The subsequent sections provide additional detail on the operation of the devices. SDI2P SDI2N SDI3P SDI3N AV DD O XTALP XTALN/REFCLK Regulator Digital Supply Crystal Oscillator 4x1 Mux Reclocker 50Ω Output Buffer Programmable De-emphasis SDI1P SDI1N 50Ω Input Buffer Programmable Equalization Regulator Analog Supply SDI0P SDI0N DVDD _CORE DVDD IO AV DD _CO RE M08035/M08045 Block Diagram AV DD I Figure 4-1. SDOAP SDOAN SDOB/SCLKP SDOB/SCLKN M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ xALARM SD/xHD SDOB/CLKEN xREG_EN MODE_SEL MF[0:5] SDOB/SCLK_EN Control Logic I 2C/SPI Serial Bus and Hardware Mode 20 Functional Description 4.2 High-Speed Differential Inputs The M08035/M08045 feature four differential inputs compatible with PCML. LVDS and LVPECL signal levels are also accommodated. Serial data to be retimed is presented to these four inputs. Each input is terminated with a 50 Ω termination to AVDDI. AVDDI can be supplied from any voltage ranging from 1.2 V to 3.3 V. In order to improve signal integrity when used in large systems, each input also comes equipped with programmable input equalization (IE) for FR4 trace. There are four settings for input equalization: 0 dB (or no equalization), 2 dB, 4 dB, and 6 dB. In serial control mode, the input equalization level for each input may be set by programming the desired value to reg00h-reg03h. Alternatively, in hardware mode, the input equalization for all of the inputs may be set globally through the IE_CTRL (MF2) pin. In hardware mode only the three settings of 0 dB, 4 dB, and 6 dB are available. In most video applications, it is important to avoid AC coupled data interfaces between devices wherever possible. In addition to reducing the number of components, DC coupling will result in more system jitter margin. In order to accommodate DC coupling with the upstream device, the AVDDI power domain of the M08035/M08045 is electrically independent from all other power domains, allowing it to be tied to the VDD of the upstream device. This is demonstrated in Figure 4-2 below. Figure 4-2. M08035/M08045 AVDDI Connected to the VDD of the Upstream Device Upstream Device VDD 1.2V – 3.3V M08035/M08045 AV DDI 50 Ω 50 Ω Alternatively and under certain conditions, the M08035/M08045 allow for the inputs to be self biased eliminating the need for an electrical connection between the supply voltages of the upstream device and the M08035/ M08045. This configuration offers the benefit of keeping the supply of the previous device and the power domain(s) of the M08035/M08045 completely isolated, while using DC coupling. AC coupling should not be used with the self bias interface. This self biasing scheme is demonstrated in Figure 4-3 below. When using the M08035/M08045 in self biased mode, specific conditions must be met: 1. The self biased inputs must be DC coupled. No AC coupling is supported in self biased mode. 2. The AVDDO of the upstream device must be 2.5 V or greater. AVDDO levels 1.2 V and 1.8 V are not supported in this mode. 3. The common mode of the upstream signals must be greater than 600 mV. 4. Internal voltage regulators are disabled. 5. All inputs are configured in self biased mode. Combination of self biased and non-self biased is not supported. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 21 Functional Description Figure 4-3. Self Biasing the Input of M08035/M08045 AVDDI do not supply a voltage AVDDO 2.5V– 3.3V 50 Ω 0.1 µF per AV DDI pin 50 Ω DC coupled only, Do not use internal voltage regulator Upstream Device M08035 /M08045 NOTE: 1. For self bias applications, no voltage must be applied to the AVDDI pin. Every AVDDI pin should be decoupled to GND with a 0.1 µF capacitor as shown in Figure 4-3. A Loss of Signal (LOS) detector monitors each input and issues an alarm when the input signal level dips below the detection threshold set in register 06h. See Section 4.3 for more information on the LOS circuit. In order to correct any duty cycle distortion (DCD) in the input signal, or any DC offset buildup in the internal signal path, a DC correction loop has been added. Programming register 0Dh bit 1 to a '1' will disable the DC correction loop for all inputs. The M08035/M08045 include a 4:1 multiplexer. This allows any one of the four input signals to be routed to the reclocker. By default SDI0 is selected to be routed to SDO0. The selected input can be set using MUX control register 07h. By default, only the selected input is powered up, with all other inputs powered down. When an input is powered down, its associated LOS circuitry is disabled. If required, all the other inputs can also be powered up by setting bit[3] in register 0Dh. This will allow a faster response if rapid input switching is required as there is no delay waiting for the circuitry to power-up and adjust to the input signal, but has the disadvantage of consuming more power. With all inputs enabled, the power consumption increases by 100 mW. 4.3 LOS (Loss of Signal) The M08035/M08045 have integrated LOS circuits on each of their four high-speed inputs. This circuit monitors the input amplitude and if it falls below the detection threshold it asserts the LOS alarm bit by setting this to a logic high. These alarm bits are latched and will need to be reset with the CLR_ALARMS, register 85h, by setting bit 0 to a high and back to a low. Hysteresis is built into the LOS circuit to avoid chattering. The LOS threshold can be set to a different level by using the bits[7:5] in register 06h, this changes the level on all four inputs. By default, the LOS alarm mutes the signal from that particular input. Setting register 06h bit[3] to a high will disable this feature. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 22 Functional Description 4.4 High-Speed Output Description There are two high-speed outputs available on the M08035/M08045. By default, only SDOA is powered up, setting bit 2 of register 0Ch high will enable SDOB. The output signal will be a copy of SDOA. In hardware mode, SDOB is enabled with the SDOB/SCLK_EN input pin in a floating (F) or high (H) (see Table 3-1). A further function of this output is a serial clock source. By setting register 06h, bit 0 to high, the reclockers recovered clock is output to the SDOB/SCLK pins. In hardware mode this function is selected by setting SDOB/ SCLK_EN high (see Table 3-1). The M08035/M08045 feature differential current mode logic (CML) drivers with integrated 50 Ω pull ups to AVDDO for the output of each reclocker channel. AVDDO may be supplied from any voltage ranging from 1.2 V to 3.3 V. The differential, peak-to-peak, output swing for each CML driver is programmable and may be set to 600 mVPPD, 800 mVPPD, or 1200 mVPPD. Please note that the 1200 mVPPD output swing setting is only available when AVDDO is supplied from a voltage of 1.8 V or greater. The swing setting may be programmed by writing to register 09h for SDOA, and register 0Bh for SDOB. In order to improve signal integrity when used in large systems, each output also comes equipped with programmable de-emphasis (DE) for FR4 trace. There are four settings for output de-emphasis: 0 dB (or no DE), 2 dB, 4 dB, and 6 dB. In serial control mode, the output de-emphasis level for each input may be set by programming the desired value to register 09h for SDOA and register 0Ah for SDOB. Alternatively, in hardware mode, the de-emphasis level for all of the outputs may be globally set through pin DE_CTRL (MF3). In hardware mode only the three settings of 0 dB, 4 dB, and 6 dB are available. In most video applications, it is important to avoid AC coupled data interfaces between devices wherever possible. In addition to reducing the number of components, DC coupling will result in more system jitter margin. In order to accommodate DC coupling with the upstream device, the AVDDO power domain of the M08035/M08045 is electrically independent from all other power domains therefore allowing it to be tied to the VDD of the downstream device. This is demonstrated in Figure 4-4 below. Figure 4-4. M08035/M08045 AVDDO Connected to the VDD of the Downstream Device M08035/M08045 AVDDO 1.2V – 3.3V Downstream Device VDD 50 Ω 50 Ω If AC coupling is desired or necessary, then the capacitor should be at least 10 µF. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 23 Functional Description 4.5 Logic Signals To allow interfacing to logic levels other than the 1.2 V core voltage, or any of the analog input and output supplies, the digital interface signals are referenced to DVDDIO which is an isolated power domain. DVDDIO may be supplied from any voltage ranging from 1.2 V to 3.3 V. Many digital control pins have three states, high (H), low (L), or floating (F). In order to assert the F or floating state, the pin must be left unconnected or undriven. 4.6 Control Modes The M08035/M08045 may be configured in four separate control modes. The control mode is determined by the setting of the MODE_SEL pin as shown in Table 4-1 below. Table 4-1. Control Mode Setting MODE_SEL Control Mode MODE_SEL = F Hardware Control Mode (HIC) MODE_SEL = H Four-wire Serial Interface Control Mode (SIC4 or SPI) Two-wire Serial Interface control Mode (SIC2 or I2C) MODE_SEL = L Memory Interface Configuration Mode (MIC) When the reclocker is configured through an external EEPROM The MIC mode is a subset of the two-wire Interface mode and is initiated by writing to special reserved address when the device is set in two-wire Interface mode. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 24 Functional Description 4.6.1 HIC Mode Configuring the M08035/M08045 in hardware mode avoids the complication of adding a microcontroller, but offers limited control options. When in hardware mode, the MF (Multi Function IO) pins are configured as shown in Table 4-2 below. Table 4-2. MF Pin Configuration in Hardware Mode MF HIC Mode Pin Name MF2 IE_CTRL Function Input trace equalization control for all SDI inputs H = 6 dB Input EQ F = 2 dB Input EQ L = 0 dB Input EQ MF3 DE_CTRL Output de-emphasis (DE) control for all SDO outputs H = 6 dB of output DE F = 4 dB of output DE L = 0 dB output DE MF4 RC_BYPASS Reclockers bypass control for all outputs L/H = Normal operation, Reclocker not bypassed H = Reclocker bypassed MF5 SDO_DIS SDO disable control for all outputs H = SDO disabled output logic high L/F = SDO enabled NOTE: 4.6.2 In this mode, xALARM is not supported. Four-wire Interface Mode (SIC4) In this mode, a four-wire serial interface is used to program the device's internal registers, configuring the operation of the M08035/M08045. When in SIC4 mode, MF[0:3] pins comprise the four-wire bus as shown in Table 4-3 below. Table 4-3. MF Pin Configuration in Four-wire Interface Mode MF SIC4 Mode Pin Name Function MF0 SCLK Serial clock input MF1 SO Serial data output MF2 SI Serial Data input MF3 xCS Chip Select (active low) The interface shifts data in from the external controller on the rising edge of SCLK. The serial I/O operation is gated by xCS. Data is shifted in to the M08035/M08045 from the Host (Master) to SI on the falling edge of SCLK, and shifted out through SO on the rising edge of SCLK. To address a register, a 10-bit input needs to be shifted, consisting of the first bit (Start Bit, SB = 1), the second bit (Operation Bit, OP = 1 for read, = 0 for write), and the 8bit address (MSB first). M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 25 Functional Description Figure 4-5. Four-wire Interface Word Format Figure 4-6 illustrates a Serial Write Mode followed by a Serial Read mode. To initiate a Write sequence, xCS goes low before the falling edge of SCLK. On each falling edge of the clock, the 18 bits consisting of the SB = 1, OP = 0, ADDR, and DATA, are latched into the input shift register through SI. The rising edge of xCS may occur before or after the falling edge of SCLK for the last bit. Upon receipt of the last bit, one additional cycle of SCLK is necessary before DATA transfers from the input shift register to the addressed register. To initiate a read sequence, xCS goes low before the falling edge of SCLK. On each falling edge of SCLK, the 10 bits consisting of SB = 1, OP = 1, and the 8-bit ADDR are written to the serial input shift register and copied to the serial output shift register. On the next rising edge after the address LSB, the SB and 8 bits of the DATA are shifted out. The SB for a Read is always 1. Figure 4-6. Four-Wire Write Followed by a Read Sequence 1 2 3 ... 10 11 ... 17 18 19 20 21 22 23 ... 31 32 33 ... 41 SCLK xCS SI Tcs Tcs 1 W Address[7:0] Tdh Data[7:0] Tds Tcs Tch 1 R Address[7:0] Trdd SO D7 Dx D1 D0 The 4-wire interface supports multiple consecutive writes. In this case, the address header is not needed and each additional 8 bits of data will be written into consecutive addresses. If consecutive read/write cycles are being performed, it is not necessary to insert an extra clock cycle between read/write cycles, however one extra clock cycle is needed after the last data bit of the last read/write cycle. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 26 Functional Description Figure 4-7. Four-Wire Sequential WRITE 1 2 3 ... 11 12 13 14 ... 20 21 22 23 ... 29 30 ... SCLK xCS Tcs SI 1 R/W Address[7:0] 1st Data[7:0] Tdh 2nd Data[7:0] 3rd Data[7:0] Tds SO On a Write cycle, any bits that follow the expected number of bits are ignored, and only the first 15 bits following SB and OP are used. On a Read cycle, any extra clock cycles will result in the repeat of the data LSB. An invalid SB or OP renders the operation undefined. The falling edge of xCS always resets the serial operation for a new Read or Write cycle. Detailed timing information is shown below. Table 4-4. Four-wire Interface Timing Timing Symbol Description Min Max Unit Tds Data set-up time 5 — ns Tdh Data hold time 5 — ns Tcs xCS set-up time 5 — ns Tch xCS hold time 5 — ns Tfreq, write Four-wire interface write clock frequency — 40 MHz Tfreq, read Four-wire interface clock read frequency, DVDDIO=2.5 V or 3.3 V — 40 MHz Four-wire interface read clock frequency, DVDDIO=1.8 V — 20 MHz Four-wire interface read clock frequency, DVDDIO=1.2 V — 5 MHz SCLK duty cycle 40 60 % Read data output delay (measured with max 30 pF loading, DVDDIO=3.3 V) 1 8 ns TDUTY Tdd M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 27 Functional Description 4.6.3 Two-wire Interface Mode (SIC2) In this mode a two-wire serial interface is used to program the device's internal registers, configuring the operation of the M08035/M08045. When in SIC2 mode, MF[0:5] pins are configured as shown below. Table 4-5. MF Pin Configuration in Two-wire Interface Mode MF SIC4 Mode Pin Name Function MF0 SCL Clock input from master host MF1 SDA Serial data input/output MF2 ADD0 Address bit 0 MF3 ADD1 Address bit 1 MF4 ADD2 Address bit 2 MF5 ADD3 Address bit 3 Each device has an individual address and is addressed using an address byte, which is latched upon Power-OnReset (POR). In this mode, the M08035/M08045 are I2C-compatible slave devices that can operate at 100 kHz and 400 kHz for all allowed voltages seen at the DVDDIO pin. The M08035/M08045 allow for forty different addresses to be programmed using the inputs ADD[3:0]; these inputs have three states, low (L), high (H) and floating (F). The slave addresses are from 21h to 48h. Table 4-6. M08035/M08045 2-Wire Interface Address Map (1 of 2) Pin Setting Dec Add Hex Add Bin Add Function ADD3 ADD2 ADD1 ADD0 32 20 010 0000b L L L L EEPROM only, Address 50h 32 20 010 0000b L L L H EEPROM only, Address 51h 32 20 010 0000b L L H L EEPROM only, Address 52h 32 20 010 0000b L L H H EEPROM only, Address 53h 33 21 010 0001b L H L L Slave 1 34 22 010 0010b L H L H Slave 2 35 23 010 0011b L H L F Slave 3 36 24 010 0100 b L H H L Slave 4 37 25 010 0101b L H H H Slave 5 38 26 010 0110b L H H F Slave 6 39 27 010 0111b L H F L Slave 7 40 28 010 1000 b L H F H Slave 8 41 29 010 1001b L H F F Slave 9 42 2A 010 1010b L F L L Slave 10 43 2B 010 1011b L F L H Slave 11 44 2C 010 1100b L F L F Slave 12 45 2D 010 1101b L F H L Slave 13 M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 28 Functional Description Table 4-6. M08035/M08045 2-Wire Interface Address Map (2 of 2) Pin Setting Dec Add Hex Add Bin Add Function ADD3 ADD2 ADD1 ADD0 46 2E 010 1110b L F H H Slave 14 47 2F 010 1111b L F H F Slave 15 48 30 011 0000 b L F F L Slave 16 49 31 011 0001 b L F F H Slave 17 50 32 011 0010 b L F F F Slave 18 51 33 011 0011 b F L L L Slave 19 52 34 011 0100 b F L L H Slave 20 53 35 011 0101 b F L L F Slave 21 54 36 011 0110 b F L H L Slave 22 55 37 011 0111 b F L H H Slave 23 56 38 011 1000 b F L H F Slave 24 57 39 011 1001b F L F L Slave 25 58 3A 011 1010b F L F H Slave 26 59 3B 011 1011b F L F F Slave 27 60 3C 011 1100b F H L L Slave 28 61 3D 011 1101b F H L H Slave 29 62 3E 011 1110b F H L F Slave 30 63 3F 011 1111b F H H L Slave 31 64 40 100 0000b F H H H Slave 32 65 41 100 0001b F H H F Slave 33 66 42 100 0010b F H F L Slave 34 67 43 100 0011b F H F H Slave 35 68 44 100 0100 b F H F F Slave 36 69 45 100 0101b F F L L Slave 37 70 46 100 0110b F F L H Slave 38 71 47 100 0111b F F L F Slave 39 72 48 100 1000 b F F H L Slave 40 Table 4-7. Supported AT24C01 EEPROM Addresses Fixed by EEPROM Dec Add Hex Add Address Pin Setting Bin Add ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 80 50 010 0000b H L H L L L L 81 51 010 0001b H L H L L L H 82 52 010 0010b H L H L L H L 83 53 010 0011b H L H L L H H M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 29 Functional Description Figure 4-8 illustrates typical waveforms and timing seen at SCL and SDA for a read and write operation. Figure 4-8. Two-wire Interface Timing Diagram Table 4-8. Two-wire Interface Timing Specifications (Standard Mode or Fast Mode) Symbol Parameter Minimum Typical Maximum Unit fSCL Clock Frequency, SCL — — 400 kHz tLOW Clock Pulse Width Low 1.3 — — µs tHIGH Clock Pulse Width High 1 — — µs Clock Low to Data Out Valid 0.05 — 0.9 µs tHDSTA Start Hold Time 200 — — ns tSUSTA Start Set-up Time 200 — — ns tHDDAT Data In Hold Time 0 — — ns tSUDAT Data In Set-up Time 100 — — ns tSUSTO Stop Set-up Time 200 — — ns Data Out Hold Time 50 — — ns tAA tDH Notes: 500 pF @ 100 kHz and 250 pF @ 400 kHz with 1k Ω pull-up. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 30 Functional Description 4.6.4 MIC Mode Operation In this mode, the reclocker is initialized with an EEPROM. To use this mode, the EEPROM must be programmed with the register data required. The I2C address of the memory can be 50h, 51h, 52h or 53h; the reclocker loads its register contents from this address. This mode is enabled when the I2C mode is set and address 20h has been hardwired on the address pins. When the reclocker locates the memory at one of the above addresses, it sets itself into I2C quasi-master mode. It will then load its registers from the EEPROM. Addresses 00h to 19h should be used when only one reclocker is used. Register 0Fh contains the number of slave reclockers; if there are none this is set to 0. Once the master has finished the task of downloading the registers, it will revert to slave mode at address 20h and can be accessed for debugging purposes. Note that when using MIC power mode supply, ramp time is important. The EEPROM should be powered from the same supply as DVDDIO and the ramp up of the supply should be < 100 ms. If the ramp time is not met, the reclocker I2C will time-out before the EEPROM is ready to receive serial data. The target EEPROM is the AT24C01 or equivalent. If there is more than one reclocker to be programmed, a checksum is used to confirm that the data is correct. This works as follows: 1. The slave reclocker sums all registers from 00h to 1Ah, then truncates this to leave the 8 LSB bits. This is then compared with the value 2Eh. If it is not equal, then the registers are not loaded and it returns to the default value. It will then try up to 512 times before timing out. When the checksum is equal to 2Eh, the registers are loaded with the EEPROM settings. 2. To make the checksum = 2Eh, register 1Ah must be programmed with the 8 LSBs from the following calculation: Register 1Ah = 2Eh - (sum of registers 00h to 19h) M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 31 Functional Description 4.7 Reclocker Operation 4.7.1 Clock Recovery This block generates a serial clock signal at a frequency close to the data rate. The clock signal is generated by a phased locked loop (PLL) which uses the 27 MHz input clock as a reference. The presence of the reference clock is monitored by the device. An alarm bit (NOREF) in register 88h is set to '1' when a suitable reference clock is not present. Once the PLL has locked to the reference clock, the REFLOL bit in the same register will be set to '0'. A value of '1' in this bit indicates that the PLL has not locked to the input reference clock. The frequency locked clock signal is supplied to the phase lock block. In this block, a bang-bang phase comparator is used to make fine adjustments to the phase and frequency of the clock, aligning it with the incoming serial data. Once the clock signal is phase and frequency aligned with the serial data stream, it is used to re-time the data, producing a clean data signal that is provided at the output of the device. The phase lock block uses an integrated, programmable loop filter. The bandwidth of the phase lock block may be programmed using the BW[2:0] bits in register 16h. A wide bandwidth increases the jitter tolerance and reduces the lock time of the loop. However, a wide bandwidth also allows more jitter from the input serial data stream to be transferred to the output. Alternatively, a low bandwidth setting causes the loop to reject more of the incoming data stream's jitter, while increasing lock time, and reducing input jitter tolerance. The bandwidth setting can be optimized for each system. Furthermore, since the phase lock block uses a non-linear, bang-bang loop, the bandwidth of the system is inversely proportional to the incoming data stream's jitter. This offers several advantages over linear PLLs. It achieves higher jitter attenuation with large input jitter, while it corrects for small variations quickly with low input jitter. With higher input jitter, the loop automatically reduces the bandwidth, causing more of the jitter to be rejected. Conversely, a data stream with lower jitter will cause the loop bandwidth to be widened. Note that bandwidth settings greater than 2x will increase output jitter. When the recovered serial clock output is enabled, the clock alignment to the SDOA data output will be typically 60 ps, where the falling edge of the clock lags the transition edge of the SDOA signal. 4.7.2 Automatic Rate Detection The reclocker features an Automatic Rate Detector (ARD) circuit that monitors the input signal rate and automatically sets the reclocker to the correct video rate. The data rate determined by the ARD block may be read from bits 1:0 in register 89h as shown in Table 4-9. Table 4-9. Reclocker Rate Detection Reg89h (Bits 1:0) Function 00b Reclocker unlocked 01b SD rate detected 10b HD rate detected 11b 3G rate detected (M08045) M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 32 Functional Description As an alternative to the ARD, the user may manually set the reclocker to the desired data rate by programming bits[3:2] in register 12h to the desired values as shown in Table 4-10. Table 4-10. Reclocker Data Rate Selection Reg12h (Bits 3:2) Function 00b ARD Enabled 01b Manual SD rate programmed 10b Manual HD rate programmed 11b Manual 3G rate programmed (M08045) Please note that when configured in manual ARD mode, the reclocker is guaranteed to lock to the program data rate. However, it may also lock to the harmonics of that program data rate as well. For example, if the reclocker is programmed to lock to HD data, it will also try to lock to 3G data as 2.97 Gbps is exactly twice 1.485 Gbps. When in auto-bypass mode, if the ARD cannot determine the rate of the input data stream, it will switch the reclocker into bypass mode. This allows a data rate other than those specified to be passed through the reclocker. The auto-bypass mode may be disabled through Register 14h. 4.7.3 Lock Detection Several circuits monitor each reclocker for Loss of Lock. One in particular compares the recovered serial clock to one derived from the reference clock. If the clock frequency is within ±2000 ppm of the serial data frequency, the Loss of Lock (LOL) alarm will be set to '0'. If the clock is outside of this window, then the LOL alarm will be asserted to '1'. The LOL bit can be read from bit[0] in register 88h. 4.7.4 Reference Clock The M08035/M08045 can operate from a crystal or an external reference clock, but better jitter results are obtained with a crystal. If using an external reference clock, this should be a 27 MHz clock with a frequency accuracy of ±100 ppm or better. Reference clock jitter is important and care must be taken to supply a low jitter reference clock to the reclocker of 1 ps RMS or less. The reference clock may either be from an external CMOS clock oscillator or an external parallel resonance crystal. If a low jitter 27 MHz signal is already available on the board then it may be used. Due to the higher jitter, a genlocked 27 MHz clock is likely not suitable for this device. When supplying an external clock signal, it is recommended to use AC coupling through a 0.1 µF capacitor. Refer to Table 1-7 for recommended input levels. 4.8 SD/xHD Output When the reclocker is locked to the input data, the SD/xHD output indicates whether an SD or HD rate is detected. When a 3G rate is being received, the output will indicate HD. This output is designed to be connected to the slew rate control on a downstream cable driver. The SD/xHD pin has two available modes as shown in Table 4-11. These are controlled by the SDALG bit, reg 18h[5], by default this is a 0 and only goes high when the reclocker is locked to a 270 Mbps input signal. This mode sets the fast edge on the cable driver and allows for any signal in the reclockers data range to be bypassed. If the slow edge is set, any signal above 540 Mbps would be distorted by the slow edge on the cable driver. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 33 Functional Description When SDALG is high it also sets the SD/xHD pin high when the reclocker is unlocked. This is used when the user requires other SD rates such as 143 Mbps and 360 Mbps to be output from the cable driver with the slow SD edge when the reclocker is not locked. Table 4-11. SD/xHD Output Algorithm SD/xHD Pin Rate (Gbps) SDALG Bit = 0 SDALG Bit = 1 0.270 H H 1.485/1.4835 L L 2.97/2.967 L L unlocked L H 4.9 xALARM The xALARM output pin is provided so the user can monitor alarm activity on the reclocker. The output is open drain as shown in Figure 3-10. Table 4-12 shows the reclocker alarms and their function. The assertion of any of the alarms in Table 4-12 will trigger xALARM. NOTE: Table 4-12. Please note that xAlarm is not supported in hardware control mode (HIC). Reclocker Alarm Function Alarm Function LOS Asserted when input signal goes below LOS threshold as set in register 06h. LOL Asserted when reclocker cannot lock to the incoming data. NOREF Asserted when no input reference is present at the reference clock inputs. REFLOL Asserted when frequency lock block cannot lock to the reference clock input. The xAlarm pin may be used when the device is controlled using standard four-wire or two-wire serial interfaces (SIC4 and SIC2). The xAlarm pin operates in an interrupt mode. It goes low on the assertion of any of the internal alarm flags and stays low for a fixed period of time before returning to high (see Figure 4-9). This period is set by the Interrupt Control register (0Eh). By default this is 0 and that corresponds to 20 ns. The maximum period is 2.560 µs, when INT[3:0] is set to Fh. The xAlarm pin is designed to be connected to a microprocessor's interrupt pin. After the interrupt occurs, the microprocessor can read the reclocker's alarm registers to determine which alarm was asserted. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 34 Functional Description Figure 4-9. xALARM-Output Interrupt Mode LOS LOL xALARM t Interrupt occurs when LOS or LOL changes state. xALARM pulse width is programmable. 4.9.1 Reading Register Alarm Bits The LOS and LOL alarm bits are latched when asserted. After reading they should be cleared using the CLRALRM bit in register 88h. This bit needs to be set to '1' to reset the alarms. It should then be reset to a '0' to re-enable normal alarm operation. 4.10 Internal Regulator Both digital and analog cores of the M08035/M08045 are designed to run from a 1.2 V supply. If a 1.2 V supply is not available locally, then the internal regulator can be used to create this domain from AVDDI/AVDDO and DVDDIO. Setting the xREG_EN pin LOW, enables the internal regulator. This regulator generates a 1.2 V domain at pins AVDD and DVDD. See Figure 4-10 through Figure 4-12 for the three different supply configurations. Note that the decoupling capacitors should be at least 100 nF. When the internal regulator is used, all the current for the device is taken through the AVDDI/AVDDO and DVDDIO pins. Because of this, care should be taken to ensure that the supplies to these pins are sufficient to handle the total current. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 35 Functional Description Figure 4-10. All Power Pins Connected to 1.2 V, Internal Regulators Not Used 1.2V AVDDI AVDDO DVDDIO DVDDCORE AVDDCORE xREG_EN Figure 4-11. AVDDI, AVDDO, and DVDDIO Connected to a Supply at 1.8 V or 3.3 V, 1.2 V is Supplied to AVDD and DVDD, Internal Regulator not Used 1.2V 1.8V-3.3V AVDDI AVDDO DVDDIO DVDDCORE AVDDCORE xREG_EN M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 36 Functional Description Figure 4-12. AVDDI, AVDDO, and DVDDIO Connected to a Supply at 1.8 V or 3.3 V. Internal Regulator Generates On-Chip 1.2 V 1.8V-3.3V AVDDI AVDDO DVDDIO AVDDCORE DVDDCORE xREG_EN Note: In order to simplify the diagrams, AVDDI, AVDDO, and DVDDIO are shown to be shorted together. In practice, they may all be separated and connected to different supply domains if desired. AVDDO is sensitive to noise and therefore should be filtered through a ferrite bead, with a 10 nF ceramic capacitor adjacent to each AVDDO pin. Since this core can take a current in the order of 500 mA, the ferrite bead should be very low resistance to ensure the drop across it is minimal. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 37 5.0 Control Registers Map and Descriptions Table 5-1. Addr M08035/M08045 Register Map (1 of 2) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W Input/Output Configuration 00h Input EQ Config 0 RSVD RSVD IE0[1] IE0[0] RSVD RSVD RSVD RSVD 00h R/W 01h Input EQ Config 1 RSVD RSVD RSVD RSVD IE1[1] IE1[0] RSVD RSVD 00h R/W 02h Input EQ Config 2 RSVD RSVD RSVD RSVD IE2[1] IE2[0] RSVD RSVD 00h R/W 03h Input EQ Config 3 RSVD RSVD RSVD RSVD IE3[1] IE3[0] RSVD RSVD 00h R/W 04h Input Polarity Flip 0 RSVD RSVD POL1 RSVD RSVD POL0 RSVD RSVD 00h R/W 05h Input Polarity Flip 1 RSVD RSVD POL3 RSVD RSVD RSVD POL2 RSVD 00h R/W 06h LOS Config/CLK EN LVL[2] LVL[1] LVL[0] F_LOS NVRSQ SQPOL RSVD SCLK_EN 20h R/W 07h Input MUX CTRL RSVD RSVD RSVD RSVD RSVD RSVD IN[1] IN[0] 40h R/W 08h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD C8h R/W 09h SDOA CTRL RSVD RSVD RSVD RSVD LVL_A[1] LVL_A[0] DE_A[1] DE_A[0] 88h R/W 0Ah SDOB CTRL DE RSVD RSVD DE_B[1] DE_B[0] RSVD RSVD RSVD RSVD 00h R/W 0Bh Output CTRL RSVD RSVD RSVD SDOA_MUTE SCLK_LVL[1] SCLK_LVL[0] RSVD RSVD 08h R/W 0Ch SDOB CTRL RSVD RSVD RSVD RSVD RSVD SDOB_EN RSVD RSVD 02h R/W 0Dh GBL CTRL1 RSVD RSVD RSVD RSVD FORCESDION RSVD OFFLOOP PDALL 00h R/W 0Eh Interrupt CTRL RSVD RSVD RSVD RSVD INT[3] INT[2] INT[1] INT[0] 00h R/W 0Fh MicReg RSVD RSVD MICDEV MICDEV MICDEV MICDEV MICDEV MICDEV 00h R/W Reclocker Configuration 10h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 30h R/W 11h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 00h R/W 12h RCLK CTRL 0 RSVD RSVD RSVD RSVD RATE[1] RATE[0] BYPASS PDOWN 00h R/W 13h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 00h R/W 14h RCLK CTRL 1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD BYPDIS 00h R/W 15h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 00h R/W 16h RCLK BW CTRL RSVD BW[2] BW[1] BW[0] RSVD RSVD RSVD RSVD 20h R/W 17h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD C0h R/W 18h RSVD RSVD RSVD SDALG RSVD RSVD RSVD RSVD RSVD C8h R/W 19h RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD 03h R/W M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 38 Control Registers Map and Descriptions Table 5-1. Addr M08035/M08045 Register Map (2 of 2) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default R/W CHKSUM CHKSUM CHKSUM 55h R/W Checksum for Memory Interface Configuration 1Ah CHECKSUM CHKSUM CHKSUM CHKSUM CHKSUM CHKSUM Status/Monitoring Registers 80h MASTER RESET RST RST RST RST RST RST RST RST 00h R/W 81h CHIP ID ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] 0Bh R 82h CHIP REV REV[7] REV [6] REV [5] REV [4] REV [3] REV [2] REV [1] REV [0] 04h R 83h LOS STATUS 0 RSVD RSVD LOS1 RSVD RSVD LOS0 RSVD RSVD 00h R 84h LOS STATUS 1 RSVD RSVD LOS3 RSVD RSVD RSVD LOS2 RSVD 00h R 85h CLEAR ALARMS RSVD RSVD RSVD RSVD RSVD RSVD SOFTRST CLRALARMS 00h R/W 87h CHECKSUM RESULT CHKRES CHKRES CHKRES CHKRES CHKRES CHKRES CHKRES CHKRES 00h R/W 88h RCLK ALARMS RSVD RSVD NOREF REFLOL RSVD RSVD RSVD LOL 00h R 89h RCLK RATE DETECT RSVD RSVD RSVD RSVD RSVD RSVD RATE[1] RATE[0] 00h R 96h LOL CONFIG RSVD MASK[0] RSVD RSVD RSVD RSVD RSVD RSVD 00h R/W NOTE: 1. RSVD are reserved bits that should never be changed from the default level. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 39 Control Registers Map and Descriptions 5.1 Registers Description 5.1.1 Input/Output Configuration Register Address: Default: Register Name: Description: 00h 00h Input EQ Config 0 Select input equalization level, input 0 Bit 7:6 5:4 Bit Description Default R/W Reserved 00b R/W 00b: SDI0, Input equalization disabled 00b R/W 01b: SDI0, Small input equalization level 10b: SDI0, Medium input equalization level 11b: SDI0, Large input equalization level 3:2 Reserved 00b R/W 1:0 Reserved 00b R/W Default R/W Register Address: Default: Register Name: Description: 01h 00h Input EQ Config 1 Select input equalization level, input 1 Bit Bit Description 7:6 Reserved 00b R/W 5:4 Reserved 00b R/W 00b: SDI1, Input equalization disabled 00b R/W 00b R/W Default R/W 3:2 01b: SDI1, Small input equalization level 10b: SDI1, Medium input equalization level 11b: SDI1, Large input equalization level 1:0 Reserved Register Address: Default: Register Name: Description: 02h 00h Input EQ Config 2 Select input equalization level, input 2 Bit Bit Description 7:6 Reserved 00b R/W 5:4 Reserved 00b R/W 00b: SDI2, input equalization disabled 00b R/W 00b R/W 3:2 01b: SDI2, Small input equalization level 10b: SDI2, Medium input equalization level 11b: SDI2, Large input equalization level 1:0 Reserved M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 40 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 03h 00h Input EQ Config 3 Select input equalization level, input 3 Bit Bit Description Default R/W 7:6 Reserved 00b R/W 5:4 Reserved 00b R/W 00b: SDI3, input equalization disabled 00b R/W 00b R/W 3:2 01b: SDI3, Small input equalization level 10b: SDI3, Medium input equalization level 11b: SDI3, Large input equalization level 1:0 Reserved Register Address: Default: Register Name: Description: 04h 00h Input Polarity Flip 0 Setting to a '1' inverts associated input, inputs 0 to 1 Bit Bit Description Default R/W 7 Reserved 0b R/W 6 Reserved 0b R/W 0b: SDI1, Input normal 0b R/W 5 1b: SDI1, Input inverted 4 Reserved 0b R/W 3 Reserved 0b R/W 0b: SDI0, Input normal 0b R/W 2 1b: SDI0, Input inverted 1 Reserved 0b R/W 0 Reserved 0b R/W Default R/W Register Address: Default: Register Name: Description: 05h 00h Input Polarity Flip 1 Setting to a '1' inverts associated input, inputs 2 to 3 Bit Bit Description 7 Reserved 0b R/W 6 Reserved 0b R/W 5 0b: SDI3, Input normal 0b R/W 1b: SDI3, Input inverted 4 Reserved 0b R/W 3 Reserved 0b R/W 2 Reserved 0b R/W 1 0b: SDI2, Input normal 0b R/W 0b R/W 1b: SDI2, Input inverted 0 Reserved M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 41 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 06h 20h LOS Config/CLK EN Sets configuration for Loss of Signal alarm/Enables serial clock output buffer Bit 7:5 Bit Description 000b: 70 mVPPD assert, 80 mVPPD de-assert Default R/W 001b R/W 0b R/W 0b R/W 0b R/W 001b: 80 mVPPD assert, 90 mVPPD de-assert [default] 010b: 90 mVPPD assert, 100 mVPPD de-assert 011b: 100 mVPPD assert, 110 mVPPD de-assert 100b: 110 mVPPD assert, 120 mVPPD de-assert 101b: 120 mVPPD assert, 130 mVPPD de-assert 110b: 130 mVPPD assert, 140 mVPPD de-assert 111b: LOS power down (globally applied for all input channels) 4 0b: Normal LOS operation 1b: Force LOS to asserted 3 0b: Squelch input upon LOS assertion 1b: Never squelch input upon LOS assertion 2 0b: Squelch to logic high state 1b: Squelch to logic low state 1 Reserved 0b R/W 0 0b: Serial clock output is disabled 0b R/W Default R/W 010000b R/W 00b R/W 1b: Serial clock output is enabled (output level controlled by reg0Bh[3:2]) Register Address: Default: Register Name: Description: 07h 40h Input Mux Control Selects the input that is selected for the serial data output Bit Bit Description 7:2 Reserved 1:0 00b: select input 0 to SDO 01b: select input 1 to SDO 10b: select input 2 to SDO 11b: select input 3 to SDO M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 42 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 09h 88h SDOA CTRL Sets output level and De-emphasis for SDO0 Bit 7:4 3:2 Bit Description Reserved 00b: SDO powered down Default R/W 1000b R/W 10b R/W 00b R/W Default R/W 01b: SDO output swing = 600 mVPPD 10b: SDO output swing = 800 mVPPD 11b: SDO output swing = 1200 mVPPD 1:0 00b: SDO De-emphasis off 01b: SDO De-emphasis = small 10b: SDO De-emphasis = medium 11b: SDO De-emphasis = large Register Address: Default: Register Name: Description: 0Ah 00h Data Output De-Emphasis Control Sets output level and de-emphasis for SDOB. Bit Bit Description 7:6 Reserved 000b R/W 5:4 00b: SDOB de-emphasis off 00b R/W 00b R/W Default R/W 000b R/W 0b R/W 10b R/W 00b R/W 01b: SDOB de-emphasis = small 10b: SDOB de-emphasis = medium 11b: SDOB de-emphasis = large 3:0 Reserved Register Address: Default: Register Name: Description: 0Bh 08h Output Control SDOA Mute and SDOB/SCLK swing control. Bit 7:5 4 Bit Description Reserved 0b: SDOA output in normal operation 1b: SDOA output muted 3:2 00b: SDOB/SCLK output powered down 01b: SDOB/SCLK output swing = 600 mVPPD 10b: SDOB/SCLK output swing = 800 mVPPD 11b: SDOB/SCLK output swing = 1200 mVPPD 1:0 Reserved M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 43 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 0Ch 02h SDOB Control Enable for second data output. Bit 7:3 2 Bit Description Reserved 0b: SDOB output disabled Default R/W 00000b R/W 0b R/W 10b R/W Default R/W 0000b R/W 0b R/W 1b: SDOB output enabled 1:0 Reserved Register Address: Default: Register Name: Description: 0Dh 00h Global Control1 Controls Global Configuration Bit 7:4 3 Bit Description Reserved 0b: Inputs that are not used are powered down 1b: All inputs are forced on 2 Reserved 0b R/W 1 0b: Input offset correction loop On (all inputs) 0b R/W 0b R/W Default R/W 00000b R/W 0b R/W 000b R/W 1b: Input offset correction loop Off (all inputs) 0 0b: Normal Operation 1b: Global Power Down Register Address: Default: Register Name: Description: 0Eh 00h Interrupt Control Sets configuration for xALARM Output pin Bit 7:4 3 Bit Description Reserved 0b: xALARM output is used in Interrupt mode 1b: Not supported 2:0 000b: xALARM pulse width = 140 ns 001b: xALARM pulse width = 180 ns 010b: xALARM pulse width = 200 ns 011b: xALARM pulse width = 300 ns 100b: xALARM pulse width = 450 ns 101b: xALARM pulse width = 800 ns 110b: xALARM pulse width = 1.5 µs 111b: xALARM pulse width = 2.8 µs Measured with a 10 kΩ pull up resistor. Actual pulse width varies with the value of the pull-up resistor. M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 44 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 0Fh 00h Memory Interface Configuration Control Defines the number of slave RCLK devices, controlled by quasi master/EEPROM Bit 7:6 5:0 Bit Description Reserved 000000b: no slave RCLKs Default R/W 00b R/W 000000b R/W Default R/W 0000b R/W 00b R/W 0b R/W 0b R/W Default R/W 0000b R/W 0b R/W 000001b: 1 slave RCLK 000010b: 2 slave RCLKs 5.1.2 Reclocker Configuration Register Address: Default: Register Name: Description: 12h 00h Reclocker Control 0 Controls Reclocker Bit 7:4 3:2 Bit Description Reserved 00b: ARD enabled 01b: SD data rate selected for reclocker 10b: HD data rate selected for reclocker 11b: 3G data rate selected for reclocker (M08045) 1 0b: Normal operation (reclocker not bypassed) 1b: Reclocker bypassed 0 0b: Normal operation 1b: Reclocker powered down Register Address: Default: Register Name: Description: 14h 00h Reclocker Control 1 Controls Reclocker Bit 7:1 0 Bit Description Reserved 0b: Normal operation 1b: Reclocker auto-bypass feature disabled M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 45 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 16h 20h Reclocker BW Control Controls bandwidth of Reclocker Bit 7 6:4 Bit Description Default R/W 0b R/W 010b R/W 0000b R/W Default R/W Reserved 00b R/W 0b: SD/xHD output conforms to case 1, Table 4-11 0b R/W 00000b R/W Default R/W 01010101b R/W Default R/W 00000000b R/W Reserved 000b: Reserved (do not use) 001b: 0.5 x Nominal LBW 010b: 1 x Nominal LBW 011b: 4 x Nominal LBW 100b: 2 x Nominal LBW 101b: 3 x Nominal LBW 110b: 1.5 x Nominal LBW 111b: 0.875 x Nominal LBW 3:0 Reserved Register Address: Default: Register Name: Description: 18h 00h SD/xHD Algorithm Control Controls SD/xHD output of Reclocker Bit 7:6 5 Bit Description 1b SD/xHD output conforms to case 2, Table 4-11 4:0 Reserved 5.1.3 Checksum for Memory Interface Configuration Register Address: Default: Register Name: Description: 1Ah 55h Checksum Checksum value to be added to sum of reg 00h to 19h contents Bit 7:0 Bit Description Checksum value 5.1.4 Status/Monitoring Register Address: Default: Register Name: Description: 80h 00h Reset Does Master Reset on Device Bit 7:0 Bit Description 00h: Normal Operation AAh: Master Reset M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 46 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 81h 0Bh Chip ID Chip Identification Number Bit 7:0 Bit Description M08035/M08045 Register Address: Default: Register Name: Description: Bit Description Chip revision Register Address: Default: Register Name: Description: 5 N/A R Default R/W 00000100b R 83h 00h LOS Status 0 Inputs 0-1, Set to a '1' when LOS asserted (single-event latched operation). Proper status is obtained after clearing all latched alarms by using Register 85h bit 0. Bit 7:6 R/W 82h 04h Chip Rev Chip Revision Bit 7:0 Default Bit Description Default R/W Reserved 00b R 0b: SDI1, Input present 0b R 1b: SDI1, LOS Asserted 4:3 2 Reserved 00b R 0b: SDI0, Input present 0b R 00b R 1b: SDI0, LOS Asserted 1:0 Reserved Register Address: Default: Register Name: Description: 84h 00h LOS Status 1 Inputs 2-3, Set to a '1' when LOS asserted (single-event latched operation). Proper status is obtained after clearing all latched alarms by using Register 85h bit 0. Bit 7:6 5 Bit Description Default R/W Reserved 00b R 0b: SDI3, Input present 0b R 000b R 0b R 0b R 1b: SDI3, LOS Asserted 4:2 1 Reserved 0b: SDI2, Input present 1b: SDI2, LOS Asserted 0 Reserved M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 47 Control Registers Map and Descriptions Register Address: Default: Register Name: Description: 85h 00h Alarm Clear Clears Latched Alarms. To properly clear all alarm bits, write “1” followed by a “0” to bit 0. Bit 7:2 1 Bit Description Default R/W 000000b R/W 0b R/W 0b R/W Default R/W 00000000b R/W Default R/W Reserved 00b R 0b: Reference clock is present 0b R 0b R XXXb R 0b R Default R/W XXXXXXb R 00b R Reserved 0b: Normal operation 1b: Soft reset for Reclocker (for master reset use reg 80h) 0 0b: Normal operation 1b: Clears all alarm bits in registers 83h, 84h and 88h Register Address: Default: Register Name: Description: 87h 00h Checksum result Shows the result of the checksum calculation Bit 7:0 Bit Description Checksum result Register Address: Default: Register Name: Description: 88h 00h Reclocker Status Register Reads status of the Reclocker Bit 7:6 5 Bit Description 1b: Reference clock is not present 4 0b: PLL locked 1b: PLL unlocked 3:1 0 Reserved 0b: Reclocker, locked 1b: Reclocker, un-locked Register Address: Default: Register Name: Description: 89h 00h Reclocker Rate Detect Reads data rate for Reclocker Bit 7:2 1:0 Bit Description Reserved 00b: Reclocker: un-locked 01b: Reclocker: SD data rate detected 10b: Reclocker: HD data rate detected 11b: Reclocker: 3G data rate detected (M08045) M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 48 www.macomtech.com General Information: 100 Chelmsford Street Lowell, Massachusetts 01851 Phone: 978.656.2500 © 2014 M/A-COM Technology Solutions Inc. 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M08035, M08045 Data Sheet V1 080x5-DSH-001 MACOM™ 49