tw6874

DATASHEET
To request the full datasheet, please visit www.intersil.com/products/TW6874
Quad (SD/HD) SDI Receiver with Adaptive Equalizer,
VC-2 Decoder and Audio CODEC
TW6874
Features
The TW6874 is a quad (SD/HD) SDI receiver. It has four
independent channels, each consisting of an adaptive
equalizer, clock data recovery, audio decoder and VC-2
decompression engine. Each channel receives high speed
serial data over extended coaxial cable lengths and deserialize
the data into video/audio streams for the back-end device.
• Quad (SD/HD) SDI receiver for standard (SD) and high (HD)
definition 10-bit component video
• Automatic SDI detection of SMPTE 259M Level C (SD-SDI),
SMPTE ST 292 (1.5G SDI) signals
The video streams are output as: 8-bit BT.656 for SD; BT.1120
in 8/16 bit mode for HD. The audio streams are output
through an I2S audio digital interface in a multichannel
interleaving format. In addition to the extraction of embedded
SDI audio, the TW6874 incorporates a 5-channel audio ADC
decoder to decode analog audio inputs and output them
through the same I2S interface.
• Converts 10-bit serial digital component video input to 8-bit
parallel video output
• Adaptive equalizer/clock data recovery/VC-2 decompression
engine for each channel
• 4 separate video output ports with BT.656/BT.1120 output
format
• 5-channel audio ADC (Analog-to-Digital Converter)
• Each SDI input standard supported with ITU-R BT.656 (SD) or
ITU-R BT.1120 (1.5G) interface
A visually lossless VC-2 (Dirac) compression/decompression
engine is implemented in the TW6872/TW6874 SDI Tx/Rx
pair to extend the reach of HD-SDI to that of SD-SDI. An
interrupt pin can be used to signal the host processor of
ancillary data packet detection. Finally, integrated audio test
patterns and PRBS checker ease system design and
implementation.
• Single multiplexed audio output DAC (Digital-to-Analog
Converter)
• Supports I2S master/slave interface for record output and
playback input with cascade
• I2C and SPI interface
• Pb-free (RoHS compliant) 256 ball LFBGA
Applications
• SD/HD DVR
1.0V
TERMINATION NETWORK
R
C
L
3.3V
AIN5
VO1
C
VO3 18
SDI1N
VO4
18
I2S record
3
I2S play
3
R
2.2µF
AIN1
d
u
m
m
y
18
VO2 18
SDI1P
R
75
1.8V
4.7k
BACK-END
CHIP (CODEC,
VIDEO MUX)
d
u
m
m
y
TW6874
TERMINATION
NETWORK
SDI2P
SDI2N
AIN2
IRQ
HOST
PROCESSOR
I2C/SPI
TERMINATION
NETWORK
TERMINATION
NETWORK
SDIP3
SDIN3
AIN3
SDIP4
SDIN4
AIN4
22pF
XTI
XTO
AOUT
TESTEN
27MHz
22pF
3.7k
8.2nF
0
FIGURE 1. TW6874 TYPICAL APPLICATION
March 25, 2015
FN8430.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
IAll other trademarks mentioned are the property of their respective owners.
TW6874
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
2
FN8430.1
March 25, 2015