M21528-13

M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
Applications
• Input equalization for up to 36" of FR4 + 2 connectors
• 3G/HD/SD Video Switchers
• Integrated, selectable 75Ω or 50Ω output termination
• 3G/HD/SD Video Routers
• Integrated 50Ω input termination
• 3G/HD/SD Distribution Amplifiers
• Integrated 2x2 crosspoint switch with broadcast mode
• DVB-ASI Equipment
• On-chip regulators for operation from 1.8V to 3.3V DC supply
• SMPTE 259C/D, 292M, 424M, DVB ASI 270Mb/s
• Universal DC coupling at the input, from 1.2V to 3.3V
Features
• Cable detect with automatic power down and power up upon cable disconnect
and re-connect
• Dual channel cable driver
• Loss of input signal detection
• Two pairs of non-inverting, SMPTE compliant outputs
• Independent channel mute and power down
• Typical output jitter of 12 ps peak–to–peak at 2.97 Gbps
• Industrial operating temperature range: -40°C to 85°C
• Exceptional Output Return Loss with no matching network
• 4 kV HBM and 500V CDM ESD rating
• Very low power design; 40 mW/channel @1.8V
• 4 mm x 4 mm 24 pin QFN package
• Selectable slew rate for SD and 3G/HD operation
• Green and RoHS compliant
The M21528 is a very low power, highly integrated, dual cable driver for SMPTE compliant digital video applications. It can drive 2 pairs
of 75Ω coaxial cables, or 50Ω equivalent loads, at SDI data rates from 270 Mbps to 2.97 Gbps. The device is capable of outputting SDI
signals with typical jitter values of 12 ps peak–to–peak, when operating at 2.97 Gbps.
The dual cable driver includes a 2x2 input crosspoint and integrated input and output termination resistors. The M21528, with input
equalization for up to 36" of FR4 trace in addition to two connectors and exceptional Output Return Loss (ORL), is ideal for high speed,
3G-SDI, designs.
The device features integrated supply regulators, allowing it to be powered from 1.8V, 2.5V, or 3.3V supply voltages. When operating at
1.8V, it consumes only 40 mW per channel at 2.97 Gbps. Furthermore, the power rails for the input and output circuitry are electrically
isolated on-chip and as such may be connected to different voltage rails on the board. This feature enables the M21528 to be DC coupled to any upstream device in the 1.2V to 3.3V range.
The integrated 2x2 crosspoint allows for either input to be routed to either output, eliminating the need for an external multiplexer. Additionally, one input may be routed to both outputs. The cable driver also provides cable detect and Loss of Signal (LOS) functionality. It
can be configured to automatically power down at cable disconnect or loss of input signal.
The M21528 is offered in a green and RoHS compliant 24 pin QFN package.
M21528 Block Diagram
75Ω/50Ω
SDO0A
75Ω/50Ω
SDO0B
75Ω/50Ω
SDO1A
75Ω/50Ω
SDO1B
LOS
SDI0P
SDI0N
IE
2x2
Crosspoint
SDI1P
SDI1N
IE
LOS
1
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
Ordering Information
Part Number
Package
Operating Temperature
M21528G-13
4 mm x 4 mm 24-pin QFN (RoHS compliant)
–40 °C to 85 °C
* The letter “G” designator after the part number indicates that the device is RoHS compliant. The RoHS compliant devices are backwards compatible with 225 °C
reflow profiles.
Revision History
Revision
Level
Date
V3
Release
May 2015
Description
Revised Z_CTRL resistor value for 75Ω output impedance in Table 3-1.
Revised Section 4.3.
Updated Marking Diagram.
Updated Figure 3-7 with new package diagram.
E (V2)
Release
March 2010
D (V1)
Release
December 2009
C (V1P)
Preliminary
May 2009
B (V2A)
Advance
February 2009
A (V1A)
Advance
June 2008
Corrected Figure 3-7 center pad dimensions.
Revised Table 1-5; DRIN min, JAO 3G, HD max.
Added marking diagram.
Added Eye Diagams in Section 2.0.
Revised typical and Maximum values in Table 1-3.
Revised Table 1-4.
Revised Figure 3-2 and Figure 3-3.
Added Note 5 to Table 1-5.
Removed Note 2 from Table 3-1 (2-state/I-Digital inputs have an internal 100KΩ resistor to
AVDDI).
Revised Figure 4-3, Figure 4-4, Figure 4-5.
Added input/output circuits in Section 3.0.
Major revisions throughout document.
Initial Release.
M21528 Marking Diagram
52813
XXXX .X
YYWWCO
Part Number
Lot Number
Date Country of Origin
2
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.0
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.0
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.0
Pinout Diagram, Pin Description, and Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.2
Input Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3
Output Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4
Power Supply Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.5
Logic Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.6
4.5.1
Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.2
Crosspoint Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.5.3
Powerdown Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Cable Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3
M/A-COM Technology Solutions Inc. (MACOM) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice.
Visit www.macom.com for additional data sheets and product information.
For further information and support please visit:
http://www.macom.com/support
M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
1.0 Electrical Characteristics
Unless noted otherwise, specifications apply for typical recommended operating conditions shown in Table 1-2,
with AVDDO = 1.8V, AVDDI = 1.2V, CML inputs at 800 mV differential (RL = 50Ω), PRBS 215 – 1 test pattern at 2.97
Gbps.
Table 1-1.
Absolute Maximum Ratings
Symbol
Parameter
Note
Minimum
Typical
Maximum
Unit
AVDDI
Analog supply for input circuitry
1
-0.5
—
3.6
V
AVDDO0/1
Analog supply for output circuitry
1
-0.5
—
3.6
V
TST
Storage Temperature
1
-65
—
150
ºC
ESD
Human Body Model (HBM)
1
-4
—
4
KV
ESD
Charge Device Model (CDM)
1
-500
—
500
V
Latch Up @ 85ºC
1
-200
—
200
mA
HSIC
Maximum High-speed input current
1
-100
—
100
mA
HSOC
Maximum High-speed output short circuit current
1
-100
—
100
mA
VINMAX
Input voltage range
1
-0.5
—
AVDDI+0.5
V
Note
Minimum
Typical
Maximum
Unit
LU
NOTES:
1.
Exposure to these conditions over extended periods of time may affect device reliability
Table 1-2.
Recommended Operating Conditions
Symbol
Parameter
AVDDI
Analog supply for input circuitry
—
1.14
1.2, 1.8,
2.5, or 3.3
3.465
V
AVDDO0/1
Analog supply for output circuitry
—
1.71
1.8, 2.5, or
3.3
3.465
V
TCASE
Operating temperature
1
-40
25
+85
ESD
Human Body Model (HBM)
—
-4
—
4
NOTES:
1.
Case temperature.
4
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o
C
kV
M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Table 1-3.
Power Consumption Specifications
Symbol
PDISS
Rev V3
Parameter
Conditions
Total power consumption
Note
AVDDI = 1.2V
Minimum
Typical
Maximum
Unit
78
122
mW
61
95
mW
49
86
mW
1
AVDDO = 1.8V
—
Both channels active, 4 outputs on
1
AVDDI = 1.2V
AVDDO = 1.8V
—
Both channels active, one output per channel
on
1
AVDDI = 1.2V
AVDDO = 1.8V
—
One channel active, one output on
I_ AVDDI
Total AVDDI supply current
AVDDI = 1.2V
1
—
1
3.0
mA
I_ AVDDI
Total AVDDI supply current
AVDDI = 1.8V
1
—
3
7.0
mA
I_ AVDDI
Total AVDDI supply current
AVDDI = 3.3V
1
—
10
17.0
mA
I_ AVDDO
Total AVDDO supply current
Both channels active
1,2
—
43
68.0
mA
I_ AVDDO
Total AVDDO supply current
Only channel 0 active
1,2
—
43
68.0
mA
I_ AVDDO0
Total AVDDO0 supply current
Only channel 1 active
1,2
—
27
49.0
θJA
Junction to ambient Thermal
Resistance
3
—
mA
o
—
63
C/W
Note
Minimum
Typical
Maximum
Unit
NOTES:
1.
Recommended operating condition—see Table 1-2.
2.
Current consumption does not change with AVDDO = 1.8V, 2.5V or 3.3V.
3.
Airflow = 0 m/s.
Table 1-4.
Digital Input Specifications
Symbol
Parameter
VIH
Input Logic High
—
0.85 x AVDDI
—
AVDDI + 0.5
V
VIF
Input Logic Floating State
—
0.25 x AVDDI
—
0.75 x AVDDI
V
VIL
Input Logic Low
—
0
—
0.15 x AVDDI
V
IIH
Input Current—Logic High
—
-100
—
100
μA
IIL
Input Current—Logic Low
—
-100
—
100
μA
5
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Table 1-5.
Rev V3
High Speed Input/Output Electrical Specifications
Symbol
Parameter
Note
Minimum
Typical
Maximum
Unit
1
730
800
850
mV
1,3,4
400
600
800
ps
1
—
70
90
ps
1,3,4
—
—
125
ps
VO
Output Voltage Range
tr/tf
SD Rise/Fall Time (20–80%)
tr/tf
3G/HD Rise/Fall Time (20–80%)
tr-tf
SD Rise/Fall Time Mismatch
tr-tf
3G/HD Rise/Fall Time Mismatch
1,3
—
—
30
ps
DCD
Duty Cycle Distortion, SD
1,4
—
—
100
ps
DCD
Duty Cycle Distortion, 3G, HD
1,3
—
—
30
ps
1,2,4
—
60
100
ps
JAOPP
Additive Output Jitter, SD
JAOPP
Additive Output Jitter, 3G, HD
1,2
—
12
29
ps
S22
Output Return Loss (5 MHz to 1.5 GHz)
6,8
20
—
—
dB
S22
Output Return Loss (5 MHz to 3.0 GHz)
5,8
11
—
—
dB
S22
Output Return Loss (5 MHz to 3.0 GHz)
6,8
14
—
—
dB
DRIN
Input Data rate
—
270
—
2970
Mbps
VID
Differential Input Voltage (p–p)
7
400
—
1600
mV
VIC
Input Common mode range
—
AVDDI – 0.6
—
AVDDI + 0.1
V
IE
Input Equalizer Gain Off (EN_EQ = 0)
—
—
0
—
dB
Input Equalizer Gain Med (EN_EQ = F)
—
—
4
—
dB
Input Equalizer Gain High (EN_EQ = H)
—
—
6
—
dB
Input Termination to AVDDI
—
40
50
60
Ω
RINT
NOTES:
1.
Measured AC coupled into 1m coaxial cable, terminated with appropriate 75Ω or 50Ω load.
2.
Measured with PRBS 215-1 test pattern.
3.
For data rates above 360 Mb/s, the cable driver must be in HD mode (SD/xHD = 0).
4.
SD/xHD = 1, measured at 270 Mb/s.
5.
Without external matching network.
6.
With external matching network Rmatching=75Ω, Lmatching=1nH, only applicable to 75Ω mode.
7.
EQ_EN = L (input equalization off) PD_MODE = F (LOS enabled), point blank.
8.
As measured on MACOM EVM at BNC connector with output impedance set to 75Ω.
6
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
2.0 Typical Performance Characteristics
Figure 2-1.
Eye Diagram at 270 Mbps
Figure 2-3.
Eye Diagram at 2970 Mbps
Figure 2-2.
Eye Diagram at 1485 Mbps
7
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
3.0 Pinout Diagram, Pin Description, and
Package Drawing
SDO0B
17
AVDDReg0
16
AVDDO0
15
AVDDO1
14
AVDDReg1
13
SDO1B
SD/xHD0
PD0
Z_CTRL
XPT_CTRL
AVDDReg0
SDO0A
23
22
21
20
19
5
10
11
12
AVDD Reg1
SDO1A
6
PD_MODE
SDI1N
4
9
SDI1P
M21528
4mmX4mm
QFN
AVDD I
EN_EQ1
3
8
EN_EQ0
18
2
PD1
SDI0N
1
7
SDI0P
24
Pinout Diagram (Top View)
SD/xHD1
Figure 3-1.
8
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Table 3-1.
Rev V3
Pin Description (1 of 2)
Pin Name
Pin Number
Type
Description
AVSS
Center Ground Paddle
Power
Chip Ground
AVDDI
9
Power
Positive supply for inputs circuitry
AVDDReg0
17,20
Power
Regulator0 bypass capacitor connection, positive supply for output0
AVDDReg1
11,14
Power
Regulator1 bypass capacitor connection, positive supply for output1
AVDDO0
16
Power
Positive supply for reglator0
AVDDO1
15
Power
Positive supply for reglator1
SDO0A
19
O-Analog
High speed serial output, channel0, output A
SDO0B
18
O-Analog
High speed serial output, channel0, output B
SDO1A
12
O-Analog
High speed serial output, channel1, output A
SDO1B
13
O-Analog
High speed serial output, channel1 output B
SDI0P/N
1,2
I-Analog
High speed serial video data input, channel0
SDI1P/N
5,6
I-Analog
High speed serial video data input, channel1
Z_CTRL
22
I-Analog
Sets output impedance through an external Z_CTRL resistor
connected to AVSS
Z_CTRL=665Ω to set 75Ω output impedance
Z_CTRL=250Ω to set 50Ω output impedance
SD/xHD0
24
I-DIGITAL
Output slew rate control for channel 0
L = SDO0 has 3G/HD slew rate
H = SDO0 has SD slew rate
SD/xHD1
7
I-DIGITAL
Output slew rate control for channel 1
L = SDO1 has 3G/HD slew rate
H = SDO1 has SD slew rate
PD0
23
3-state/I-DIGITAL
Power down control for channel 0
L = SDO0A on, SDO0B power down
F = Both outputs on
H = Power down both outputs
PD1
8
3-state/I-DIGITAL
Power down control for channel 1
L = SDO1A on, SDO1B power down
F = Both outputs on
H = Power down both outputs
XPT_CTRL
21
3-state/I-DIGITAL
Crosspoint control
L = SDI0 to SDO1, SDI1 to SDO0
F = SDI0 to SDO0, SDI1 to SDO1
H = SDI0 to SDO0 and SDO1
9
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Table 3-1.
Rev V3
Pin Description (2 of 2)
Pin Name
Pin Number
Type
Description
PD_MODE
10
3-state/I-DIGITAL
Power down and cable detect control
L = Cable detect disabled, PD upon LOS disabled
F = Cable detect enabled, PD upon LOS enabled
H = Cable detect enabled, PD upon LOS disabled
EN_EQ0
3
3-state/I-DIGITAL
Input equalization control for channel 0
L = No Input Equalization on SDI0P/N
F = Medium Input Equalization on SDI0P/N
H = High Input Equalization on SDI0P/N
EN_EQ1
4
3-state/I-DIGITAL
Input equalization control for channel 1
L = No Input Equalization on SDI1P/N
F = Medium Input Equalization on SDI1P/N
H = High Input Equalization on SDI1P/N
NOTES:
1.
3-state inputs have a default of F (floating).
2.
A Z_CTRL resistance of 665Ω will also provide 800mVpp output swing.
Figure 3-2.
Differential Input (SDIP, SDIN)
AVDDI
50Ω
SDIP
AVSS
Input Buffer
with Trace
Equalizer
AVDDI
50Ω
SDIN
AVSS
10
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Figure 3-3.
Rev V3
Single-Ended Output (SDO0A, SDO0B, SDO1A, SDO1B)
AVDDReg
50Ω / 75Ω
Set by Z _CTRL
SDO
AVSS
Figure 3-4.
Digital Input Pin (SD/xHD0, SD/xHD1)
AVDDI
2.0kΩ
INPUT
AVSS
11
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Figure 3-5.
Rev V3
State Logic Input (PD0, PD1, XPT_CTRL, PD_MODE, EN_EQ0, EN_EQ1)
AVDD I
VREF_LOW
AVDD I
2.0kΩ
INPUT
AVSS
AVDD I
AVSS
VREF_HIGH
AVSS
The M21528 is assembled in 24 pin 4 mm x 4 mm Quad Flat No-Lead (QFN) package. The exposed die paddle
serves as the IC ground (AVSS), and the primary means of thermal dissipation. This die paddle should be soldered
to the PCB ground. A cross-section of the QFN package can be found in Figure 3-6.
Figure 3-6.
QFN Package Cross Section
Mold Compound
Ag Plating
Die
Solder
Plating
Gold Wire
Cu Leadframe
Down Bond
Exposed Die
Paddle
Ground Bond
Die Attach Material
12
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Figure 3-7.
Rev V3
Package Drawing
13
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
4.0 Functional Description
4.1
Block Diagram
Figure 4-1 is the functional block diagram of the M21528. The subsequent sections provide additional detail on the
operation of the device.
AVDD O1
AVDD O0
Regulator
Z_CTRL
PD1
PD0
SD/xHD1
SD/xHD0
XPT_CTRL
PD_MODE
EN_EQ1
EN_EQ0
AVDD Reg1
AVDD Reg0
M21528 Functional Block Diagram
AVDD Reg1
AVDD Reg0
Figure 4-1.
Control Logic
Cable
Detect
Z
Control
LOS
R
SDO0A
R
SDO0B
R
SDO1A
R
SDO1B
AV DDI
2 x2
SDI0P
SDI0N
Xpoint
Input
Buff &
FR4 EQ
SDI1P
SDI1N
14
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
4.2
Rev V3
Input Description
The M21528 has differential inputs, with integrated 50Ω pull ups to AVDDI. AVDDI may be supplied from a 1.2V,
1.8V, 2.5V, or 3.3V supply. The input buffers are compatible with PCML, LVDS or LVPECL signal levels.
To improve signal integrity in large systems, all inputs have programmable input equalization (IE) with three gain
levels: 0 dB, 4 dB, 6 dB.
Setting the gain to 0dB effectively disables the IE feature. The pins EN_EQ0 and EN_EQ1 allow for the selecting
the proper level of input equalization based on the board characteristics for each input. The maximum level of
equalization compensates for up to 36” of FR4 trace. The operation of the EN_EQ0/1 pin is summarized in
Table 4-1 below.
Table 4-1.
Pin
EN_EQ0
EN_EQ1
Operation of EQ_EN0 and EQ_EN1 Pins
Level
Function
L
SDI0P/N IE EQ gain = 0 dB
F
SDI0P/N IE EQ gain = 4 dB
H
SDI0P/N IE EQ gain = 6 dB
L
SDI1P/N IE EQ gain = 0 dB
F
SDI1P/N IE EQ gain = 4 dB
H
SDI1P/N IE EQ gain = 6 dB
In 3G/HD/SD SDI applications, it is best to avoid AC coupling data interfaces between devices, if possible. DC
coupling will result in increased system jitter margin. Also, DC coupling eliminates the requirement for additional
components on the board. In order to accommodate DC coupling to the upstream device, the AVDDI domain of the
M21528 is electrically isolated from all other power domains on chip. This allows for it to be tied to the VDD of the
previous device’s driver enabling a fully DC coupled system, as shown below.
Upstream
VDD
50Ω
1.2V – 3.3V
M21528
AVDDI
50Ω
15
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
Alternatively, a “self-biasing” scheme can be used at the input. This offers the benefit of having the VDD of the
previous device and the power domain(s) of the M21528 completely separated, while allowing dc coupling:
Previous device
VDD
50Ω
M21528
AVDDI
0.1uF
50Ω
In this configuration, the minimum input common mode that can be tolerated, is 1.2V.
If, for any reason, AC coupling is necessary, then a capacitor of 4.7 µF or greater must be used.
A Loss of Signal (LOS) detector circuit monitors each input and issues an internal alarm when the input signal goes
below the detection threshold. The detection threshold is 90 mVpp with +90 mV hysteresis. This means that if the
input signal level drops below 90 mVpp, then the internal LOS alarm is asserted. For the alarm to be de-asserted,
the input signal must increase to greater than 180 mVpp; the hysteresis prevents the internal LOS alarm from
chattering.
Depending on the state of the PD_MODE pin, the LOS alarm at a particular input can power down the associated
signal path and forces the corresponding output to low level.
4.3
Output Description
The M21528 contains two independent signal channels, each with two positive polarity cable driver outputs. Unlike
conventional SMPTE compliant cable drivers, the M21528 uses a voltage mode implementation as opposed to
current mode. This allows for significant power savings when compared to previous generation cable drivers with
the added benefit of two positive polarity outputs per channel.
Internally an output buffer drives a 1.6V amplitude signal through an integrated impedance load. The impedance of
the load is set by the external Z_CTRL resistor to AVSS. For most applications Z_CTRL should be 665Ω, which
sets the output load to 75Ω and provides 800mVpp output swing. If the application requires a 50Ω output
impedance, Z_CTRL may be 250Ω. In both cases Z_CTRL must have 1% tolerance.
The M21528 can meet SMPTE ORL specifications without the need for an external matching network. However,
for additional margin a matching network consisting of a 75Ω resistor and a 1 nH inductor may be used.
Each channel has a dedicated power down pin, PD0 and PD1. The operation of the PD pin is summarized in
Table 4-2 below. When powered down, the signal at the output is set to low.
16
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Table 4-2.
Operation of PD0 and PD1 Pins
Pin
Level
PD0
L
SDO0A on, SDO0B powered down
F
Both SDO0A and SDO0B on
H
Both SDO0A and SDO0B powered down
L
SDO1A on, SDO1B powered down
F
Both SDO1A and SDO1B on
H
Both SDO1A and SDO1B powered down
PD1
Rev V3
Function
Figure 4-2 shows a typical output circuit.
When the cable detect function is enabled, only the outputs used need to be connected, unused outputs may be
left floating.
However, if the cable detection function is disabled, unused outputs must be powered down or properly terminated.
Figure 4-2.
Typical Output Circuit (all outputs connected)
Circuit A
SDO0A
4.7 µF
M21528
SDO0B
SDO1A
SDO1B
Circuit A
Circuit A
Circuit A
17
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
4.4
Rev V3
Power Supply Description
The device features two internal regulators to supply the power for the output drivers for each channel. AVDDO0
and AVDDO1 supply the voltage to each channel’s respective regulator. These pins may be connected to DC
voltages ranging from 1.8V to 3.3V. Each regulator requires an external 1µF bypass capacitor to ground, which
must be connected to AVDDReg0 and AVDDReg1. It is recommended to add a secondary 10 nF bypass capacitor
on each regulator output as close to the pin as possible.
In addition to supplying the output stage for channel1, AVDDO1 is also used to power the core circuitry for both
channels.
A completely separate supply domain, AVDDI, provides the supply for the high-speed serial input pins. The input
termination and ESD protection for the SDI pins and the digital control input pins are referenced to this supply. The
isolated domain allows DC coupling to an upstream device that is running from a different supply voltage. For
example, if, in order to save power, AVDDO0/1 are connected to 1.8V, but the cable driver must interface to a
reclocker that uses a 3.3V supply, then DC coupling can be achieved by simply connecting AVDDI to the 3.3V rail.
Figure 4-3 to 4-5 show three examples of how the cable driver can be configured. Note that even when only one
channel is enabled, both output regulators must be supplied with the correct voltage.
Figure 4-3.
Supply configuration, both channels and both A and B outputs used
1.2V to 3.3V
PD0
PD1
AVDD I
AVDDReg0
1.8V to 3.3V
1μF
AVDDO1
10 nF
AVDDReg1
0.1uF
AVDDO0
1μF
10 nF
18
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Figure 4-4.
Rev V3
Supply configuration, channel0, outputs A and B used, channel 1 powered down
1.2V to 3.3V
PD0
PD1
AVDD I
AVDDReg0
1.8V to 3.3V
1μF
10 nF
AVDD O1
AVDDReg1
0.1uF
Figure 4-5.
1μF
AVDDO0
10 nF
Supply configuration, both channels used, but only A outputs used
1.2V to 3.3V
PD0
PD1
AVDD I
AVDDReg0
1.8V to 3.3V
1μF
10 nF
AVDDO1
AVDDReg1
0.1uF
AVDDO0
1μF
10 nF
19
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
4.5
Rev V3
Logic Control Signals
The digital logic control signals are ESD protected and referenced to the AVDDI. This allows the device to interface
to many different logic levels from different supply domains.
Some pins have a state called “F”; this stands for “floating”. To assert this state leave the pin unconnected.
4.5.1
Slew Rate Control
Pins SD/xHD0 and SD/xHD1 control the slew rate of the associated channel outputs. To comply with the SMPTE
SD specification the slew rate is slowed down to approximately 600 ps when in SD mode. Note that there is no pullup on the SD/xHD pins, so it should not be left floating.
Table 4-3.
Operation of SD/xHD0 and SD/xHD1 Pins
Pin
Level
SD/xHD0
L
Set SDO0A/B Slew rate to 3G/HD Levels
H
Set SDO0A/B Slew rate to SD Levels
L
Set SDO1A/B Slew rate to 3G/HD Levels
H
Set SDO1A/B Slew rate to SD Levels
SD/xHD1
4.5.2
Function
Crosspoint Control
The XPT_CTRL pin controls the 2 x 2 crosspoint at the input. It can be used to redirect the input signal to the other
output or from channel 0 to make broadcast mode, so the input on channel 0 appears on both channel 0 and 1
outputs. This last mode is useful in distribution amplifiers where one input can drive fours positive outputs.
The crossover feature can be used in routers to select a second input bank. The functionality of the XPT_CTRL pin
is summarized in the table below.
Table 4-4.
Operation of XPT_CTRL Pin
Pin
Level
XPT_CTRL
L
Function
Crossover mode:
SDI0 routed to SDO1
SDI1 routed to SDO0
F
Default mode:
SDI0 routed to SDO0
SDI1 routed to SDO1
H
Broadcast mode:
SDI0 routed to SDO0 and SDO1
20
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
4.5.3
Rev V3
Powerdown Mode Control
The M21528 has integrated output cable detection and input LOS detection circuitry. Depending on the setting of
the PD_MODE pin, the device can automatically power down each channel when output cables are disconnected
or there is no signal present at the input.
The functionality of the PD_MODE pin is summarized in the table below.
Table 4-5.
Operation of PD_MODE
Pin
Level
PD_MODE
L
Function
Cable detection disabled
Power down on LOS disabled
F
Cable detection enabled
Power down on LOS enabled
H
Cable detection enabled
Power down on LOS disabled
4.6
Cable Detection
The M21528 features an integrated near-end cable detector. This circuit can detect whether a cable has been
disconnected from an output and whether or not it is reconnected without requiring any additional external
components.
Utilizing the cable detection feature has several system level advantages such as:
•
Reduced power consumption when no cable is connected to both outputs of a single channel
•
Reduced EMI
•
Eliminate the requirement for external termination
Depending on the state of the PD_MODE pin, when both output A and B of either channel are disconnected, the
device can automatically power down the channel resulting in a 75% power reduction for that channel.
Furthermore, if output B is manually powered down (PD = L), then disconnecting output A will result in completely
powering down the channel (both outputs).
Due to the detection mechanism, the signal at each output within a channel will experience a phase step of
approximately 15 ps when the other output’s state is changed: powered down, powered up, disconnected, or reconnected.
If one output is disconnected but the other remains connected, and both outputs are toggling, the signal at the
connected output may experience up to 10% overshoot for a period of approximately 500 ns. The overshoot is
caused by the reflections coupled from the unconnected output to the connected one. 500 ns is the duration
required by the circuit to detect the disconnection. If cable detection is disabled and the output is not properly
terminated, the overshoot will persist. Therefore, it is strongly recommended to enable cable detection, or
terminate both outputs properly; when both outputs of one channel are turned on.
The cable detection function may be disabled by setting PD_MODE=L.
21
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M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V3
M/A-COM Technology Solutions Inc. All rights reserved.
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22
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