MIC59P60

MIC59P60
8-Bit Serial-Input Protected Latched Driver
General Description
Features
The MIC59P60 serial-input latched driver is a high-voltage
(80V), high-current (500mA) integrated circuit comprised of
eight CMOS data latches, a bipolar Darlington transistor
driver for each latch, and CMOS control circuitry for the
common CLEAR, STROBE, CLOCK, SERIAL DATA
INPUT, and OUTPUT ENABLE functions. Additional
protection circuitry supplied on this device includes thermal
shutdown, undervoltage lockout (UVLO), and overcurrent
shutdown.
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The bipolar/CMOS combination provides an extremely
low-power latch with maximum interface flexibility. The
MIC59P60 has open-collector outputs capable of sinking
500mA, and integral diodes for inductive load transient
suppression with a minimum output breakdown voltage
rating of 80V (50V sustaining). The drivers can be
operated with a split supply, where the negative supply is
down to –20V and may be paralleled for higher load
current capability.
3.3MHz minimum data input rate
Output current shutdown (500mA typical)
Undervoltage lockout
Thermal shutdown
Output fault flag
CMOS, PMOS, NMOS, and TTL compatible
Internal pull-up/pull-down resistors
Low-power CMOS logic and latches
High-voltage current sink outputs
Output transient-protection diodes
Single or split supply operation
Using a 5V logic supply, the MIC59P60 will typically
operate at better than 5MHz. With a 12V logic supply,
significantly higher speeds can be obtained. The CMOS
inputs are compatible with standard CMOS, PMOS, and
NMOS circuits. TTL circuits may require pull-up resistors.
By using the serial data output, drivers may be cascaded
for interface applications requiring additional drive lines.
Each of the eight outputs has an independent overcurrent
shutdown of 500mA. Upon over-current shutdown, the
affected channel will turn OFF, and the flag will go low until
VDD is cycled or the ENABLE/RESET pin is pulsed high.
Current pulses less than 2μs will not activate current
shutdown.
Temperatures above 165°C will shut down the device and
activate the error flag. The UVLO circuit prevents
operation at low VDD; hysteresis of 0.5V is provided.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 4, 2015
Revision 2.0
Micrel, Inc.
MIC59P60
Functional Diagram
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MIC59P60
Ordering Information
Part Number
Junction Temperature Range
Package
Pb-Free
MIC59P60YN
–40°C to +85°C
20-Pin Plastic DIP
√
MIC59P60YV
–40°C to +85°C
20-Pin PLCC
√
MICP60YWM
–40°C to +85°C
20-Pin Wide SOIC
√
Pin Configuration
20-Pin PLCC (V)
(Top View)
20-Pin PDIP (N)
20-Pin Wide SOIC (WM)
(Top View)
Pin Description
Pin
Number
Pin Name
1
CLEAR
2, 10
VEE
3
CLOCK
4
SERIAL DATA IN
5
VSS
Logic reference (Ground) pin.
6
VDD
Logic Positive Supply voltage.
7
SERIAL DATA OUT
8
STROBE
9
OE / RESET
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Pin Function
Sets All Latches OFF (open).
Output Ground (Substrate). Most negative voltage in the system connects here.
Serial Data Clock. A CLEAR must also be clocked into the latches.
Serial Data Input pin.
Serial Data Output pin. (Flow through).
Output Strobe pin. Loads output latches when High. A STROBE is needed to CLEAR latches.
When low, outputs are active. When high, device is inactive and reset from a fault condition.
An under voltage condition emulates a high OE/RESET input.
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MIC59P60
Pin Description (Continued)
Pin
Number
Pin Name
11
K
12 – 19
OUT N
Open collector outputs 8 through 1.
20
FLAG
Error flag. Open-collector output is low upon overcurrent or overtemperature fault. OE/RESET
must be pulled high to reset the flag and fault condition.
Pin Function
Transient suppression diode’s cathode common pin.
Typical Inputs
Typical Output Driver
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MIC59P60
Absolute Maximum Ratings(1)
Operating Ratings(2)
Output Voltage (VCE) .................................................... +80V
Output Voltage (VCE(SUS))(3) ........................................... +50V
Supply Voltage (VDD) with reference to VSS ................. +15V
Supply Voltage (VDD) with reference to VEE ................. +25V
Emitter Supply Voltage (VEE) ........................................ –20V
Input Voltage Range (VIN) ..................... –0.3V to VDD +0.3V
Protective Current(4) ...................................................... 1.5A
Storage Temperature Range (TS) ............. –65°C to +150°C
ESD Rating(5)(6) .............................................. ESD Sensitive
Package Power Dissipation, PD
Plastic DIP (N) ............................................................. 2.0W
Derate above TA = +25°C ..................................... 20mW/°C
PLCC (V) ..................................................................... 1.4W
Derate above TA = +25°C ..................................... 16mW/°C
Wide SOIC (WM) ........................................................ 1.2W
Derate above TA = +25°C ..................................... 12mW/°C
Operating Temperature Range (TA) ............ –40°C to +85°C
Electrical Characteristics(7)
VDD = 5V, VSS = VEE = 0V; TA = +25°C, unless noted.
Symbol
ICEX
VCE(SAT)
VCE(SUS)
Parameter
Output Leakage Current
Collector-Emitter Saturation Voltage
Collector-Emitter Sustaining Voltage
Condition
Min.
Typ.
VOUT = 80V
50
VOUT = 80V, TA = 70°C
100
IOUT = 100mA
0.9
1.1
IOUT = 200mA
1.1
1.3
IOUT = 350mA
1.3
1.6
IOUT = 350mA, L = 2mH
VDD = 12V
10.5
VDD = 10V
8.5
(8)
RIN
V
V
1.0
Input Voltage
Input Resistance
IOL
Flag Output Current
IOH
Flag Output Leakage
V
V
VDD = 5V
3.5
VDD = 12V
50
200
VDD = 10V
50
300
VDD = 5V
50
600
VOL = 0.4V
Units
µA
50
VIN(0)
VIN(1)
Max.
kΩ
15
mA
50
nA
Notes:
1. Exceeding the absolute maximum ratings may damage the device.
2. The device is not guaranteed to function outside its operating ratings.
3. For inductive load applications.
4. Each channel. VEE connection must be designed to minimize inductance and resistance.
5. Devices are input-static protected but can be damaged by extremely high static charges.
6. Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5kΩ in series with 100pF.
7. Specification for packaged product only
8. Operation of these devices with standard TTL or DTL may require the use of appropriate pull-up resistors to insure a minimum logic "1".
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MIC59P60
Electrical Characteristics(7)
VDD = 5V, VSS = VEE = 0V; TA = +25°C, unless noted.
Symbol
Parameter
IDD(ON)
IDD(1
Supply Current
OUTPUT)
IDD(OFF)
Condition
Typ.
Max.
All Drivers ON, VDD = 12V
6.4
10.0
All Drivers ON, VDD = 10V
6.0
9.0
All Drivers ON, VDD = 5V
4.6
7.5
One Driver ON, All others OFF, VDD = 12V
3.1
4.5
One Driver ON, All others OFF, VDD = 10V
2.9
4.5
One Driver ON, All others OFF, VDD = 5V
2.3
3.6
All Drivers OFF, VDD = 12V
2.6
4.2
All Drivers OFF, VDD = 10V
2.4
3.6
All Drivers OFF, VDD = 5V
1.9
3.0
IR
Clamp Diode Leakage Current
VR = 80V
VF
Clamp Diode Forward Voltage
IF = 350mA
ILIM
Overcurrent Shutdown Threshold
VSU
Start-Up Voltage
VDD MIN
Minimum Supply (VDD)
Min.
1.7
mA
mA
mA
50
µA
2.0
V
500
Note 9
Units
mA
3.5
4.0
4.5
V
3.0
3.5
4.0
V
Thermal Shutdown
165
°C
Thermal Shutdown Hysteresis
10
°C
Note:
9. Undervoltage lockout is guaranteed to release device at no more than 4.5V, and disable the device at no less than 3.0V.
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MIC59P60
Test Circuit
Timing Conditions
(TA = +25°C, Logic Levels are VDD and VSS, VDD = 5V)
A. Typical data active time before clock pulse (data set-up time).................................................................................. 75ns
B. Minimum data active time after clock pulse (data hold time)..................................................................................... 75ns
C. Minimum data pulse width ......................................................................................................................................... 150ns
D. Minimum clock pulse width ........................................................................................................................................ 150ns
E. Minimum time between clock activation and strobe .................................................................................................. 300ns
F. Minimum strobe pulse width ..................................................................................................................................... 100ns
G. Typical time between strobe activation and output transition .................................................................................. 500ns
SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Holding CLEAR high
results in a data logic "0" being clocked into the shift register, turning off respective channels.
Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel
conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the
latches are bypassed (STROBE tied high) will require that the ENABLE input be high to prevent invalid output states.
When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the
latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches. A positive
OE/RESET pulse resets the FLAG and the output after a current shutdown fault. Over-temperature faults are not latched
and require no reset pulse.
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Micrel, Inc.
MIC59P60
MIC59P60 Truth Table
Serial
Data
Input
Clear
Input
Clock
Input
Shift Register
Contents
I1 I2 I3 …… I8
Serial
Data
Output
Strobe
Input
Latch Contents
Output
Enable
I1 I2 I3 …… I8
Output
Contents
I1 I2 I3 …… I8
H
H R1 R2 …… R7
R7
L
L R1 R2 …… R7
R7
X
R1 R2 R3 …… R8
R8
O O O…… O
L
X X X…… X
X
L
R1 R2 R3 …… R8
P1 P2 P3 …… P8
P8
H
P1 P2 P3 …… P8
L
P1 P2 P3 …… P8
X X X …… X
H
H H H …… H
H
Note:
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
O = Output OFF
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MIC59P60
Typical Characteristics
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MIC59P60
Maximum Allowable Duty Cycle (Plastic DIP)
VDD = 5.0V
Number of
Outputs ON
(IOUT = 200mA
VDD = 5.0V)
Max. Allowable Duty Cycle at Ambient Temperature of
25°C
40°C
50°C
60°C
70°C
8
85%
72%
64%
55%
46%
7
97%
82%
73%
63%
53%
6
100%
96%
85%
73%
62%
5
100%
100%
100%
88%
75%
4
100%
100%
100%
100%
93%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
VDD = 12V
Number of
Outputs ON
(IOUT = 200mA
VDD = 12V)
Max. Allowable Duty Cycle at Ambient Temperature of
25°C
40°C
50°C
60°C
70°C
8
80%
68%
60%
52%
44%
7
91%
77%
68%
59%
50%
6
100%
90%
79%
69%
58%
5
100%
100%
95%
82%
69%
4
100%
100%
100%
100%
86%
3
100%
100%
100%
100%
100%
2
100%
100%
100%
100%
100%
1
100%
100%
100%
100%
100%
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MIC59P60
Typical Application
Protected Solenoid Driver with Output Enable
Hammer Driver
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MIC59P60
Protected Negative/Positive PIN Diode Driver Transmit/Receive Switch
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MIC59P60
Package Information and Recommended Landing Pattern(10)
20-Pin 300mil Plastic PDIP (N)
20-Pin Wide SOIC (WM)
Note:
10. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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MIC59P60
Package Information and Recommended Landing Pattern(10) (Continued)
20-Pin PLCC (V)
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MIC59P60
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications
markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock
management, MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs. Company
customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products.
Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and
advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network
of distributors and reps worldwide.
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
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© 2001 Micrel, Incorporated.
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