SM802141

SM802141
ClockWorks Selectable 62.5MHz,
125MHz, 156.25MHz and 312.5MHz
Ultra-Low Jitter, LVPECL Frequency
Synthesizer
General Description
Features
The SM802141 is a part of Micrel’s ClockWorks family of
devices and provides an extremely low-noise timing
solution for Ethernet clock signals.
The device operates from a 3.3V or 2.5V power supply
and synthesizes differential LVPECL output clocks at
62.5MHz, 125MHz, 156.25MHz or 312.5MHz, selectable
through logic control pins. The SM802141 accepts a
25MHz crystal or LVCMOS reference clock.
Data sheet and support documentation can be found on
Micrel’s web site at: www.micrel.com.
 Configurable to generate up to four different LVPECL
clock frequencies
 2.5V or 3.3V operating range
 Typical phase jitter @ 125MHz
(12kHz to 20MHz): 255 fsrms
 Industrial temperature range (–40C to +85C)
 Green, RoHS, and PFOS compliant
 Available in 24-pin 4mm  4mm QFN package
Applications
 Ethernet PHY
 Storage networking (SAN, NAS)
Block Diagram
ClockWorks is a trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2012
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SM802141
Ordering Information(1)
Part Number
Marking
Shipping
Temperature Range
Package
SM802141UMG
802141
Tube
–40C to +85C
24-Pin QFN
SM802141UMGTR
802141
Tape and Reel
–40C to +85C
24-Pin QFN
Note:
1. Devices are Green, RoHS, and PFOS compliant.
Pin Configuration
24-Pin QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
19, 20
/Q1, Q1
O, (DIF)
LVPECL
Differential Clock Output from Bank 1, 156.25MHz or
312.5MHz.
22, 23
/Q2, Q2
O, (DIF)
LVPECL
Differential Clock Output from Bank 2, 62.5MHz or 125MHz.
24
VDDO2
PWR
Power Supply for Output Bank 2.
2
VSSO2
PWR
Power Supply Ground for Output Bank 2.
3
PLL_BYPASS
I, (SE)
LVCMOS
PLL Bypass, Selects Output Source, 0 = Normal PLL
Operation, 1 = Output from Input Reference Clock or Crystal
45KΩ pull-down.
4
XTAL_SEL
I, (SE)
LVCMOS
Selects PLL Input Reference Source (0 = REF_IN, 1 =
XTAL, 45KΩ pull-up).
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SM802141
Pin Description (Continued)
Pin
Type
Pin Number
Pin Name
Pin Level
Pin Function
5, 11, 16, 18
TEST
1
VDD
PWR
Core Power Supply .
13, 14, 15
VSS (Exposed Pad)
PWR
Core Power Supply Ground. The exposed pad must be
connected to the VSS ground plane.
17
VDDO1
PWR
Power Supply for Output Bank 1.
21
VSSO1
PWR
Power Supply Ground for Output Bank 1.
8
REF_IN
I, (SE)
LVCMOS
9
XTAL_IN
I, (SE)
XTAL
Crystal Reference Input. No load caps needed (see Figure 5).
10
XTAL_OUT
O, (SE)
XTAL
6
FSEL
I, (SE)
LVCMOS
7
OE1
I, (SE)
LVCMOS
12
OE2
I, (SE)
LVCMOS
Crystal Reference Output. No load caps needed (see Figure 5).
Frequency Select, 1 = 312.5/125 MHz, 0 = 156.25/62.5MHz,
45KΩ pull-up.
Output Enable, Q1 disables to tri-state, 0 = Disabled, 1 =
Enabled, 45KΩ pull-up.
Output Enable, Q2 disables to tri-state, 0 = Disabled, 1 =
Enabled, 45KΩ pull-up.
Factory test pins. Do not connect anything to these pins.
Reference Clock Input.
Truth Table
PLL_BYPASS
XTAL_SEL
OE1
OE2
INPUT
OUTPUT
0

1
1

PLL
1

1
1

XTAL/REF_IN

0
1
1
REF_IN


1
1
1
XTAL




1
0


0
1
Q1 Tri-State
Q2 Tri-State

Output Selection Table
XTAL_SEL
PLL_Bypass
F SEL
L
H
x
H (Default)
H
x
H (Default)
L (Default)
H (Default)
H (Default)
L (Default)
H (Default)
H (Default)
L (Default)
L
H (Default)
L (Default)
L
April 2012
OE1
H
H
H
L
H
L
OE2
L
L
L
H
L
H
3
Div 1
x
x
10
10
20
20
Div 2
x
x
25
25
50
50
Q1
Q2
Reference Input
25
312.5
Hi-Z
156.25
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
62.5
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SM802141
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD, VDDO1/2) ......................................+4.6V
Input Voltage (VIN) .............................. 0.50V to VDD + 0.5V
Lead Temperature (soldering, 20s)............................ 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts) ......................... 65C to 150°C
Supply Voltage (VDD, VDDO1/2)............... +2.375V to +3.465V
Ambient Temperature (TA).......................... –40°C to +85°C
Junction Thermal Resistance(3)
QFN (JA)
Still-Air......................................................... 50°C/W
QFN (JB)
Junction-to-Board ....................................... 30°C/W
DC Electrical Characteristics(4)
VDD = VDDO1, 2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5% & VDDO1,2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C.
Symbol
Parameter
VDD, VDDO1/2
Condition
Min.
Typ.
Max.
Units
2.5V Operating Voltage
2.375
2.5
2.625
V
VDD, VDDO1/2
3.3V Operating Voltage
3.135
3.3
3.465
V
IDD XTAL
Supply Current VDD + VDDO
XTAL_SEL = 1
Outputs Open
62.5MHz; 1 output enabled
80
125MHz; 1 output enabled
86
156.25MHz; 1 output enabled
88
312.5MHz; 1 output enabled
97
mA
125
LVPECL OUTPUT DC Electrical Characteristics(4)
VDD = VDDO1, 2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5% & VDDO1, 2 = 3.3V 5% or 2.5V 5%,
TA = 40C to 85C, RL = 50Ω to VDDO  2V
Symbol
Parameter
VOH
Condition
Min.
Typ.
Max.
Units
Output High Voltage
VDDO – 1.145
VDDO – 0.97
VDDO – 0.845
V
VOL
Output Low Voltage
VDDO – 1.945
VDDO – 1.77
VDDO – 1.645
V
VSWING
Output Voltage Swing
0.6
0.8
1.0
V
Notes:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4.
The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
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SM802141
LVCMOS (PLL_BYPASS, XTAL_SEL, OE1/2, FSEL) DC Electrical Characteristics(4)
VDD = 3.3V 5%, or 2.5V 5%, TA = 40C to 85C.
Symbol
Parameter
Condition
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
Min.
Typ.
Max.
Units
2
VDD + 0.3
V
0.3
0.8
V
150
A
150
A
REF_IN DC Electrical Characteristics(4)
VDD = 3.3V 5%, or 2.5V 5%, TA = 40C to 85C.
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
Condition
Min.
XTAL_SEL = VIL, VIN = 0V to VDD
Max.
Units
1.1
VDD + 0.3
V
0.3
0.6
V
5
5
A
XTAL_SEL = VIH, VIN = VDD
Typ.
20
µA
Crystal Characteristics
Parameter
Condition
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitor, C0
Correlation Drive Level
10pF Load
April 2012
Min.
Typ.
Max.
Units
Fundamental, Parallel Resonant
25
1
10
5
50
5
100
MHz
Ω
pF
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SM802141
AC Electrical Characteristics(4, 5)
VDD = VDDO1/2 = 3.3V 5% or 2.5V 5%
VDD = 3.3V 5% & VDDO1, 2 = 3.3V 5% or 2.5V 5%
TA = 40C to 85C, RL = 50Ω to VDDO  2V
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
FOUT1
Output Frequency 1(7)
XTAL_SEL = H, FSEL =X, OE1 = H,
OE2 = L, PLL Bypass = H
25
MHz
FOUT2
Output Frequency 2(7)
XTAL_SEL = H, FSEL =1, OE1 = H,
OE2 = H, PLL Bypass = L
312.5/
125
MHz
FOUT3
Output Frequency 3(7)
XTAL_SEL = H, FSEL =0, OE1 = H,
OE2 = H, PLL Bypass = L
156.25/
62.5
MHz
FOUT4
Output Frequency 4(7)
XTAL_SEL = L, FSEL =X, OE1 = H,
OE2 = L, PLL Bypass = H
REF_IN
MHz
FREF
Reference Input Frequency
25
MHz
TR/TF
LVPECL Output Rise/Fall Time
ODC
Output Duty Cycle
TLOCK
PLL Lock Time
Tjit()
RMS Phase Jitter
(6)
Spurious Noise Components
20% – 80%
80
175
350
ps
48
50
52
%
20
ms
25MHz
Integration Range (12kHz – 5MHz)
62.5MHz
Integration Range (12kHz – 10MHz)
125MHz
Integration Range (12kHz – 20MHz)
156.25MHz
Integration Range (12kHz – 20MHz)
312.5MHz
Integration Range (12kHz – 20MHz)
240
12.5MHz using 62.5MHz
25MHz using 125MHz
6.25MHz using 156.25MHz
25MHz using 156.25MHz
12.5MHz using 312.5MHz
-76
-80
-82
-62
-79
315
255
fsrms
245
250
dBc
Notes:
5.
All phase-noise measurements were taken with an Agilent 5052B phase-noise system.
6.
Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase-noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
7.
When output bank Q1 and output bank Q2 are externally tied together. Refer to Output selection Table.
April 2012
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SM802141
Application Information
Input Reference
When operating with a crystal input reference, do not
apply a switching signal to REF_IN.
Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal.
Crystal load capacitance is built inside the die so no
external capacitance is needed. See the Selecting a
Quartz Crystal for the Clockworks Flex I Family of
Precision Synthesizers application note for further
details.
Contact Micrel’s HBW applications group if you need
assistance on selecting a suitable crystal for your
application at [email protected].
Parallel outputs to achieve four frequencies
Four frequencies, 62.5MHz, 125MHz, 156.25MHz and
312.5MHz can be achieved in one output channel by
shorting Q1 and Q2 outputs together at the device pins.
Frequency selection is achieved using FSEL, OE1 and
OE2 pins as outlined in the Output Selection Table.
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SM802141
Phase Noise Plots
Phase Noise Plot: 25MHz, 12kHz  5MHz, 241 fsrms
Phase Noise Plot: 62.5MHz, 12kHz  10MHz, 315 fsrms
April 2012
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SM802141
Phase Noise Plots (Continued)
Phase Noise Plot: 125MHz, 12kHz  20MHz, 254 fsrms
Phase Noise Plot: 156.25MHz, 12kHz  20MHz, 244 fsrms
April 2012
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SM802141
Phase Noise Plots (Continued)
Phase Noise Plot: 312.5MHz, 12kHz  20MHz, 248 fsrms
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SM802141
Figure 1. Duty Cycle Timing
Figure 2. All Outputs Rise/Fall Time
Figure 3. RMS Phase Noise Jitter
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Figure 4. LVPECL Output Load and Test Circuit
Figure 5. Crystal Input Interface
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SM802141
Package Information
24-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
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© 2012 Micrel, Incorporated.
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