SY898531L

SY898531L
Precision Differential 3.3V Low-Skew
LVPECL 1:9 Fanout Buffer
Precision Edge®
General Description
The SY898531L is a 3.3V, low-skew, 1:9 LVPECL fanout
buffer with two selectable clock input pairs. Most standard
differential input levels can be applied to the CLK, /CLK
pair while LVPECL, CML, or SSTL input levels can be
applied to the PCLK, /PCLK pair. To eliminate runt pulses
on the outputs during asynchronous assertion/de-assertion
of the clock enable pin, the clock enable is synchronized
with the input signal.
The SY898531L operates from a 3.3V ±5% supply and is
guaranteed over the full industrial temperature range of
0°C to +70°C. The SY898531L is part of Micrel’s high®
speed, Precision Edge product line.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge
Features
• Provides nine differential 3.3V LVPECL copies
• Selects between differential CLK, /CLK or LVPECL
clock inputs
• CLK, /CLK pair accepts LVDS, LVPECL, LVHSTL,
SSTL, HCSL input levels
• PCLK, /PCLK pair accepts LVPECL, CML, SSTL input
levels
• Guaranteed AC performance over temperature and
supply voltage:
− 500MHz maximum output frequency
− < 2ns propagation delay (In-to-Q)
− < 50ps output skew
− < 250ps part-to-part skew
• Additive phase jitter, RMS: 0.17ps (typical)
• 3.3V ±5% supply voltage
• 0°C to +70°C temperature operating range
• Available in a 32-pin TQFP package
Applications
• SONET clock distribution
• Backplane distribution
Markets
•
•
•
•
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 25, 2013
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®
Micrel, Inc.
SY898531L
Ordering Information
Part Number
Package Type
SY898531LTZ
T32-1
T32-1
(2)
SY898531LTZTR
Operating Range
(1)
Package Marking
Lead Finish
Commercial
SY898531LTZ
with Pb-Free Bar-Line Indicator
Matte-Tin, Pb-Free
Commercial
SY898531LTZ
with Pb-Free Bar-Line Indicator
Matte-Tin, Pb-Free
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only.
2. Tape and Reel.
Pin Configuration
32-Pin 7mm × 7mm TQFP (T32-1)
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SY898531L
Pin Description
Pin Number
Pin Name
7
VEE
Pin Function
Ground.
8
CLK_EN
Single-Ended Input: This TTL/CMOS input disables and enables the Q0 − Q8 outputs. It is
internally connected to a 50kΩ pull-up resistor and will default to a logic HIGH state if left
open. When disabled, Q goes LOW and /Q goes HIGH. Since CLK_EN is synchronous
with the input clock, the outputs will be enabled/disabled following a rising and a falling
edge of the input clock. VTH = is approximately 1.5V.
4
CLK_SEL
Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the input to the
multiplexer. Note that this input is internally connected to a 50kΩ pull-down resistor and will
default to logic LOW state if left open. VTH = is approximately 1.5V.
CLK, /CLK
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. CLK is internally connected to a 28kΩ pull-down
resistor and will default to a logic LOW state if left open while /CLK is connected to a 50kΩ
pull-up resistor and will default to a logic HIGH state if left open. This input pair is selected
when CLK_SEL is set to logic LOW.
2, 3
Differential Input: This input pair is a differential signal input to the device. This input
accepts AC- or DC-coupled signals. PCLK is internally connected to a 50kΩ pull-down
resistor and will default to a logic LOW state if left open while /PCLK is connected to a
50kΩ pull-up resistor and will default to a logic HIGH state if left open. This input pair is
selected when CLK_SEL is set to logic HIGH.
5, 6
PCLK, /PCLK
1
VCC
Positive Power Supply Pin: Bypass with 0.1µF||0.01µF low-ESR capacitor as close to the
VCC pin as possible.
9, 16, 17, 24, 25, 32
VCCO
Output Positive Power Supply Pins: Bypass with 0.1µF||0.01µF low-ESR capacitors as
close to the VCCO pins as possible.
30, 31
28, 29
26, 27
22, 23
20, 21
18, 19
14, 15
12, 13
10, 11
Q0, /Q0
Q1, /Q1
Q2, /Q2
Q3, /Q3
Q4, /Q4
Q5, /Q5
Q6, /Q6
Q7, /Q7
Q8, /Q8
LVPECL Differential Output Pairs: Differential buffered output copies of the selected input
signal. The output swing is typically 800mV. Unused output pairs may be left floating with
no impact on jitter. These differential LVPECL outputs are a logic function of the CLK, /CLK
and PCLK, /PCLK, and CLK_SEL inputs (see Truth Table).
Truth Table
Inputs
Outputs
CLK_EN
CLK_SEL
Selected Source
Q0 :Q8
/Q0:/Q8
0
0
CLK, /CLK
Disabled : LOW
Disabled : HIGH
0
1
PCLK, /PCLK
Disabled : LOW
Disabled : HIGH
1
0
CLK, /CLK
CLK
/CLK
1
1
PCLK, /PCLK
PCLK
/PCLK
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SY898531L
Absolute Maximum Ratings(3)
Operating Ratings(4)
Supply Voltage (VCC) .................................... –0.5V to +4.6V
Input Voltage (VIN) .................................. –0.5V to VCC +0.5V
LVPECL Output Current (IOUT)
Continuous ............................................................ 50mA
Surge .................................................................. 100mA
Lead Temperature (soldering, 20s) .......................... +260°C
Storage Temperature (Ts) ........................... –65°C to 150°C
Supply Voltage (VCC) ............................ +3.135V to +3.465V
Ambient Temperature (TA) .............................. 0°C to +70°C
(5)
Package Thermal Resistance
TSSOP (θ JA)
Still-Air ......................................................... 50°C/W
Power Supply DC Electrical Characteristics(6)
VCC = VCCO = 3.3V ±5%; TA = 0°C to +70°C, unless otherwise stated.
Symbol
Parameter
VCC
Condition
Min.
Typ.
Max.
Units
Power Supply
3.135
3.3
3.465
V
VCCO
Output Power Supply
3.135
3.3
3.465
V
IEE
Power Supply Current
80
mA
Max.
Units
No load, maximum VCC
LVCMOS/LVTTL DC Electrical Characteristics(6)
VCC = VCCO = 3.3V ±5%; TA = 0°C to +70°C, unless otherwise stated.
Symbol
Parameter
Condition
Min.
Typ.
VIH
Input High Voltage
2
VCC + 0.3
VIL
Input Low Voltage
−0.3
0.8
IIH
Input High Current
IIL
Input Low Current
CLK_EN
VIN = VCC = 3.465V
5
CLK_SEL
VIN = VCC = 3.465V
150
CLK_EN
VIN = 0V, VCC = 3.465V
−150
CLK_SEL
VIN = 0V, VCC = 3.465V
−5
V
V
µA
µA
Notes:
3. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
4. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
5. θJA value is determined for a 4-layer board in still air unless otherwise stated.
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY898531L
Differential DC Electrical Characteristics(6)
VCC = VCCO = 3.3V ±5%; TA = 0°C to +70°C, unless otherwise stated.
Symbol
IIH
Parameter
Condition
Input Low Current
VPP
Peak-to-Peak Input Voltage
VCMR
Typ.
Max.
CLK
VIN = VCC = 3.465V
150
/CLK
VIN = VCC = 3.465V
5
CLK
VIN = 0.5V, VCC = 3.465V
−5
/CLK
VIN = 0.5V, VCC = 3.465V
−150
Input High Current
IIL
Min.
(7, 8)
Common Mode Input Voltage
Units
µA
µA
0.15
1.3
V
VEE + 0.5
VCC − 0.85
V
LVPECL DC Electrical Characteristics(9)
VCC = VCCO = 3.3V ±5%; TA = 0°C to +70°C, unless otherwise stated
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
VCMR
VOH
Condition
Min.
Max.
PCLK
VIN = VCC = 3.465V
150
/PCLK
VIN = VCC = 3.465V
5
PCLK
VIN = 0V, VCC = 3.465V
-5
/PCLK
VIN = 0V, VCC = 3.465V
−150
(10, 11)
Common Mode Input Voltage
Output High Voltage
Typ.
(12)
(12)
VOL
Output Low Voltage
VSWING
Peak-to-Peak Output Voltage Swing
Units
µA
µA
0.3
1
V
VEE + 1.5
VCC
V
VCC − 1.4
VCC – 1.0
V
VCC – 2.0
VCC − 1.7
V
0.6
1.0
V
Notes:
7. Maximum input voltage for CLK and /CLK is VCC + 0.3V for single-ended applications.
8. VIH is defined as the common-mode voltage.
9. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
10. Maximum input voltage for PCLK and /PCLK is VCC + 0.3V for single-ended applications.
11. VIH is defined as the common-mode voltage.
12. 50Ω to VCCO − 2V terminated outputs.
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SY898531L
AC Electrical Characteristics(13)
VCC = VCCO = 3.3V ±5%; RL = 50Ω to VCCO − 2V; TA = 0°C to +70°C, unless otherwise stated.
Symb
ol
Parameter
fMAX
Maximum Operating Frequency
tPD
Differential Propagation Delay
CLK-to-Q, PCLK-to-Q
Condition
Min.
Typ.
500
f ≤ 250MHz
1
2
Output-to-Output Skew
(15)
Part-to-Part Skew
(16)
tJITTER
Additive Phase Jitter
155.52MHz, (12KHz to 20MHz)
tr , tf
Output Rise/Fall Time
20% to 80% @ 50MHz
odc
Output Duty Cycle
300
50
ns
50
ps
250
ps
0.17
48
Units
MHz
(14)
tSKEW
Max.
psRMS
700
ps
52
%
Note:
13. High-frequency AC-parameters are guaranteed by design and characterization.
14. Output-to-output skew is measured between two different outputs under identical transitions.
15. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs. This parameter is defined in accordance with JEDEC Standard 65.
16. Driving only one input clock.
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SY898531L
Timing Diagrams
Figure 1. CLK_EN Timing Diagram
Figure 2. Propagation Delay
Figure 3. Output-to-Output Skew
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SY898531L
Typical Operating Characteristics
VCC = 3.3V, VEE = 0V, VIN = 800mV, RL = 50Ω to VCC − 2V; TA = 25°C, unless otherwise stated.
Output Swing
vs. Frequency
900
OUTPUT SWING (mV)
800
700
600
500
400
300
200
100
1100
900
1000
800
700
600
500
400
300
200
0
100
0
FREQUENCY (MHz)
Functional Characteristics
VCC = 3.3V, VEE = 0V, VIN = 800mV, RL = 50Ω to VCC − 2V; TA = 25°C, unless otherwise stated.
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SY898531L
CLK, /CLK Input Interface Applications
Figure 4. LVHSTL Interface (DC-Coupled)
Figure 5. LVPECL Interface (DC-Coupled)
Figure 6. LVPECL Interface (DC-Coupled)
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SY898531L
CLK, /CLK Input Interface Applications (Continued)
Figure 7. LVDS Interface (DC-Coupled)
Figure 8. LVPECL Interface (AC-Coupled)
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SY898531L
PCLK, /PCLK Input Interface Applications
Figure 9. CML Open Collector Interface (DC-Coupled)
Figure 10. CML Built-In Pull-Up Interface (DC-Coupled)
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PCLK, /PCLK Input Interface Applications (Continued)
Figure 11. LVPECL Interface (DC-Coupled)
Figure 12. LVPECL Interface (AC-Coupled)
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SY898531L
PCLK, /PCLK Input Interface Applications (Continued)
Figure 13. SSTL Interface (DC-Coupled)
Figure 14. LVDS Interface (AC-Coupled)
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SY898531L
Package Information(17)
32-Pin 7mm × 7mm TQFP (T32-1)
Note:
17. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com.
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SY898531L
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical
implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
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© 2009 Micrel, Incorporated.
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